//
// Copyright (c) 2018 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ___ARTKE_BPMP_H_INC_
#define ___ARTKE_BPMP_H_INC_
#define NV_MOBILE_ARTKE_BPMP_H_UNIT_OF_OFFSET 1B


// Register TKE_BPMP_SHARED_TKETSC0_0
#define TKE_BPMP_SHARED_TKETSC0_0                       _MK_ADDR_CONST(0x0)
#define TKE_BPMP_SHARED_TKETSC0_0_SECURE                        0x0
#define TKE_BPMP_SHARED_TKETSC0_0_DUAL                  0x0
#define TKE_BPMP_SHARED_TKETSC0_0_SCR                   TKESCR_0
#define TKE_BPMP_SHARED_TKETSC0_0_WORD_COUNT                    0x1
#define TKE_BPMP_SHARED_TKETSC0_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKETSC0_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define TKE_BPMP_SHARED_TKETSC0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKETSC0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKETSC0_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define TKE_BPMP_SHARED_TKETSC0_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKETSC0_0_CV_SHIFT                      _MK_SHIFT_CONST(0)
#define TKE_BPMP_SHARED_TKETSC0_0_CV_FIELD                      _MK_FIELD_CONST(0xffffffff, TKE_BPMP_SHARED_TKETSC0_0_CV_SHIFT)
#define TKE_BPMP_SHARED_TKETSC0_0_CV_RANGE                      31:0
#define TKE_BPMP_SHARED_TKETSC0_0_CV_WOFFSET                    0x0
#define TKE_BPMP_SHARED_TKETSC0_0_CV_DEFAULT                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKETSC0_0_CV_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define TKE_BPMP_SHARED_TKETSC0_0_CV_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKETSC0_0_CV_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKETSC0_0_CV_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKETSC0_0_CV_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register TKE_BPMP_SHARED_TKETSC1_0
#define TKE_BPMP_SHARED_TKETSC1_0                       _MK_ADDR_CONST(0x4)
#define TKE_BPMP_SHARED_TKETSC1_0_SECURE                        0x0
#define TKE_BPMP_SHARED_TKETSC1_0_DUAL                  0x0
#define TKE_BPMP_SHARED_TKETSC1_0_SCR                   TKESCR_0
#define TKE_BPMP_SHARED_TKETSC1_0_WORD_COUNT                    0x1
#define TKE_BPMP_SHARED_TKETSC1_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKETSC1_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define TKE_BPMP_SHARED_TKETSC1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKETSC1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKETSC1_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define TKE_BPMP_SHARED_TKETSC1_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKETSC1_0_CV_SHIFT                      _MK_SHIFT_CONST(0)
#define TKE_BPMP_SHARED_TKETSC1_0_CV_FIELD                      _MK_FIELD_CONST(0xffffffff, TKE_BPMP_SHARED_TKETSC1_0_CV_SHIFT)
#define TKE_BPMP_SHARED_TKETSC1_0_CV_RANGE                      31:0
#define TKE_BPMP_SHARED_TKETSC1_0_CV_WOFFSET                    0x0
#define TKE_BPMP_SHARED_TKETSC1_0_CV_DEFAULT                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKETSC1_0_CV_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define TKE_BPMP_SHARED_TKETSC1_0_CV_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKETSC1_0_CV_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKETSC1_0_CV_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKETSC1_0_CV_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register TKE_BPMP_SHARED_TKEUSEC_0
#define TKE_BPMP_SHARED_TKEUSEC_0                       _MK_ADDR_CONST(0x8)
#define TKE_BPMP_SHARED_TKEUSEC_0_SECURE                        0x0
#define TKE_BPMP_SHARED_TKEUSEC_0_DUAL                  0x0
#define TKE_BPMP_SHARED_TKEUSEC_0_SCR                   TKESCR_0
#define TKE_BPMP_SHARED_TKEUSEC_0_WORD_COUNT                    0x1
#define TKE_BPMP_SHARED_TKEUSEC_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKEUSEC_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define TKE_BPMP_SHARED_TKEUSEC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKEUSEC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKEUSEC_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define TKE_BPMP_SHARED_TKEUSEC_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKEUSEC_0_CV_SHIFT                      _MK_SHIFT_CONST(0)
#define TKE_BPMP_SHARED_TKEUSEC_0_CV_FIELD                      _MK_FIELD_CONST(0xffffffff, TKE_BPMP_SHARED_TKEUSEC_0_CV_SHIFT)
#define TKE_BPMP_SHARED_TKEUSEC_0_CV_RANGE                      31:0
#define TKE_BPMP_SHARED_TKEUSEC_0_CV_WOFFSET                    0x0
#define TKE_BPMP_SHARED_TKEUSEC_0_CV_DEFAULT                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKEUSEC_0_CV_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define TKE_BPMP_SHARED_TKEUSEC_0_CV_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKEUSEC_0_CV_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKEUSEC_0_CV_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKEUSEC_0_CV_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register TKE_BPMP_SHARED_TKEOSC_0
#define TKE_BPMP_SHARED_TKEOSC_0                        _MK_ADDR_CONST(0xc)
#define TKE_BPMP_SHARED_TKEOSC_0_SECURE                         0x0
#define TKE_BPMP_SHARED_TKEOSC_0_DUAL                   0x0
#define TKE_BPMP_SHARED_TKEOSC_0_SCR                    TKESCR_0
#define TKE_BPMP_SHARED_TKEOSC_0_WORD_COUNT                     0x1
#define TKE_BPMP_SHARED_TKEOSC_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKEOSC_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define TKE_BPMP_SHARED_TKEOSC_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKEOSC_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKEOSC_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define TKE_BPMP_SHARED_TKEOSC_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKEOSC_0_CV_SHIFT                       _MK_SHIFT_CONST(0)
#define TKE_BPMP_SHARED_TKEOSC_0_CV_FIELD                       _MK_FIELD_CONST(0xffffffff, TKE_BPMP_SHARED_TKEOSC_0_CV_SHIFT)
#define TKE_BPMP_SHARED_TKEOSC_0_CV_RANGE                       31:0
#define TKE_BPMP_SHARED_TKEOSC_0_CV_WOFFSET                     0x0
#define TKE_BPMP_SHARED_TKEOSC_0_CV_DEFAULT                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKEOSC_0_CV_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define TKE_BPMP_SHARED_TKEOSC_0_CV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKEOSC_0_CV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKEOSC_0_CV_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKEOSC_0_CV_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register TKE_BPMP_SHARED_TKECR_0
#define TKE_BPMP_SHARED_TKECR_0                 _MK_ADDR_CONST(0x10)
#define TKE_BPMP_SHARED_TKECR_0_SECURE                  0x0
#define TKE_BPMP_SHARED_TKECR_0_DUAL                    0x0
#define TKE_BPMP_SHARED_TKECR_0_SCR                     TKESCR_0
#define TKE_BPMP_SHARED_TKECR_0_WORD_COUNT                      0x1
#define TKE_BPMP_SHARED_TKECR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKECR_0_RESET_MASK                      _MK_MASK_CONST(0xf)
#define TKE_BPMP_SHARED_TKECR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKECR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKECR_0_READ_MASK                       _MK_MASK_CONST(0xf)
#define TKE_BPMP_SHARED_TKECR_0_WRITE_MASK                      _MK_MASK_CONST(0xf)
#define TKE_BPMP_SHARED_TKECR_0_TSC_DIS_SHIFT                   _MK_SHIFT_CONST(0)
#define TKE_BPMP_SHARED_TKECR_0_TSC_DIS_FIELD                   _MK_FIELD_CONST(0x1, TKE_BPMP_SHARED_TKECR_0_TSC_DIS_SHIFT)
#define TKE_BPMP_SHARED_TKECR_0_TSC_DIS_RANGE                   0:0
#define TKE_BPMP_SHARED_TKECR_0_TSC_DIS_WOFFSET                 0x0
#define TKE_BPMP_SHARED_TKECR_0_TSC_DIS_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKECR_0_TSC_DIS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define TKE_BPMP_SHARED_TKECR_0_TSC_DIS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKECR_0_TSC_DIS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKECR_0_TSC_DIS_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKECR_0_TSC_DIS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define TKE_BPMP_SHARED_TKECR_0_USEC_DIS_SHIFT                  _MK_SHIFT_CONST(1)
#define TKE_BPMP_SHARED_TKECR_0_USEC_DIS_FIELD                  _MK_FIELD_CONST(0x1, TKE_BPMP_SHARED_TKECR_0_USEC_DIS_SHIFT)
#define TKE_BPMP_SHARED_TKECR_0_USEC_DIS_RANGE                  1:1
#define TKE_BPMP_SHARED_TKECR_0_USEC_DIS_WOFFSET                        0x0
#define TKE_BPMP_SHARED_TKECR_0_USEC_DIS_DEFAULT                        _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKECR_0_USEC_DIS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define TKE_BPMP_SHARED_TKECR_0_USEC_DIS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKECR_0_USEC_DIS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKECR_0_USEC_DIS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKECR_0_USEC_DIS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define TKE_BPMP_SHARED_TKECR_0_OSC_DIS_SHIFT                   _MK_SHIFT_CONST(2)
#define TKE_BPMP_SHARED_TKECR_0_OSC_DIS_FIELD                   _MK_FIELD_CONST(0x1, TKE_BPMP_SHARED_TKECR_0_OSC_DIS_SHIFT)
#define TKE_BPMP_SHARED_TKECR_0_OSC_DIS_RANGE                   2:2
#define TKE_BPMP_SHARED_TKECR_0_OSC_DIS_WOFFSET                 0x0
#define TKE_BPMP_SHARED_TKECR_0_OSC_DIS_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKECR_0_OSC_DIS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define TKE_BPMP_SHARED_TKECR_0_OSC_DIS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKECR_0_OSC_DIS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKECR_0_OSC_DIS_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKECR_0_OSC_DIS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define TKE_BPMP_SHARED_TKECR_0_HDBG_SHIFT                      _MK_SHIFT_CONST(3)
#define TKE_BPMP_SHARED_TKECR_0_HDBG_FIELD                      _MK_FIELD_CONST(0x1, TKE_BPMP_SHARED_TKECR_0_HDBG_SHIFT)
#define TKE_BPMP_SHARED_TKECR_0_HDBG_RANGE                      3:3
#define TKE_BPMP_SHARED_TKECR_0_HDBG_WOFFSET                    0x0
#define TKE_BPMP_SHARED_TKECR_0_HDBG_DEFAULT                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKECR_0_HDBG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define TKE_BPMP_SHARED_TKECR_0_HDBG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKECR_0_HDBG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKECR_0_HDBG_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_TKECR_0_HDBG_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register TKE_BPMP_SHARED_CLK_OVR_ON_0
#define TKE_BPMP_SHARED_CLK_OVR_ON_0                    _MK_ADDR_CONST(0x14)
#define TKE_BPMP_SHARED_CLK_OVR_ON_0_SECURE                     0x0
#define TKE_BPMP_SHARED_CLK_OVR_ON_0_DUAL                       0x0
#define TKE_BPMP_SHARED_CLK_OVR_ON_0_SCR                        TKESCR_0
#define TKE_BPMP_SHARED_CLK_OVR_ON_0_WORD_COUNT                         0x1
#define TKE_BPMP_SHARED_CLK_OVR_ON_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_CLK_OVR_ON_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define TKE_BPMP_SHARED_CLK_OVR_ON_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_CLK_OVR_ON_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_CLK_OVR_ON_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define TKE_BPMP_SHARED_CLK_OVR_ON_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define TKE_BPMP_SHARED_CLK_OVR_ON_0_OSC_SHIFT                  _MK_SHIFT_CONST(0)
#define TKE_BPMP_SHARED_CLK_OVR_ON_0_OSC_FIELD                  _MK_FIELD_CONST(0x1, TKE_BPMP_SHARED_CLK_OVR_ON_0_OSC_SHIFT)
#define TKE_BPMP_SHARED_CLK_OVR_ON_0_OSC_RANGE                  0:0
#define TKE_BPMP_SHARED_CLK_OVR_ON_0_OSC_WOFFSET                        0x0
#define TKE_BPMP_SHARED_CLK_OVR_ON_0_OSC_DEFAULT                        _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_CLK_OVR_ON_0_OSC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define TKE_BPMP_SHARED_CLK_OVR_ON_0_OSC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_CLK_OVR_ON_0_OSC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_CLK_OVR_ON_0_OSC_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_SHARED_CLK_OVR_ON_0_OSC_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define TKE_BPMP_SHARED_CLK_OVR_ON_0_OSC_DISABLE                        _MK_ENUM_CONST(0)
#define TKE_BPMP_SHARED_CLK_OVR_ON_0_OSC_ENABLE                 _MK_ENUM_CONST(1)


// Register TKE_BPMP_TIMER_TMR0_TMRCR_0
#define TKE_BPMP_TIMER_TMR0_TMRCR_0                     _MK_ADDR_CONST(0x10000)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_SECURE                      0x0
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_DUAL                        0x0
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_SCR                         TMRSCR0_0
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_WORD_COUNT                  0x1
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_RESET_VAL                   _MK_MASK_CONST(0x40000000)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_RESET_MASK                  _MK_MASK_CONST(0xdfffffff)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_READ_MASK                   _MK_MASK_CONST(0xdfffffff)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_WRITE_MASK                  _MK_MASK_CONST(0xdfffffff)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_EN_SHIFT                    _MK_SHIFT_CONST(31)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_EN_FIELD                    _MK_FIELD_CONST(0x1, TKE_BPMP_TIMER_TMR0_TMRCR_0_EN_SHIFT)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_EN_RANGE                    31:31
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_EN_WOFFSET                  0x0
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define TKE_BPMP_TIMER_TMR0_TMRCR_0_PER_SHIFT                   _MK_SHIFT_CONST(30)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_PER_FIELD                   _MK_FIELD_CONST(0x1, TKE_BPMP_TIMER_TMR0_TMRCR_0_PER_SHIFT)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_PER_RANGE                   30:30
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_PER_WOFFSET                 0x0
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_PER_DEFAULT                 _MK_MASK_CONST(0x1)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_PER_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_PER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_PER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_PER_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_PER_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define TKE_BPMP_TIMER_TMR0_TMRCR_0_PTV_SHIFT                   _MK_SHIFT_CONST(0)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_PTV_FIELD                   _MK_FIELD_CONST(0x1fffffff, TKE_BPMP_TIMER_TMR0_TMRCR_0_PTV_SHIFT)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_PTV_RANGE                   28:0
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_PTV_WOFFSET                 0x0
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_PTV_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_PTV_DEFAULT_MASK                    _MK_MASK_CONST(0x1fffffff)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_PTV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_PTV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_PTV_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRCR_0_PTV_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register TKE_BPMP_TIMER_TMR0_TMRSR_0
#define TKE_BPMP_TIMER_TMR0_TMRSR_0                     _MK_ADDR_CONST(0x10004)
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_SECURE                      0x0
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_DUAL                        0x0
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_SCR                         TMRSCR0_0
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_WORD_COUNT                  0x1
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_RESET_MASK                  _MK_MASK_CONST(0x5fffffff)
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_READ_MASK                   _MK_MASK_CONST(0x5fffffff)
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_INTR_CLR_SHIFT                      _MK_SHIFT_CONST(30)
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_INTR_CLR_FIELD                      _MK_FIELD_CONST(0x1, TKE_BPMP_TIMER_TMR0_TMRSR_0_INTR_CLR_SHIFT)
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_INTR_CLR_RANGE                      30:30
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_INTR_CLR_WOFFSET                    0x0
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_INTR_CLR_DEFAULT                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_INTR_CLR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_INTR_CLR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_INTR_CLR_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define TKE_BPMP_TIMER_TMR0_TMRSR_0_PCV_SHIFT                   _MK_SHIFT_CONST(0)
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_PCV_FIELD                   _MK_FIELD_CONST(0x1fffffff, TKE_BPMP_TIMER_TMR0_TMRSR_0_PCV_SHIFT)
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_PCV_RANGE                   28:0
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_PCV_WOFFSET                 0x0
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_PCV_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_PCV_DEFAULT_MASK                    _MK_MASK_CONST(0x1fffffff)
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_PCV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_PCV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_PCV_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRSR_0_PCV_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register TKE_BPMP_TIMER_TMR0_TMRCSSR_0
#define TKE_BPMP_TIMER_TMR0_TMRCSSR_0                   _MK_ADDR_CONST(0x10008)
#define TKE_BPMP_TIMER_TMR0_TMRCSSR_0_SECURE                    0x0
#define TKE_BPMP_TIMER_TMR0_TMRCSSR_0_DUAL                      0x0
#define TKE_BPMP_TIMER_TMR0_TMRCSSR_0_SCR                       TMRSCR0_0
#define TKE_BPMP_TIMER_TMR0_TMRCSSR_0_WORD_COUNT                        0x1
#define TKE_BPMP_TIMER_TMR0_TMRCSSR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRCSSR_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define TKE_BPMP_TIMER_TMR0_TMRCSSR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRCSSR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRCSSR_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define TKE_BPMP_TIMER_TMR0_TMRCSSR_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define TKE_BPMP_TIMER_TMR0_TMRCSSR_0_SRC_ID_SHIFT                      _MK_SHIFT_CONST(0)
#define TKE_BPMP_TIMER_TMR0_TMRCSSR_0_SRC_ID_FIELD                      _MK_FIELD_CONST(0x3, TKE_BPMP_TIMER_TMR0_TMRCSSR_0_SRC_ID_SHIFT)
#define TKE_BPMP_TIMER_TMR0_TMRCSSR_0_SRC_ID_RANGE                      1:0
#define TKE_BPMP_TIMER_TMR0_TMRCSSR_0_SRC_ID_WOFFSET                    0x0
#define TKE_BPMP_TIMER_TMR0_TMRCSSR_0_SRC_ID_DEFAULT                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRCSSR_0_SRC_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define TKE_BPMP_TIMER_TMR0_TMRCSSR_0_SRC_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define TKE_BPMP_TIMER_TMR0_TMRCSSR_0_SRC_ID_SRC_USECCNT                        _MK_ENUM_CONST(0)
#define TKE_BPMP_TIMER_TMR0_TMRCSSR_0_SRC_ID_SRC_OSCCNT                 _MK_ENUM_CONST(1)
#define TKE_BPMP_TIMER_TMR0_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                    _MK_ENUM_CONST(2)
#define TKE_BPMP_TIMER_TMR0_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                   _MK_ENUM_CONST(3)


// Register TKE_BPMP_TIMER_TMR0_TMRATR_0
#define TKE_BPMP_TIMER_TMR0_TMRATR_0                    _MK_ADDR_CONST(0x1000c)
#define TKE_BPMP_TIMER_TMR0_TMRATR_0_SECURE                     0x0
#define TKE_BPMP_TIMER_TMR0_TMRATR_0_DUAL                       0x0
#define TKE_BPMP_TIMER_TMR0_TMRATR_0_SCR                        TMRSCR0_0
#define TKE_BPMP_TIMER_TMR0_TMRATR_0_WORD_COUNT                         0x1
#define TKE_BPMP_TIMER_TMR0_TMRATR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRATR_0_RESET_MASK                         _MK_MASK_CONST(0x3fffffff)
#define TKE_BPMP_TIMER_TMR0_TMRATR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRATR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRATR_0_READ_MASK                  _MK_MASK_CONST(0x3fffffff)
#define TKE_BPMP_TIMER_TMR0_TMRATR_0_WRITE_MASK                         _MK_MASK_CONST(0x3fffffff)
#define TKE_BPMP_TIMER_TMR0_TMRATR_0_TARGET_SHIFT                       _MK_SHIFT_CONST(0)
#define TKE_BPMP_TIMER_TMR0_TMRATR_0_TARGET_FIELD                       _MK_FIELD_CONST(0x3fffffff, TKE_BPMP_TIMER_TMR0_TMRATR_0_TARGET_SHIFT)
#define TKE_BPMP_TIMER_TMR0_TMRATR_0_TARGET_RANGE                       29:0
#define TKE_BPMP_TIMER_TMR0_TMRATR_0_TARGET_WOFFSET                     0x0
#define TKE_BPMP_TIMER_TMR0_TMRATR_0_TARGET_DEFAULT                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRATR_0_TARGET_DEFAULT_MASK                        _MK_MASK_CONST(0x3fffffff)
#define TKE_BPMP_TIMER_TMR0_TMRATR_0_TARGET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRATR_0_TARGET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRATR_0_TARGET_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR0_TMRATR_0_TARGET_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register TKE_BPMP_TIMER_TMR1_TMRCR_0
#define TKE_BPMP_TIMER_TMR1_TMRCR_0                     _MK_ADDR_CONST(0x20000)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_SECURE                      0x0
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_DUAL                        0x0
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_SCR                         TMRSCR1_0
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_WORD_COUNT                  0x1
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_RESET_VAL                   _MK_MASK_CONST(0x40000000)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_RESET_MASK                  _MK_MASK_CONST(0xdfffffff)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_READ_MASK                   _MK_MASK_CONST(0xdfffffff)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_WRITE_MASK                  _MK_MASK_CONST(0xdfffffff)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_EN_SHIFT                    _MK_SHIFT_CONST(31)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_EN_FIELD                    _MK_FIELD_CONST(0x1, TKE_BPMP_TIMER_TMR1_TMRCR_0_EN_SHIFT)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_EN_RANGE                    31:31
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_EN_WOFFSET                  0x0
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define TKE_BPMP_TIMER_TMR1_TMRCR_0_PER_SHIFT                   _MK_SHIFT_CONST(30)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_PER_FIELD                   _MK_FIELD_CONST(0x1, TKE_BPMP_TIMER_TMR1_TMRCR_0_PER_SHIFT)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_PER_RANGE                   30:30
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_PER_WOFFSET                 0x0
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_PER_DEFAULT                 _MK_MASK_CONST(0x1)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_PER_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_PER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_PER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_PER_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_PER_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define TKE_BPMP_TIMER_TMR1_TMRCR_0_PTV_SHIFT                   _MK_SHIFT_CONST(0)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_PTV_FIELD                   _MK_FIELD_CONST(0x1fffffff, TKE_BPMP_TIMER_TMR1_TMRCR_0_PTV_SHIFT)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_PTV_RANGE                   28:0
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_PTV_WOFFSET                 0x0
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_PTV_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_PTV_DEFAULT_MASK                    _MK_MASK_CONST(0x1fffffff)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_PTV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_PTV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_PTV_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRCR_0_PTV_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register TKE_BPMP_TIMER_TMR1_TMRSR_0
#define TKE_BPMP_TIMER_TMR1_TMRSR_0                     _MK_ADDR_CONST(0x20004)
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_SECURE                      0x0
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_DUAL                        0x0
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_SCR                         TMRSCR1_0
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_WORD_COUNT                  0x1
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_RESET_MASK                  _MK_MASK_CONST(0x5fffffff)
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_READ_MASK                   _MK_MASK_CONST(0x5fffffff)
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_INTR_CLR_SHIFT                      _MK_SHIFT_CONST(30)
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_INTR_CLR_FIELD                      _MK_FIELD_CONST(0x1, TKE_BPMP_TIMER_TMR1_TMRSR_0_INTR_CLR_SHIFT)
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_INTR_CLR_RANGE                      30:30
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_INTR_CLR_WOFFSET                    0x0
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_INTR_CLR_DEFAULT                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_INTR_CLR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_INTR_CLR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_INTR_CLR_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define TKE_BPMP_TIMER_TMR1_TMRSR_0_PCV_SHIFT                   _MK_SHIFT_CONST(0)
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_PCV_FIELD                   _MK_FIELD_CONST(0x1fffffff, TKE_BPMP_TIMER_TMR1_TMRSR_0_PCV_SHIFT)
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_PCV_RANGE                   28:0
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_PCV_WOFFSET                 0x0
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_PCV_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_PCV_DEFAULT_MASK                    _MK_MASK_CONST(0x1fffffff)
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_PCV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_PCV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_PCV_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRSR_0_PCV_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register TKE_BPMP_TIMER_TMR1_TMRCSSR_0
#define TKE_BPMP_TIMER_TMR1_TMRCSSR_0                   _MK_ADDR_CONST(0x20008)
#define TKE_BPMP_TIMER_TMR1_TMRCSSR_0_SECURE                    0x0
#define TKE_BPMP_TIMER_TMR1_TMRCSSR_0_DUAL                      0x0
#define TKE_BPMP_TIMER_TMR1_TMRCSSR_0_SCR                       TMRSCR1_0
#define TKE_BPMP_TIMER_TMR1_TMRCSSR_0_WORD_COUNT                        0x1
#define TKE_BPMP_TIMER_TMR1_TMRCSSR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRCSSR_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define TKE_BPMP_TIMER_TMR1_TMRCSSR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRCSSR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRCSSR_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define TKE_BPMP_TIMER_TMR1_TMRCSSR_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define TKE_BPMP_TIMER_TMR1_TMRCSSR_0_SRC_ID_SHIFT                      _MK_SHIFT_CONST(0)
#define TKE_BPMP_TIMER_TMR1_TMRCSSR_0_SRC_ID_FIELD                      _MK_FIELD_CONST(0x3, TKE_BPMP_TIMER_TMR1_TMRCSSR_0_SRC_ID_SHIFT)
#define TKE_BPMP_TIMER_TMR1_TMRCSSR_0_SRC_ID_RANGE                      1:0
#define TKE_BPMP_TIMER_TMR1_TMRCSSR_0_SRC_ID_WOFFSET                    0x0
#define TKE_BPMP_TIMER_TMR1_TMRCSSR_0_SRC_ID_DEFAULT                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRCSSR_0_SRC_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define TKE_BPMP_TIMER_TMR1_TMRCSSR_0_SRC_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define TKE_BPMP_TIMER_TMR1_TMRCSSR_0_SRC_ID_SRC_USECCNT                        _MK_ENUM_CONST(0)
#define TKE_BPMP_TIMER_TMR1_TMRCSSR_0_SRC_ID_SRC_OSCCNT                 _MK_ENUM_CONST(1)
#define TKE_BPMP_TIMER_TMR1_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                    _MK_ENUM_CONST(2)
#define TKE_BPMP_TIMER_TMR1_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                   _MK_ENUM_CONST(3)


// Register TKE_BPMP_TIMER_TMR1_TMRATR_0
#define TKE_BPMP_TIMER_TMR1_TMRATR_0                    _MK_ADDR_CONST(0x2000c)
#define TKE_BPMP_TIMER_TMR1_TMRATR_0_SECURE                     0x0
#define TKE_BPMP_TIMER_TMR1_TMRATR_0_DUAL                       0x0
#define TKE_BPMP_TIMER_TMR1_TMRATR_0_SCR                        TMRSCR1_0
#define TKE_BPMP_TIMER_TMR1_TMRATR_0_WORD_COUNT                         0x1
#define TKE_BPMP_TIMER_TMR1_TMRATR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRATR_0_RESET_MASK                         _MK_MASK_CONST(0x3fffffff)
#define TKE_BPMP_TIMER_TMR1_TMRATR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRATR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRATR_0_READ_MASK                  _MK_MASK_CONST(0x3fffffff)
#define TKE_BPMP_TIMER_TMR1_TMRATR_0_WRITE_MASK                         _MK_MASK_CONST(0x3fffffff)
#define TKE_BPMP_TIMER_TMR1_TMRATR_0_TARGET_SHIFT                       _MK_SHIFT_CONST(0)
#define TKE_BPMP_TIMER_TMR1_TMRATR_0_TARGET_FIELD                       _MK_FIELD_CONST(0x3fffffff, TKE_BPMP_TIMER_TMR1_TMRATR_0_TARGET_SHIFT)
#define TKE_BPMP_TIMER_TMR1_TMRATR_0_TARGET_RANGE                       29:0
#define TKE_BPMP_TIMER_TMR1_TMRATR_0_TARGET_WOFFSET                     0x0
#define TKE_BPMP_TIMER_TMR1_TMRATR_0_TARGET_DEFAULT                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRATR_0_TARGET_DEFAULT_MASK                        _MK_MASK_CONST(0x3fffffff)
#define TKE_BPMP_TIMER_TMR1_TMRATR_0_TARGET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRATR_0_TARGET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRATR_0_TARGET_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR1_TMRATR_0_TARGET_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register TKE_BPMP_TIMER_TMR2_TMRCR_0
#define TKE_BPMP_TIMER_TMR2_TMRCR_0                     _MK_ADDR_CONST(0x30000)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_SECURE                      0x0
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_DUAL                        0x0
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_SCR                         TMRSCR2_0
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_WORD_COUNT                  0x1
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_RESET_VAL                   _MK_MASK_CONST(0x40000000)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_RESET_MASK                  _MK_MASK_CONST(0xdfffffff)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_READ_MASK                   _MK_MASK_CONST(0xdfffffff)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_WRITE_MASK                  _MK_MASK_CONST(0xdfffffff)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_EN_SHIFT                    _MK_SHIFT_CONST(31)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_EN_FIELD                    _MK_FIELD_CONST(0x1, TKE_BPMP_TIMER_TMR2_TMRCR_0_EN_SHIFT)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_EN_RANGE                    31:31
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_EN_WOFFSET                  0x0
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define TKE_BPMP_TIMER_TMR2_TMRCR_0_PER_SHIFT                   _MK_SHIFT_CONST(30)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_PER_FIELD                   _MK_FIELD_CONST(0x1, TKE_BPMP_TIMER_TMR2_TMRCR_0_PER_SHIFT)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_PER_RANGE                   30:30
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_PER_WOFFSET                 0x0
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_PER_DEFAULT                 _MK_MASK_CONST(0x1)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_PER_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_PER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_PER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_PER_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_PER_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define TKE_BPMP_TIMER_TMR2_TMRCR_0_PTV_SHIFT                   _MK_SHIFT_CONST(0)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_PTV_FIELD                   _MK_FIELD_CONST(0x1fffffff, TKE_BPMP_TIMER_TMR2_TMRCR_0_PTV_SHIFT)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_PTV_RANGE                   28:0
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_PTV_WOFFSET                 0x0
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_PTV_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_PTV_DEFAULT_MASK                    _MK_MASK_CONST(0x1fffffff)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_PTV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_PTV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_PTV_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRCR_0_PTV_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register TKE_BPMP_TIMER_TMR2_TMRSR_0
#define TKE_BPMP_TIMER_TMR2_TMRSR_0                     _MK_ADDR_CONST(0x30004)
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_SECURE                      0x0
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_DUAL                        0x0
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_SCR                         TMRSCR2_0
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_WORD_COUNT                  0x1
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_RESET_MASK                  _MK_MASK_CONST(0x5fffffff)
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_READ_MASK                   _MK_MASK_CONST(0x5fffffff)
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_INTR_CLR_SHIFT                      _MK_SHIFT_CONST(30)
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_INTR_CLR_FIELD                      _MK_FIELD_CONST(0x1, TKE_BPMP_TIMER_TMR2_TMRSR_0_INTR_CLR_SHIFT)
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_INTR_CLR_RANGE                      30:30
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_INTR_CLR_WOFFSET                    0x0
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_INTR_CLR_DEFAULT                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_INTR_CLR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_INTR_CLR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_INTR_CLR_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define TKE_BPMP_TIMER_TMR2_TMRSR_0_PCV_SHIFT                   _MK_SHIFT_CONST(0)
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_PCV_FIELD                   _MK_FIELD_CONST(0x1fffffff, TKE_BPMP_TIMER_TMR2_TMRSR_0_PCV_SHIFT)
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_PCV_RANGE                   28:0
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_PCV_WOFFSET                 0x0
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_PCV_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_PCV_DEFAULT_MASK                    _MK_MASK_CONST(0x1fffffff)
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_PCV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_PCV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_PCV_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRSR_0_PCV_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register TKE_BPMP_TIMER_TMR2_TMRCSSR_0
#define TKE_BPMP_TIMER_TMR2_TMRCSSR_0                   _MK_ADDR_CONST(0x30008)
#define TKE_BPMP_TIMER_TMR2_TMRCSSR_0_SECURE                    0x0
#define TKE_BPMP_TIMER_TMR2_TMRCSSR_0_DUAL                      0x0
#define TKE_BPMP_TIMER_TMR2_TMRCSSR_0_SCR                       TMRSCR2_0
#define TKE_BPMP_TIMER_TMR2_TMRCSSR_0_WORD_COUNT                        0x1
#define TKE_BPMP_TIMER_TMR2_TMRCSSR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRCSSR_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define TKE_BPMP_TIMER_TMR2_TMRCSSR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRCSSR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRCSSR_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define TKE_BPMP_TIMER_TMR2_TMRCSSR_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define TKE_BPMP_TIMER_TMR2_TMRCSSR_0_SRC_ID_SHIFT                      _MK_SHIFT_CONST(0)
#define TKE_BPMP_TIMER_TMR2_TMRCSSR_0_SRC_ID_FIELD                      _MK_FIELD_CONST(0x3, TKE_BPMP_TIMER_TMR2_TMRCSSR_0_SRC_ID_SHIFT)
#define TKE_BPMP_TIMER_TMR2_TMRCSSR_0_SRC_ID_RANGE                      1:0
#define TKE_BPMP_TIMER_TMR2_TMRCSSR_0_SRC_ID_WOFFSET                    0x0
#define TKE_BPMP_TIMER_TMR2_TMRCSSR_0_SRC_ID_DEFAULT                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRCSSR_0_SRC_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define TKE_BPMP_TIMER_TMR2_TMRCSSR_0_SRC_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define TKE_BPMP_TIMER_TMR2_TMRCSSR_0_SRC_ID_SRC_USECCNT                        _MK_ENUM_CONST(0)
#define TKE_BPMP_TIMER_TMR2_TMRCSSR_0_SRC_ID_SRC_OSCCNT                 _MK_ENUM_CONST(1)
#define TKE_BPMP_TIMER_TMR2_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                    _MK_ENUM_CONST(2)
#define TKE_BPMP_TIMER_TMR2_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                   _MK_ENUM_CONST(3)


// Register TKE_BPMP_TIMER_TMR2_TMRATR_0
#define TKE_BPMP_TIMER_TMR2_TMRATR_0                    _MK_ADDR_CONST(0x3000c)
#define TKE_BPMP_TIMER_TMR2_TMRATR_0_SECURE                     0x0
#define TKE_BPMP_TIMER_TMR2_TMRATR_0_DUAL                       0x0
#define TKE_BPMP_TIMER_TMR2_TMRATR_0_SCR                        TMRSCR2_0
#define TKE_BPMP_TIMER_TMR2_TMRATR_0_WORD_COUNT                         0x1
#define TKE_BPMP_TIMER_TMR2_TMRATR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRATR_0_RESET_MASK                         _MK_MASK_CONST(0x3fffffff)
#define TKE_BPMP_TIMER_TMR2_TMRATR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRATR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRATR_0_READ_MASK                  _MK_MASK_CONST(0x3fffffff)
#define TKE_BPMP_TIMER_TMR2_TMRATR_0_WRITE_MASK                         _MK_MASK_CONST(0x3fffffff)
#define TKE_BPMP_TIMER_TMR2_TMRATR_0_TARGET_SHIFT                       _MK_SHIFT_CONST(0)
#define TKE_BPMP_TIMER_TMR2_TMRATR_0_TARGET_FIELD                       _MK_FIELD_CONST(0x3fffffff, TKE_BPMP_TIMER_TMR2_TMRATR_0_TARGET_SHIFT)
#define TKE_BPMP_TIMER_TMR2_TMRATR_0_TARGET_RANGE                       29:0
#define TKE_BPMP_TIMER_TMR2_TMRATR_0_TARGET_WOFFSET                     0x0
#define TKE_BPMP_TIMER_TMR2_TMRATR_0_TARGET_DEFAULT                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRATR_0_TARGET_DEFAULT_MASK                        _MK_MASK_CONST(0x3fffffff)
#define TKE_BPMP_TIMER_TMR2_TMRATR_0_TARGET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRATR_0_TARGET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRATR_0_TARGET_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR2_TMRATR_0_TARGET_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register TKE_BPMP_TIMER_TMR3_TMRCR_0
#define TKE_BPMP_TIMER_TMR3_TMRCR_0                     _MK_ADDR_CONST(0x40000)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_SECURE                      0x0
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_DUAL                        0x0
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_SCR                         TMRSCR3_0
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_WORD_COUNT                  0x1
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_RESET_VAL                   _MK_MASK_CONST(0x40000000)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_RESET_MASK                  _MK_MASK_CONST(0xdfffffff)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_READ_MASK                   _MK_MASK_CONST(0xdfffffff)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_WRITE_MASK                  _MK_MASK_CONST(0xdfffffff)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_EN_SHIFT                    _MK_SHIFT_CONST(31)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_EN_FIELD                    _MK_FIELD_CONST(0x1, TKE_BPMP_TIMER_TMR3_TMRCR_0_EN_SHIFT)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_EN_RANGE                    31:31
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_EN_WOFFSET                  0x0
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define TKE_BPMP_TIMER_TMR3_TMRCR_0_PER_SHIFT                   _MK_SHIFT_CONST(30)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_PER_FIELD                   _MK_FIELD_CONST(0x1, TKE_BPMP_TIMER_TMR3_TMRCR_0_PER_SHIFT)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_PER_RANGE                   30:30
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_PER_WOFFSET                 0x0
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_PER_DEFAULT                 _MK_MASK_CONST(0x1)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_PER_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_PER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_PER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_PER_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_PER_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define TKE_BPMP_TIMER_TMR3_TMRCR_0_PTV_SHIFT                   _MK_SHIFT_CONST(0)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_PTV_FIELD                   _MK_FIELD_CONST(0x1fffffff, TKE_BPMP_TIMER_TMR3_TMRCR_0_PTV_SHIFT)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_PTV_RANGE                   28:0
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_PTV_WOFFSET                 0x0
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_PTV_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_PTV_DEFAULT_MASK                    _MK_MASK_CONST(0x1fffffff)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_PTV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_PTV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_PTV_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRCR_0_PTV_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register TKE_BPMP_TIMER_TMR3_TMRSR_0
#define TKE_BPMP_TIMER_TMR3_TMRSR_0                     _MK_ADDR_CONST(0x40004)
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_SECURE                      0x0
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_DUAL                        0x0
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_SCR                         TMRSCR3_0
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_WORD_COUNT                  0x1
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_RESET_MASK                  _MK_MASK_CONST(0x5fffffff)
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_READ_MASK                   _MK_MASK_CONST(0x5fffffff)
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_INTR_CLR_SHIFT                      _MK_SHIFT_CONST(30)
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_INTR_CLR_FIELD                      _MK_FIELD_CONST(0x1, TKE_BPMP_TIMER_TMR3_TMRSR_0_INTR_CLR_SHIFT)
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_INTR_CLR_RANGE                      30:30
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_INTR_CLR_WOFFSET                    0x0
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_INTR_CLR_DEFAULT                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_INTR_CLR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_INTR_CLR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_INTR_CLR_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define TKE_BPMP_TIMER_TMR3_TMRSR_0_PCV_SHIFT                   _MK_SHIFT_CONST(0)
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_PCV_FIELD                   _MK_FIELD_CONST(0x1fffffff, TKE_BPMP_TIMER_TMR3_TMRSR_0_PCV_SHIFT)
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_PCV_RANGE                   28:0
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_PCV_WOFFSET                 0x0
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_PCV_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_PCV_DEFAULT_MASK                    _MK_MASK_CONST(0x1fffffff)
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_PCV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_PCV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_PCV_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRSR_0_PCV_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register TKE_BPMP_TIMER_TMR3_TMRCSSR_0
#define TKE_BPMP_TIMER_TMR3_TMRCSSR_0                   _MK_ADDR_CONST(0x40008)
#define TKE_BPMP_TIMER_TMR3_TMRCSSR_0_SECURE                    0x0
#define TKE_BPMP_TIMER_TMR3_TMRCSSR_0_DUAL                      0x0
#define TKE_BPMP_TIMER_TMR3_TMRCSSR_0_SCR                       TMRSCR3_0
#define TKE_BPMP_TIMER_TMR3_TMRCSSR_0_WORD_COUNT                        0x1
#define TKE_BPMP_TIMER_TMR3_TMRCSSR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRCSSR_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define TKE_BPMP_TIMER_TMR3_TMRCSSR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRCSSR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRCSSR_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define TKE_BPMP_TIMER_TMR3_TMRCSSR_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define TKE_BPMP_TIMER_TMR3_TMRCSSR_0_SRC_ID_SHIFT                      _MK_SHIFT_CONST(0)
#define TKE_BPMP_TIMER_TMR3_TMRCSSR_0_SRC_ID_FIELD                      _MK_FIELD_CONST(0x3, TKE_BPMP_TIMER_TMR3_TMRCSSR_0_SRC_ID_SHIFT)
#define TKE_BPMP_TIMER_TMR3_TMRCSSR_0_SRC_ID_RANGE                      1:0
#define TKE_BPMP_TIMER_TMR3_TMRCSSR_0_SRC_ID_WOFFSET                    0x0
#define TKE_BPMP_TIMER_TMR3_TMRCSSR_0_SRC_ID_DEFAULT                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRCSSR_0_SRC_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define TKE_BPMP_TIMER_TMR3_TMRCSSR_0_SRC_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define TKE_BPMP_TIMER_TMR3_TMRCSSR_0_SRC_ID_SRC_USECCNT                        _MK_ENUM_CONST(0)
#define TKE_BPMP_TIMER_TMR3_TMRCSSR_0_SRC_ID_SRC_OSCCNT                 _MK_ENUM_CONST(1)
#define TKE_BPMP_TIMER_TMR3_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                    _MK_ENUM_CONST(2)
#define TKE_BPMP_TIMER_TMR3_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                   _MK_ENUM_CONST(3)


// Register TKE_BPMP_TIMER_TMR3_TMRATR_0
#define TKE_BPMP_TIMER_TMR3_TMRATR_0                    _MK_ADDR_CONST(0x4000c)
#define TKE_BPMP_TIMER_TMR3_TMRATR_0_SECURE                     0x0
#define TKE_BPMP_TIMER_TMR3_TMRATR_0_DUAL                       0x0
#define TKE_BPMP_TIMER_TMR3_TMRATR_0_SCR                        TMRSCR3_0
#define TKE_BPMP_TIMER_TMR3_TMRATR_0_WORD_COUNT                         0x1
#define TKE_BPMP_TIMER_TMR3_TMRATR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRATR_0_RESET_MASK                         _MK_MASK_CONST(0x3fffffff)
#define TKE_BPMP_TIMER_TMR3_TMRATR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRATR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRATR_0_READ_MASK                  _MK_MASK_CONST(0x3fffffff)
#define TKE_BPMP_TIMER_TMR3_TMRATR_0_WRITE_MASK                         _MK_MASK_CONST(0x3fffffff)
#define TKE_BPMP_TIMER_TMR3_TMRATR_0_TARGET_SHIFT                       _MK_SHIFT_CONST(0)
#define TKE_BPMP_TIMER_TMR3_TMRATR_0_TARGET_FIELD                       _MK_FIELD_CONST(0x3fffffff, TKE_BPMP_TIMER_TMR3_TMRATR_0_TARGET_SHIFT)
#define TKE_BPMP_TIMER_TMR3_TMRATR_0_TARGET_RANGE                       29:0
#define TKE_BPMP_TIMER_TMR3_TMRATR_0_TARGET_WOFFSET                     0x0
#define TKE_BPMP_TIMER_TMR3_TMRATR_0_TARGET_DEFAULT                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRATR_0_TARGET_DEFAULT_MASK                        _MK_MASK_CONST(0x3fffffff)
#define TKE_BPMP_TIMER_TMR3_TMRATR_0_TARGET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRATR_0_TARGET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRATR_0_TARGET_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_TIMER_TMR3_TMRATR_0_TARGET_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register TKE_BPMP_WDT0_WDTCR_0
#define TKE_BPMP_WDT0_WDTCR_0                   _MK_ADDR_CONST(0x50000)
#define TKE_BPMP_WDT0_WDTCR_0_SECURE                    0x0
#define TKE_BPMP_WDT0_WDTCR_0_DUAL                      0x0
#define TKE_BPMP_WDT0_WDTCR_0_SCR                       WDTSCR0_0
#define TKE_BPMP_WDT0_WDTCR_0_WORD_COUNT                        0x1
#define TKE_BPMP_WDT0_WDTCR_0_RESET_VAL                         _MK_MASK_CONST(0x700000)
#define TKE_BPMP_WDT0_WDTCR_0_RESET_MASK                        _MK_MASK_CONST(0xf3ffffff)
#define TKE_BPMP_WDT0_WDTCR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_READ_MASK                         _MK_MASK_CONST(0xf3ffffff)
#define TKE_BPMP_WDT0_WDTCR_0_WRITE_MASK                        _MK_MASK_CONST(0xf3ffffff)
#define TKE_BPMP_WDT0_WDTCR_0_TimerSource_SHIFT                 _MK_SHIFT_CONST(0)
#define TKE_BPMP_WDT0_WDTCR_0_TimerSource_FIELD                 _MK_FIELD_CONST(0xf, TKE_BPMP_WDT0_WDTCR_0_TimerSource_SHIFT)
#define TKE_BPMP_WDT0_WDTCR_0_TimerSource_RANGE                 3:0
#define TKE_BPMP_WDT0_WDTCR_0_TimerSource_WOFFSET                       0x0
#define TKE_BPMP_WDT0_WDTCR_0_TimerSource_DEFAULT                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_TimerSource_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define TKE_BPMP_WDT0_WDTCR_0_TimerSource_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_TimerSource_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_TimerSource_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_TimerSource_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTCR_0_Period_SHIFT                      _MK_SHIFT_CONST(4)
#define TKE_BPMP_WDT0_WDTCR_0_Period_FIELD                      _MK_FIELD_CONST(0xff, TKE_BPMP_WDT0_WDTCR_0_Period_SHIFT)
#define TKE_BPMP_WDT0_WDTCR_0_Period_RANGE                      11:4
#define TKE_BPMP_WDT0_WDTCR_0_Period_WOFFSET                    0x0
#define TKE_BPMP_WDT0_WDTCR_0_Period_DEFAULT                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_Period_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define TKE_BPMP_WDT0_WDTCR_0_Period_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_Period_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_Period_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_Period_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTCR_0_LocalInterruptEnable_SHIFT                        _MK_SHIFT_CONST(12)
#define TKE_BPMP_WDT0_WDTCR_0_LocalInterruptEnable_FIELD                        _MK_FIELD_CONST(0x1, TKE_BPMP_WDT0_WDTCR_0_LocalInterruptEnable_SHIFT)
#define TKE_BPMP_WDT0_WDTCR_0_LocalInterruptEnable_RANGE                        12:12
#define TKE_BPMP_WDT0_WDTCR_0_LocalInterruptEnable_WOFFSET                      0x0
#define TKE_BPMP_WDT0_WDTCR_0_LocalInterruptEnable_DEFAULT                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_LocalInterruptEnable_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define TKE_BPMP_WDT0_WDTCR_0_LocalInterruptEnable_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_LocalInterruptEnable_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_LocalInterruptEnable_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_LocalInterruptEnable_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTCR_0_LocalFIQEnable_SHIFT                      _MK_SHIFT_CONST(13)
#define TKE_BPMP_WDT0_WDTCR_0_LocalFIQEnable_FIELD                      _MK_FIELD_CONST(0x1, TKE_BPMP_WDT0_WDTCR_0_LocalFIQEnable_SHIFT)
#define TKE_BPMP_WDT0_WDTCR_0_LocalFIQEnable_RANGE                      13:13
#define TKE_BPMP_WDT0_WDTCR_0_LocalFIQEnable_WOFFSET                    0x0
#define TKE_BPMP_WDT0_WDTCR_0_LocalFIQEnable_DEFAULT                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_LocalFIQEnable_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define TKE_BPMP_WDT0_WDTCR_0_LocalFIQEnable_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_LocalFIQEnable_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_LocalFIQEnable_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_LocalFIQEnable_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTCR_0_RemoteInterruptEnable_SHIFT                       _MK_SHIFT_CONST(14)
#define TKE_BPMP_WDT0_WDTCR_0_RemoteInterruptEnable_FIELD                       _MK_FIELD_CONST(0x1, TKE_BPMP_WDT0_WDTCR_0_RemoteInterruptEnable_SHIFT)
#define TKE_BPMP_WDT0_WDTCR_0_RemoteInterruptEnable_RANGE                       14:14
#define TKE_BPMP_WDT0_WDTCR_0_RemoteInterruptEnable_WOFFSET                     0x0
#define TKE_BPMP_WDT0_WDTCR_0_RemoteInterruptEnable_DEFAULT                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_RemoteInterruptEnable_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define TKE_BPMP_WDT0_WDTCR_0_RemoteInterruptEnable_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_RemoteInterruptEnable_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_RemoteInterruptEnable_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_RemoteInterruptEnable_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTCR_0_SystemDebugResetEnable_SHIFT                      _MK_SHIFT_CONST(15)
#define TKE_BPMP_WDT0_WDTCR_0_SystemDebugResetEnable_FIELD                      _MK_FIELD_CONST(0x1, TKE_BPMP_WDT0_WDTCR_0_SystemDebugResetEnable_SHIFT)
#define TKE_BPMP_WDT0_WDTCR_0_SystemDebugResetEnable_RANGE                      15:15
#define TKE_BPMP_WDT0_WDTCR_0_SystemDebugResetEnable_WOFFSET                    0x0
#define TKE_BPMP_WDT0_WDTCR_0_SystemDebugResetEnable_DEFAULT                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_SystemDebugResetEnable_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define TKE_BPMP_WDT0_WDTCR_0_SystemDebugResetEnable_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_SystemDebugResetEnable_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_SystemDebugResetEnable_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_SystemDebugResetEnable_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTCR_0_SystemPOResetEnable_SHIFT                 _MK_SHIFT_CONST(16)
#define TKE_BPMP_WDT0_WDTCR_0_SystemPOResetEnable_FIELD                 _MK_FIELD_CONST(0x1, TKE_BPMP_WDT0_WDTCR_0_SystemPOResetEnable_SHIFT)
#define TKE_BPMP_WDT0_WDTCR_0_SystemPOResetEnable_RANGE                 16:16
#define TKE_BPMP_WDT0_WDTCR_0_SystemPOResetEnable_WOFFSET                       0x0
#define TKE_BPMP_WDT0_WDTCR_0_SystemPOResetEnable_DEFAULT                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_SystemPOResetEnable_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define TKE_BPMP_WDT0_WDTCR_0_SystemPOResetEnable_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_SystemPOResetEnable_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_SystemPOResetEnable_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_SystemPOResetEnable_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTCR_0_WindowedOperationEnable_SHIFT                     _MK_SHIFT_CONST(17)
#define TKE_BPMP_WDT0_WDTCR_0_WindowedOperationEnable_FIELD                     _MK_FIELD_CONST(0x1, TKE_BPMP_WDT0_WDTCR_0_WindowedOperationEnable_SHIFT)
#define TKE_BPMP_WDT0_WDTCR_0_WindowedOperationEnable_RANGE                     17:17
#define TKE_BPMP_WDT0_WDTCR_0_WindowedOperationEnable_WOFFSET                   0x0
#define TKE_BPMP_WDT0_WDTCR_0_WindowedOperationEnable_DEFAULT                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_WindowedOperationEnable_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define TKE_BPMP_WDT0_WDTCR_0_WindowedOperationEnable_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_WindowedOperationEnable_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_WindowedOperationEnable_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_WindowedOperationEnable_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTCR_0_ChallengeResponseEnable_SHIFT                     _MK_SHIFT_CONST(18)
#define TKE_BPMP_WDT0_WDTCR_0_ChallengeResponseEnable_FIELD                     _MK_FIELD_CONST(0x1, TKE_BPMP_WDT0_WDTCR_0_ChallengeResponseEnable_SHIFT)
#define TKE_BPMP_WDT0_WDTCR_0_ChallengeResponseEnable_RANGE                     18:18
#define TKE_BPMP_WDT0_WDTCR_0_ChallengeResponseEnable_WOFFSET                   0x0
#define TKE_BPMP_WDT0_WDTCR_0_ChallengeResponseEnable_DEFAULT                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_ChallengeResponseEnable_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define TKE_BPMP_WDT0_WDTCR_0_ChallengeResponseEnable_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_ChallengeResponseEnable_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_ChallengeResponseEnable_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_ChallengeResponseEnable_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTCR_0_TscReferenceEnable_SHIFT                  _MK_SHIFT_CONST(19)
#define TKE_BPMP_WDT0_WDTCR_0_TscReferenceEnable_FIELD                  _MK_FIELD_CONST(0x1, TKE_BPMP_WDT0_WDTCR_0_TscReferenceEnable_SHIFT)
#define TKE_BPMP_WDT0_WDTCR_0_TscReferenceEnable_RANGE                  19:19
#define TKE_BPMP_WDT0_WDTCR_0_TscReferenceEnable_WOFFSET                        0x0
#define TKE_BPMP_WDT0_WDTCR_0_TscReferenceEnable_DEFAULT                        _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_TscReferenceEnable_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define TKE_BPMP_WDT0_WDTCR_0_TscReferenceEnable_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_TscReferenceEnable_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_TscReferenceEnable_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_TscReferenceEnable_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTCR_0_ErrorThreshold_SHIFT                      _MK_SHIFT_CONST(20)
#define TKE_BPMP_WDT0_WDTCR_0_ErrorThreshold_FIELD                      _MK_FIELD_CONST(0x7, TKE_BPMP_WDT0_WDTCR_0_ErrorThreshold_SHIFT)
#define TKE_BPMP_WDT0_WDTCR_0_ErrorThreshold_RANGE                      22:20
#define TKE_BPMP_WDT0_WDTCR_0_ErrorThreshold_WOFFSET                    0x0
#define TKE_BPMP_WDT0_WDTCR_0_ErrorThreshold_DEFAULT                    _MK_MASK_CONST(0x7)
#define TKE_BPMP_WDT0_WDTCR_0_ErrorThreshold_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define TKE_BPMP_WDT0_WDTCR_0_ErrorThreshold_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_ErrorThreshold_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_ErrorThreshold_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_ErrorThreshold_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTCR_0_RestartErrorAction_SHIFT                  _MK_SHIFT_CONST(23)
#define TKE_BPMP_WDT0_WDTCR_0_RestartErrorAction_FIELD                  _MK_FIELD_CONST(0x3, TKE_BPMP_WDT0_WDTCR_0_RestartErrorAction_SHIFT)
#define TKE_BPMP_WDT0_WDTCR_0_RestartErrorAction_RANGE                  24:23
#define TKE_BPMP_WDT0_WDTCR_0_RestartErrorAction_WOFFSET                        0x0
#define TKE_BPMP_WDT0_WDTCR_0_RestartErrorAction_DEFAULT                        _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_RestartErrorAction_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define TKE_BPMP_WDT0_WDTCR_0_RestartErrorAction_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_RestartErrorAction_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_RestartErrorAction_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_RestartErrorAction_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define TKE_BPMP_WDT0_WDTCR_0_RestartErrorAction_NOP                    _MK_ENUM_CONST(0)
#define TKE_BPMP_WDT0_WDTCR_0_RestartErrorAction_JUMP_TO_4                      _MK_ENUM_CONST(1)
#define TKE_BPMP_WDT0_WDTCR_0_RestartErrorAction_JUMP_TO_5                      _MK_ENUM_CONST(2)
#define TKE_BPMP_WDT0_WDTCR_0_RestartErrorAction_POR_RESET                      _MK_ENUM_CONST(3)

#define TKE_BPMP_WDT0_WDTCR_0_DisallowWDTFreeze_SHIFT                   _MK_SHIFT_CONST(25)
#define TKE_BPMP_WDT0_WDTCR_0_DisallowWDTFreeze_FIELD                   _MK_FIELD_CONST(0x1, TKE_BPMP_WDT0_WDTCR_0_DisallowWDTFreeze_SHIFT)
#define TKE_BPMP_WDT0_WDTCR_0_DisallowWDTFreeze_RANGE                   25:25
#define TKE_BPMP_WDT0_WDTCR_0_DisallowWDTFreeze_WOFFSET                 0x0
#define TKE_BPMP_WDT0_WDTCR_0_DisallowWDTFreeze_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_DisallowWDTFreeze_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define TKE_BPMP_WDT0_WDTCR_0_DisallowWDTFreeze_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_DisallowWDTFreeze_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_DisallowWDTFreeze_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_DisallowWDTFreeze_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTCR_0_WindowedRestartDisableMap_SHIFT                   _MK_SHIFT_CONST(28)
#define TKE_BPMP_WDT0_WDTCR_0_WindowedRestartDisableMap_FIELD                   _MK_FIELD_CONST(0xf, TKE_BPMP_WDT0_WDTCR_0_WindowedRestartDisableMap_SHIFT)
#define TKE_BPMP_WDT0_WDTCR_0_WindowedRestartDisableMap_RANGE                   31:28
#define TKE_BPMP_WDT0_WDTCR_0_WindowedRestartDisableMap_WOFFSET                 0x0
#define TKE_BPMP_WDT0_WDTCR_0_WindowedRestartDisableMap_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_WindowedRestartDisableMap_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define TKE_BPMP_WDT0_WDTCR_0_WindowedRestartDisableMap_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_WindowedRestartDisableMap_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_WindowedRestartDisableMap_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCR_0_WindowedRestartDisableMap_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register TKE_BPMP_WDT0_WDTSR_0
#define TKE_BPMP_WDT0_WDTSR_0                   _MK_ADDR_CONST(0x50004)
#define TKE_BPMP_WDT0_WDTSR_0_SECURE                    0x0
#define TKE_BPMP_WDT0_WDTSR_0_DUAL                      0x0
#define TKE_BPMP_WDT0_WDTSR_0_SCR                       WDTSCR0_0
#define TKE_BPMP_WDT0_WDTSR_0_WORD_COUNT                        0x1
#define TKE_BPMP_WDT0_WDTSR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_RESET_MASK                        _MK_MASK_CONST(0xf7fff)
#define TKE_BPMP_WDT0_WDTSR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_READ_MASK                         _MK_MASK_CONST(0xf7fff)
#define TKE_BPMP_WDT0_WDTSR_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_Enabled_SHIFT                     _MK_SHIFT_CONST(0)
#define TKE_BPMP_WDT0_WDTSR_0_Enabled_FIELD                     _MK_FIELD_CONST(0x1, TKE_BPMP_WDT0_WDTSR_0_Enabled_SHIFT)
#define TKE_BPMP_WDT0_WDTSR_0_Enabled_RANGE                     0:0
#define TKE_BPMP_WDT0_WDTSR_0_Enabled_WOFFSET                   0x0
#define TKE_BPMP_WDT0_WDTSR_0_Enabled_DEFAULT                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_Enabled_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define TKE_BPMP_WDT0_WDTSR_0_Enabled_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_Enabled_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_Enabled_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_Enabled_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTSR_0_LocalInterruptStatus_SHIFT                        _MK_SHIFT_CONST(1)
#define TKE_BPMP_WDT0_WDTSR_0_LocalInterruptStatus_FIELD                        _MK_FIELD_CONST(0x1, TKE_BPMP_WDT0_WDTSR_0_LocalInterruptStatus_SHIFT)
#define TKE_BPMP_WDT0_WDTSR_0_LocalInterruptStatus_RANGE                        1:1
#define TKE_BPMP_WDT0_WDTSR_0_LocalInterruptStatus_WOFFSET                      0x0
#define TKE_BPMP_WDT0_WDTSR_0_LocalInterruptStatus_DEFAULT                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_LocalInterruptStatus_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define TKE_BPMP_WDT0_WDTSR_0_LocalInterruptStatus_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_LocalInterruptStatus_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_LocalInterruptStatus_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_LocalInterruptStatus_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTSR_0_LocalFIQStatus_SHIFT                      _MK_SHIFT_CONST(2)
#define TKE_BPMP_WDT0_WDTSR_0_LocalFIQStatus_FIELD                      _MK_FIELD_CONST(0x1, TKE_BPMP_WDT0_WDTSR_0_LocalFIQStatus_SHIFT)
#define TKE_BPMP_WDT0_WDTSR_0_LocalFIQStatus_RANGE                      2:2
#define TKE_BPMP_WDT0_WDTSR_0_LocalFIQStatus_WOFFSET                    0x0
#define TKE_BPMP_WDT0_WDTSR_0_LocalFIQStatus_DEFAULT                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_LocalFIQStatus_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define TKE_BPMP_WDT0_WDTSR_0_LocalFIQStatus_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_LocalFIQStatus_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_LocalFIQStatus_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_LocalFIQStatus_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTSR_0_RemoteInterruptStatus_SHIFT                       _MK_SHIFT_CONST(3)
#define TKE_BPMP_WDT0_WDTSR_0_RemoteInterruptStatus_FIELD                       _MK_FIELD_CONST(0x1, TKE_BPMP_WDT0_WDTSR_0_RemoteInterruptStatus_SHIFT)
#define TKE_BPMP_WDT0_WDTSR_0_RemoteInterruptStatus_RANGE                       3:3
#define TKE_BPMP_WDT0_WDTSR_0_RemoteInterruptStatus_WOFFSET                     0x0
#define TKE_BPMP_WDT0_WDTSR_0_RemoteInterruptStatus_DEFAULT                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_RemoteInterruptStatus_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define TKE_BPMP_WDT0_WDTSR_0_RemoteInterruptStatus_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_RemoteInterruptStatus_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_RemoteInterruptStatus_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_RemoteInterruptStatus_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTSR_0_CurrentCount_SHIFT                        _MK_SHIFT_CONST(4)
#define TKE_BPMP_WDT0_WDTSR_0_CurrentCount_FIELD                        _MK_FIELD_CONST(0xff, TKE_BPMP_WDT0_WDTSR_0_CurrentCount_SHIFT)
#define TKE_BPMP_WDT0_WDTSR_0_CurrentCount_RANGE                        11:4
#define TKE_BPMP_WDT0_WDTSR_0_CurrentCount_WOFFSET                      0x0
#define TKE_BPMP_WDT0_WDTSR_0_CurrentCount_DEFAULT                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_CurrentCount_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define TKE_BPMP_WDT0_WDTSR_0_CurrentCount_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_CurrentCount_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_CurrentCount_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_CurrentCount_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTSR_0_CurrentExpirationCount_SHIFT                      _MK_SHIFT_CONST(12)
#define TKE_BPMP_WDT0_WDTSR_0_CurrentExpirationCount_FIELD                      _MK_FIELD_CONST(0x7, TKE_BPMP_WDT0_WDTSR_0_CurrentExpirationCount_SHIFT)
#define TKE_BPMP_WDT0_WDTSR_0_CurrentExpirationCount_RANGE                      14:12
#define TKE_BPMP_WDT0_WDTSR_0_CurrentExpirationCount_WOFFSET                    0x0
#define TKE_BPMP_WDT0_WDTSR_0_CurrentExpirationCount_DEFAULT                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_CurrentExpirationCount_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define TKE_BPMP_WDT0_WDTSR_0_CurrentExpirationCount_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_CurrentExpirationCount_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_CurrentExpirationCount_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_CurrentExpirationCount_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTSR_0_CurrentError_SHIFT                        _MK_SHIFT_CONST(16)
#define TKE_BPMP_WDT0_WDTSR_0_CurrentError_FIELD                        _MK_FIELD_CONST(0x1, TKE_BPMP_WDT0_WDTSR_0_CurrentError_SHIFT)
#define TKE_BPMP_WDT0_WDTSR_0_CurrentError_RANGE                        16:16
#define TKE_BPMP_WDT0_WDTSR_0_CurrentError_WOFFSET                      0x0
#define TKE_BPMP_WDT0_WDTSR_0_CurrentError_DEFAULT                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_CurrentError_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define TKE_BPMP_WDT0_WDTSR_0_CurrentError_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_CurrentError_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_CurrentError_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_CurrentError_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTSR_0_StickyEnabled_SHIFT                       _MK_SHIFT_CONST(17)
#define TKE_BPMP_WDT0_WDTSR_0_StickyEnabled_FIELD                       _MK_FIELD_CONST(0x1, TKE_BPMP_WDT0_WDTSR_0_StickyEnabled_SHIFT)
#define TKE_BPMP_WDT0_WDTSR_0_StickyEnabled_RANGE                       17:17
#define TKE_BPMP_WDT0_WDTSR_0_StickyEnabled_WOFFSET                     0x0
#define TKE_BPMP_WDT0_WDTSR_0_StickyEnabled_DEFAULT                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_StickyEnabled_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define TKE_BPMP_WDT0_WDTSR_0_StickyEnabled_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_StickyEnabled_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_StickyEnabled_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_StickyEnabled_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTSR_0_ErrorForced_SHIFT                 _MK_SHIFT_CONST(18)
#define TKE_BPMP_WDT0_WDTSR_0_ErrorForced_FIELD                 _MK_FIELD_CONST(0x1, TKE_BPMP_WDT0_WDTSR_0_ErrorForced_SHIFT)
#define TKE_BPMP_WDT0_WDTSR_0_ErrorForced_RANGE                 18:18
#define TKE_BPMP_WDT0_WDTSR_0_ErrorForced_WOFFSET                       0x0
#define TKE_BPMP_WDT0_WDTSR_0_ErrorForced_DEFAULT                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_ErrorForced_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define TKE_BPMP_WDT0_WDTSR_0_ErrorForced_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_ErrorForced_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_ErrorForced_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_ErrorForced_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTSR_0_Frozen_SHIFT                      _MK_SHIFT_CONST(19)
#define TKE_BPMP_WDT0_WDTSR_0_Frozen_FIELD                      _MK_FIELD_CONST(0x1, TKE_BPMP_WDT0_WDTSR_0_Frozen_SHIFT)
#define TKE_BPMP_WDT0_WDTSR_0_Frozen_RANGE                      19:19
#define TKE_BPMP_WDT0_WDTSR_0_Frozen_WOFFSET                    0x0
#define TKE_BPMP_WDT0_WDTSR_0_Frozen_DEFAULT                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_Frozen_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define TKE_BPMP_WDT0_WDTSR_0_Frozen_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_Frozen_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_Frozen_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSR_0_Frozen_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register TKE_BPMP_WDT0_WDTCMDR_0
#define TKE_BPMP_WDT0_WDTCMDR_0                 _MK_ADDR_CONST(0x50008)
#define TKE_BPMP_WDT0_WDTCMDR_0_SECURE                  0x0
#define TKE_BPMP_WDT0_WDTCMDR_0_DUAL                    0x0
#define TKE_BPMP_WDT0_WDTCMDR_0_SCR                     WDTSCR0_0
#define TKE_BPMP_WDT0_WDTCMDR_0_WORD_COUNT                      0x1
#define TKE_BPMP_WDT0_WDTCMDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCMDR_0_RESET_MASK                      _MK_MASK_CONST(0xf)
#define TKE_BPMP_WDT0_WDTCMDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCMDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCMDR_0_READ_MASK                       _MK_MASK_CONST(0xf)
#define TKE_BPMP_WDT0_WDTCMDR_0_WRITE_MASK                      _MK_MASK_CONST(0xf)
#define TKE_BPMP_WDT0_WDTCMDR_0_StartCounter_SHIFT                      _MK_SHIFT_CONST(0)
#define TKE_BPMP_WDT0_WDTCMDR_0_StartCounter_FIELD                      _MK_FIELD_CONST(0x1, TKE_BPMP_WDT0_WDTCMDR_0_StartCounter_SHIFT)
#define TKE_BPMP_WDT0_WDTCMDR_0_StartCounter_RANGE                      0:0
#define TKE_BPMP_WDT0_WDTCMDR_0_StartCounter_WOFFSET                    0x0
#define TKE_BPMP_WDT0_WDTCMDR_0_StartCounter_DEFAULT                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCMDR_0_StartCounter_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define TKE_BPMP_WDT0_WDTCMDR_0_StartCounter_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCMDR_0_StartCounter_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCMDR_0_StartCounter_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCMDR_0_StartCounter_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTCMDR_0_DisableCounter_SHIFT                    _MK_SHIFT_CONST(1)
#define TKE_BPMP_WDT0_WDTCMDR_0_DisableCounter_FIELD                    _MK_FIELD_CONST(0x1, TKE_BPMP_WDT0_WDTCMDR_0_DisableCounter_SHIFT)
#define TKE_BPMP_WDT0_WDTCMDR_0_DisableCounter_RANGE                    1:1
#define TKE_BPMP_WDT0_WDTCMDR_0_DisableCounter_WOFFSET                  0x0
#define TKE_BPMP_WDT0_WDTCMDR_0_DisableCounter_DEFAULT                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCMDR_0_DisableCounter_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define TKE_BPMP_WDT0_WDTCMDR_0_DisableCounter_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCMDR_0_DisableCounter_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCMDR_0_DisableCounter_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCMDR_0_DisableCounter_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTCMDR_0_StickyStart_SHIFT                       _MK_SHIFT_CONST(2)
#define TKE_BPMP_WDT0_WDTCMDR_0_StickyStart_FIELD                       _MK_FIELD_CONST(0x1, TKE_BPMP_WDT0_WDTCMDR_0_StickyStart_SHIFT)
#define TKE_BPMP_WDT0_WDTCMDR_0_StickyStart_RANGE                       2:2
#define TKE_BPMP_WDT0_WDTCMDR_0_StickyStart_WOFFSET                     0x0
#define TKE_BPMP_WDT0_WDTCMDR_0_StickyStart_DEFAULT                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCMDR_0_StickyStart_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define TKE_BPMP_WDT0_WDTCMDR_0_StickyStart_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCMDR_0_StickyStart_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCMDR_0_StickyStart_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCMDR_0_StickyStart_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTCMDR_0_ForceError_SHIFT                        _MK_SHIFT_CONST(3)
#define TKE_BPMP_WDT0_WDTCMDR_0_ForceError_FIELD                        _MK_FIELD_CONST(0x1, TKE_BPMP_WDT0_WDTCMDR_0_ForceError_SHIFT)
#define TKE_BPMP_WDT0_WDTCMDR_0_ForceError_RANGE                        3:3
#define TKE_BPMP_WDT0_WDTCMDR_0_ForceError_WOFFSET                      0x0
#define TKE_BPMP_WDT0_WDTCMDR_0_ForceError_DEFAULT                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCMDR_0_ForceError_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define TKE_BPMP_WDT0_WDTCMDR_0_ForceError_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCMDR_0_ForceError_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCMDR_0_ForceError_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTCMDR_0_ForceError_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register TKE_BPMP_WDT0_WDTUR_0
#define TKE_BPMP_WDT0_WDTUR_0                   _MK_ADDR_CONST(0x5000c)
#define TKE_BPMP_WDT0_WDTUR_0_SECURE                    0x0
#define TKE_BPMP_WDT0_WDTUR_0_DUAL                      0x0
#define TKE_BPMP_WDT0_WDTUR_0_SCR                       WDTSCR0_0
#define TKE_BPMP_WDT0_WDTUR_0_WORD_COUNT                        0x1
#define TKE_BPMP_WDT0_WDTUR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTUR_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define TKE_BPMP_WDT0_WDTUR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTUR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTUR_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define TKE_BPMP_WDT0_WDTUR_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define TKE_BPMP_WDT0_WDTUR_0_UnlockPattern_SHIFT                       _MK_SHIFT_CONST(0)
#define TKE_BPMP_WDT0_WDTUR_0_UnlockPattern_FIELD                       _MK_FIELD_CONST(0xffffffff, TKE_BPMP_WDT0_WDTUR_0_UnlockPattern_SHIFT)
#define TKE_BPMP_WDT0_WDTUR_0_UnlockPattern_RANGE                       31:0
#define TKE_BPMP_WDT0_WDTUR_0_UnlockPattern_WOFFSET                     0x0
#define TKE_BPMP_WDT0_WDTUR_0_UnlockPattern_DEFAULT                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTUR_0_UnlockPattern_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define TKE_BPMP_WDT0_WDTUR_0_UnlockPattern_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTUR_0_UnlockPattern_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTUR_0_UnlockPattern_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTUR_0_UnlockPattern_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register TKE_BPMP_WDT0_WDTSCR_0
#define TKE_BPMP_WDT0_WDTSCR_0                  _MK_ADDR_CONST(0x50010)
#define TKE_BPMP_WDT0_WDTSCR_0_SECURE                   0x0
#define TKE_BPMP_WDT0_WDTSCR_0_DUAL                     0x0
#define TKE_BPMP_WDT0_WDTSCR_0_SCR                      WDTSCR0_0
#define TKE_BPMP_WDT0_WDTSCR_0_WORD_COUNT                       0x1
#define TKE_BPMP_WDT0_WDTSCR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSCR_0_RESET_MASK                       _MK_MASK_CONST(0x7777)
#define TKE_BPMP_WDT0_WDTSCR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSCR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSCR_0_READ_MASK                        _MK_MASK_CONST(0x7777)
#define TKE_BPMP_WDT0_WDTSCR_0_WRITE_MASK                       _MK_MASK_CONST(0x7777)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip0_SHIFT                      _MK_SHIFT_CONST(0)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip0_FIELD                      _MK_FIELD_CONST(0x7, TKE_BPMP_WDT0_WDTSCR_0_Skip0_SHIFT)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip0_RANGE                      2:0
#define TKE_BPMP_WDT0_WDTSCR_0_Skip0_WOFFSET                    0x0
#define TKE_BPMP_WDT0_WDTSCR_0_Skip0_DEFAULT                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip0_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip0_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip0_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTSCR_0_Skip1_SHIFT                      _MK_SHIFT_CONST(4)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip1_FIELD                      _MK_FIELD_CONST(0x7, TKE_BPMP_WDT0_WDTSCR_0_Skip1_SHIFT)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip1_RANGE                      6:4
#define TKE_BPMP_WDT0_WDTSCR_0_Skip1_WOFFSET                    0x0
#define TKE_BPMP_WDT0_WDTSCR_0_Skip1_DEFAULT                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip1_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip1_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip1_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTSCR_0_Skip2_SHIFT                      _MK_SHIFT_CONST(8)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip2_FIELD                      _MK_FIELD_CONST(0x7, TKE_BPMP_WDT0_WDTSCR_0_Skip2_SHIFT)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip2_RANGE                      10:8
#define TKE_BPMP_WDT0_WDTSCR_0_Skip2_WOFFSET                    0x0
#define TKE_BPMP_WDT0_WDTSCR_0_Skip2_DEFAULT                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip2_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip2_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip2_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTSCR_0_Skip3_SHIFT                      _MK_SHIFT_CONST(12)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip3_FIELD                      _MK_FIELD_CONST(0x7, TKE_BPMP_WDT0_WDTSCR_0_Skip3_SHIFT)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip3_RANGE                      14:12
#define TKE_BPMP_WDT0_WDTSCR_0_Skip3_WOFFSET                    0x0
#define TKE_BPMP_WDT0_WDTSCR_0_Skip3_DEFAULT                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip3_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip3_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTSCR_0_Skip3_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register TKE_BPMP_WDT0_WDTFWCR_0
#define TKE_BPMP_WDT0_WDTFWCR_0                 _MK_ADDR_CONST(0x50014)
#define TKE_BPMP_WDT0_WDTFWCR_0_SECURE                  0x0
#define TKE_BPMP_WDT0_WDTFWCR_0_DUAL                    0x0
#define TKE_BPMP_WDT0_WDTFWCR_0_SCR                     WDTSCR0_0
#define TKE_BPMP_WDT0_WDTFWCR_0_WORD_COUNT                      0x1
#define TKE_BPMP_WDT0_WDTFWCR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTFWCR_0_RESET_MASK                      _MK_MASK_CONST(0x700ff)
#define TKE_BPMP_WDT0_WDTFWCR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTFWCR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTFWCR_0_READ_MASK                       _MK_MASK_CONST(0x700ff)
#define TKE_BPMP_WDT0_WDTFWCR_0_WRITE_MASK                      _MK_MASK_CONST(0x700ff)
#define TKE_BPMP_WDT0_WDTFWCR_0_StartCount_SHIFT                        _MK_SHIFT_CONST(0)
#define TKE_BPMP_WDT0_WDTFWCR_0_StartCount_FIELD                        _MK_FIELD_CONST(0xff, TKE_BPMP_WDT0_WDTFWCR_0_StartCount_SHIFT)
#define TKE_BPMP_WDT0_WDTFWCR_0_StartCount_RANGE                        7:0
#define TKE_BPMP_WDT0_WDTFWCR_0_StartCount_WOFFSET                      0x0
#define TKE_BPMP_WDT0_WDTFWCR_0_StartCount_DEFAULT                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTFWCR_0_StartCount_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define TKE_BPMP_WDT0_WDTFWCR_0_StartCount_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTFWCR_0_StartCount_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTFWCR_0_StartCount_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTFWCR_0_StartCount_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define TKE_BPMP_WDT0_WDTFWCR_0_StartLevel_SHIFT                        _MK_SHIFT_CONST(16)
#define TKE_BPMP_WDT0_WDTFWCR_0_StartLevel_FIELD                        _MK_FIELD_CONST(0x7, TKE_BPMP_WDT0_WDTFWCR_0_StartLevel_SHIFT)
#define TKE_BPMP_WDT0_WDTFWCR_0_StartLevel_RANGE                        18:16
#define TKE_BPMP_WDT0_WDTFWCR_0_StartLevel_WOFFSET                      0x0
#define TKE_BPMP_WDT0_WDTFWCR_0_StartLevel_DEFAULT                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTFWCR_0_StartLevel_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define TKE_BPMP_WDT0_WDTFWCR_0_StartLevel_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTFWCR_0_StartLevel_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTFWCR_0_StartLevel_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define TKE_BPMP_WDT0_WDTFWCR_0_StartLevel_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


//
// REGISTER LIST
//
#define LIST_ARTKE_BPMP_REGS(_op_) \
_op_(TKE_BPMP_SHARED_TKETSC0_0) \
_op_(TKE_BPMP_SHARED_TKETSC1_0) \
_op_(TKE_BPMP_SHARED_TKEUSEC_0) \
_op_(TKE_BPMP_SHARED_TKEOSC_0) \
_op_(TKE_BPMP_SHARED_TKECR_0) \
_op_(TKE_BPMP_SHARED_CLK_OVR_ON_0) \
_op_(TKE_BPMP_TIMER_TMR0_TMRCR_0) \
_op_(TKE_BPMP_TIMER_TMR0_TMRSR_0) \
_op_(TKE_BPMP_TIMER_TMR0_TMRCSSR_0) \
_op_(TKE_BPMP_TIMER_TMR0_TMRATR_0) \
_op_(TKE_BPMP_TIMER_TMR1_TMRCR_0) \
_op_(TKE_BPMP_TIMER_TMR1_TMRSR_0) \
_op_(TKE_BPMP_TIMER_TMR1_TMRCSSR_0) \
_op_(TKE_BPMP_TIMER_TMR1_TMRATR_0) \
_op_(TKE_BPMP_TIMER_TMR2_TMRCR_0) \
_op_(TKE_BPMP_TIMER_TMR2_TMRSR_0) \
_op_(TKE_BPMP_TIMER_TMR2_TMRCSSR_0) \
_op_(TKE_BPMP_TIMER_TMR2_TMRATR_0) \
_op_(TKE_BPMP_TIMER_TMR3_TMRCR_0) \
_op_(TKE_BPMP_TIMER_TMR3_TMRSR_0) \
_op_(TKE_BPMP_TIMER_TMR3_TMRCSSR_0) \
_op_(TKE_BPMP_TIMER_TMR3_TMRATR_0) \
_op_(TKE_BPMP_WDT0_WDTCR_0) \
_op_(TKE_BPMP_WDT0_WDTSR_0) \
_op_(TKE_BPMP_WDT0_WDTCMDR_0) \
_op_(TKE_BPMP_WDT0_WDTUR_0) \
_op_(TKE_BPMP_WDT0_WDTSCR_0) \
_op_(TKE_BPMP_WDT0_WDTFWCR_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_TKE_BPMP_SHARED    0x00000000
#define BASE_ADDRESS_TKE_BPMP_TIMER_TMR0        0x00010000
#define BASE_ADDRESS_TKE_BPMP_TIMER_TMR1        0x00020000
#define BASE_ADDRESS_TKE_BPMP_TIMER_TMR2        0x00030000
#define BASE_ADDRESS_TKE_BPMP_TIMER_TMR3        0x00040000
#define BASE_ADDRESS_TKE_BPMP_WDT0      0x00050000

//
// ARTKE_BPMP REGISTER BANKS
//

#define TKE_BPMP_SHARED0_FIRST_REG 0x0000 // TKE_BPMP_SHARED_TKETSC0_0
#define TKE_BPMP_SHARED0_LAST_REG 0x0014 // TKE_BPMP_SHARED_CLK_OVR_ON_0
#define TKE_BPMP_TIMER_TMR00_FIRST_REG 0x10000 // TKE_BPMP_TIMER_TMR0_TMRCR_0
#define TKE_BPMP_TIMER_TMR00_LAST_REG 0x1000c // TKE_BPMP_TIMER_TMR0_TMRATR_0
#define TKE_BPMP_TIMER_TMR10_FIRST_REG 0x20000 // TKE_BPMP_TIMER_TMR1_TMRCR_0
#define TKE_BPMP_TIMER_TMR10_LAST_REG 0x2000c // TKE_BPMP_TIMER_TMR1_TMRATR_0
#define TKE_BPMP_TIMER_TMR20_FIRST_REG 0x30000 // TKE_BPMP_TIMER_TMR2_TMRCR_0
#define TKE_BPMP_TIMER_TMR20_LAST_REG 0x3000c // TKE_BPMP_TIMER_TMR2_TMRATR_0
#define TKE_BPMP_TIMER_TMR30_FIRST_REG 0x40000 // TKE_BPMP_TIMER_TMR3_TMRCR_0
#define TKE_BPMP_TIMER_TMR30_LAST_REG 0x4000c // TKE_BPMP_TIMER_TMR3_TMRATR_0
#define TKE_BPMP_WDT00_FIRST_REG 0x50000 // TKE_BPMP_WDT0_WDTCR_0
#define TKE_BPMP_WDT00_LAST_REG 0x50014 // TKE_BPMP_WDT0_WDTFWCR_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif
#ifndef _MK_FIELD_CONST
  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
#endif

#endif // ifndef ___ARTKE_BPMP_H_INC_
