//
// Copyright (c) 2018 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ___ARPADCTL_CONN_H_INC_
#define ___ARPADCTL_CONN_H_INC_
#define NV_MOBILE_ARPADCTL_CONN_H_UNIT_OF_OFFSET 1B


// Register PADCTL_CONN_DAP2_DIN_0
#define PADCTL_CONN_DAP2_DIN_0                  _MK_ADDR_CONST(0x0)
#define PADCTL_CONN_DAP2_DIN_0_SECURE                   0x0
#define PADCTL_CONN_DAP2_DIN_0_DUAL                     0x0
#define PADCTL_CONN_DAP2_DIN_0_SCR                      SCR_DAP2_DIN_0
#define PADCTL_CONN_DAP2_DIN_0_WORD_COUNT                       0x1
#define PADCTL_CONN_DAP2_DIN_0_RESET_VAL                        _MK_MASK_CONST(0x454)
#define PADCTL_CONN_DAP2_DIN_0_RESET_MASK                       _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_DAP2_DIN_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DIN_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DIN_0_READ_MASK                        _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_DAP2_DIN_0_WRITE_MASK                       _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_DAP2_DIN_0_PM_SHIFT                 _MK_SHIFT_CONST(0)
#define PADCTL_CONN_DAP2_DIN_0_PM_FIELD                 _MK_FIELD_CONST(0x3, PADCTL_CONN_DAP2_DIN_0_PM_SHIFT)
#define PADCTL_CONN_DAP2_DIN_0_PM_RANGE                 1:0
#define PADCTL_CONN_DAP2_DIN_0_PM_WOFFSET                       0x0
#define PADCTL_CONN_DAP2_DIN_0_PM_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DIN_0_PM_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define PADCTL_CONN_DAP2_DIN_0_PM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DIN_0_PM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DIN_0_PM_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DIN_0_PM_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DIN_0_PM_INIT_ENUM                     I2S2
#define PADCTL_CONN_DAP2_DIN_0_PM_I2S2                  _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_DIN_0_PM_RSVD1                 _MK_ENUM_CONST(1)
#define PADCTL_CONN_DAP2_DIN_0_PM_RSVD2                 _MK_ENUM_CONST(2)
#define PADCTL_CONN_DAP2_DIN_0_PM_RSVD3                 _MK_ENUM_CONST(3)

#define PADCTL_CONN_DAP2_DIN_0_GPIO_SF_SEL_SHIFT                        _MK_SHIFT_CONST(10)
#define PADCTL_CONN_DAP2_DIN_0_GPIO_SF_SEL_FIELD                        _MK_FIELD_CONST(0x1, PADCTL_CONN_DAP2_DIN_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_CONN_DAP2_DIN_0_GPIO_SF_SEL_RANGE                        10:10
#define PADCTL_CONN_DAP2_DIN_0_GPIO_SF_SEL_WOFFSET                      0x0
#define PADCTL_CONN_DAP2_DIN_0_GPIO_SF_SEL_DEFAULT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DIN_0_GPIO_SF_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DIN_0_GPIO_SF_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DIN_0_GPIO_SF_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DIN_0_GPIO_SF_SEL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DIN_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DIN_0_GPIO_SF_SEL_INIT_ENUM                    SFIO
#define PADCTL_CONN_DAP2_DIN_0_GPIO_SF_SEL_GPIO                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_DIN_0_GPIO_SF_SEL_SFIO                 _MK_ENUM_CONST(1)

#define PADCTL_CONN_DAP2_DIN_0_TRISTATE_SHIFT                   _MK_SHIFT_CONST(4)
#define PADCTL_CONN_DAP2_DIN_0_TRISTATE_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_CONN_DAP2_DIN_0_TRISTATE_SHIFT)
#define PADCTL_CONN_DAP2_DIN_0_TRISTATE_RANGE                   4:4
#define PADCTL_CONN_DAP2_DIN_0_TRISTATE_WOFFSET                 0x0
#define PADCTL_CONN_DAP2_DIN_0_TRISTATE_DEFAULT                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DIN_0_TRISTATE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DIN_0_TRISTATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DIN_0_TRISTATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DIN_0_TRISTATE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DIN_0_TRISTATE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DIN_0_TRISTATE_INIT_ENUM                       TRISTATE
#define PADCTL_CONN_DAP2_DIN_0_TRISTATE_PASSTHROUGH                     _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_DIN_0_TRISTATE_TRISTATE                        _MK_ENUM_CONST(1)

#define PADCTL_CONN_DAP2_DIN_0_PUPD_SHIFT                       _MK_SHIFT_CONST(2)
#define PADCTL_CONN_DAP2_DIN_0_PUPD_FIELD                       _MK_FIELD_CONST(0x3, PADCTL_CONN_DAP2_DIN_0_PUPD_SHIFT)
#define PADCTL_CONN_DAP2_DIN_0_PUPD_RANGE                       3:2
#define PADCTL_CONN_DAP2_DIN_0_PUPD_WOFFSET                     0x0
#define PADCTL_CONN_DAP2_DIN_0_PUPD_DEFAULT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DIN_0_PUPD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define PADCTL_CONN_DAP2_DIN_0_PUPD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DIN_0_PUPD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DIN_0_PUPD_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DIN_0_PUPD_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DIN_0_PUPD_INIT_ENUM                   PULL_DOWN
#define PADCTL_CONN_DAP2_DIN_0_PUPD_NONE                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_DIN_0_PUPD_PULL_DOWN                   _MK_ENUM_CONST(1)
#define PADCTL_CONN_DAP2_DIN_0_PUPD_PULL_UP                     _MK_ENUM_CONST(2)
#define PADCTL_CONN_DAP2_DIN_0_PUPD_RSVD                        _MK_ENUM_CONST(3)

#define PADCTL_CONN_DAP2_DIN_0_E_INPUT_SHIFT                    _MK_SHIFT_CONST(6)
#define PADCTL_CONN_DAP2_DIN_0_E_INPUT_FIELD                    _MK_FIELD_CONST(0x1, PADCTL_CONN_DAP2_DIN_0_E_INPUT_SHIFT)
#define PADCTL_CONN_DAP2_DIN_0_E_INPUT_RANGE                    6:6
#define PADCTL_CONN_DAP2_DIN_0_E_INPUT_WOFFSET                  0x0
#define PADCTL_CONN_DAP2_DIN_0_E_INPUT_DEFAULT                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DIN_0_E_INPUT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DIN_0_E_INPUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DIN_0_E_INPUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DIN_0_E_INPUT_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DIN_0_E_INPUT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DIN_0_E_INPUT_INIT_ENUM                        ENABLE
#define PADCTL_CONN_DAP2_DIN_0_E_INPUT_DISABLE                  _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_DIN_0_E_INPUT_ENABLE                   _MK_ENUM_CONST(1)

#define PADCTL_CONN_DAP2_DIN_0_E_LPDR_SHIFT                     _MK_SHIFT_CONST(8)
#define PADCTL_CONN_DAP2_DIN_0_E_LPDR_FIELD                     _MK_FIELD_CONST(0x1, PADCTL_CONN_DAP2_DIN_0_E_LPDR_SHIFT)
#define PADCTL_CONN_DAP2_DIN_0_E_LPDR_RANGE                     8:8
#define PADCTL_CONN_DAP2_DIN_0_E_LPDR_WOFFSET                   0x0
#define PADCTL_CONN_DAP2_DIN_0_E_LPDR_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DIN_0_E_LPDR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DIN_0_E_LPDR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DIN_0_E_LPDR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DIN_0_E_LPDR_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DIN_0_E_LPDR_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DIN_0_E_LPDR_INIT_ENUM                 DISABLE
#define PADCTL_CONN_DAP2_DIN_0_E_LPDR_DISABLE                   _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_DIN_0_E_LPDR_ENABLE                    _MK_ENUM_CONST(1)

#define PADCTL_CONN_DAP2_DIN_0_E_SCHMT_SHIFT                    _MK_SHIFT_CONST(12)
#define PADCTL_CONN_DAP2_DIN_0_E_SCHMT_FIELD                    _MK_FIELD_CONST(0x1, PADCTL_CONN_DAP2_DIN_0_E_SCHMT_SHIFT)
#define PADCTL_CONN_DAP2_DIN_0_E_SCHMT_RANGE                    12:12
#define PADCTL_CONN_DAP2_DIN_0_E_SCHMT_WOFFSET                  0x0
#define PADCTL_CONN_DAP2_DIN_0_E_SCHMT_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DIN_0_E_SCHMT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DIN_0_E_SCHMT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DIN_0_E_SCHMT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DIN_0_E_SCHMT_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DIN_0_E_SCHMT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DIN_0_E_SCHMT_INIT_ENUM                        DISABLE
#define PADCTL_CONN_DAP2_DIN_0_E_SCHMT_DISABLE                  _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_DIN_0_E_SCHMT_ENABLE                   _MK_ENUM_CONST(1)


// Register PADCTL_CONN_CFG2TMC_DAP2_DIN_0
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0                  _MK_ADDR_CONST(0x4)
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_SECURE                   0x0
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_DUAL                     0x0
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_SCR                      SCR_DAP2_DIN_0
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_WORD_COUNT                       0x1
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_RESET_MASK                       _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_READ_MASK                        _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_WRITE_MASK                       _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_CFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_CFG_CAL_DRVDN_FIELD                      _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_DAP2_DIN_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_CFG_CAL_DRVDN_RANGE                      16:12
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_CFG_CAL_DRVDN_WOFFSET                    0x0
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_CFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_CFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_CFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_CFG_CAL_DRVDN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_CFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_CFG_CAL_DRVUP_FIELD                      _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_DAP2_DIN_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_CFG_CAL_DRVUP_RANGE                      24:20
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_CFG_CAL_DRVUP_WOFFSET                    0x0
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_CFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_CFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_CFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_CFG_CAL_DRVUP_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_DIN_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register PADCTL_CONN_DAP2_DOUT_0
#define PADCTL_CONN_DAP2_DOUT_0                 _MK_ADDR_CONST(0x8)
#define PADCTL_CONN_DAP2_DOUT_0_SECURE                  0x0
#define PADCTL_CONN_DAP2_DOUT_0_DUAL                    0x0
#define PADCTL_CONN_DAP2_DOUT_0_SCR                     SCR_DAP2_DOUT_0
#define PADCTL_CONN_DAP2_DOUT_0_WORD_COUNT                      0x1
#define PADCTL_CONN_DAP2_DOUT_0_RESET_VAL                       _MK_MASK_CONST(0x414)
#define PADCTL_CONN_DAP2_DOUT_0_RESET_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_DAP2_DOUT_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DOUT_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DOUT_0_READ_MASK                       _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_DAP2_DOUT_0_WRITE_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_DAP2_DOUT_0_PM_SHIFT                        _MK_SHIFT_CONST(0)
#define PADCTL_CONN_DAP2_DOUT_0_PM_FIELD                        _MK_FIELD_CONST(0x3, PADCTL_CONN_DAP2_DOUT_0_PM_SHIFT)
#define PADCTL_CONN_DAP2_DOUT_0_PM_RANGE                        1:0
#define PADCTL_CONN_DAP2_DOUT_0_PM_WOFFSET                      0x0
#define PADCTL_CONN_DAP2_DOUT_0_PM_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DOUT_0_PM_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define PADCTL_CONN_DAP2_DOUT_0_PM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DOUT_0_PM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DOUT_0_PM_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DOUT_0_PM_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DOUT_0_PM_INIT_ENUM                    I2S2
#define PADCTL_CONN_DAP2_DOUT_0_PM_I2S2                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_DOUT_0_PM_RSVD1                        _MK_ENUM_CONST(1)
#define PADCTL_CONN_DAP2_DOUT_0_PM_RSVD2                        _MK_ENUM_CONST(2)
#define PADCTL_CONN_DAP2_DOUT_0_PM_RSVD3                        _MK_ENUM_CONST(3)

#define PADCTL_CONN_DAP2_DOUT_0_GPIO_SF_SEL_SHIFT                       _MK_SHIFT_CONST(10)
#define PADCTL_CONN_DAP2_DOUT_0_GPIO_SF_SEL_FIELD                       _MK_FIELD_CONST(0x1, PADCTL_CONN_DAP2_DOUT_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_CONN_DAP2_DOUT_0_GPIO_SF_SEL_RANGE                       10:10
#define PADCTL_CONN_DAP2_DOUT_0_GPIO_SF_SEL_WOFFSET                     0x0
#define PADCTL_CONN_DAP2_DOUT_0_GPIO_SF_SEL_DEFAULT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DOUT_0_GPIO_SF_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DOUT_0_GPIO_SF_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DOUT_0_GPIO_SF_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DOUT_0_GPIO_SF_SEL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DOUT_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DOUT_0_GPIO_SF_SEL_INIT_ENUM                   SFIO
#define PADCTL_CONN_DAP2_DOUT_0_GPIO_SF_SEL_GPIO                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_DOUT_0_GPIO_SF_SEL_SFIO                        _MK_ENUM_CONST(1)

#define PADCTL_CONN_DAP2_DOUT_0_TRISTATE_SHIFT                  _MK_SHIFT_CONST(4)
#define PADCTL_CONN_DAP2_DOUT_0_TRISTATE_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_CONN_DAP2_DOUT_0_TRISTATE_SHIFT)
#define PADCTL_CONN_DAP2_DOUT_0_TRISTATE_RANGE                  4:4
#define PADCTL_CONN_DAP2_DOUT_0_TRISTATE_WOFFSET                        0x0
#define PADCTL_CONN_DAP2_DOUT_0_TRISTATE_DEFAULT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DOUT_0_TRISTATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DOUT_0_TRISTATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DOUT_0_TRISTATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DOUT_0_TRISTATE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DOUT_0_TRISTATE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DOUT_0_TRISTATE_INIT_ENUM                      TRISTATE
#define PADCTL_CONN_DAP2_DOUT_0_TRISTATE_PASSTHROUGH                    _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_DOUT_0_TRISTATE_TRISTATE                       _MK_ENUM_CONST(1)

#define PADCTL_CONN_DAP2_DOUT_0_PUPD_SHIFT                      _MK_SHIFT_CONST(2)
#define PADCTL_CONN_DAP2_DOUT_0_PUPD_FIELD                      _MK_FIELD_CONST(0x3, PADCTL_CONN_DAP2_DOUT_0_PUPD_SHIFT)
#define PADCTL_CONN_DAP2_DOUT_0_PUPD_RANGE                      3:2
#define PADCTL_CONN_DAP2_DOUT_0_PUPD_WOFFSET                    0x0
#define PADCTL_CONN_DAP2_DOUT_0_PUPD_DEFAULT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DOUT_0_PUPD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define PADCTL_CONN_DAP2_DOUT_0_PUPD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DOUT_0_PUPD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DOUT_0_PUPD_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DOUT_0_PUPD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DOUT_0_PUPD_INIT_ENUM                  PULL_DOWN
#define PADCTL_CONN_DAP2_DOUT_0_PUPD_NONE                       _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_DOUT_0_PUPD_PULL_DOWN                  _MK_ENUM_CONST(1)
#define PADCTL_CONN_DAP2_DOUT_0_PUPD_PULL_UP                    _MK_ENUM_CONST(2)
#define PADCTL_CONN_DAP2_DOUT_0_PUPD_RSVD                       _MK_ENUM_CONST(3)

#define PADCTL_CONN_DAP2_DOUT_0_E_INPUT_SHIFT                   _MK_SHIFT_CONST(6)
#define PADCTL_CONN_DAP2_DOUT_0_E_INPUT_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_CONN_DAP2_DOUT_0_E_INPUT_SHIFT)
#define PADCTL_CONN_DAP2_DOUT_0_E_INPUT_RANGE                   6:6
#define PADCTL_CONN_DAP2_DOUT_0_E_INPUT_WOFFSET                 0x0
#define PADCTL_CONN_DAP2_DOUT_0_E_INPUT_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DOUT_0_E_INPUT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DOUT_0_E_INPUT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DOUT_0_E_INPUT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DOUT_0_E_INPUT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DOUT_0_E_INPUT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DOUT_0_E_INPUT_INIT_ENUM                       DISABLE
#define PADCTL_CONN_DAP2_DOUT_0_E_INPUT_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_DOUT_0_E_INPUT_ENABLE                  _MK_ENUM_CONST(1)

#define PADCTL_CONN_DAP2_DOUT_0_E_LPDR_SHIFT                    _MK_SHIFT_CONST(8)
#define PADCTL_CONN_DAP2_DOUT_0_E_LPDR_FIELD                    _MK_FIELD_CONST(0x1, PADCTL_CONN_DAP2_DOUT_0_E_LPDR_SHIFT)
#define PADCTL_CONN_DAP2_DOUT_0_E_LPDR_RANGE                    8:8
#define PADCTL_CONN_DAP2_DOUT_0_E_LPDR_WOFFSET                  0x0
#define PADCTL_CONN_DAP2_DOUT_0_E_LPDR_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DOUT_0_E_LPDR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DOUT_0_E_LPDR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DOUT_0_E_LPDR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DOUT_0_E_LPDR_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DOUT_0_E_LPDR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DOUT_0_E_LPDR_INIT_ENUM                        DISABLE
#define PADCTL_CONN_DAP2_DOUT_0_E_LPDR_DISABLE                  _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_DOUT_0_E_LPDR_ENABLE                   _MK_ENUM_CONST(1)

#define PADCTL_CONN_DAP2_DOUT_0_E_SCHMT_SHIFT                   _MK_SHIFT_CONST(12)
#define PADCTL_CONN_DAP2_DOUT_0_E_SCHMT_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_CONN_DAP2_DOUT_0_E_SCHMT_SHIFT)
#define PADCTL_CONN_DAP2_DOUT_0_E_SCHMT_RANGE                   12:12
#define PADCTL_CONN_DAP2_DOUT_0_E_SCHMT_WOFFSET                 0x0
#define PADCTL_CONN_DAP2_DOUT_0_E_SCHMT_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DOUT_0_E_SCHMT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DOUT_0_E_SCHMT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DOUT_0_E_SCHMT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DOUT_0_E_SCHMT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_DOUT_0_E_SCHMT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_DOUT_0_E_SCHMT_INIT_ENUM                       DISABLE
#define PADCTL_CONN_DAP2_DOUT_0_E_SCHMT_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_DOUT_0_E_SCHMT_ENABLE                  _MK_ENUM_CONST(1)


// Register PADCTL_CONN_CFG2TMC_DAP2_DOUT_0
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0                 _MK_ADDR_CONST(0xc)
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_SECURE                  0x0
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_DUAL                    0x0
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_SCR                     SCR_DAP2_DOUT_0
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_WORD_COUNT                      0x1
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_RESET_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_READ_MASK                       _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_WRITE_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_CFG_CAL_DRVDN_SHIFT                     _MK_SHIFT_CONST(12)
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_CFG_CAL_DRVDN_FIELD                     _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_CFG_CAL_DRVDN_RANGE                     16:12
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_CFG_CAL_DRVDN_WOFFSET                   0x0
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_CFG_CAL_DRVDN_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_CFG_CAL_DRVDN_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_CFG_CAL_DRVDN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_CFG_CAL_DRVDN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_CFG_CAL_DRVUP_SHIFT                     _MK_SHIFT_CONST(20)
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_CFG_CAL_DRVUP_FIELD                     _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_CFG_CAL_DRVUP_RANGE                     24:20
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_CFG_CAL_DRVUP_WOFFSET                   0x0
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_CFG_CAL_DRVUP_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_CFG_CAL_DRVUP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_CFG_CAL_DRVUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_CFG_CAL_DRVUP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_DOUT_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register PADCTL_CONN_DAP2_FS_0
#define PADCTL_CONN_DAP2_FS_0                   _MK_ADDR_CONST(0x10)
#define PADCTL_CONN_DAP2_FS_0_SECURE                    0x0
#define PADCTL_CONN_DAP2_FS_0_DUAL                      0x0
#define PADCTL_CONN_DAP2_FS_0_SCR                       SCR_DAP2_FS_0
#define PADCTL_CONN_DAP2_FS_0_WORD_COUNT                        0x1
#define PADCTL_CONN_DAP2_FS_0_RESET_VAL                         _MK_MASK_CONST(0x454)
#define PADCTL_CONN_DAP2_FS_0_RESET_MASK                        _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_DAP2_FS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_FS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_FS_0_READ_MASK                         _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_DAP2_FS_0_WRITE_MASK                        _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_DAP2_FS_0_PM_SHIFT                  _MK_SHIFT_CONST(0)
#define PADCTL_CONN_DAP2_FS_0_PM_FIELD                  _MK_FIELD_CONST(0x3, PADCTL_CONN_DAP2_FS_0_PM_SHIFT)
#define PADCTL_CONN_DAP2_FS_0_PM_RANGE                  1:0
#define PADCTL_CONN_DAP2_FS_0_PM_WOFFSET                        0x0
#define PADCTL_CONN_DAP2_FS_0_PM_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_FS_0_PM_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define PADCTL_CONN_DAP2_FS_0_PM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_FS_0_PM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_FS_0_PM_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_FS_0_PM_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_FS_0_PM_INIT_ENUM                      I2S2
#define PADCTL_CONN_DAP2_FS_0_PM_I2S2                   _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_FS_0_PM_RSVD1                  _MK_ENUM_CONST(1)
#define PADCTL_CONN_DAP2_FS_0_PM_RSVD2                  _MK_ENUM_CONST(2)
#define PADCTL_CONN_DAP2_FS_0_PM_RSVD3                  _MK_ENUM_CONST(3)

#define PADCTL_CONN_DAP2_FS_0_GPIO_SF_SEL_SHIFT                 _MK_SHIFT_CONST(10)
#define PADCTL_CONN_DAP2_FS_0_GPIO_SF_SEL_FIELD                 _MK_FIELD_CONST(0x1, PADCTL_CONN_DAP2_FS_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_CONN_DAP2_FS_0_GPIO_SF_SEL_RANGE                 10:10
#define PADCTL_CONN_DAP2_FS_0_GPIO_SF_SEL_WOFFSET                       0x0
#define PADCTL_CONN_DAP2_FS_0_GPIO_SF_SEL_DEFAULT                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_FS_0_GPIO_SF_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_FS_0_GPIO_SF_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_FS_0_GPIO_SF_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_FS_0_GPIO_SF_SEL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_FS_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_FS_0_GPIO_SF_SEL_INIT_ENUM                     SFIO
#define PADCTL_CONN_DAP2_FS_0_GPIO_SF_SEL_GPIO                  _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_FS_0_GPIO_SF_SEL_SFIO                  _MK_ENUM_CONST(1)

#define PADCTL_CONN_DAP2_FS_0_TRISTATE_SHIFT                    _MK_SHIFT_CONST(4)
#define PADCTL_CONN_DAP2_FS_0_TRISTATE_FIELD                    _MK_FIELD_CONST(0x1, PADCTL_CONN_DAP2_FS_0_TRISTATE_SHIFT)
#define PADCTL_CONN_DAP2_FS_0_TRISTATE_RANGE                    4:4
#define PADCTL_CONN_DAP2_FS_0_TRISTATE_WOFFSET                  0x0
#define PADCTL_CONN_DAP2_FS_0_TRISTATE_DEFAULT                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_FS_0_TRISTATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_FS_0_TRISTATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_FS_0_TRISTATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_FS_0_TRISTATE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_FS_0_TRISTATE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_FS_0_TRISTATE_INIT_ENUM                        TRISTATE
#define PADCTL_CONN_DAP2_FS_0_TRISTATE_PASSTHROUGH                      _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_FS_0_TRISTATE_TRISTATE                 _MK_ENUM_CONST(1)

#define PADCTL_CONN_DAP2_FS_0_PUPD_SHIFT                        _MK_SHIFT_CONST(2)
#define PADCTL_CONN_DAP2_FS_0_PUPD_FIELD                        _MK_FIELD_CONST(0x3, PADCTL_CONN_DAP2_FS_0_PUPD_SHIFT)
#define PADCTL_CONN_DAP2_FS_0_PUPD_RANGE                        3:2
#define PADCTL_CONN_DAP2_FS_0_PUPD_WOFFSET                      0x0
#define PADCTL_CONN_DAP2_FS_0_PUPD_DEFAULT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_FS_0_PUPD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define PADCTL_CONN_DAP2_FS_0_PUPD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_FS_0_PUPD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_FS_0_PUPD_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_FS_0_PUPD_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_FS_0_PUPD_INIT_ENUM                    PULL_DOWN
#define PADCTL_CONN_DAP2_FS_0_PUPD_NONE                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_FS_0_PUPD_PULL_DOWN                    _MK_ENUM_CONST(1)
#define PADCTL_CONN_DAP2_FS_0_PUPD_PULL_UP                      _MK_ENUM_CONST(2)
#define PADCTL_CONN_DAP2_FS_0_PUPD_RSVD                 _MK_ENUM_CONST(3)

#define PADCTL_CONN_DAP2_FS_0_E_INPUT_SHIFT                     _MK_SHIFT_CONST(6)
#define PADCTL_CONN_DAP2_FS_0_E_INPUT_FIELD                     _MK_FIELD_CONST(0x1, PADCTL_CONN_DAP2_FS_0_E_INPUT_SHIFT)
#define PADCTL_CONN_DAP2_FS_0_E_INPUT_RANGE                     6:6
#define PADCTL_CONN_DAP2_FS_0_E_INPUT_WOFFSET                   0x0
#define PADCTL_CONN_DAP2_FS_0_E_INPUT_DEFAULT                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_FS_0_E_INPUT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_FS_0_E_INPUT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_FS_0_E_INPUT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_FS_0_E_INPUT_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_FS_0_E_INPUT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_FS_0_E_INPUT_INIT_ENUM                 ENABLE
#define PADCTL_CONN_DAP2_FS_0_E_INPUT_DISABLE                   _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_FS_0_E_INPUT_ENABLE                    _MK_ENUM_CONST(1)

#define PADCTL_CONN_DAP2_FS_0_E_LPDR_SHIFT                      _MK_SHIFT_CONST(8)
#define PADCTL_CONN_DAP2_FS_0_E_LPDR_FIELD                      _MK_FIELD_CONST(0x1, PADCTL_CONN_DAP2_FS_0_E_LPDR_SHIFT)
#define PADCTL_CONN_DAP2_FS_0_E_LPDR_RANGE                      8:8
#define PADCTL_CONN_DAP2_FS_0_E_LPDR_WOFFSET                    0x0
#define PADCTL_CONN_DAP2_FS_0_E_LPDR_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_FS_0_E_LPDR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_FS_0_E_LPDR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_FS_0_E_LPDR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_FS_0_E_LPDR_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_FS_0_E_LPDR_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_FS_0_E_LPDR_INIT_ENUM                  DISABLE
#define PADCTL_CONN_DAP2_FS_0_E_LPDR_DISABLE                    _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_FS_0_E_LPDR_ENABLE                     _MK_ENUM_CONST(1)

#define PADCTL_CONN_DAP2_FS_0_E_SCHMT_SHIFT                     _MK_SHIFT_CONST(12)
#define PADCTL_CONN_DAP2_FS_0_E_SCHMT_FIELD                     _MK_FIELD_CONST(0x1, PADCTL_CONN_DAP2_FS_0_E_SCHMT_SHIFT)
#define PADCTL_CONN_DAP2_FS_0_E_SCHMT_RANGE                     12:12
#define PADCTL_CONN_DAP2_FS_0_E_SCHMT_WOFFSET                   0x0
#define PADCTL_CONN_DAP2_FS_0_E_SCHMT_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_FS_0_E_SCHMT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_FS_0_E_SCHMT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_FS_0_E_SCHMT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_FS_0_E_SCHMT_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_FS_0_E_SCHMT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_FS_0_E_SCHMT_INIT_ENUM                 DISABLE
#define PADCTL_CONN_DAP2_FS_0_E_SCHMT_DISABLE                   _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_FS_0_E_SCHMT_ENABLE                    _MK_ENUM_CONST(1)


// Register PADCTL_CONN_CFG2TMC_DAP2_FS_0
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0                   _MK_ADDR_CONST(0x14)
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_SECURE                    0x0
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_DUAL                      0x0
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_SCR                       SCR_DAP2_FS_0
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_WORD_COUNT                        0x1
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_RESET_MASK                        _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_READ_MASK                         _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_WRITE_MASK                        _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_CFG_CAL_DRVDN_SHIFT                       _MK_SHIFT_CONST(12)
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_CFG_CAL_DRVDN_FIELD                       _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_DAP2_FS_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_CFG_CAL_DRVDN_RANGE                       16:12
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_CFG_CAL_DRVDN_WOFFSET                     0x0
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_CFG_CAL_DRVDN_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_CFG_CAL_DRVDN_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_CFG_CAL_DRVDN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_CFG_CAL_DRVDN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_CFG_CAL_DRVUP_SHIFT                       _MK_SHIFT_CONST(20)
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_CFG_CAL_DRVUP_FIELD                       _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_DAP2_FS_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_CFG_CAL_DRVUP_RANGE                       24:20
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_CFG_CAL_DRVUP_WOFFSET                     0x0
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_CFG_CAL_DRVUP_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_CFG_CAL_DRVUP_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_CFG_CAL_DRVUP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_CFG_CAL_DRVUP_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_FS_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register PADCTL_CONN_DAP2_SCLK_0
#define PADCTL_CONN_DAP2_SCLK_0                 _MK_ADDR_CONST(0x18)
#define PADCTL_CONN_DAP2_SCLK_0_SECURE                  0x0
#define PADCTL_CONN_DAP2_SCLK_0_DUAL                    0x0
#define PADCTL_CONN_DAP2_SCLK_0_SCR                     SCR_DAP2_SCLK_0
#define PADCTL_CONN_DAP2_SCLK_0_WORD_COUNT                      0x1
#define PADCTL_CONN_DAP2_SCLK_0_RESET_VAL                       _MK_MASK_CONST(0x454)
#define PADCTL_CONN_DAP2_SCLK_0_RESET_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_DAP2_SCLK_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_SCLK_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_SCLK_0_READ_MASK                       _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_DAP2_SCLK_0_WRITE_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_DAP2_SCLK_0_PM_SHIFT                        _MK_SHIFT_CONST(0)
#define PADCTL_CONN_DAP2_SCLK_0_PM_FIELD                        _MK_FIELD_CONST(0x3, PADCTL_CONN_DAP2_SCLK_0_PM_SHIFT)
#define PADCTL_CONN_DAP2_SCLK_0_PM_RANGE                        1:0
#define PADCTL_CONN_DAP2_SCLK_0_PM_WOFFSET                      0x0
#define PADCTL_CONN_DAP2_SCLK_0_PM_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_SCLK_0_PM_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define PADCTL_CONN_DAP2_SCLK_0_PM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_SCLK_0_PM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_SCLK_0_PM_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_SCLK_0_PM_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_SCLK_0_PM_INIT_ENUM                    I2S2
#define PADCTL_CONN_DAP2_SCLK_0_PM_I2S2                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_SCLK_0_PM_RSVD1                        _MK_ENUM_CONST(1)
#define PADCTL_CONN_DAP2_SCLK_0_PM_RSVD2                        _MK_ENUM_CONST(2)
#define PADCTL_CONN_DAP2_SCLK_0_PM_RSVD3                        _MK_ENUM_CONST(3)

#define PADCTL_CONN_DAP2_SCLK_0_GPIO_SF_SEL_SHIFT                       _MK_SHIFT_CONST(10)
#define PADCTL_CONN_DAP2_SCLK_0_GPIO_SF_SEL_FIELD                       _MK_FIELD_CONST(0x1, PADCTL_CONN_DAP2_SCLK_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_CONN_DAP2_SCLK_0_GPIO_SF_SEL_RANGE                       10:10
#define PADCTL_CONN_DAP2_SCLK_0_GPIO_SF_SEL_WOFFSET                     0x0
#define PADCTL_CONN_DAP2_SCLK_0_GPIO_SF_SEL_DEFAULT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_SCLK_0_GPIO_SF_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_SCLK_0_GPIO_SF_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_SCLK_0_GPIO_SF_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_SCLK_0_GPIO_SF_SEL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_SCLK_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_SCLK_0_GPIO_SF_SEL_INIT_ENUM                   SFIO
#define PADCTL_CONN_DAP2_SCLK_0_GPIO_SF_SEL_GPIO                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_SCLK_0_GPIO_SF_SEL_SFIO                        _MK_ENUM_CONST(1)

#define PADCTL_CONN_DAP2_SCLK_0_TRISTATE_SHIFT                  _MK_SHIFT_CONST(4)
#define PADCTL_CONN_DAP2_SCLK_0_TRISTATE_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_CONN_DAP2_SCLK_0_TRISTATE_SHIFT)
#define PADCTL_CONN_DAP2_SCLK_0_TRISTATE_RANGE                  4:4
#define PADCTL_CONN_DAP2_SCLK_0_TRISTATE_WOFFSET                        0x0
#define PADCTL_CONN_DAP2_SCLK_0_TRISTATE_DEFAULT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_SCLK_0_TRISTATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_SCLK_0_TRISTATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_SCLK_0_TRISTATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_SCLK_0_TRISTATE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_SCLK_0_TRISTATE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_SCLK_0_TRISTATE_INIT_ENUM                      TRISTATE
#define PADCTL_CONN_DAP2_SCLK_0_TRISTATE_PASSTHROUGH                    _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_SCLK_0_TRISTATE_TRISTATE                       _MK_ENUM_CONST(1)

#define PADCTL_CONN_DAP2_SCLK_0_PUPD_SHIFT                      _MK_SHIFT_CONST(2)
#define PADCTL_CONN_DAP2_SCLK_0_PUPD_FIELD                      _MK_FIELD_CONST(0x3, PADCTL_CONN_DAP2_SCLK_0_PUPD_SHIFT)
#define PADCTL_CONN_DAP2_SCLK_0_PUPD_RANGE                      3:2
#define PADCTL_CONN_DAP2_SCLK_0_PUPD_WOFFSET                    0x0
#define PADCTL_CONN_DAP2_SCLK_0_PUPD_DEFAULT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_SCLK_0_PUPD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define PADCTL_CONN_DAP2_SCLK_0_PUPD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_SCLK_0_PUPD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_SCLK_0_PUPD_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_SCLK_0_PUPD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_SCLK_0_PUPD_INIT_ENUM                  PULL_DOWN
#define PADCTL_CONN_DAP2_SCLK_0_PUPD_NONE                       _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_SCLK_0_PUPD_PULL_DOWN                  _MK_ENUM_CONST(1)
#define PADCTL_CONN_DAP2_SCLK_0_PUPD_PULL_UP                    _MK_ENUM_CONST(2)
#define PADCTL_CONN_DAP2_SCLK_0_PUPD_RSVD                       _MK_ENUM_CONST(3)

#define PADCTL_CONN_DAP2_SCLK_0_E_INPUT_SHIFT                   _MK_SHIFT_CONST(6)
#define PADCTL_CONN_DAP2_SCLK_0_E_INPUT_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_CONN_DAP2_SCLK_0_E_INPUT_SHIFT)
#define PADCTL_CONN_DAP2_SCLK_0_E_INPUT_RANGE                   6:6
#define PADCTL_CONN_DAP2_SCLK_0_E_INPUT_WOFFSET                 0x0
#define PADCTL_CONN_DAP2_SCLK_0_E_INPUT_DEFAULT                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_SCLK_0_E_INPUT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_SCLK_0_E_INPUT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_SCLK_0_E_INPUT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_SCLK_0_E_INPUT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_SCLK_0_E_INPUT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_SCLK_0_E_INPUT_INIT_ENUM                       ENABLE
#define PADCTL_CONN_DAP2_SCLK_0_E_INPUT_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_SCLK_0_E_INPUT_ENABLE                  _MK_ENUM_CONST(1)

#define PADCTL_CONN_DAP2_SCLK_0_E_LPDR_SHIFT                    _MK_SHIFT_CONST(8)
#define PADCTL_CONN_DAP2_SCLK_0_E_LPDR_FIELD                    _MK_FIELD_CONST(0x1, PADCTL_CONN_DAP2_SCLK_0_E_LPDR_SHIFT)
#define PADCTL_CONN_DAP2_SCLK_0_E_LPDR_RANGE                    8:8
#define PADCTL_CONN_DAP2_SCLK_0_E_LPDR_WOFFSET                  0x0
#define PADCTL_CONN_DAP2_SCLK_0_E_LPDR_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_SCLK_0_E_LPDR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_SCLK_0_E_LPDR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_SCLK_0_E_LPDR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_SCLK_0_E_LPDR_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_SCLK_0_E_LPDR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_SCLK_0_E_LPDR_INIT_ENUM                        DISABLE
#define PADCTL_CONN_DAP2_SCLK_0_E_LPDR_DISABLE                  _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_SCLK_0_E_LPDR_ENABLE                   _MK_ENUM_CONST(1)

#define PADCTL_CONN_DAP2_SCLK_0_E_SCHMT_SHIFT                   _MK_SHIFT_CONST(12)
#define PADCTL_CONN_DAP2_SCLK_0_E_SCHMT_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_CONN_DAP2_SCLK_0_E_SCHMT_SHIFT)
#define PADCTL_CONN_DAP2_SCLK_0_E_SCHMT_RANGE                   12:12
#define PADCTL_CONN_DAP2_SCLK_0_E_SCHMT_WOFFSET                 0x0
#define PADCTL_CONN_DAP2_SCLK_0_E_SCHMT_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_SCLK_0_E_SCHMT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_SCLK_0_E_SCHMT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_SCLK_0_E_SCHMT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_SCLK_0_E_SCHMT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_DAP2_SCLK_0_E_SCHMT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_DAP2_SCLK_0_E_SCHMT_INIT_ENUM                       DISABLE
#define PADCTL_CONN_DAP2_SCLK_0_E_SCHMT_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_DAP2_SCLK_0_E_SCHMT_ENABLE                  _MK_ENUM_CONST(1)


// Register PADCTL_CONN_CFG2TMC_DAP2_SCLK_0
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0                 _MK_ADDR_CONST(0x1c)
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_SECURE                  0x0
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_DUAL                    0x0
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_SCR                     SCR_DAP2_SCLK_0
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_WORD_COUNT                      0x1
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_RESET_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_READ_MASK                       _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_WRITE_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_CFG_CAL_DRVDN_SHIFT                     _MK_SHIFT_CONST(12)
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_CFG_CAL_DRVDN_FIELD                     _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_CFG_CAL_DRVDN_RANGE                     16:12
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_CFG_CAL_DRVDN_WOFFSET                   0x0
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_CFG_CAL_DRVDN_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_CFG_CAL_DRVDN_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_CFG_CAL_DRVDN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_CFG_CAL_DRVDN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_CFG_CAL_DRVUP_SHIFT                     _MK_SHIFT_CONST(20)
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_CFG_CAL_DRVUP_FIELD                     _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_CFG_CAL_DRVUP_RANGE                     24:20
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_CFG_CAL_DRVUP_WOFFSET                   0x0
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_CFG_CAL_DRVUP_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_CFG_CAL_DRVUP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_CFG_CAL_DRVUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_CFG_CAL_DRVUP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_DAP2_SCLK_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register PADCTL_CONN_UART4_CTS_0
#define PADCTL_CONN_UART4_CTS_0                 _MK_ADDR_CONST(0x20)
#define PADCTL_CONN_UART4_CTS_0_SECURE                  0x0
#define PADCTL_CONN_UART4_CTS_0_DUAL                    0x0
#define PADCTL_CONN_UART4_CTS_0_SCR                     SCR_UART4_CTS_0
#define PADCTL_CONN_UART4_CTS_0_WORD_COUNT                      0x1
#define PADCTL_CONN_UART4_CTS_0_RESET_VAL                       _MK_MASK_CONST(0x458)
#define PADCTL_CONN_UART4_CTS_0_RESET_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_UART4_CTS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_CTS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_CTS_0_READ_MASK                       _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_UART4_CTS_0_WRITE_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_UART4_CTS_0_PM_SHIFT                        _MK_SHIFT_CONST(0)
#define PADCTL_CONN_UART4_CTS_0_PM_FIELD                        _MK_FIELD_CONST(0x3, PADCTL_CONN_UART4_CTS_0_PM_SHIFT)
#define PADCTL_CONN_UART4_CTS_0_PM_RANGE                        1:0
#define PADCTL_CONN_UART4_CTS_0_PM_WOFFSET                      0x0
#define PADCTL_CONN_UART4_CTS_0_PM_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_CTS_0_PM_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define PADCTL_CONN_UART4_CTS_0_PM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_CTS_0_PM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_CTS_0_PM_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_CTS_0_PM_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_CTS_0_PM_INIT_ENUM                    UARTD
#define PADCTL_CONN_UART4_CTS_0_PM_UARTD                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_CTS_0_PM_RSVD1                        _MK_ENUM_CONST(1)
#define PADCTL_CONN_UART4_CTS_0_PM_RSVD2                        _MK_ENUM_CONST(2)
#define PADCTL_CONN_UART4_CTS_0_PM_RSVD3                        _MK_ENUM_CONST(3)

#define PADCTL_CONN_UART4_CTS_0_GPIO_SF_SEL_SHIFT                       _MK_SHIFT_CONST(10)
#define PADCTL_CONN_UART4_CTS_0_GPIO_SF_SEL_FIELD                       _MK_FIELD_CONST(0x1, PADCTL_CONN_UART4_CTS_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_CONN_UART4_CTS_0_GPIO_SF_SEL_RANGE                       10:10
#define PADCTL_CONN_UART4_CTS_0_GPIO_SF_SEL_WOFFSET                     0x0
#define PADCTL_CONN_UART4_CTS_0_GPIO_SF_SEL_DEFAULT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_CTS_0_GPIO_SF_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_CTS_0_GPIO_SF_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_CTS_0_GPIO_SF_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_CTS_0_GPIO_SF_SEL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_CTS_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_CTS_0_GPIO_SF_SEL_INIT_ENUM                   SFIO
#define PADCTL_CONN_UART4_CTS_0_GPIO_SF_SEL_GPIO                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_CTS_0_GPIO_SF_SEL_SFIO                        _MK_ENUM_CONST(1)

#define PADCTL_CONN_UART4_CTS_0_TRISTATE_SHIFT                  _MK_SHIFT_CONST(4)
#define PADCTL_CONN_UART4_CTS_0_TRISTATE_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_CONN_UART4_CTS_0_TRISTATE_SHIFT)
#define PADCTL_CONN_UART4_CTS_0_TRISTATE_RANGE                  4:4
#define PADCTL_CONN_UART4_CTS_0_TRISTATE_WOFFSET                        0x0
#define PADCTL_CONN_UART4_CTS_0_TRISTATE_DEFAULT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_CTS_0_TRISTATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_CTS_0_TRISTATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_CTS_0_TRISTATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_CTS_0_TRISTATE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_CTS_0_TRISTATE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_CTS_0_TRISTATE_INIT_ENUM                      TRISTATE
#define PADCTL_CONN_UART4_CTS_0_TRISTATE_PASSTHROUGH                    _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_CTS_0_TRISTATE_TRISTATE                       _MK_ENUM_CONST(1)

#define PADCTL_CONN_UART4_CTS_0_PUPD_SHIFT                      _MK_SHIFT_CONST(2)
#define PADCTL_CONN_UART4_CTS_0_PUPD_FIELD                      _MK_FIELD_CONST(0x3, PADCTL_CONN_UART4_CTS_0_PUPD_SHIFT)
#define PADCTL_CONN_UART4_CTS_0_PUPD_RANGE                      3:2
#define PADCTL_CONN_UART4_CTS_0_PUPD_WOFFSET                    0x0
#define PADCTL_CONN_UART4_CTS_0_PUPD_DEFAULT                    _MK_MASK_CONST(0x2)
#define PADCTL_CONN_UART4_CTS_0_PUPD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define PADCTL_CONN_UART4_CTS_0_PUPD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_CTS_0_PUPD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_CTS_0_PUPD_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_CTS_0_PUPD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_CTS_0_PUPD_INIT_ENUM                  PULL_UP
#define PADCTL_CONN_UART4_CTS_0_PUPD_NONE                       _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_CTS_0_PUPD_PULL_DOWN                  _MK_ENUM_CONST(1)
#define PADCTL_CONN_UART4_CTS_0_PUPD_PULL_UP                    _MK_ENUM_CONST(2)
#define PADCTL_CONN_UART4_CTS_0_PUPD_RSVD                       _MK_ENUM_CONST(3)

#define PADCTL_CONN_UART4_CTS_0_E_INPUT_SHIFT                   _MK_SHIFT_CONST(6)
#define PADCTL_CONN_UART4_CTS_0_E_INPUT_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_CONN_UART4_CTS_0_E_INPUT_SHIFT)
#define PADCTL_CONN_UART4_CTS_0_E_INPUT_RANGE                   6:6
#define PADCTL_CONN_UART4_CTS_0_E_INPUT_WOFFSET                 0x0
#define PADCTL_CONN_UART4_CTS_0_E_INPUT_DEFAULT                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_CTS_0_E_INPUT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_CTS_0_E_INPUT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_CTS_0_E_INPUT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_CTS_0_E_INPUT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_CTS_0_E_INPUT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_CTS_0_E_INPUT_INIT_ENUM                       ENABLE
#define PADCTL_CONN_UART4_CTS_0_E_INPUT_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_CTS_0_E_INPUT_ENABLE                  _MK_ENUM_CONST(1)

#define PADCTL_CONN_UART4_CTS_0_E_LPDR_SHIFT                    _MK_SHIFT_CONST(8)
#define PADCTL_CONN_UART4_CTS_0_E_LPDR_FIELD                    _MK_FIELD_CONST(0x1, PADCTL_CONN_UART4_CTS_0_E_LPDR_SHIFT)
#define PADCTL_CONN_UART4_CTS_0_E_LPDR_RANGE                    8:8
#define PADCTL_CONN_UART4_CTS_0_E_LPDR_WOFFSET                  0x0
#define PADCTL_CONN_UART4_CTS_0_E_LPDR_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_CTS_0_E_LPDR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_CTS_0_E_LPDR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_CTS_0_E_LPDR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_CTS_0_E_LPDR_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_CTS_0_E_LPDR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_CTS_0_E_LPDR_INIT_ENUM                        DISABLE
#define PADCTL_CONN_UART4_CTS_0_E_LPDR_DISABLE                  _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_CTS_0_E_LPDR_ENABLE                   _MK_ENUM_CONST(1)

#define PADCTL_CONN_UART4_CTS_0_E_SCHMT_SHIFT                   _MK_SHIFT_CONST(12)
#define PADCTL_CONN_UART4_CTS_0_E_SCHMT_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_CONN_UART4_CTS_0_E_SCHMT_SHIFT)
#define PADCTL_CONN_UART4_CTS_0_E_SCHMT_RANGE                   12:12
#define PADCTL_CONN_UART4_CTS_0_E_SCHMT_WOFFSET                 0x0
#define PADCTL_CONN_UART4_CTS_0_E_SCHMT_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_CTS_0_E_SCHMT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_CTS_0_E_SCHMT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_CTS_0_E_SCHMT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_CTS_0_E_SCHMT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_CTS_0_E_SCHMT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_CTS_0_E_SCHMT_INIT_ENUM                       DISABLE
#define PADCTL_CONN_UART4_CTS_0_E_SCHMT_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_CTS_0_E_SCHMT_ENABLE                  _MK_ENUM_CONST(1)


// Register PADCTL_CONN_CFG2TMC_UART4_CTS_0
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0                 _MK_ADDR_CONST(0x24)
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_SECURE                  0x0
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_DUAL                    0x0
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_SCR                     SCR_UART4_CTS_0
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_WORD_COUNT                      0x1
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_RESET_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_READ_MASK                       _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_WRITE_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_CFG_CAL_DRVDN_SHIFT                     _MK_SHIFT_CONST(12)
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_CFG_CAL_DRVDN_FIELD                     _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_UART4_CTS_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_CFG_CAL_DRVDN_RANGE                     16:12
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_CFG_CAL_DRVDN_WOFFSET                   0x0
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_CFG_CAL_DRVDN_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_CFG_CAL_DRVDN_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_CFG_CAL_DRVDN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_CFG_CAL_DRVDN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_CFG_CAL_DRVUP_SHIFT                     _MK_SHIFT_CONST(20)
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_CFG_CAL_DRVUP_FIELD                     _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_UART4_CTS_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_CFG_CAL_DRVUP_RANGE                     24:20
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_CFG_CAL_DRVUP_WOFFSET                   0x0
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_CFG_CAL_DRVUP_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_CFG_CAL_DRVUP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_CFG_CAL_DRVUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_CFG_CAL_DRVUP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_CTS_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register PADCTL_CONN_UART4_RTS_0
#define PADCTL_CONN_UART4_RTS_0                 _MK_ADDR_CONST(0x28)
#define PADCTL_CONN_UART4_RTS_0_SECURE                  0x0
#define PADCTL_CONN_UART4_RTS_0_DUAL                    0x0
#define PADCTL_CONN_UART4_RTS_0_SCR                     SCR_UART4_RTS_0
#define PADCTL_CONN_UART4_RTS_0_WORD_COUNT                      0x1
#define PADCTL_CONN_UART4_RTS_0_RESET_VAL                       _MK_MASK_CONST(0x414)
#define PADCTL_CONN_UART4_RTS_0_RESET_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_UART4_RTS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RTS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RTS_0_READ_MASK                       _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_UART4_RTS_0_WRITE_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_UART4_RTS_0_PM_SHIFT                        _MK_SHIFT_CONST(0)
#define PADCTL_CONN_UART4_RTS_0_PM_FIELD                        _MK_FIELD_CONST(0x3, PADCTL_CONN_UART4_RTS_0_PM_SHIFT)
#define PADCTL_CONN_UART4_RTS_0_PM_RANGE                        1:0
#define PADCTL_CONN_UART4_RTS_0_PM_WOFFSET                      0x0
#define PADCTL_CONN_UART4_RTS_0_PM_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RTS_0_PM_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define PADCTL_CONN_UART4_RTS_0_PM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RTS_0_PM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RTS_0_PM_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RTS_0_PM_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RTS_0_PM_INIT_ENUM                    UARTD
#define PADCTL_CONN_UART4_RTS_0_PM_UARTD                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_RTS_0_PM_RSVD1                        _MK_ENUM_CONST(1)
#define PADCTL_CONN_UART4_RTS_0_PM_RSVD2                        _MK_ENUM_CONST(2)
#define PADCTL_CONN_UART4_RTS_0_PM_RSVD3                        _MK_ENUM_CONST(3)

#define PADCTL_CONN_UART4_RTS_0_GPIO_SF_SEL_SHIFT                       _MK_SHIFT_CONST(10)
#define PADCTL_CONN_UART4_RTS_0_GPIO_SF_SEL_FIELD                       _MK_FIELD_CONST(0x1, PADCTL_CONN_UART4_RTS_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_CONN_UART4_RTS_0_GPIO_SF_SEL_RANGE                       10:10
#define PADCTL_CONN_UART4_RTS_0_GPIO_SF_SEL_WOFFSET                     0x0
#define PADCTL_CONN_UART4_RTS_0_GPIO_SF_SEL_DEFAULT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RTS_0_GPIO_SF_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RTS_0_GPIO_SF_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RTS_0_GPIO_SF_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RTS_0_GPIO_SF_SEL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RTS_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RTS_0_GPIO_SF_SEL_INIT_ENUM                   SFIO
#define PADCTL_CONN_UART4_RTS_0_GPIO_SF_SEL_GPIO                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_RTS_0_GPIO_SF_SEL_SFIO                        _MK_ENUM_CONST(1)

#define PADCTL_CONN_UART4_RTS_0_TRISTATE_SHIFT                  _MK_SHIFT_CONST(4)
#define PADCTL_CONN_UART4_RTS_0_TRISTATE_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_CONN_UART4_RTS_0_TRISTATE_SHIFT)
#define PADCTL_CONN_UART4_RTS_0_TRISTATE_RANGE                  4:4
#define PADCTL_CONN_UART4_RTS_0_TRISTATE_WOFFSET                        0x0
#define PADCTL_CONN_UART4_RTS_0_TRISTATE_DEFAULT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RTS_0_TRISTATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RTS_0_TRISTATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RTS_0_TRISTATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RTS_0_TRISTATE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RTS_0_TRISTATE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RTS_0_TRISTATE_INIT_ENUM                      TRISTATE
#define PADCTL_CONN_UART4_RTS_0_TRISTATE_PASSTHROUGH                    _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_RTS_0_TRISTATE_TRISTATE                       _MK_ENUM_CONST(1)

#define PADCTL_CONN_UART4_RTS_0_PUPD_SHIFT                      _MK_SHIFT_CONST(2)
#define PADCTL_CONN_UART4_RTS_0_PUPD_FIELD                      _MK_FIELD_CONST(0x3, PADCTL_CONN_UART4_RTS_0_PUPD_SHIFT)
#define PADCTL_CONN_UART4_RTS_0_PUPD_RANGE                      3:2
#define PADCTL_CONN_UART4_RTS_0_PUPD_WOFFSET                    0x0
#define PADCTL_CONN_UART4_RTS_0_PUPD_DEFAULT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RTS_0_PUPD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define PADCTL_CONN_UART4_RTS_0_PUPD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RTS_0_PUPD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RTS_0_PUPD_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RTS_0_PUPD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RTS_0_PUPD_INIT_ENUM                  PULL_DOWN
#define PADCTL_CONN_UART4_RTS_0_PUPD_NONE                       _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_RTS_0_PUPD_PULL_DOWN                  _MK_ENUM_CONST(1)
#define PADCTL_CONN_UART4_RTS_0_PUPD_PULL_UP                    _MK_ENUM_CONST(2)
#define PADCTL_CONN_UART4_RTS_0_PUPD_RSVD                       _MK_ENUM_CONST(3)

#define PADCTL_CONN_UART4_RTS_0_E_INPUT_SHIFT                   _MK_SHIFT_CONST(6)
#define PADCTL_CONN_UART4_RTS_0_E_INPUT_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_CONN_UART4_RTS_0_E_INPUT_SHIFT)
#define PADCTL_CONN_UART4_RTS_0_E_INPUT_RANGE                   6:6
#define PADCTL_CONN_UART4_RTS_0_E_INPUT_WOFFSET                 0x0
#define PADCTL_CONN_UART4_RTS_0_E_INPUT_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RTS_0_E_INPUT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RTS_0_E_INPUT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RTS_0_E_INPUT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RTS_0_E_INPUT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RTS_0_E_INPUT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RTS_0_E_INPUT_INIT_ENUM                       DISABLE
#define PADCTL_CONN_UART4_RTS_0_E_INPUT_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_RTS_0_E_INPUT_ENABLE                  _MK_ENUM_CONST(1)

#define PADCTL_CONN_UART4_RTS_0_E_LPDR_SHIFT                    _MK_SHIFT_CONST(8)
#define PADCTL_CONN_UART4_RTS_0_E_LPDR_FIELD                    _MK_FIELD_CONST(0x1, PADCTL_CONN_UART4_RTS_0_E_LPDR_SHIFT)
#define PADCTL_CONN_UART4_RTS_0_E_LPDR_RANGE                    8:8
#define PADCTL_CONN_UART4_RTS_0_E_LPDR_WOFFSET                  0x0
#define PADCTL_CONN_UART4_RTS_0_E_LPDR_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RTS_0_E_LPDR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RTS_0_E_LPDR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RTS_0_E_LPDR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RTS_0_E_LPDR_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RTS_0_E_LPDR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RTS_0_E_LPDR_INIT_ENUM                        DISABLE
#define PADCTL_CONN_UART4_RTS_0_E_LPDR_DISABLE                  _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_RTS_0_E_LPDR_ENABLE                   _MK_ENUM_CONST(1)

#define PADCTL_CONN_UART4_RTS_0_E_SCHMT_SHIFT                   _MK_SHIFT_CONST(12)
#define PADCTL_CONN_UART4_RTS_0_E_SCHMT_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_CONN_UART4_RTS_0_E_SCHMT_SHIFT)
#define PADCTL_CONN_UART4_RTS_0_E_SCHMT_RANGE                   12:12
#define PADCTL_CONN_UART4_RTS_0_E_SCHMT_WOFFSET                 0x0
#define PADCTL_CONN_UART4_RTS_0_E_SCHMT_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RTS_0_E_SCHMT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RTS_0_E_SCHMT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RTS_0_E_SCHMT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RTS_0_E_SCHMT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RTS_0_E_SCHMT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RTS_0_E_SCHMT_INIT_ENUM                       DISABLE
#define PADCTL_CONN_UART4_RTS_0_E_SCHMT_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_RTS_0_E_SCHMT_ENABLE                  _MK_ENUM_CONST(1)


// Register PADCTL_CONN_CFG2TMC_UART4_RTS_0
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0                 _MK_ADDR_CONST(0x2c)
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_SECURE                  0x0
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_DUAL                    0x0
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_SCR                     SCR_UART4_RTS_0
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_WORD_COUNT                      0x1
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_RESET_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_READ_MASK                       _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_WRITE_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_CFG_CAL_DRVDN_SHIFT                     _MK_SHIFT_CONST(12)
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_CFG_CAL_DRVDN_FIELD                     _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_UART4_RTS_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_CFG_CAL_DRVDN_RANGE                     16:12
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_CFG_CAL_DRVDN_WOFFSET                   0x0
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_CFG_CAL_DRVDN_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_CFG_CAL_DRVDN_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_CFG_CAL_DRVDN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_CFG_CAL_DRVDN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_CFG_CAL_DRVUP_SHIFT                     _MK_SHIFT_CONST(20)
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_CFG_CAL_DRVUP_FIELD                     _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_UART4_RTS_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_CFG_CAL_DRVUP_RANGE                     24:20
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_CFG_CAL_DRVUP_WOFFSET                   0x0
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_CFG_CAL_DRVUP_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_CFG_CAL_DRVUP_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_CFG_CAL_DRVUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_CFG_CAL_DRVUP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_RTS_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register PADCTL_CONN_UART4_RX_0
#define PADCTL_CONN_UART4_RX_0                  _MK_ADDR_CONST(0x30)
#define PADCTL_CONN_UART4_RX_0_SECURE                   0x0
#define PADCTL_CONN_UART4_RX_0_DUAL                     0x0
#define PADCTL_CONN_UART4_RX_0_SCR                      SCR_UART4_RX_0
#define PADCTL_CONN_UART4_RX_0_WORD_COUNT                       0x1
#define PADCTL_CONN_UART4_RX_0_RESET_VAL                        _MK_MASK_CONST(0x454)
#define PADCTL_CONN_UART4_RX_0_RESET_MASK                       _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_UART4_RX_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RX_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RX_0_READ_MASK                        _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_UART4_RX_0_WRITE_MASK                       _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_UART4_RX_0_PM_SHIFT                 _MK_SHIFT_CONST(0)
#define PADCTL_CONN_UART4_RX_0_PM_FIELD                 _MK_FIELD_CONST(0x3, PADCTL_CONN_UART4_RX_0_PM_SHIFT)
#define PADCTL_CONN_UART4_RX_0_PM_RANGE                 1:0
#define PADCTL_CONN_UART4_RX_0_PM_WOFFSET                       0x0
#define PADCTL_CONN_UART4_RX_0_PM_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RX_0_PM_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define PADCTL_CONN_UART4_RX_0_PM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RX_0_PM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RX_0_PM_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RX_0_PM_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RX_0_PM_INIT_ENUM                     UARTD
#define PADCTL_CONN_UART4_RX_0_PM_UARTD                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_RX_0_PM_RSVD1                 _MK_ENUM_CONST(1)
#define PADCTL_CONN_UART4_RX_0_PM_RSVD2                 _MK_ENUM_CONST(2)
#define PADCTL_CONN_UART4_RX_0_PM_RSVD3                 _MK_ENUM_CONST(3)

#define PADCTL_CONN_UART4_RX_0_GPIO_SF_SEL_SHIFT                        _MK_SHIFT_CONST(10)
#define PADCTL_CONN_UART4_RX_0_GPIO_SF_SEL_FIELD                        _MK_FIELD_CONST(0x1, PADCTL_CONN_UART4_RX_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_CONN_UART4_RX_0_GPIO_SF_SEL_RANGE                        10:10
#define PADCTL_CONN_UART4_RX_0_GPIO_SF_SEL_WOFFSET                      0x0
#define PADCTL_CONN_UART4_RX_0_GPIO_SF_SEL_DEFAULT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RX_0_GPIO_SF_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RX_0_GPIO_SF_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RX_0_GPIO_SF_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RX_0_GPIO_SF_SEL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RX_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RX_0_GPIO_SF_SEL_INIT_ENUM                    SFIO
#define PADCTL_CONN_UART4_RX_0_GPIO_SF_SEL_GPIO                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_RX_0_GPIO_SF_SEL_SFIO                 _MK_ENUM_CONST(1)

#define PADCTL_CONN_UART4_RX_0_TRISTATE_SHIFT                   _MK_SHIFT_CONST(4)
#define PADCTL_CONN_UART4_RX_0_TRISTATE_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_CONN_UART4_RX_0_TRISTATE_SHIFT)
#define PADCTL_CONN_UART4_RX_0_TRISTATE_RANGE                   4:4
#define PADCTL_CONN_UART4_RX_0_TRISTATE_WOFFSET                 0x0
#define PADCTL_CONN_UART4_RX_0_TRISTATE_DEFAULT                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RX_0_TRISTATE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RX_0_TRISTATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RX_0_TRISTATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RX_0_TRISTATE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RX_0_TRISTATE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RX_0_TRISTATE_INIT_ENUM                       TRISTATE
#define PADCTL_CONN_UART4_RX_0_TRISTATE_PASSTHROUGH                     _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_RX_0_TRISTATE_TRISTATE                        _MK_ENUM_CONST(1)

#define PADCTL_CONN_UART4_RX_0_PUPD_SHIFT                       _MK_SHIFT_CONST(2)
#define PADCTL_CONN_UART4_RX_0_PUPD_FIELD                       _MK_FIELD_CONST(0x3, PADCTL_CONN_UART4_RX_0_PUPD_SHIFT)
#define PADCTL_CONN_UART4_RX_0_PUPD_RANGE                       3:2
#define PADCTL_CONN_UART4_RX_0_PUPD_WOFFSET                     0x0
#define PADCTL_CONN_UART4_RX_0_PUPD_DEFAULT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RX_0_PUPD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define PADCTL_CONN_UART4_RX_0_PUPD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RX_0_PUPD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RX_0_PUPD_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RX_0_PUPD_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RX_0_PUPD_INIT_ENUM                   PULL_DOWN
#define PADCTL_CONN_UART4_RX_0_PUPD_NONE                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_RX_0_PUPD_PULL_DOWN                   _MK_ENUM_CONST(1)
#define PADCTL_CONN_UART4_RX_0_PUPD_PULL_UP                     _MK_ENUM_CONST(2)
#define PADCTL_CONN_UART4_RX_0_PUPD_RSVD                        _MK_ENUM_CONST(3)

#define PADCTL_CONN_UART4_RX_0_E_INPUT_SHIFT                    _MK_SHIFT_CONST(6)
#define PADCTL_CONN_UART4_RX_0_E_INPUT_FIELD                    _MK_FIELD_CONST(0x1, PADCTL_CONN_UART4_RX_0_E_INPUT_SHIFT)
#define PADCTL_CONN_UART4_RX_0_E_INPUT_RANGE                    6:6
#define PADCTL_CONN_UART4_RX_0_E_INPUT_WOFFSET                  0x0
#define PADCTL_CONN_UART4_RX_0_E_INPUT_DEFAULT                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RX_0_E_INPUT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RX_0_E_INPUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RX_0_E_INPUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RX_0_E_INPUT_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RX_0_E_INPUT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RX_0_E_INPUT_INIT_ENUM                        ENABLE
#define PADCTL_CONN_UART4_RX_0_E_INPUT_DISABLE                  _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_RX_0_E_INPUT_ENABLE                   _MK_ENUM_CONST(1)

#define PADCTL_CONN_UART4_RX_0_E_LPDR_SHIFT                     _MK_SHIFT_CONST(8)
#define PADCTL_CONN_UART4_RX_0_E_LPDR_FIELD                     _MK_FIELD_CONST(0x1, PADCTL_CONN_UART4_RX_0_E_LPDR_SHIFT)
#define PADCTL_CONN_UART4_RX_0_E_LPDR_RANGE                     8:8
#define PADCTL_CONN_UART4_RX_0_E_LPDR_WOFFSET                   0x0
#define PADCTL_CONN_UART4_RX_0_E_LPDR_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RX_0_E_LPDR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RX_0_E_LPDR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RX_0_E_LPDR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RX_0_E_LPDR_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RX_0_E_LPDR_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RX_0_E_LPDR_INIT_ENUM                 DISABLE
#define PADCTL_CONN_UART4_RX_0_E_LPDR_DISABLE                   _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_RX_0_E_LPDR_ENABLE                    _MK_ENUM_CONST(1)

#define PADCTL_CONN_UART4_RX_0_E_SCHMT_SHIFT                    _MK_SHIFT_CONST(12)
#define PADCTL_CONN_UART4_RX_0_E_SCHMT_FIELD                    _MK_FIELD_CONST(0x1, PADCTL_CONN_UART4_RX_0_E_SCHMT_SHIFT)
#define PADCTL_CONN_UART4_RX_0_E_SCHMT_RANGE                    12:12
#define PADCTL_CONN_UART4_RX_0_E_SCHMT_WOFFSET                  0x0
#define PADCTL_CONN_UART4_RX_0_E_SCHMT_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RX_0_E_SCHMT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RX_0_E_SCHMT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RX_0_E_SCHMT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RX_0_E_SCHMT_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_RX_0_E_SCHMT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_RX_0_E_SCHMT_INIT_ENUM                        DISABLE
#define PADCTL_CONN_UART4_RX_0_E_SCHMT_DISABLE                  _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_RX_0_E_SCHMT_ENABLE                   _MK_ENUM_CONST(1)


// Register PADCTL_CONN_CFG2TMC_UART4_RX_0
#define PADCTL_CONN_CFG2TMC_UART4_RX_0                  _MK_ADDR_CONST(0x34)
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_SECURE                   0x0
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_DUAL                     0x0
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_SCR                      SCR_UART4_RX_0
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_WORD_COUNT                       0x1
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_RESET_MASK                       _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_READ_MASK                        _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_WRITE_MASK                       _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_CFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_CFG_CAL_DRVDN_FIELD                      _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_UART4_RX_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_CFG_CAL_DRVDN_RANGE                      16:12
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_CFG_CAL_DRVDN_WOFFSET                    0x0
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_CFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_CFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_CFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_CFG_CAL_DRVDN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define PADCTL_CONN_CFG2TMC_UART4_RX_0_CFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_CFG_CAL_DRVUP_FIELD                      _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_UART4_RX_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_CFG_CAL_DRVUP_RANGE                      24:20
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_CFG_CAL_DRVUP_WOFFSET                    0x0
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_CFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_CFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_CFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_CFG_CAL_DRVUP_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_RX_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register PADCTL_CONN_UART4_TX_0
#define PADCTL_CONN_UART4_TX_0                  _MK_ADDR_CONST(0x38)
#define PADCTL_CONN_UART4_TX_0_SECURE                   0x0
#define PADCTL_CONN_UART4_TX_0_DUAL                     0x0
#define PADCTL_CONN_UART4_TX_0_SCR                      SCR_UART4_TX_0
#define PADCTL_CONN_UART4_TX_0_WORD_COUNT                       0x1
#define PADCTL_CONN_UART4_TX_0_RESET_VAL                        _MK_MASK_CONST(0x414)
#define PADCTL_CONN_UART4_TX_0_RESET_MASK                       _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_UART4_TX_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_TX_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_TX_0_READ_MASK                        _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_UART4_TX_0_WRITE_MASK                       _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_UART4_TX_0_PM_SHIFT                 _MK_SHIFT_CONST(0)
#define PADCTL_CONN_UART4_TX_0_PM_FIELD                 _MK_FIELD_CONST(0x3, PADCTL_CONN_UART4_TX_0_PM_SHIFT)
#define PADCTL_CONN_UART4_TX_0_PM_RANGE                 1:0
#define PADCTL_CONN_UART4_TX_0_PM_WOFFSET                       0x0
#define PADCTL_CONN_UART4_TX_0_PM_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_TX_0_PM_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define PADCTL_CONN_UART4_TX_0_PM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_TX_0_PM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_TX_0_PM_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_TX_0_PM_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_TX_0_PM_INIT_ENUM                     UARTD
#define PADCTL_CONN_UART4_TX_0_PM_UARTD                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_TX_0_PM_RSVD1                 _MK_ENUM_CONST(1)
#define PADCTL_CONN_UART4_TX_0_PM_RSVD2                 _MK_ENUM_CONST(2)
#define PADCTL_CONN_UART4_TX_0_PM_RSVD3                 _MK_ENUM_CONST(3)

#define PADCTL_CONN_UART4_TX_0_GPIO_SF_SEL_SHIFT                        _MK_SHIFT_CONST(10)
#define PADCTL_CONN_UART4_TX_0_GPIO_SF_SEL_FIELD                        _MK_FIELD_CONST(0x1, PADCTL_CONN_UART4_TX_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_CONN_UART4_TX_0_GPIO_SF_SEL_RANGE                        10:10
#define PADCTL_CONN_UART4_TX_0_GPIO_SF_SEL_WOFFSET                      0x0
#define PADCTL_CONN_UART4_TX_0_GPIO_SF_SEL_DEFAULT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_TX_0_GPIO_SF_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_TX_0_GPIO_SF_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_TX_0_GPIO_SF_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_TX_0_GPIO_SF_SEL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_TX_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_TX_0_GPIO_SF_SEL_INIT_ENUM                    SFIO
#define PADCTL_CONN_UART4_TX_0_GPIO_SF_SEL_GPIO                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_TX_0_GPIO_SF_SEL_SFIO                 _MK_ENUM_CONST(1)

#define PADCTL_CONN_UART4_TX_0_TRISTATE_SHIFT                   _MK_SHIFT_CONST(4)
#define PADCTL_CONN_UART4_TX_0_TRISTATE_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_CONN_UART4_TX_0_TRISTATE_SHIFT)
#define PADCTL_CONN_UART4_TX_0_TRISTATE_RANGE                   4:4
#define PADCTL_CONN_UART4_TX_0_TRISTATE_WOFFSET                 0x0
#define PADCTL_CONN_UART4_TX_0_TRISTATE_DEFAULT                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_TX_0_TRISTATE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_TX_0_TRISTATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_TX_0_TRISTATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_TX_0_TRISTATE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_TX_0_TRISTATE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_TX_0_TRISTATE_INIT_ENUM                       TRISTATE
#define PADCTL_CONN_UART4_TX_0_TRISTATE_PASSTHROUGH                     _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_TX_0_TRISTATE_TRISTATE                        _MK_ENUM_CONST(1)

#define PADCTL_CONN_UART4_TX_0_PUPD_SHIFT                       _MK_SHIFT_CONST(2)
#define PADCTL_CONN_UART4_TX_0_PUPD_FIELD                       _MK_FIELD_CONST(0x3, PADCTL_CONN_UART4_TX_0_PUPD_SHIFT)
#define PADCTL_CONN_UART4_TX_0_PUPD_RANGE                       3:2
#define PADCTL_CONN_UART4_TX_0_PUPD_WOFFSET                     0x0
#define PADCTL_CONN_UART4_TX_0_PUPD_DEFAULT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_TX_0_PUPD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define PADCTL_CONN_UART4_TX_0_PUPD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_TX_0_PUPD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_TX_0_PUPD_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_TX_0_PUPD_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_TX_0_PUPD_INIT_ENUM                   PULL_DOWN
#define PADCTL_CONN_UART4_TX_0_PUPD_NONE                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_TX_0_PUPD_PULL_DOWN                   _MK_ENUM_CONST(1)
#define PADCTL_CONN_UART4_TX_0_PUPD_PULL_UP                     _MK_ENUM_CONST(2)
#define PADCTL_CONN_UART4_TX_0_PUPD_RSVD                        _MK_ENUM_CONST(3)

#define PADCTL_CONN_UART4_TX_0_E_INPUT_SHIFT                    _MK_SHIFT_CONST(6)
#define PADCTL_CONN_UART4_TX_0_E_INPUT_FIELD                    _MK_FIELD_CONST(0x1, PADCTL_CONN_UART4_TX_0_E_INPUT_SHIFT)
#define PADCTL_CONN_UART4_TX_0_E_INPUT_RANGE                    6:6
#define PADCTL_CONN_UART4_TX_0_E_INPUT_WOFFSET                  0x0
#define PADCTL_CONN_UART4_TX_0_E_INPUT_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_TX_0_E_INPUT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_TX_0_E_INPUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_TX_0_E_INPUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_TX_0_E_INPUT_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_TX_0_E_INPUT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_TX_0_E_INPUT_INIT_ENUM                        DISABLE
#define PADCTL_CONN_UART4_TX_0_E_INPUT_DISABLE                  _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_TX_0_E_INPUT_ENABLE                   _MK_ENUM_CONST(1)

#define PADCTL_CONN_UART4_TX_0_E_LPDR_SHIFT                     _MK_SHIFT_CONST(8)
#define PADCTL_CONN_UART4_TX_0_E_LPDR_FIELD                     _MK_FIELD_CONST(0x1, PADCTL_CONN_UART4_TX_0_E_LPDR_SHIFT)
#define PADCTL_CONN_UART4_TX_0_E_LPDR_RANGE                     8:8
#define PADCTL_CONN_UART4_TX_0_E_LPDR_WOFFSET                   0x0
#define PADCTL_CONN_UART4_TX_0_E_LPDR_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_TX_0_E_LPDR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_TX_0_E_LPDR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_TX_0_E_LPDR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_TX_0_E_LPDR_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_TX_0_E_LPDR_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_TX_0_E_LPDR_INIT_ENUM                 DISABLE
#define PADCTL_CONN_UART4_TX_0_E_LPDR_DISABLE                   _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_TX_0_E_LPDR_ENABLE                    _MK_ENUM_CONST(1)

#define PADCTL_CONN_UART4_TX_0_E_SCHMT_SHIFT                    _MK_SHIFT_CONST(12)
#define PADCTL_CONN_UART4_TX_0_E_SCHMT_FIELD                    _MK_FIELD_CONST(0x1, PADCTL_CONN_UART4_TX_0_E_SCHMT_SHIFT)
#define PADCTL_CONN_UART4_TX_0_E_SCHMT_RANGE                    12:12
#define PADCTL_CONN_UART4_TX_0_E_SCHMT_WOFFSET                  0x0
#define PADCTL_CONN_UART4_TX_0_E_SCHMT_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_TX_0_E_SCHMT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_TX_0_E_SCHMT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_TX_0_E_SCHMT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_TX_0_E_SCHMT_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_UART4_TX_0_E_SCHMT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_UART4_TX_0_E_SCHMT_INIT_ENUM                        DISABLE
#define PADCTL_CONN_UART4_TX_0_E_SCHMT_DISABLE                  _MK_ENUM_CONST(0)
#define PADCTL_CONN_UART4_TX_0_E_SCHMT_ENABLE                   _MK_ENUM_CONST(1)


// Register PADCTL_CONN_CFG2TMC_UART4_TX_0
#define PADCTL_CONN_CFG2TMC_UART4_TX_0                  _MK_ADDR_CONST(0x3c)
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_SECURE                   0x0
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_DUAL                     0x0
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_SCR                      SCR_UART4_TX_0
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_WORD_COUNT                       0x1
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_RESET_MASK                       _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_READ_MASK                        _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_WRITE_MASK                       _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_CFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_CFG_CAL_DRVDN_FIELD                      _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_UART4_TX_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_CFG_CAL_DRVDN_RANGE                      16:12
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_CFG_CAL_DRVDN_WOFFSET                    0x0
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_CFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_CFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_CFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_CFG_CAL_DRVDN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define PADCTL_CONN_CFG2TMC_UART4_TX_0_CFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_CFG_CAL_DRVUP_FIELD                      _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_UART4_TX_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_CFG_CAL_DRVUP_RANGE                      24:20
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_CFG_CAL_DRVUP_WOFFSET                    0x0
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_CFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_CFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_CFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_CFG_CAL_DRVUP_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_UART4_TX_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register PADCTL_CONN_SOC_GPIO03_0
#define PADCTL_CONN_SOC_GPIO03_0                        _MK_ADDR_CONST(0x40)
#define PADCTL_CONN_SOC_GPIO03_0_SECURE                         0x0
#define PADCTL_CONN_SOC_GPIO03_0_DUAL                   0x0
#define PADCTL_CONN_SOC_GPIO03_0_SCR                    SCR_SOC_GPIO03_0
#define PADCTL_CONN_SOC_GPIO03_0_WORD_COUNT                     0x1
#define PADCTL_CONN_SOC_GPIO03_0_RESET_VAL                      _MK_MASK_CONST(0x458)
#define PADCTL_CONN_SOC_GPIO03_0_RESET_MASK                     _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO03_0_READ_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO03_0_WRITE_MASK                     _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO03_0_PM_SHIFT                       _MK_SHIFT_CONST(0)
#define PADCTL_CONN_SOC_GPIO03_0_PM_FIELD                       _MK_FIELD_CONST(0x3, PADCTL_CONN_SOC_GPIO03_0_PM_SHIFT)
#define PADCTL_CONN_SOC_GPIO03_0_PM_RANGE                       1:0
#define PADCTL_CONN_SOC_GPIO03_0_PM_WOFFSET                     0x0
#define PADCTL_CONN_SOC_GPIO03_0_PM_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO03_0_PM_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define PADCTL_CONN_SOC_GPIO03_0_PM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO03_0_PM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO03_0_PM_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO03_0_PM_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO03_0_PM_INIT_ENUM                   RSVD0
#define PADCTL_CONN_SOC_GPIO03_0_PM_RSVD0                       _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO03_0_PM_RSVD1                       _MK_ENUM_CONST(1)
#define PADCTL_CONN_SOC_GPIO03_0_PM_RSVD2                       _MK_ENUM_CONST(2)
#define PADCTL_CONN_SOC_GPIO03_0_PM_RSVD3                       _MK_ENUM_CONST(3)

#define PADCTL_CONN_SOC_GPIO03_0_GPIO_SF_SEL_SHIFT                      _MK_SHIFT_CONST(10)
#define PADCTL_CONN_SOC_GPIO03_0_GPIO_SF_SEL_FIELD                      _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO03_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_CONN_SOC_GPIO03_0_GPIO_SF_SEL_RANGE                      10:10
#define PADCTL_CONN_SOC_GPIO03_0_GPIO_SF_SEL_WOFFSET                    0x0
#define PADCTL_CONN_SOC_GPIO03_0_GPIO_SF_SEL_DEFAULT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO03_0_GPIO_SF_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO03_0_GPIO_SF_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO03_0_GPIO_SF_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO03_0_GPIO_SF_SEL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO03_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO03_0_GPIO_SF_SEL_INIT_ENUM                  SFIO
#define PADCTL_CONN_SOC_GPIO03_0_GPIO_SF_SEL_GPIO                       _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO03_0_GPIO_SF_SEL_SFIO                       _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO03_0_TRISTATE_SHIFT                 _MK_SHIFT_CONST(4)
#define PADCTL_CONN_SOC_GPIO03_0_TRISTATE_FIELD                 _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO03_0_TRISTATE_SHIFT)
#define PADCTL_CONN_SOC_GPIO03_0_TRISTATE_RANGE                 4:4
#define PADCTL_CONN_SOC_GPIO03_0_TRISTATE_WOFFSET                       0x0
#define PADCTL_CONN_SOC_GPIO03_0_TRISTATE_DEFAULT                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO03_0_TRISTATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO03_0_TRISTATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO03_0_TRISTATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO03_0_TRISTATE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO03_0_TRISTATE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO03_0_TRISTATE_INIT_ENUM                     TRISTATE
#define PADCTL_CONN_SOC_GPIO03_0_TRISTATE_PASSTHROUGH                   _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO03_0_TRISTATE_TRISTATE                      _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO03_0_PUPD_SHIFT                     _MK_SHIFT_CONST(2)
#define PADCTL_CONN_SOC_GPIO03_0_PUPD_FIELD                     _MK_FIELD_CONST(0x3, PADCTL_CONN_SOC_GPIO03_0_PUPD_SHIFT)
#define PADCTL_CONN_SOC_GPIO03_0_PUPD_RANGE                     3:2
#define PADCTL_CONN_SOC_GPIO03_0_PUPD_WOFFSET                   0x0
#define PADCTL_CONN_SOC_GPIO03_0_PUPD_DEFAULT                   _MK_MASK_CONST(0x2)
#define PADCTL_CONN_SOC_GPIO03_0_PUPD_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define PADCTL_CONN_SOC_GPIO03_0_PUPD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO03_0_PUPD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO03_0_PUPD_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO03_0_PUPD_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO03_0_PUPD_INIT_ENUM                 PULL_UP
#define PADCTL_CONN_SOC_GPIO03_0_PUPD_NONE                      _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO03_0_PUPD_PULL_DOWN                 _MK_ENUM_CONST(1)
#define PADCTL_CONN_SOC_GPIO03_0_PUPD_PULL_UP                   _MK_ENUM_CONST(2)
#define PADCTL_CONN_SOC_GPIO03_0_PUPD_RSVD                      _MK_ENUM_CONST(3)

#define PADCTL_CONN_SOC_GPIO03_0_E_INPUT_SHIFT                  _MK_SHIFT_CONST(6)
#define PADCTL_CONN_SOC_GPIO03_0_E_INPUT_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO03_0_E_INPUT_SHIFT)
#define PADCTL_CONN_SOC_GPIO03_0_E_INPUT_RANGE                  6:6
#define PADCTL_CONN_SOC_GPIO03_0_E_INPUT_WOFFSET                        0x0
#define PADCTL_CONN_SOC_GPIO03_0_E_INPUT_DEFAULT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO03_0_E_INPUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO03_0_E_INPUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO03_0_E_INPUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO03_0_E_INPUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO03_0_E_INPUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO03_0_E_INPUT_INIT_ENUM                      ENABLE
#define PADCTL_CONN_SOC_GPIO03_0_E_INPUT_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO03_0_E_INPUT_ENABLE                 _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO03_0_E_LPDR_SHIFT                   _MK_SHIFT_CONST(8)
#define PADCTL_CONN_SOC_GPIO03_0_E_LPDR_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO03_0_E_LPDR_SHIFT)
#define PADCTL_CONN_SOC_GPIO03_0_E_LPDR_RANGE                   8:8
#define PADCTL_CONN_SOC_GPIO03_0_E_LPDR_WOFFSET                 0x0
#define PADCTL_CONN_SOC_GPIO03_0_E_LPDR_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO03_0_E_LPDR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO03_0_E_LPDR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO03_0_E_LPDR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO03_0_E_LPDR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO03_0_E_LPDR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO03_0_E_LPDR_INIT_ENUM                       DISABLE
#define PADCTL_CONN_SOC_GPIO03_0_E_LPDR_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO03_0_E_LPDR_ENABLE                  _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO03_0_E_SCHMT_SHIFT                  _MK_SHIFT_CONST(12)
#define PADCTL_CONN_SOC_GPIO03_0_E_SCHMT_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO03_0_E_SCHMT_SHIFT)
#define PADCTL_CONN_SOC_GPIO03_0_E_SCHMT_RANGE                  12:12
#define PADCTL_CONN_SOC_GPIO03_0_E_SCHMT_WOFFSET                        0x0
#define PADCTL_CONN_SOC_GPIO03_0_E_SCHMT_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO03_0_E_SCHMT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO03_0_E_SCHMT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO03_0_E_SCHMT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO03_0_E_SCHMT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO03_0_E_SCHMT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO03_0_E_SCHMT_INIT_ENUM                      DISABLE
#define PADCTL_CONN_SOC_GPIO03_0_E_SCHMT_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO03_0_E_SCHMT_ENABLE                 _MK_ENUM_CONST(1)


// Register PADCTL_CONN_CFG2TMC_SOC_GPIO03_0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0                        _MK_ADDR_CONST(0x44)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_SECURE                         0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_DUAL                   0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_SCR                    SCR_SOC_GPIO03_0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_WORD_COUNT                     0x1
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_RESET_MASK                     _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_READ_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_WRITE_MASK                     _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_CFG_CAL_DRVDN_FIELD                    _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_CFG_CAL_DRVDN_RANGE                    16:12
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_CFG_CAL_DRVDN_WOFFSET                  0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_CFG_CAL_DRVDN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_CFG_CAL_DRVUP_FIELD                    _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_CFG_CAL_DRVUP_RANGE                    24:20
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_CFG_CAL_DRVUP_WOFFSET                  0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_CFG_CAL_DRVUP_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO03_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register PADCTL_CONN_SOC_GPIO02_0
#define PADCTL_CONN_SOC_GPIO02_0                        _MK_ADDR_CONST(0x48)
#define PADCTL_CONN_SOC_GPIO02_0_SECURE                         0x0
#define PADCTL_CONN_SOC_GPIO02_0_DUAL                   0x0
#define PADCTL_CONN_SOC_GPIO02_0_SCR                    SCR_SOC_GPIO02_0
#define PADCTL_CONN_SOC_GPIO02_0_WORD_COUNT                     0x1
#define PADCTL_CONN_SOC_GPIO02_0_RESET_VAL                      _MK_MASK_CONST(0x454)
#define PADCTL_CONN_SOC_GPIO02_0_RESET_MASK                     _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO02_0_READ_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO02_0_WRITE_MASK                     _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO02_0_PM_SHIFT                       _MK_SHIFT_CONST(0)
#define PADCTL_CONN_SOC_GPIO02_0_PM_FIELD                       _MK_FIELD_CONST(0x3, PADCTL_CONN_SOC_GPIO02_0_PM_SHIFT)
#define PADCTL_CONN_SOC_GPIO02_0_PM_RANGE                       1:0
#define PADCTL_CONN_SOC_GPIO02_0_PM_WOFFSET                     0x0
#define PADCTL_CONN_SOC_GPIO02_0_PM_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO02_0_PM_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define PADCTL_CONN_SOC_GPIO02_0_PM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO02_0_PM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO02_0_PM_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO02_0_PM_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO02_0_PM_INIT_ENUM                   RSVD0
#define PADCTL_CONN_SOC_GPIO02_0_PM_RSVD0                       _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO02_0_PM_RSVD1                       _MK_ENUM_CONST(1)
#define PADCTL_CONN_SOC_GPIO02_0_PM_RSVD2                       _MK_ENUM_CONST(2)
#define PADCTL_CONN_SOC_GPIO02_0_PM_RSVD3                       _MK_ENUM_CONST(3)

#define PADCTL_CONN_SOC_GPIO02_0_GPIO_SF_SEL_SHIFT                      _MK_SHIFT_CONST(10)
#define PADCTL_CONN_SOC_GPIO02_0_GPIO_SF_SEL_FIELD                      _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO02_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_CONN_SOC_GPIO02_0_GPIO_SF_SEL_RANGE                      10:10
#define PADCTL_CONN_SOC_GPIO02_0_GPIO_SF_SEL_WOFFSET                    0x0
#define PADCTL_CONN_SOC_GPIO02_0_GPIO_SF_SEL_DEFAULT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO02_0_GPIO_SF_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO02_0_GPIO_SF_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO02_0_GPIO_SF_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO02_0_GPIO_SF_SEL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO02_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO02_0_GPIO_SF_SEL_INIT_ENUM                  SFIO
#define PADCTL_CONN_SOC_GPIO02_0_GPIO_SF_SEL_GPIO                       _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO02_0_GPIO_SF_SEL_SFIO                       _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO02_0_TRISTATE_SHIFT                 _MK_SHIFT_CONST(4)
#define PADCTL_CONN_SOC_GPIO02_0_TRISTATE_FIELD                 _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO02_0_TRISTATE_SHIFT)
#define PADCTL_CONN_SOC_GPIO02_0_TRISTATE_RANGE                 4:4
#define PADCTL_CONN_SOC_GPIO02_0_TRISTATE_WOFFSET                       0x0
#define PADCTL_CONN_SOC_GPIO02_0_TRISTATE_DEFAULT                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO02_0_TRISTATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO02_0_TRISTATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO02_0_TRISTATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO02_0_TRISTATE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO02_0_TRISTATE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO02_0_TRISTATE_INIT_ENUM                     TRISTATE
#define PADCTL_CONN_SOC_GPIO02_0_TRISTATE_PASSTHROUGH                   _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO02_0_TRISTATE_TRISTATE                      _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO02_0_PUPD_SHIFT                     _MK_SHIFT_CONST(2)
#define PADCTL_CONN_SOC_GPIO02_0_PUPD_FIELD                     _MK_FIELD_CONST(0x3, PADCTL_CONN_SOC_GPIO02_0_PUPD_SHIFT)
#define PADCTL_CONN_SOC_GPIO02_0_PUPD_RANGE                     3:2
#define PADCTL_CONN_SOC_GPIO02_0_PUPD_WOFFSET                   0x0
#define PADCTL_CONN_SOC_GPIO02_0_PUPD_DEFAULT                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO02_0_PUPD_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define PADCTL_CONN_SOC_GPIO02_0_PUPD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO02_0_PUPD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO02_0_PUPD_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO02_0_PUPD_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO02_0_PUPD_INIT_ENUM                 PULL_DOWN
#define PADCTL_CONN_SOC_GPIO02_0_PUPD_NONE                      _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO02_0_PUPD_PULL_DOWN                 _MK_ENUM_CONST(1)
#define PADCTL_CONN_SOC_GPIO02_0_PUPD_PULL_UP                   _MK_ENUM_CONST(2)
#define PADCTL_CONN_SOC_GPIO02_0_PUPD_RSVD                      _MK_ENUM_CONST(3)

#define PADCTL_CONN_SOC_GPIO02_0_E_INPUT_SHIFT                  _MK_SHIFT_CONST(6)
#define PADCTL_CONN_SOC_GPIO02_0_E_INPUT_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO02_0_E_INPUT_SHIFT)
#define PADCTL_CONN_SOC_GPIO02_0_E_INPUT_RANGE                  6:6
#define PADCTL_CONN_SOC_GPIO02_0_E_INPUT_WOFFSET                        0x0
#define PADCTL_CONN_SOC_GPIO02_0_E_INPUT_DEFAULT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO02_0_E_INPUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO02_0_E_INPUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO02_0_E_INPUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO02_0_E_INPUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO02_0_E_INPUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO02_0_E_INPUT_INIT_ENUM                      ENABLE
#define PADCTL_CONN_SOC_GPIO02_0_E_INPUT_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO02_0_E_INPUT_ENABLE                 _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO02_0_E_LPDR_SHIFT                   _MK_SHIFT_CONST(8)
#define PADCTL_CONN_SOC_GPIO02_0_E_LPDR_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO02_0_E_LPDR_SHIFT)
#define PADCTL_CONN_SOC_GPIO02_0_E_LPDR_RANGE                   8:8
#define PADCTL_CONN_SOC_GPIO02_0_E_LPDR_WOFFSET                 0x0
#define PADCTL_CONN_SOC_GPIO02_0_E_LPDR_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO02_0_E_LPDR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO02_0_E_LPDR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO02_0_E_LPDR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO02_0_E_LPDR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO02_0_E_LPDR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO02_0_E_LPDR_INIT_ENUM                       DISABLE
#define PADCTL_CONN_SOC_GPIO02_0_E_LPDR_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO02_0_E_LPDR_ENABLE                  _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO02_0_E_SCHMT_SHIFT                  _MK_SHIFT_CONST(12)
#define PADCTL_CONN_SOC_GPIO02_0_E_SCHMT_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO02_0_E_SCHMT_SHIFT)
#define PADCTL_CONN_SOC_GPIO02_0_E_SCHMT_RANGE                  12:12
#define PADCTL_CONN_SOC_GPIO02_0_E_SCHMT_WOFFSET                        0x0
#define PADCTL_CONN_SOC_GPIO02_0_E_SCHMT_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO02_0_E_SCHMT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO02_0_E_SCHMT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO02_0_E_SCHMT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO02_0_E_SCHMT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO02_0_E_SCHMT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO02_0_E_SCHMT_INIT_ENUM                      DISABLE
#define PADCTL_CONN_SOC_GPIO02_0_E_SCHMT_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO02_0_E_SCHMT_ENABLE                 _MK_ENUM_CONST(1)


// Register PADCTL_CONN_CFG2TMC_SOC_GPIO02_0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0                        _MK_ADDR_CONST(0x4c)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_SECURE                         0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_DUAL                   0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_SCR                    SCR_SOC_GPIO02_0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_WORD_COUNT                     0x1
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_RESET_MASK                     _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_READ_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_WRITE_MASK                     _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_CFG_CAL_DRVDN_FIELD                    _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_CFG_CAL_DRVDN_RANGE                    16:12
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_CFG_CAL_DRVDN_WOFFSET                  0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_CFG_CAL_DRVDN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_CFG_CAL_DRVUP_FIELD                    _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_CFG_CAL_DRVUP_RANGE                    24:20
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_CFG_CAL_DRVUP_WOFFSET                  0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_CFG_CAL_DRVUP_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO02_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register PADCTL_CONN_SOC_GPIO01_0
#define PADCTL_CONN_SOC_GPIO01_0                        _MK_ADDR_CONST(0x50)
#define PADCTL_CONN_SOC_GPIO01_0_SECURE                         0x0
#define PADCTL_CONN_SOC_GPIO01_0_DUAL                   0x0
#define PADCTL_CONN_SOC_GPIO01_0_SCR                    SCR_SOC_GPIO01_0
#define PADCTL_CONN_SOC_GPIO01_0_WORD_COUNT                     0x1
#define PADCTL_CONN_SOC_GPIO01_0_RESET_VAL                      _MK_MASK_CONST(0x458)
#define PADCTL_CONN_SOC_GPIO01_0_RESET_MASK                     _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO01_0_READ_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO01_0_WRITE_MASK                     _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO01_0_PM_SHIFT                       _MK_SHIFT_CONST(0)
#define PADCTL_CONN_SOC_GPIO01_0_PM_FIELD                       _MK_FIELD_CONST(0x3, PADCTL_CONN_SOC_GPIO01_0_PM_SHIFT)
#define PADCTL_CONN_SOC_GPIO01_0_PM_RANGE                       1:0
#define PADCTL_CONN_SOC_GPIO01_0_PM_WOFFSET                     0x0
#define PADCTL_CONN_SOC_GPIO01_0_PM_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO01_0_PM_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define PADCTL_CONN_SOC_GPIO01_0_PM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO01_0_PM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO01_0_PM_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO01_0_PM_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO01_0_PM_INIT_ENUM                   RSVD0
#define PADCTL_CONN_SOC_GPIO01_0_PM_RSVD0                       _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO01_0_PM_RSVD1                       _MK_ENUM_CONST(1)
#define PADCTL_CONN_SOC_GPIO01_0_PM_RSVD2                       _MK_ENUM_CONST(2)
#define PADCTL_CONN_SOC_GPIO01_0_PM_RSVD3                       _MK_ENUM_CONST(3)

#define PADCTL_CONN_SOC_GPIO01_0_GPIO_SF_SEL_SHIFT                      _MK_SHIFT_CONST(10)
#define PADCTL_CONN_SOC_GPIO01_0_GPIO_SF_SEL_FIELD                      _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO01_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_CONN_SOC_GPIO01_0_GPIO_SF_SEL_RANGE                      10:10
#define PADCTL_CONN_SOC_GPIO01_0_GPIO_SF_SEL_WOFFSET                    0x0
#define PADCTL_CONN_SOC_GPIO01_0_GPIO_SF_SEL_DEFAULT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO01_0_GPIO_SF_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO01_0_GPIO_SF_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO01_0_GPIO_SF_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO01_0_GPIO_SF_SEL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO01_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO01_0_GPIO_SF_SEL_INIT_ENUM                  SFIO
#define PADCTL_CONN_SOC_GPIO01_0_GPIO_SF_SEL_GPIO                       _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO01_0_GPIO_SF_SEL_SFIO                       _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO01_0_TRISTATE_SHIFT                 _MK_SHIFT_CONST(4)
#define PADCTL_CONN_SOC_GPIO01_0_TRISTATE_FIELD                 _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO01_0_TRISTATE_SHIFT)
#define PADCTL_CONN_SOC_GPIO01_0_TRISTATE_RANGE                 4:4
#define PADCTL_CONN_SOC_GPIO01_0_TRISTATE_WOFFSET                       0x0
#define PADCTL_CONN_SOC_GPIO01_0_TRISTATE_DEFAULT                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO01_0_TRISTATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO01_0_TRISTATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO01_0_TRISTATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO01_0_TRISTATE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO01_0_TRISTATE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO01_0_TRISTATE_INIT_ENUM                     TRISTATE
#define PADCTL_CONN_SOC_GPIO01_0_TRISTATE_PASSTHROUGH                   _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO01_0_TRISTATE_TRISTATE                      _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO01_0_PUPD_SHIFT                     _MK_SHIFT_CONST(2)
#define PADCTL_CONN_SOC_GPIO01_0_PUPD_FIELD                     _MK_FIELD_CONST(0x3, PADCTL_CONN_SOC_GPIO01_0_PUPD_SHIFT)
#define PADCTL_CONN_SOC_GPIO01_0_PUPD_RANGE                     3:2
#define PADCTL_CONN_SOC_GPIO01_0_PUPD_WOFFSET                   0x0
#define PADCTL_CONN_SOC_GPIO01_0_PUPD_DEFAULT                   _MK_MASK_CONST(0x2)
#define PADCTL_CONN_SOC_GPIO01_0_PUPD_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define PADCTL_CONN_SOC_GPIO01_0_PUPD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO01_0_PUPD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO01_0_PUPD_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO01_0_PUPD_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO01_0_PUPD_INIT_ENUM                 PULL_UP
#define PADCTL_CONN_SOC_GPIO01_0_PUPD_NONE                      _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO01_0_PUPD_PULL_DOWN                 _MK_ENUM_CONST(1)
#define PADCTL_CONN_SOC_GPIO01_0_PUPD_PULL_UP                   _MK_ENUM_CONST(2)
#define PADCTL_CONN_SOC_GPIO01_0_PUPD_RSVD                      _MK_ENUM_CONST(3)

#define PADCTL_CONN_SOC_GPIO01_0_E_INPUT_SHIFT                  _MK_SHIFT_CONST(6)
#define PADCTL_CONN_SOC_GPIO01_0_E_INPUT_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO01_0_E_INPUT_SHIFT)
#define PADCTL_CONN_SOC_GPIO01_0_E_INPUT_RANGE                  6:6
#define PADCTL_CONN_SOC_GPIO01_0_E_INPUT_WOFFSET                        0x0
#define PADCTL_CONN_SOC_GPIO01_0_E_INPUT_DEFAULT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO01_0_E_INPUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO01_0_E_INPUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO01_0_E_INPUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO01_0_E_INPUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO01_0_E_INPUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO01_0_E_INPUT_INIT_ENUM                      ENABLE
#define PADCTL_CONN_SOC_GPIO01_0_E_INPUT_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO01_0_E_INPUT_ENABLE                 _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO01_0_E_LPDR_SHIFT                   _MK_SHIFT_CONST(8)
#define PADCTL_CONN_SOC_GPIO01_0_E_LPDR_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO01_0_E_LPDR_SHIFT)
#define PADCTL_CONN_SOC_GPIO01_0_E_LPDR_RANGE                   8:8
#define PADCTL_CONN_SOC_GPIO01_0_E_LPDR_WOFFSET                 0x0
#define PADCTL_CONN_SOC_GPIO01_0_E_LPDR_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO01_0_E_LPDR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO01_0_E_LPDR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO01_0_E_LPDR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO01_0_E_LPDR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO01_0_E_LPDR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO01_0_E_LPDR_INIT_ENUM                       DISABLE
#define PADCTL_CONN_SOC_GPIO01_0_E_LPDR_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO01_0_E_LPDR_ENABLE                  _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO01_0_E_SCHMT_SHIFT                  _MK_SHIFT_CONST(12)
#define PADCTL_CONN_SOC_GPIO01_0_E_SCHMT_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO01_0_E_SCHMT_SHIFT)
#define PADCTL_CONN_SOC_GPIO01_0_E_SCHMT_RANGE                  12:12
#define PADCTL_CONN_SOC_GPIO01_0_E_SCHMT_WOFFSET                        0x0
#define PADCTL_CONN_SOC_GPIO01_0_E_SCHMT_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO01_0_E_SCHMT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO01_0_E_SCHMT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO01_0_E_SCHMT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO01_0_E_SCHMT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO01_0_E_SCHMT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO01_0_E_SCHMT_INIT_ENUM                      DISABLE
#define PADCTL_CONN_SOC_GPIO01_0_E_SCHMT_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO01_0_E_SCHMT_ENABLE                 _MK_ENUM_CONST(1)


// Register PADCTL_CONN_CFG2TMC_SOC_GPIO01_0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0                        _MK_ADDR_CONST(0x54)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_SECURE                         0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_DUAL                   0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_SCR                    SCR_SOC_GPIO01_0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_WORD_COUNT                     0x1
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_RESET_MASK                     _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_READ_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_WRITE_MASK                     _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_CFG_CAL_DRVDN_FIELD                    _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_CFG_CAL_DRVDN_RANGE                    16:12
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_CFG_CAL_DRVDN_WOFFSET                  0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_CFG_CAL_DRVDN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_CFG_CAL_DRVUP_FIELD                    _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_CFG_CAL_DRVUP_RANGE                    24:20
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_CFG_CAL_DRVUP_WOFFSET                  0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_CFG_CAL_DRVUP_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO01_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register PADCTL_CONN_SOC_GPIO00_0
#define PADCTL_CONN_SOC_GPIO00_0                        _MK_ADDR_CONST(0x58)
#define PADCTL_CONN_SOC_GPIO00_0_SECURE                         0x0
#define PADCTL_CONN_SOC_GPIO00_0_DUAL                   0x0
#define PADCTL_CONN_SOC_GPIO00_0_SCR                    SCR_SOC_GPIO00_0
#define PADCTL_CONN_SOC_GPIO00_0_WORD_COUNT                     0x1
#define PADCTL_CONN_SOC_GPIO00_0_RESET_VAL                      _MK_MASK_CONST(0x458)
#define PADCTL_CONN_SOC_GPIO00_0_RESET_MASK                     _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO00_0_READ_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO00_0_WRITE_MASK                     _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO00_0_PM_SHIFT                       _MK_SHIFT_CONST(0)
#define PADCTL_CONN_SOC_GPIO00_0_PM_FIELD                       _MK_FIELD_CONST(0x3, PADCTL_CONN_SOC_GPIO00_0_PM_SHIFT)
#define PADCTL_CONN_SOC_GPIO00_0_PM_RANGE                       1:0
#define PADCTL_CONN_SOC_GPIO00_0_PM_WOFFSET                     0x0
#define PADCTL_CONN_SOC_GPIO00_0_PM_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO00_0_PM_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define PADCTL_CONN_SOC_GPIO00_0_PM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO00_0_PM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO00_0_PM_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO00_0_PM_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO00_0_PM_INIT_ENUM                   RSVD0
#define PADCTL_CONN_SOC_GPIO00_0_PM_RSVD0                       _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO00_0_PM_RSVD1                       _MK_ENUM_CONST(1)
#define PADCTL_CONN_SOC_GPIO00_0_PM_RSVD2                       _MK_ENUM_CONST(2)
#define PADCTL_CONN_SOC_GPIO00_0_PM_RSVD3                       _MK_ENUM_CONST(3)

#define PADCTL_CONN_SOC_GPIO00_0_GPIO_SF_SEL_SHIFT                      _MK_SHIFT_CONST(10)
#define PADCTL_CONN_SOC_GPIO00_0_GPIO_SF_SEL_FIELD                      _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO00_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_CONN_SOC_GPIO00_0_GPIO_SF_SEL_RANGE                      10:10
#define PADCTL_CONN_SOC_GPIO00_0_GPIO_SF_SEL_WOFFSET                    0x0
#define PADCTL_CONN_SOC_GPIO00_0_GPIO_SF_SEL_DEFAULT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO00_0_GPIO_SF_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO00_0_GPIO_SF_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO00_0_GPIO_SF_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO00_0_GPIO_SF_SEL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO00_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO00_0_GPIO_SF_SEL_INIT_ENUM                  SFIO
#define PADCTL_CONN_SOC_GPIO00_0_GPIO_SF_SEL_GPIO                       _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO00_0_GPIO_SF_SEL_SFIO                       _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO00_0_TRISTATE_SHIFT                 _MK_SHIFT_CONST(4)
#define PADCTL_CONN_SOC_GPIO00_0_TRISTATE_FIELD                 _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO00_0_TRISTATE_SHIFT)
#define PADCTL_CONN_SOC_GPIO00_0_TRISTATE_RANGE                 4:4
#define PADCTL_CONN_SOC_GPIO00_0_TRISTATE_WOFFSET                       0x0
#define PADCTL_CONN_SOC_GPIO00_0_TRISTATE_DEFAULT                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO00_0_TRISTATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO00_0_TRISTATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO00_0_TRISTATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO00_0_TRISTATE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO00_0_TRISTATE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO00_0_TRISTATE_INIT_ENUM                     TRISTATE
#define PADCTL_CONN_SOC_GPIO00_0_TRISTATE_PASSTHROUGH                   _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO00_0_TRISTATE_TRISTATE                      _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO00_0_PUPD_SHIFT                     _MK_SHIFT_CONST(2)
#define PADCTL_CONN_SOC_GPIO00_0_PUPD_FIELD                     _MK_FIELD_CONST(0x3, PADCTL_CONN_SOC_GPIO00_0_PUPD_SHIFT)
#define PADCTL_CONN_SOC_GPIO00_0_PUPD_RANGE                     3:2
#define PADCTL_CONN_SOC_GPIO00_0_PUPD_WOFFSET                   0x0
#define PADCTL_CONN_SOC_GPIO00_0_PUPD_DEFAULT                   _MK_MASK_CONST(0x2)
#define PADCTL_CONN_SOC_GPIO00_0_PUPD_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define PADCTL_CONN_SOC_GPIO00_0_PUPD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO00_0_PUPD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO00_0_PUPD_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO00_0_PUPD_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO00_0_PUPD_INIT_ENUM                 PULL_UP
#define PADCTL_CONN_SOC_GPIO00_0_PUPD_NONE                      _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO00_0_PUPD_PULL_DOWN                 _MK_ENUM_CONST(1)
#define PADCTL_CONN_SOC_GPIO00_0_PUPD_PULL_UP                   _MK_ENUM_CONST(2)
#define PADCTL_CONN_SOC_GPIO00_0_PUPD_RSVD                      _MK_ENUM_CONST(3)

#define PADCTL_CONN_SOC_GPIO00_0_E_INPUT_SHIFT                  _MK_SHIFT_CONST(6)
#define PADCTL_CONN_SOC_GPIO00_0_E_INPUT_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO00_0_E_INPUT_SHIFT)
#define PADCTL_CONN_SOC_GPIO00_0_E_INPUT_RANGE                  6:6
#define PADCTL_CONN_SOC_GPIO00_0_E_INPUT_WOFFSET                        0x0
#define PADCTL_CONN_SOC_GPIO00_0_E_INPUT_DEFAULT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO00_0_E_INPUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO00_0_E_INPUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO00_0_E_INPUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO00_0_E_INPUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO00_0_E_INPUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO00_0_E_INPUT_INIT_ENUM                      ENABLE
#define PADCTL_CONN_SOC_GPIO00_0_E_INPUT_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO00_0_E_INPUT_ENABLE                 _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO00_0_E_LPDR_SHIFT                   _MK_SHIFT_CONST(8)
#define PADCTL_CONN_SOC_GPIO00_0_E_LPDR_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO00_0_E_LPDR_SHIFT)
#define PADCTL_CONN_SOC_GPIO00_0_E_LPDR_RANGE                   8:8
#define PADCTL_CONN_SOC_GPIO00_0_E_LPDR_WOFFSET                 0x0
#define PADCTL_CONN_SOC_GPIO00_0_E_LPDR_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO00_0_E_LPDR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO00_0_E_LPDR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO00_0_E_LPDR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO00_0_E_LPDR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO00_0_E_LPDR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO00_0_E_LPDR_INIT_ENUM                       DISABLE
#define PADCTL_CONN_SOC_GPIO00_0_E_LPDR_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO00_0_E_LPDR_ENABLE                  _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO00_0_E_SCHMT_SHIFT                  _MK_SHIFT_CONST(12)
#define PADCTL_CONN_SOC_GPIO00_0_E_SCHMT_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO00_0_E_SCHMT_SHIFT)
#define PADCTL_CONN_SOC_GPIO00_0_E_SCHMT_RANGE                  12:12
#define PADCTL_CONN_SOC_GPIO00_0_E_SCHMT_WOFFSET                        0x0
#define PADCTL_CONN_SOC_GPIO00_0_E_SCHMT_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO00_0_E_SCHMT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO00_0_E_SCHMT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO00_0_E_SCHMT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO00_0_E_SCHMT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO00_0_E_SCHMT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO00_0_E_SCHMT_INIT_ENUM                      DISABLE
#define PADCTL_CONN_SOC_GPIO00_0_E_SCHMT_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO00_0_E_SCHMT_ENABLE                 _MK_ENUM_CONST(1)


// Register PADCTL_CONN_CFG2TMC_SOC_GPIO00_0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0                        _MK_ADDR_CONST(0x5c)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_SECURE                         0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_DUAL                   0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_SCR                    SCR_SOC_GPIO00_0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_WORD_COUNT                     0x1
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_RESET_MASK                     _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_READ_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_WRITE_MASK                     _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_CFG_CAL_DRVDN_FIELD                    _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_CFG_CAL_DRVDN_RANGE                    16:12
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_CFG_CAL_DRVDN_WOFFSET                  0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_CFG_CAL_DRVDN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_CFG_CAL_DRVUP_FIELD                    _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_CFG_CAL_DRVUP_RANGE                    24:20
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_CFG_CAL_DRVUP_WOFFSET                  0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_CFG_CAL_DRVUP_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO00_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register PADCTL_CONN_GEN1_I2C_SCL_0
#define PADCTL_CONN_GEN1_I2C_SCL_0                      _MK_ADDR_CONST(0x60)
#define PADCTL_CONN_GEN1_I2C_SCL_0_SECURE                       0x0
#define PADCTL_CONN_GEN1_I2C_SCL_0_DUAL                         0x0
#define PADCTL_CONN_GEN1_I2C_SCL_0_SCR                  SCR_GEN1_I2C_SCL_0
#define PADCTL_CONN_GEN1_I2C_SCL_0_WORD_COUNT                   0x1
#define PADCTL_CONN_GEN1_I2C_SCL_0_RESET_VAL                    _MK_MASK_CONST(0x1570)
#define PADCTL_CONN_GEN1_I2C_SCL_0_RESET_MASK                   _MK_MASK_CONST(0x157f)
#define PADCTL_CONN_GEN1_I2C_SCL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_READ_MASK                    _MK_MASK_CONST(0x157f)
#define PADCTL_CONN_GEN1_I2C_SCL_0_WRITE_MASK                   _MK_MASK_CONST(0x157f)
#define PADCTL_CONN_GEN1_I2C_SCL_0_PM_SHIFT                     _MK_SHIFT_CONST(0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_PM_FIELD                     _MK_FIELD_CONST(0x3, PADCTL_CONN_GEN1_I2C_SCL_0_PM_SHIFT)
#define PADCTL_CONN_GEN1_I2C_SCL_0_PM_RANGE                     1:0
#define PADCTL_CONN_GEN1_I2C_SCL_0_PM_WOFFSET                   0x0
#define PADCTL_CONN_GEN1_I2C_SCL_0_PM_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_PM_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define PADCTL_CONN_GEN1_I2C_SCL_0_PM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_PM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_PM_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_PM_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SCL_0_PM_INIT_ENUM                 I2C1
#define PADCTL_CONN_GEN1_I2C_SCL_0_PM_I2C1                      _MK_ENUM_CONST(0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_PM_RSVD1                     _MK_ENUM_CONST(1)
#define PADCTL_CONN_GEN1_I2C_SCL_0_PM_RSVD2                     _MK_ENUM_CONST(2)
#define PADCTL_CONN_GEN1_I2C_SCL_0_PM_RSVD3                     _MK_ENUM_CONST(3)

#define PADCTL_CONN_GEN1_I2C_SCL_0_GPIO_SF_SEL_SHIFT                    _MK_SHIFT_CONST(10)
#define PADCTL_CONN_GEN1_I2C_SCL_0_GPIO_SF_SEL_FIELD                    _MK_FIELD_CONST(0x1, PADCTL_CONN_GEN1_I2C_SCL_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_CONN_GEN1_I2C_SCL_0_GPIO_SF_SEL_RANGE                    10:10
#define PADCTL_CONN_GEN1_I2C_SCL_0_GPIO_SF_SEL_WOFFSET                  0x0
#define PADCTL_CONN_GEN1_I2C_SCL_0_GPIO_SF_SEL_DEFAULT                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SCL_0_GPIO_SF_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SCL_0_GPIO_SF_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_GPIO_SF_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_GPIO_SF_SEL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SCL_0_GPIO_SF_SEL_INIT_ENUM                        SFIO
#define PADCTL_CONN_GEN1_I2C_SCL_0_GPIO_SF_SEL_GPIO                     _MK_ENUM_CONST(0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_GPIO_SF_SEL_SFIO                     _MK_ENUM_CONST(1)

#define PADCTL_CONN_GEN1_I2C_SCL_0_TRISTATE_SHIFT                       _MK_SHIFT_CONST(4)
#define PADCTL_CONN_GEN1_I2C_SCL_0_TRISTATE_FIELD                       _MK_FIELD_CONST(0x1, PADCTL_CONN_GEN1_I2C_SCL_0_TRISTATE_SHIFT)
#define PADCTL_CONN_GEN1_I2C_SCL_0_TRISTATE_RANGE                       4:4
#define PADCTL_CONN_GEN1_I2C_SCL_0_TRISTATE_WOFFSET                     0x0
#define PADCTL_CONN_GEN1_I2C_SCL_0_TRISTATE_DEFAULT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SCL_0_TRISTATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SCL_0_TRISTATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_TRISTATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_TRISTATE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_TRISTATE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SCL_0_TRISTATE_INIT_ENUM                   TRISTATE
#define PADCTL_CONN_GEN1_I2C_SCL_0_TRISTATE_PASSTHROUGH                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_TRISTATE_TRISTATE                    _MK_ENUM_CONST(1)

#define PADCTL_CONN_GEN1_I2C_SCL_0_PUPD_SHIFT                   _MK_SHIFT_CONST(2)
#define PADCTL_CONN_GEN1_I2C_SCL_0_PUPD_FIELD                   _MK_FIELD_CONST(0x3, PADCTL_CONN_GEN1_I2C_SCL_0_PUPD_SHIFT)
#define PADCTL_CONN_GEN1_I2C_SCL_0_PUPD_RANGE                   3:2
#define PADCTL_CONN_GEN1_I2C_SCL_0_PUPD_WOFFSET                 0x0
#define PADCTL_CONN_GEN1_I2C_SCL_0_PUPD_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_PUPD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define PADCTL_CONN_GEN1_I2C_SCL_0_PUPD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_PUPD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_PUPD_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_PUPD_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SCL_0_PUPD_INIT_ENUM                       NONE
#define PADCTL_CONN_GEN1_I2C_SCL_0_PUPD_NONE                    _MK_ENUM_CONST(0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_PUPD_PULL_DOWN                       _MK_ENUM_CONST(1)
#define PADCTL_CONN_GEN1_I2C_SCL_0_PUPD_PULL_UP                 _MK_ENUM_CONST(2)
#define PADCTL_CONN_GEN1_I2C_SCL_0_PUPD_RSVD                    _MK_ENUM_CONST(3)

#define PADCTL_CONN_GEN1_I2C_SCL_0_E_INPUT_SHIFT                        _MK_SHIFT_CONST(6)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_INPUT_FIELD                        _MK_FIELD_CONST(0x1, PADCTL_CONN_GEN1_I2C_SCL_0_E_INPUT_SHIFT)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_INPUT_RANGE                        6:6
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_INPUT_WOFFSET                      0x0
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_INPUT_DEFAULT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_INPUT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_INPUT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_INPUT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_INPUT_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_INPUT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_INPUT_INIT_ENUM                    ENABLE
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_INPUT_DISABLE                      _MK_ENUM_CONST(0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_INPUT_ENABLE                       _MK_ENUM_CONST(1)

#define PADCTL_CONN_GEN1_I2C_SCL_0_E_LPDR_SHIFT                 _MK_SHIFT_CONST(8)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_LPDR_FIELD                 _MK_FIELD_CONST(0x1, PADCTL_CONN_GEN1_I2C_SCL_0_E_LPDR_SHIFT)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_LPDR_RANGE                 8:8
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_LPDR_WOFFSET                       0x0
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_LPDR_DEFAULT                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_LPDR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_LPDR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_LPDR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_LPDR_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_LPDR_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_LPDR_INIT_ENUM                     ENABLE
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_LPDR_DISABLE                       _MK_ENUM_CONST(0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_LPDR_ENABLE                        _MK_ENUM_CONST(1)

#define PADCTL_CONN_GEN1_I2C_SCL_0_E_IO_HV_SHIFT                        _MK_SHIFT_CONST(5)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_IO_HV_FIELD                        _MK_FIELD_CONST(0x1, PADCTL_CONN_GEN1_I2C_SCL_0_E_IO_HV_SHIFT)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_IO_HV_RANGE                        5:5
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_IO_HV_WOFFSET                      0x0
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_IO_HV_DEFAULT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_IO_HV_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_IO_HV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_IO_HV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_IO_HV_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_IO_HV_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_IO_HV_INIT_ENUM                    ENABLE
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_IO_HV_DISABLE                      _MK_ENUM_CONST(0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_IO_HV_ENABLE                       _MK_ENUM_CONST(1)

#define PADCTL_CONN_GEN1_I2C_SCL_0_E_SCHMT_SHIFT                        _MK_SHIFT_CONST(12)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_SCHMT_FIELD                        _MK_FIELD_CONST(0x1, PADCTL_CONN_GEN1_I2C_SCL_0_E_SCHMT_SHIFT)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_SCHMT_RANGE                        12:12
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_SCHMT_WOFFSET                      0x0
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_SCHMT_DEFAULT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_SCHMT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_SCHMT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_SCHMT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_SCHMT_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_SCHMT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_SCHMT_INIT_ENUM                    ENABLE
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_SCHMT_DISABLE                      _MK_ENUM_CONST(0)
#define PADCTL_CONN_GEN1_I2C_SCL_0_E_SCHMT_ENABLE                       _MK_ENUM_CONST(1)


// Register PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0                      _MK_ADDR_CONST(0x64)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_SECURE                       0x0
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_DUAL                         0x0
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_SCR                  SCR_GEN1_I2C_SCL_0
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_WORD_COUNT                   0x1
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_RESET_MASK                   _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_READ_MASK                    _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_WRITE_MASK                   _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_CFG_CAL_DRVDN_FIELD                  _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_CFG_CAL_DRVDN_RANGE                  16:12
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_CFG_CAL_DRVDN_WOFFSET                        0x0
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_CFG_CAL_DRVDN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_CFG_CAL_DRVUP_FIELD                  _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_CFG_CAL_DRVUP_RANGE                  24:20
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_CFG_CAL_DRVUP_WOFFSET                        0x0
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_CFG_CAL_DRVUP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register PADCTL_CONN_GEN1_I2C_SDA_0
#define PADCTL_CONN_GEN1_I2C_SDA_0                      _MK_ADDR_CONST(0x68)
#define PADCTL_CONN_GEN1_I2C_SDA_0_SECURE                       0x0
#define PADCTL_CONN_GEN1_I2C_SDA_0_DUAL                         0x0
#define PADCTL_CONN_GEN1_I2C_SDA_0_SCR                  SCR_GEN1_I2C_SDA_0
#define PADCTL_CONN_GEN1_I2C_SDA_0_WORD_COUNT                   0x1
#define PADCTL_CONN_GEN1_I2C_SDA_0_RESET_VAL                    _MK_MASK_CONST(0x1570)
#define PADCTL_CONN_GEN1_I2C_SDA_0_RESET_MASK                   _MK_MASK_CONST(0x157f)
#define PADCTL_CONN_GEN1_I2C_SDA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_READ_MASK                    _MK_MASK_CONST(0x157f)
#define PADCTL_CONN_GEN1_I2C_SDA_0_WRITE_MASK                   _MK_MASK_CONST(0x157f)
#define PADCTL_CONN_GEN1_I2C_SDA_0_PM_SHIFT                     _MK_SHIFT_CONST(0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_PM_FIELD                     _MK_FIELD_CONST(0x3, PADCTL_CONN_GEN1_I2C_SDA_0_PM_SHIFT)
#define PADCTL_CONN_GEN1_I2C_SDA_0_PM_RANGE                     1:0
#define PADCTL_CONN_GEN1_I2C_SDA_0_PM_WOFFSET                   0x0
#define PADCTL_CONN_GEN1_I2C_SDA_0_PM_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_PM_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define PADCTL_CONN_GEN1_I2C_SDA_0_PM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_PM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_PM_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_PM_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SDA_0_PM_INIT_ENUM                 I2C1
#define PADCTL_CONN_GEN1_I2C_SDA_0_PM_I2C1                      _MK_ENUM_CONST(0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_PM_RSVD1                     _MK_ENUM_CONST(1)
#define PADCTL_CONN_GEN1_I2C_SDA_0_PM_RSVD2                     _MK_ENUM_CONST(2)
#define PADCTL_CONN_GEN1_I2C_SDA_0_PM_RSVD3                     _MK_ENUM_CONST(3)

#define PADCTL_CONN_GEN1_I2C_SDA_0_GPIO_SF_SEL_SHIFT                    _MK_SHIFT_CONST(10)
#define PADCTL_CONN_GEN1_I2C_SDA_0_GPIO_SF_SEL_FIELD                    _MK_FIELD_CONST(0x1, PADCTL_CONN_GEN1_I2C_SDA_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_CONN_GEN1_I2C_SDA_0_GPIO_SF_SEL_RANGE                    10:10
#define PADCTL_CONN_GEN1_I2C_SDA_0_GPIO_SF_SEL_WOFFSET                  0x0
#define PADCTL_CONN_GEN1_I2C_SDA_0_GPIO_SF_SEL_DEFAULT                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SDA_0_GPIO_SF_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SDA_0_GPIO_SF_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_GPIO_SF_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_GPIO_SF_SEL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SDA_0_GPIO_SF_SEL_INIT_ENUM                        SFIO
#define PADCTL_CONN_GEN1_I2C_SDA_0_GPIO_SF_SEL_GPIO                     _MK_ENUM_CONST(0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_GPIO_SF_SEL_SFIO                     _MK_ENUM_CONST(1)

#define PADCTL_CONN_GEN1_I2C_SDA_0_TRISTATE_SHIFT                       _MK_SHIFT_CONST(4)
#define PADCTL_CONN_GEN1_I2C_SDA_0_TRISTATE_FIELD                       _MK_FIELD_CONST(0x1, PADCTL_CONN_GEN1_I2C_SDA_0_TRISTATE_SHIFT)
#define PADCTL_CONN_GEN1_I2C_SDA_0_TRISTATE_RANGE                       4:4
#define PADCTL_CONN_GEN1_I2C_SDA_0_TRISTATE_WOFFSET                     0x0
#define PADCTL_CONN_GEN1_I2C_SDA_0_TRISTATE_DEFAULT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SDA_0_TRISTATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SDA_0_TRISTATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_TRISTATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_TRISTATE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_TRISTATE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SDA_0_TRISTATE_INIT_ENUM                   TRISTATE
#define PADCTL_CONN_GEN1_I2C_SDA_0_TRISTATE_PASSTHROUGH                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_TRISTATE_TRISTATE                    _MK_ENUM_CONST(1)

#define PADCTL_CONN_GEN1_I2C_SDA_0_PUPD_SHIFT                   _MK_SHIFT_CONST(2)
#define PADCTL_CONN_GEN1_I2C_SDA_0_PUPD_FIELD                   _MK_FIELD_CONST(0x3, PADCTL_CONN_GEN1_I2C_SDA_0_PUPD_SHIFT)
#define PADCTL_CONN_GEN1_I2C_SDA_0_PUPD_RANGE                   3:2
#define PADCTL_CONN_GEN1_I2C_SDA_0_PUPD_WOFFSET                 0x0
#define PADCTL_CONN_GEN1_I2C_SDA_0_PUPD_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_PUPD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define PADCTL_CONN_GEN1_I2C_SDA_0_PUPD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_PUPD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_PUPD_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_PUPD_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SDA_0_PUPD_INIT_ENUM                       NONE
#define PADCTL_CONN_GEN1_I2C_SDA_0_PUPD_NONE                    _MK_ENUM_CONST(0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_PUPD_PULL_DOWN                       _MK_ENUM_CONST(1)
#define PADCTL_CONN_GEN1_I2C_SDA_0_PUPD_PULL_UP                 _MK_ENUM_CONST(2)
#define PADCTL_CONN_GEN1_I2C_SDA_0_PUPD_RSVD                    _MK_ENUM_CONST(3)

#define PADCTL_CONN_GEN1_I2C_SDA_0_E_INPUT_SHIFT                        _MK_SHIFT_CONST(6)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_INPUT_FIELD                        _MK_FIELD_CONST(0x1, PADCTL_CONN_GEN1_I2C_SDA_0_E_INPUT_SHIFT)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_INPUT_RANGE                        6:6
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_INPUT_WOFFSET                      0x0
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_INPUT_DEFAULT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_INPUT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_INPUT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_INPUT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_INPUT_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_INPUT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_INPUT_INIT_ENUM                    ENABLE
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_INPUT_DISABLE                      _MK_ENUM_CONST(0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_INPUT_ENABLE                       _MK_ENUM_CONST(1)

#define PADCTL_CONN_GEN1_I2C_SDA_0_E_LPDR_SHIFT                 _MK_SHIFT_CONST(8)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_LPDR_FIELD                 _MK_FIELD_CONST(0x1, PADCTL_CONN_GEN1_I2C_SDA_0_E_LPDR_SHIFT)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_LPDR_RANGE                 8:8
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_LPDR_WOFFSET                       0x0
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_LPDR_DEFAULT                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_LPDR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_LPDR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_LPDR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_LPDR_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_LPDR_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_LPDR_INIT_ENUM                     ENABLE
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_LPDR_DISABLE                       _MK_ENUM_CONST(0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_LPDR_ENABLE                        _MK_ENUM_CONST(1)

#define PADCTL_CONN_GEN1_I2C_SDA_0_E_IO_HV_SHIFT                        _MK_SHIFT_CONST(5)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_IO_HV_FIELD                        _MK_FIELD_CONST(0x1, PADCTL_CONN_GEN1_I2C_SDA_0_E_IO_HV_SHIFT)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_IO_HV_RANGE                        5:5
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_IO_HV_WOFFSET                      0x0
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_IO_HV_DEFAULT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_IO_HV_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_IO_HV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_IO_HV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_IO_HV_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_IO_HV_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_IO_HV_INIT_ENUM                    ENABLE
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_IO_HV_DISABLE                      _MK_ENUM_CONST(0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_IO_HV_ENABLE                       _MK_ENUM_CONST(1)

#define PADCTL_CONN_GEN1_I2C_SDA_0_E_SCHMT_SHIFT                        _MK_SHIFT_CONST(12)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_SCHMT_FIELD                        _MK_FIELD_CONST(0x1, PADCTL_CONN_GEN1_I2C_SDA_0_E_SCHMT_SHIFT)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_SCHMT_RANGE                        12:12
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_SCHMT_WOFFSET                      0x0
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_SCHMT_DEFAULT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_SCHMT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_SCHMT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_SCHMT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_SCHMT_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_SCHMT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_SCHMT_INIT_ENUM                    ENABLE
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_SCHMT_DISABLE                      _MK_ENUM_CONST(0)
#define PADCTL_CONN_GEN1_I2C_SDA_0_E_SCHMT_ENABLE                       _MK_ENUM_CONST(1)


// Register PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0                      _MK_ADDR_CONST(0x6c)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_SECURE                       0x0
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_DUAL                         0x0
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_SCR                  SCR_GEN1_I2C_SDA_0
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_WORD_COUNT                   0x1
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_RESET_MASK                   _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_READ_MASK                    _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_WRITE_MASK                   _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_CFG_CAL_DRVDN_FIELD                  _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_CFG_CAL_DRVDN_RANGE                  16:12
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_CFG_CAL_DRVDN_WOFFSET                        0x0
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_CFG_CAL_DRVDN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_CFG_CAL_DRVUP_FIELD                  _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_CFG_CAL_DRVUP_RANGE                  24:20
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_CFG_CAL_DRVUP_WOFFSET                        0x0
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_CFG_CAL_DRVUP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register PADCTL_CONN_SOC_GPIO08_0
#define PADCTL_CONN_SOC_GPIO08_0                        _MK_ADDR_CONST(0x70)
#define PADCTL_CONN_SOC_GPIO08_0_SECURE                         0x0
#define PADCTL_CONN_SOC_GPIO08_0_DUAL                   0x0
#define PADCTL_CONN_SOC_GPIO08_0_SCR                    SCR_SOC_GPIO08_0
#define PADCTL_CONN_SOC_GPIO08_0_WORD_COUNT                     0x1
#define PADCTL_CONN_SOC_GPIO08_0_RESET_VAL                      _MK_MASK_CONST(0x454)
#define PADCTL_CONN_SOC_GPIO08_0_RESET_MASK                     _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO08_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO08_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO08_0_READ_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO08_0_WRITE_MASK                     _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO08_0_PM_SHIFT                       _MK_SHIFT_CONST(0)
#define PADCTL_CONN_SOC_GPIO08_0_PM_FIELD                       _MK_FIELD_CONST(0x3, PADCTL_CONN_SOC_GPIO08_0_PM_SHIFT)
#define PADCTL_CONN_SOC_GPIO08_0_PM_RANGE                       1:0
#define PADCTL_CONN_SOC_GPIO08_0_PM_WOFFSET                     0x0
#define PADCTL_CONN_SOC_GPIO08_0_PM_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO08_0_PM_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define PADCTL_CONN_SOC_GPIO08_0_PM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO08_0_PM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO08_0_PM_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO08_0_PM_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO08_0_PM_INIT_ENUM                   RSVD0
#define PADCTL_CONN_SOC_GPIO08_0_PM_RSVD0                       _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO08_0_PM_CCLA                        _MK_ENUM_CONST(1)
#define PADCTL_CONN_SOC_GPIO08_0_PM_RSVD2                       _MK_ENUM_CONST(2)
#define PADCTL_CONN_SOC_GPIO08_0_PM_RSVD3                       _MK_ENUM_CONST(3)

#define PADCTL_CONN_SOC_GPIO08_0_GPIO_SF_SEL_SHIFT                      _MK_SHIFT_CONST(10)
#define PADCTL_CONN_SOC_GPIO08_0_GPIO_SF_SEL_FIELD                      _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO08_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_CONN_SOC_GPIO08_0_GPIO_SF_SEL_RANGE                      10:10
#define PADCTL_CONN_SOC_GPIO08_0_GPIO_SF_SEL_WOFFSET                    0x0
#define PADCTL_CONN_SOC_GPIO08_0_GPIO_SF_SEL_DEFAULT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO08_0_GPIO_SF_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO08_0_GPIO_SF_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO08_0_GPIO_SF_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO08_0_GPIO_SF_SEL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO08_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO08_0_GPIO_SF_SEL_INIT_ENUM                  SFIO
#define PADCTL_CONN_SOC_GPIO08_0_GPIO_SF_SEL_GPIO                       _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO08_0_GPIO_SF_SEL_SFIO                       _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO08_0_TRISTATE_SHIFT                 _MK_SHIFT_CONST(4)
#define PADCTL_CONN_SOC_GPIO08_0_TRISTATE_FIELD                 _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO08_0_TRISTATE_SHIFT)
#define PADCTL_CONN_SOC_GPIO08_0_TRISTATE_RANGE                 4:4
#define PADCTL_CONN_SOC_GPIO08_0_TRISTATE_WOFFSET                       0x0
#define PADCTL_CONN_SOC_GPIO08_0_TRISTATE_DEFAULT                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO08_0_TRISTATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO08_0_TRISTATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO08_0_TRISTATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO08_0_TRISTATE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO08_0_TRISTATE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO08_0_TRISTATE_INIT_ENUM                     TRISTATE
#define PADCTL_CONN_SOC_GPIO08_0_TRISTATE_PASSTHROUGH                   _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO08_0_TRISTATE_TRISTATE                      _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO08_0_PUPD_SHIFT                     _MK_SHIFT_CONST(2)
#define PADCTL_CONN_SOC_GPIO08_0_PUPD_FIELD                     _MK_FIELD_CONST(0x3, PADCTL_CONN_SOC_GPIO08_0_PUPD_SHIFT)
#define PADCTL_CONN_SOC_GPIO08_0_PUPD_RANGE                     3:2
#define PADCTL_CONN_SOC_GPIO08_0_PUPD_WOFFSET                   0x0
#define PADCTL_CONN_SOC_GPIO08_0_PUPD_DEFAULT                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO08_0_PUPD_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define PADCTL_CONN_SOC_GPIO08_0_PUPD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO08_0_PUPD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO08_0_PUPD_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO08_0_PUPD_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO08_0_PUPD_INIT_ENUM                 PULL_DOWN
#define PADCTL_CONN_SOC_GPIO08_0_PUPD_NONE                      _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO08_0_PUPD_PULL_DOWN                 _MK_ENUM_CONST(1)
#define PADCTL_CONN_SOC_GPIO08_0_PUPD_PULL_UP                   _MK_ENUM_CONST(2)
#define PADCTL_CONN_SOC_GPIO08_0_PUPD_RSVD                      _MK_ENUM_CONST(3)

#define PADCTL_CONN_SOC_GPIO08_0_E_INPUT_SHIFT                  _MK_SHIFT_CONST(6)
#define PADCTL_CONN_SOC_GPIO08_0_E_INPUT_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO08_0_E_INPUT_SHIFT)
#define PADCTL_CONN_SOC_GPIO08_0_E_INPUT_RANGE                  6:6
#define PADCTL_CONN_SOC_GPIO08_0_E_INPUT_WOFFSET                        0x0
#define PADCTL_CONN_SOC_GPIO08_0_E_INPUT_DEFAULT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO08_0_E_INPUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO08_0_E_INPUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO08_0_E_INPUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO08_0_E_INPUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO08_0_E_INPUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO08_0_E_INPUT_INIT_ENUM                      ENABLE
#define PADCTL_CONN_SOC_GPIO08_0_E_INPUT_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO08_0_E_INPUT_ENABLE                 _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO08_0_E_LPDR_SHIFT                   _MK_SHIFT_CONST(8)
#define PADCTL_CONN_SOC_GPIO08_0_E_LPDR_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO08_0_E_LPDR_SHIFT)
#define PADCTL_CONN_SOC_GPIO08_0_E_LPDR_RANGE                   8:8
#define PADCTL_CONN_SOC_GPIO08_0_E_LPDR_WOFFSET                 0x0
#define PADCTL_CONN_SOC_GPIO08_0_E_LPDR_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO08_0_E_LPDR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO08_0_E_LPDR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO08_0_E_LPDR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO08_0_E_LPDR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO08_0_E_LPDR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO08_0_E_LPDR_INIT_ENUM                       DISABLE
#define PADCTL_CONN_SOC_GPIO08_0_E_LPDR_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO08_0_E_LPDR_ENABLE                  _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO08_0_E_SCHMT_SHIFT                  _MK_SHIFT_CONST(12)
#define PADCTL_CONN_SOC_GPIO08_0_E_SCHMT_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO08_0_E_SCHMT_SHIFT)
#define PADCTL_CONN_SOC_GPIO08_0_E_SCHMT_RANGE                  12:12
#define PADCTL_CONN_SOC_GPIO08_0_E_SCHMT_WOFFSET                        0x0
#define PADCTL_CONN_SOC_GPIO08_0_E_SCHMT_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO08_0_E_SCHMT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO08_0_E_SCHMT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO08_0_E_SCHMT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO08_0_E_SCHMT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO08_0_E_SCHMT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO08_0_E_SCHMT_INIT_ENUM                      DISABLE
#define PADCTL_CONN_SOC_GPIO08_0_E_SCHMT_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO08_0_E_SCHMT_ENABLE                 _MK_ENUM_CONST(1)


// Register PADCTL_CONN_CFG2TMC_SOC_GPIO08_0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0                        _MK_ADDR_CONST(0x74)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_SECURE                         0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_DUAL                   0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_SCR                    SCR_SOC_GPIO08_0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_WORD_COUNT                     0x1
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_RESET_MASK                     _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_READ_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_WRITE_MASK                     _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_CFG_CAL_DRVDN_FIELD                    _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_CFG_CAL_DRVDN_RANGE                    16:12
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_CFG_CAL_DRVDN_WOFFSET                  0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_CFG_CAL_DRVDN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_CFG_CAL_DRVUP_FIELD                    _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_CFG_CAL_DRVUP_RANGE                    24:20
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_CFG_CAL_DRVUP_WOFFSET                  0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_CFG_CAL_DRVUP_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO08_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register PADCTL_CONN_SOC_GPIO09_0
#define PADCTL_CONN_SOC_GPIO09_0                        _MK_ADDR_CONST(0x78)
#define PADCTL_CONN_SOC_GPIO09_0_SECURE                         0x0
#define PADCTL_CONN_SOC_GPIO09_0_DUAL                   0x0
#define PADCTL_CONN_SOC_GPIO09_0_SCR                    SCR_SOC_GPIO09_0
#define PADCTL_CONN_SOC_GPIO09_0_WORD_COUNT                     0x1
#define PADCTL_CONN_SOC_GPIO09_0_RESET_VAL                      _MK_MASK_CONST(0x454)
#define PADCTL_CONN_SOC_GPIO09_0_RESET_MASK                     _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO09_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO09_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO09_0_READ_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO09_0_WRITE_MASK                     _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO09_0_PM_SHIFT                       _MK_SHIFT_CONST(0)
#define PADCTL_CONN_SOC_GPIO09_0_PM_FIELD                       _MK_FIELD_CONST(0x3, PADCTL_CONN_SOC_GPIO09_0_PM_SHIFT)
#define PADCTL_CONN_SOC_GPIO09_0_PM_RANGE                       1:0
#define PADCTL_CONN_SOC_GPIO09_0_PM_WOFFSET                     0x0
#define PADCTL_CONN_SOC_GPIO09_0_PM_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO09_0_PM_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define PADCTL_CONN_SOC_GPIO09_0_PM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO09_0_PM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO09_0_PM_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO09_0_PM_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO09_0_PM_INIT_ENUM                   RSVD0
#define PADCTL_CONN_SOC_GPIO09_0_PM_RSVD0                       _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO09_0_PM_RSVD1                       _MK_ENUM_CONST(1)
#define PADCTL_CONN_SOC_GPIO09_0_PM_RSVD2                       _MK_ENUM_CONST(2)
#define PADCTL_CONN_SOC_GPIO09_0_PM_RSVD3                       _MK_ENUM_CONST(3)

#define PADCTL_CONN_SOC_GPIO09_0_GPIO_SF_SEL_SHIFT                      _MK_SHIFT_CONST(10)
#define PADCTL_CONN_SOC_GPIO09_0_GPIO_SF_SEL_FIELD                      _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO09_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_CONN_SOC_GPIO09_0_GPIO_SF_SEL_RANGE                      10:10
#define PADCTL_CONN_SOC_GPIO09_0_GPIO_SF_SEL_WOFFSET                    0x0
#define PADCTL_CONN_SOC_GPIO09_0_GPIO_SF_SEL_DEFAULT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO09_0_GPIO_SF_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO09_0_GPIO_SF_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO09_0_GPIO_SF_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO09_0_GPIO_SF_SEL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO09_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO09_0_GPIO_SF_SEL_INIT_ENUM                  SFIO
#define PADCTL_CONN_SOC_GPIO09_0_GPIO_SF_SEL_GPIO                       _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO09_0_GPIO_SF_SEL_SFIO                       _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO09_0_TRISTATE_SHIFT                 _MK_SHIFT_CONST(4)
#define PADCTL_CONN_SOC_GPIO09_0_TRISTATE_FIELD                 _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO09_0_TRISTATE_SHIFT)
#define PADCTL_CONN_SOC_GPIO09_0_TRISTATE_RANGE                 4:4
#define PADCTL_CONN_SOC_GPIO09_0_TRISTATE_WOFFSET                       0x0
#define PADCTL_CONN_SOC_GPIO09_0_TRISTATE_DEFAULT                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO09_0_TRISTATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO09_0_TRISTATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO09_0_TRISTATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO09_0_TRISTATE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO09_0_TRISTATE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO09_0_TRISTATE_INIT_ENUM                     TRISTATE
#define PADCTL_CONN_SOC_GPIO09_0_TRISTATE_PASSTHROUGH                   _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO09_0_TRISTATE_TRISTATE                      _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO09_0_PUPD_SHIFT                     _MK_SHIFT_CONST(2)
#define PADCTL_CONN_SOC_GPIO09_0_PUPD_FIELD                     _MK_FIELD_CONST(0x3, PADCTL_CONN_SOC_GPIO09_0_PUPD_SHIFT)
#define PADCTL_CONN_SOC_GPIO09_0_PUPD_RANGE                     3:2
#define PADCTL_CONN_SOC_GPIO09_0_PUPD_WOFFSET                   0x0
#define PADCTL_CONN_SOC_GPIO09_0_PUPD_DEFAULT                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO09_0_PUPD_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define PADCTL_CONN_SOC_GPIO09_0_PUPD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO09_0_PUPD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO09_0_PUPD_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO09_0_PUPD_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO09_0_PUPD_INIT_ENUM                 PULL_DOWN
#define PADCTL_CONN_SOC_GPIO09_0_PUPD_NONE                      _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO09_0_PUPD_PULL_DOWN                 _MK_ENUM_CONST(1)
#define PADCTL_CONN_SOC_GPIO09_0_PUPD_PULL_UP                   _MK_ENUM_CONST(2)
#define PADCTL_CONN_SOC_GPIO09_0_PUPD_RSVD                      _MK_ENUM_CONST(3)

#define PADCTL_CONN_SOC_GPIO09_0_E_INPUT_SHIFT                  _MK_SHIFT_CONST(6)
#define PADCTL_CONN_SOC_GPIO09_0_E_INPUT_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO09_0_E_INPUT_SHIFT)
#define PADCTL_CONN_SOC_GPIO09_0_E_INPUT_RANGE                  6:6
#define PADCTL_CONN_SOC_GPIO09_0_E_INPUT_WOFFSET                        0x0
#define PADCTL_CONN_SOC_GPIO09_0_E_INPUT_DEFAULT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO09_0_E_INPUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO09_0_E_INPUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO09_0_E_INPUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO09_0_E_INPUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO09_0_E_INPUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO09_0_E_INPUT_INIT_ENUM                      ENABLE
#define PADCTL_CONN_SOC_GPIO09_0_E_INPUT_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO09_0_E_INPUT_ENABLE                 _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO09_0_E_LPDR_SHIFT                   _MK_SHIFT_CONST(8)
#define PADCTL_CONN_SOC_GPIO09_0_E_LPDR_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO09_0_E_LPDR_SHIFT)
#define PADCTL_CONN_SOC_GPIO09_0_E_LPDR_RANGE                   8:8
#define PADCTL_CONN_SOC_GPIO09_0_E_LPDR_WOFFSET                 0x0
#define PADCTL_CONN_SOC_GPIO09_0_E_LPDR_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO09_0_E_LPDR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO09_0_E_LPDR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO09_0_E_LPDR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO09_0_E_LPDR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO09_0_E_LPDR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO09_0_E_LPDR_INIT_ENUM                       DISABLE
#define PADCTL_CONN_SOC_GPIO09_0_E_LPDR_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO09_0_E_LPDR_ENABLE                  _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO09_0_E_SCHMT_SHIFT                  _MK_SHIFT_CONST(12)
#define PADCTL_CONN_SOC_GPIO09_0_E_SCHMT_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO09_0_E_SCHMT_SHIFT)
#define PADCTL_CONN_SOC_GPIO09_0_E_SCHMT_RANGE                  12:12
#define PADCTL_CONN_SOC_GPIO09_0_E_SCHMT_WOFFSET                        0x0
#define PADCTL_CONN_SOC_GPIO09_0_E_SCHMT_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO09_0_E_SCHMT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO09_0_E_SCHMT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO09_0_E_SCHMT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO09_0_E_SCHMT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO09_0_E_SCHMT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO09_0_E_SCHMT_INIT_ENUM                      DISABLE
#define PADCTL_CONN_SOC_GPIO09_0_E_SCHMT_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO09_0_E_SCHMT_ENABLE                 _MK_ENUM_CONST(1)


// Register PADCTL_CONN_CFG2TMC_SOC_GPIO09_0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0                        _MK_ADDR_CONST(0x7c)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_SECURE                         0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_DUAL                   0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_SCR                    SCR_SOC_GPIO09_0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_WORD_COUNT                     0x1
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_RESET_MASK                     _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_READ_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_WRITE_MASK                     _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_CFG_CAL_DRVDN_FIELD                    _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_CFG_CAL_DRVDN_RANGE                    16:12
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_CFG_CAL_DRVDN_WOFFSET                  0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_CFG_CAL_DRVDN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_CFG_CAL_DRVUP_FIELD                    _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_CFG_CAL_DRVUP_RANGE                    24:20
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_CFG_CAL_DRVUP_WOFFSET                  0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_CFG_CAL_DRVUP_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO09_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register PADCTL_CONN_SOC_GPIO10_0
#define PADCTL_CONN_SOC_GPIO10_0                        _MK_ADDR_CONST(0x80)
#define PADCTL_CONN_SOC_GPIO10_0_SECURE                         0x0
#define PADCTL_CONN_SOC_GPIO10_0_DUAL                   0x0
#define PADCTL_CONN_SOC_GPIO10_0_SCR                    SCR_SOC_GPIO10_0
#define PADCTL_CONN_SOC_GPIO10_0_WORD_COUNT                     0x1
#define PADCTL_CONN_SOC_GPIO10_0_RESET_VAL                      _MK_MASK_CONST(0x410)
#define PADCTL_CONN_SOC_GPIO10_0_RESET_MASK                     _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO10_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_READ_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO10_0_WRITE_MASK                     _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO10_0_PM_SHIFT                       _MK_SHIFT_CONST(0)
#define PADCTL_CONN_SOC_GPIO10_0_PM_FIELD                       _MK_FIELD_CONST(0x3, PADCTL_CONN_SOC_GPIO10_0_PM_SHIFT)
#define PADCTL_CONN_SOC_GPIO10_0_PM_RANGE                       1:0
#define PADCTL_CONN_SOC_GPIO10_0_PM_WOFFSET                     0x0
#define PADCTL_CONN_SOC_GPIO10_0_PM_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_PM_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define PADCTL_CONN_SOC_GPIO10_0_PM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_PM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_PM_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_PM_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO10_0_PM_INIT_ENUM                   GP
#define PADCTL_CONN_SOC_GPIO10_0_PM_GP                  _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO10_0_PM_RSVD1                       _MK_ENUM_CONST(1)
#define PADCTL_CONN_SOC_GPIO10_0_PM_RSVD2                       _MK_ENUM_CONST(2)
#define PADCTL_CONN_SOC_GPIO10_0_PM_RSVD3                       _MK_ENUM_CONST(3)

#define PADCTL_CONN_SOC_GPIO10_0_GPIO_SF_SEL_SHIFT                      _MK_SHIFT_CONST(10)
#define PADCTL_CONN_SOC_GPIO10_0_GPIO_SF_SEL_FIELD                      _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO10_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_CONN_SOC_GPIO10_0_GPIO_SF_SEL_RANGE                      10:10
#define PADCTL_CONN_SOC_GPIO10_0_GPIO_SF_SEL_WOFFSET                    0x0
#define PADCTL_CONN_SOC_GPIO10_0_GPIO_SF_SEL_DEFAULT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO10_0_GPIO_SF_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO10_0_GPIO_SF_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_GPIO_SF_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_GPIO_SF_SEL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO10_0_GPIO_SF_SEL_INIT_ENUM                  SFIO
#define PADCTL_CONN_SOC_GPIO10_0_GPIO_SF_SEL_GPIO                       _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO10_0_GPIO_SF_SEL_SFIO                       _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO10_0_TRISTATE_SHIFT                 _MK_SHIFT_CONST(4)
#define PADCTL_CONN_SOC_GPIO10_0_TRISTATE_FIELD                 _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO10_0_TRISTATE_SHIFT)
#define PADCTL_CONN_SOC_GPIO10_0_TRISTATE_RANGE                 4:4
#define PADCTL_CONN_SOC_GPIO10_0_TRISTATE_WOFFSET                       0x0
#define PADCTL_CONN_SOC_GPIO10_0_TRISTATE_DEFAULT                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO10_0_TRISTATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO10_0_TRISTATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_TRISTATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_TRISTATE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_TRISTATE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO10_0_TRISTATE_INIT_ENUM                     TRISTATE
#define PADCTL_CONN_SOC_GPIO10_0_TRISTATE_PASSTHROUGH                   _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO10_0_TRISTATE_TRISTATE                      _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO10_0_PUPD_SHIFT                     _MK_SHIFT_CONST(2)
#define PADCTL_CONN_SOC_GPIO10_0_PUPD_FIELD                     _MK_FIELD_CONST(0x3, PADCTL_CONN_SOC_GPIO10_0_PUPD_SHIFT)
#define PADCTL_CONN_SOC_GPIO10_0_PUPD_RANGE                     3:2
#define PADCTL_CONN_SOC_GPIO10_0_PUPD_WOFFSET                   0x0
#define PADCTL_CONN_SOC_GPIO10_0_PUPD_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_PUPD_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define PADCTL_CONN_SOC_GPIO10_0_PUPD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_PUPD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_PUPD_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_PUPD_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO10_0_PUPD_INIT_ENUM                 NONE
#define PADCTL_CONN_SOC_GPIO10_0_PUPD_NONE                      _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO10_0_PUPD_PULL_DOWN                 _MK_ENUM_CONST(1)
#define PADCTL_CONN_SOC_GPIO10_0_PUPD_PULL_UP                   _MK_ENUM_CONST(2)
#define PADCTL_CONN_SOC_GPIO10_0_PUPD_RSVD                      _MK_ENUM_CONST(3)

#define PADCTL_CONN_SOC_GPIO10_0_E_INPUT_SHIFT                  _MK_SHIFT_CONST(6)
#define PADCTL_CONN_SOC_GPIO10_0_E_INPUT_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO10_0_E_INPUT_SHIFT)
#define PADCTL_CONN_SOC_GPIO10_0_E_INPUT_RANGE                  6:6
#define PADCTL_CONN_SOC_GPIO10_0_E_INPUT_WOFFSET                        0x0
#define PADCTL_CONN_SOC_GPIO10_0_E_INPUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_E_INPUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO10_0_E_INPUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_E_INPUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_E_INPUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_E_INPUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO10_0_E_INPUT_INIT_ENUM                      DISABLE
#define PADCTL_CONN_SOC_GPIO10_0_E_INPUT_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO10_0_E_INPUT_ENABLE                 _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO10_0_E_LPDR_SHIFT                   _MK_SHIFT_CONST(8)
#define PADCTL_CONN_SOC_GPIO10_0_E_LPDR_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO10_0_E_LPDR_SHIFT)
#define PADCTL_CONN_SOC_GPIO10_0_E_LPDR_RANGE                   8:8
#define PADCTL_CONN_SOC_GPIO10_0_E_LPDR_WOFFSET                 0x0
#define PADCTL_CONN_SOC_GPIO10_0_E_LPDR_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_E_LPDR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO10_0_E_LPDR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_E_LPDR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_E_LPDR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_E_LPDR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO10_0_E_LPDR_INIT_ENUM                       DISABLE
#define PADCTL_CONN_SOC_GPIO10_0_E_LPDR_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO10_0_E_LPDR_ENABLE                  _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO10_0_E_SCHMT_SHIFT                  _MK_SHIFT_CONST(12)
#define PADCTL_CONN_SOC_GPIO10_0_E_SCHMT_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO10_0_E_SCHMT_SHIFT)
#define PADCTL_CONN_SOC_GPIO10_0_E_SCHMT_RANGE                  12:12
#define PADCTL_CONN_SOC_GPIO10_0_E_SCHMT_WOFFSET                        0x0
#define PADCTL_CONN_SOC_GPIO10_0_E_SCHMT_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_E_SCHMT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO10_0_E_SCHMT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_E_SCHMT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_E_SCHMT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO10_0_E_SCHMT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO10_0_E_SCHMT_INIT_ENUM                      DISABLE
#define PADCTL_CONN_SOC_GPIO10_0_E_SCHMT_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO10_0_E_SCHMT_ENABLE                 _MK_ENUM_CONST(1)


// Register PADCTL_CONN_CFG2TMC_SOC_GPIO10_0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0                        _MK_ADDR_CONST(0x84)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_SECURE                         0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_DUAL                   0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_SCR                    SCR_SOC_GPIO10_0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_WORD_COUNT                     0x1
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_RESET_MASK                     _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_READ_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_WRITE_MASK                     _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_CFG_CAL_DRVDN_FIELD                    _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_CFG_CAL_DRVDN_RANGE                    16:12
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_CFG_CAL_DRVDN_WOFFSET                  0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_CFG_CAL_DRVDN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_CFG_CAL_DRVUP_FIELD                    _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_CFG_CAL_DRVUP_RANGE                    24:20
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_CFG_CAL_DRVUP_WOFFSET                  0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_CFG_CAL_DRVUP_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO10_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register PADCTL_CONN_SOC_GPIO11_0
#define PADCTL_CONN_SOC_GPIO11_0                        _MK_ADDR_CONST(0x88)
#define PADCTL_CONN_SOC_GPIO11_0_SECURE                         0x0
#define PADCTL_CONN_SOC_GPIO11_0_DUAL                   0x0
#define PADCTL_CONN_SOC_GPIO11_0_SCR                    SCR_SOC_GPIO11_0
#define PADCTL_CONN_SOC_GPIO11_0_WORD_COUNT                     0x1
#define PADCTL_CONN_SOC_GPIO11_0_RESET_VAL                      _MK_MASK_CONST(0x454)
#define PADCTL_CONN_SOC_GPIO11_0_RESET_MASK                     _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO11_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO11_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO11_0_READ_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO11_0_WRITE_MASK                     _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO11_0_PM_SHIFT                       _MK_SHIFT_CONST(0)
#define PADCTL_CONN_SOC_GPIO11_0_PM_FIELD                       _MK_FIELD_CONST(0x3, PADCTL_CONN_SOC_GPIO11_0_PM_SHIFT)
#define PADCTL_CONN_SOC_GPIO11_0_PM_RANGE                       1:0
#define PADCTL_CONN_SOC_GPIO11_0_PM_WOFFSET                     0x0
#define PADCTL_CONN_SOC_GPIO11_0_PM_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO11_0_PM_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define PADCTL_CONN_SOC_GPIO11_0_PM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO11_0_PM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO11_0_PM_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO11_0_PM_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO11_0_PM_INIT_ENUM                   RSVD0
#define PADCTL_CONN_SOC_GPIO11_0_PM_RSVD0                       _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO11_0_PM_SDMMC1                      _MK_ENUM_CONST(1)
#define PADCTL_CONN_SOC_GPIO11_0_PM_RSVD2                       _MK_ENUM_CONST(2)
#define PADCTL_CONN_SOC_GPIO11_0_PM_RSVD3                       _MK_ENUM_CONST(3)

#define PADCTL_CONN_SOC_GPIO11_0_GPIO_SF_SEL_SHIFT                      _MK_SHIFT_CONST(10)
#define PADCTL_CONN_SOC_GPIO11_0_GPIO_SF_SEL_FIELD                      _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO11_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_CONN_SOC_GPIO11_0_GPIO_SF_SEL_RANGE                      10:10
#define PADCTL_CONN_SOC_GPIO11_0_GPIO_SF_SEL_WOFFSET                    0x0
#define PADCTL_CONN_SOC_GPIO11_0_GPIO_SF_SEL_DEFAULT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO11_0_GPIO_SF_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO11_0_GPIO_SF_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO11_0_GPIO_SF_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO11_0_GPIO_SF_SEL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO11_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO11_0_GPIO_SF_SEL_INIT_ENUM                  SFIO
#define PADCTL_CONN_SOC_GPIO11_0_GPIO_SF_SEL_GPIO                       _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO11_0_GPIO_SF_SEL_SFIO                       _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO11_0_TRISTATE_SHIFT                 _MK_SHIFT_CONST(4)
#define PADCTL_CONN_SOC_GPIO11_0_TRISTATE_FIELD                 _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO11_0_TRISTATE_SHIFT)
#define PADCTL_CONN_SOC_GPIO11_0_TRISTATE_RANGE                 4:4
#define PADCTL_CONN_SOC_GPIO11_0_TRISTATE_WOFFSET                       0x0
#define PADCTL_CONN_SOC_GPIO11_0_TRISTATE_DEFAULT                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO11_0_TRISTATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO11_0_TRISTATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO11_0_TRISTATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO11_0_TRISTATE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO11_0_TRISTATE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO11_0_TRISTATE_INIT_ENUM                     TRISTATE
#define PADCTL_CONN_SOC_GPIO11_0_TRISTATE_PASSTHROUGH                   _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO11_0_TRISTATE_TRISTATE                      _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO11_0_PUPD_SHIFT                     _MK_SHIFT_CONST(2)
#define PADCTL_CONN_SOC_GPIO11_0_PUPD_FIELD                     _MK_FIELD_CONST(0x3, PADCTL_CONN_SOC_GPIO11_0_PUPD_SHIFT)
#define PADCTL_CONN_SOC_GPIO11_0_PUPD_RANGE                     3:2
#define PADCTL_CONN_SOC_GPIO11_0_PUPD_WOFFSET                   0x0
#define PADCTL_CONN_SOC_GPIO11_0_PUPD_DEFAULT                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO11_0_PUPD_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define PADCTL_CONN_SOC_GPIO11_0_PUPD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO11_0_PUPD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO11_0_PUPD_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO11_0_PUPD_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO11_0_PUPD_INIT_ENUM                 PULL_DOWN
#define PADCTL_CONN_SOC_GPIO11_0_PUPD_NONE                      _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO11_0_PUPD_PULL_DOWN                 _MK_ENUM_CONST(1)
#define PADCTL_CONN_SOC_GPIO11_0_PUPD_PULL_UP                   _MK_ENUM_CONST(2)
#define PADCTL_CONN_SOC_GPIO11_0_PUPD_RSVD                      _MK_ENUM_CONST(3)

#define PADCTL_CONN_SOC_GPIO11_0_E_INPUT_SHIFT                  _MK_SHIFT_CONST(6)
#define PADCTL_CONN_SOC_GPIO11_0_E_INPUT_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO11_0_E_INPUT_SHIFT)
#define PADCTL_CONN_SOC_GPIO11_0_E_INPUT_RANGE                  6:6
#define PADCTL_CONN_SOC_GPIO11_0_E_INPUT_WOFFSET                        0x0
#define PADCTL_CONN_SOC_GPIO11_0_E_INPUT_DEFAULT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO11_0_E_INPUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO11_0_E_INPUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO11_0_E_INPUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO11_0_E_INPUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO11_0_E_INPUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO11_0_E_INPUT_INIT_ENUM                      ENABLE
#define PADCTL_CONN_SOC_GPIO11_0_E_INPUT_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO11_0_E_INPUT_ENABLE                 _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO11_0_E_LPDR_SHIFT                   _MK_SHIFT_CONST(8)
#define PADCTL_CONN_SOC_GPIO11_0_E_LPDR_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO11_0_E_LPDR_SHIFT)
#define PADCTL_CONN_SOC_GPIO11_0_E_LPDR_RANGE                   8:8
#define PADCTL_CONN_SOC_GPIO11_0_E_LPDR_WOFFSET                 0x0
#define PADCTL_CONN_SOC_GPIO11_0_E_LPDR_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO11_0_E_LPDR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO11_0_E_LPDR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO11_0_E_LPDR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO11_0_E_LPDR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO11_0_E_LPDR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO11_0_E_LPDR_INIT_ENUM                       DISABLE
#define PADCTL_CONN_SOC_GPIO11_0_E_LPDR_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO11_0_E_LPDR_ENABLE                  _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO11_0_E_SCHMT_SHIFT                  _MK_SHIFT_CONST(12)
#define PADCTL_CONN_SOC_GPIO11_0_E_SCHMT_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO11_0_E_SCHMT_SHIFT)
#define PADCTL_CONN_SOC_GPIO11_0_E_SCHMT_RANGE                  12:12
#define PADCTL_CONN_SOC_GPIO11_0_E_SCHMT_WOFFSET                        0x0
#define PADCTL_CONN_SOC_GPIO11_0_E_SCHMT_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO11_0_E_SCHMT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO11_0_E_SCHMT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO11_0_E_SCHMT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO11_0_E_SCHMT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO11_0_E_SCHMT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO11_0_E_SCHMT_INIT_ENUM                      DISABLE
#define PADCTL_CONN_SOC_GPIO11_0_E_SCHMT_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO11_0_E_SCHMT_ENABLE                 _MK_ENUM_CONST(1)


// Register PADCTL_CONN_CFG2TMC_SOC_GPIO11_0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0                        _MK_ADDR_CONST(0x8c)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_SECURE                         0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_DUAL                   0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_SCR                    SCR_SOC_GPIO11_0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_WORD_COUNT                     0x1
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_RESET_MASK                     _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_READ_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_WRITE_MASK                     _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_CFG_CAL_DRVDN_FIELD                    _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_CFG_CAL_DRVDN_RANGE                    16:12
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_CFG_CAL_DRVDN_WOFFSET                  0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_CFG_CAL_DRVDN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_CFG_CAL_DRVUP_FIELD                    _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_CFG_CAL_DRVUP_RANGE                    24:20
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_CFG_CAL_DRVUP_WOFFSET                  0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_CFG_CAL_DRVUP_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO11_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register PADCTL_CONN_SOC_GPIO12_0
#define PADCTL_CONN_SOC_GPIO12_0                        _MK_ADDR_CONST(0x90)
#define PADCTL_CONN_SOC_GPIO12_0_SECURE                         0x0
#define PADCTL_CONN_SOC_GPIO12_0_DUAL                   0x0
#define PADCTL_CONN_SOC_GPIO12_0_SCR                    SCR_SOC_GPIO12_0
#define PADCTL_CONN_SOC_GPIO12_0_WORD_COUNT                     0x1
#define PADCTL_CONN_SOC_GPIO12_0_RESET_VAL                      _MK_MASK_CONST(0x410)
#define PADCTL_CONN_SOC_GPIO12_0_RESET_MASK                     _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO12_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_READ_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO12_0_WRITE_MASK                     _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO12_0_PM_SHIFT                       _MK_SHIFT_CONST(0)
#define PADCTL_CONN_SOC_GPIO12_0_PM_FIELD                       _MK_FIELD_CONST(0x3, PADCTL_CONN_SOC_GPIO12_0_PM_SHIFT)
#define PADCTL_CONN_SOC_GPIO12_0_PM_RANGE                       1:0
#define PADCTL_CONN_SOC_GPIO12_0_PM_WOFFSET                     0x0
#define PADCTL_CONN_SOC_GPIO12_0_PM_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_PM_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define PADCTL_CONN_SOC_GPIO12_0_PM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_PM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_PM_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_PM_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO12_0_PM_INIT_ENUM                   RSVD0
#define PADCTL_CONN_SOC_GPIO12_0_PM_RSVD0                       _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO12_0_PM_GP                  _MK_ENUM_CONST(1)
#define PADCTL_CONN_SOC_GPIO12_0_PM_RSVD2                       _MK_ENUM_CONST(2)
#define PADCTL_CONN_SOC_GPIO12_0_PM_RSVD3                       _MK_ENUM_CONST(3)

#define PADCTL_CONN_SOC_GPIO12_0_GPIO_SF_SEL_SHIFT                      _MK_SHIFT_CONST(10)
#define PADCTL_CONN_SOC_GPIO12_0_GPIO_SF_SEL_FIELD                      _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO12_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_CONN_SOC_GPIO12_0_GPIO_SF_SEL_RANGE                      10:10
#define PADCTL_CONN_SOC_GPIO12_0_GPIO_SF_SEL_WOFFSET                    0x0
#define PADCTL_CONN_SOC_GPIO12_0_GPIO_SF_SEL_DEFAULT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO12_0_GPIO_SF_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO12_0_GPIO_SF_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_GPIO_SF_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_GPIO_SF_SEL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO12_0_GPIO_SF_SEL_INIT_ENUM                  SFIO
#define PADCTL_CONN_SOC_GPIO12_0_GPIO_SF_SEL_GPIO                       _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO12_0_GPIO_SF_SEL_SFIO                       _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO12_0_TRISTATE_SHIFT                 _MK_SHIFT_CONST(4)
#define PADCTL_CONN_SOC_GPIO12_0_TRISTATE_FIELD                 _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO12_0_TRISTATE_SHIFT)
#define PADCTL_CONN_SOC_GPIO12_0_TRISTATE_RANGE                 4:4
#define PADCTL_CONN_SOC_GPIO12_0_TRISTATE_WOFFSET                       0x0
#define PADCTL_CONN_SOC_GPIO12_0_TRISTATE_DEFAULT                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO12_0_TRISTATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO12_0_TRISTATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_TRISTATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_TRISTATE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_TRISTATE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO12_0_TRISTATE_INIT_ENUM                     TRISTATE
#define PADCTL_CONN_SOC_GPIO12_0_TRISTATE_PASSTHROUGH                   _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO12_0_TRISTATE_TRISTATE                      _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO12_0_PUPD_SHIFT                     _MK_SHIFT_CONST(2)
#define PADCTL_CONN_SOC_GPIO12_0_PUPD_FIELD                     _MK_FIELD_CONST(0x3, PADCTL_CONN_SOC_GPIO12_0_PUPD_SHIFT)
#define PADCTL_CONN_SOC_GPIO12_0_PUPD_RANGE                     3:2
#define PADCTL_CONN_SOC_GPIO12_0_PUPD_WOFFSET                   0x0
#define PADCTL_CONN_SOC_GPIO12_0_PUPD_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_PUPD_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define PADCTL_CONN_SOC_GPIO12_0_PUPD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_PUPD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_PUPD_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_PUPD_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO12_0_PUPD_INIT_ENUM                 NONE
#define PADCTL_CONN_SOC_GPIO12_0_PUPD_NONE                      _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO12_0_PUPD_PULL_DOWN                 _MK_ENUM_CONST(1)
#define PADCTL_CONN_SOC_GPIO12_0_PUPD_PULL_UP                   _MK_ENUM_CONST(2)
#define PADCTL_CONN_SOC_GPIO12_0_PUPD_RSVD                      _MK_ENUM_CONST(3)

#define PADCTL_CONN_SOC_GPIO12_0_E_INPUT_SHIFT                  _MK_SHIFT_CONST(6)
#define PADCTL_CONN_SOC_GPIO12_0_E_INPUT_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO12_0_E_INPUT_SHIFT)
#define PADCTL_CONN_SOC_GPIO12_0_E_INPUT_RANGE                  6:6
#define PADCTL_CONN_SOC_GPIO12_0_E_INPUT_WOFFSET                        0x0
#define PADCTL_CONN_SOC_GPIO12_0_E_INPUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_E_INPUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO12_0_E_INPUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_E_INPUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_E_INPUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_E_INPUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO12_0_E_INPUT_INIT_ENUM                      DISABLE
#define PADCTL_CONN_SOC_GPIO12_0_E_INPUT_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO12_0_E_INPUT_ENABLE                 _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO12_0_E_LPDR_SHIFT                   _MK_SHIFT_CONST(8)
#define PADCTL_CONN_SOC_GPIO12_0_E_LPDR_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO12_0_E_LPDR_SHIFT)
#define PADCTL_CONN_SOC_GPIO12_0_E_LPDR_RANGE                   8:8
#define PADCTL_CONN_SOC_GPIO12_0_E_LPDR_WOFFSET                 0x0
#define PADCTL_CONN_SOC_GPIO12_0_E_LPDR_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_E_LPDR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO12_0_E_LPDR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_E_LPDR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_E_LPDR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_E_LPDR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO12_0_E_LPDR_INIT_ENUM                       DISABLE
#define PADCTL_CONN_SOC_GPIO12_0_E_LPDR_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO12_0_E_LPDR_ENABLE                  _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO12_0_E_SCHMT_SHIFT                  _MK_SHIFT_CONST(12)
#define PADCTL_CONN_SOC_GPIO12_0_E_SCHMT_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO12_0_E_SCHMT_SHIFT)
#define PADCTL_CONN_SOC_GPIO12_0_E_SCHMT_RANGE                  12:12
#define PADCTL_CONN_SOC_GPIO12_0_E_SCHMT_WOFFSET                        0x0
#define PADCTL_CONN_SOC_GPIO12_0_E_SCHMT_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_E_SCHMT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO12_0_E_SCHMT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_E_SCHMT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_E_SCHMT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO12_0_E_SCHMT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO12_0_E_SCHMT_INIT_ENUM                      DISABLE
#define PADCTL_CONN_SOC_GPIO12_0_E_SCHMT_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO12_0_E_SCHMT_ENABLE                 _MK_ENUM_CONST(1)


// Register PADCTL_CONN_CFG2TMC_SOC_GPIO12_0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0                        _MK_ADDR_CONST(0x94)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_SECURE                         0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_DUAL                   0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_SCR                    SCR_SOC_GPIO12_0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_WORD_COUNT                     0x1
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_RESET_MASK                     _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_READ_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_WRITE_MASK                     _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_CFG_CAL_DRVDN_FIELD                    _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_CFG_CAL_DRVDN_RANGE                    16:12
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_CFG_CAL_DRVDN_WOFFSET                  0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_CFG_CAL_DRVDN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_CFG_CAL_DRVUP_FIELD                    _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_CFG_CAL_DRVUP_RANGE                    24:20
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_CFG_CAL_DRVUP_WOFFSET                  0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_CFG_CAL_DRVUP_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO12_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register PADCTL_CONN_SOC_GPIO13_0
#define PADCTL_CONN_SOC_GPIO13_0                        _MK_ADDR_CONST(0x98)
#define PADCTL_CONN_SOC_GPIO13_0_SECURE                         0x0
#define PADCTL_CONN_SOC_GPIO13_0_DUAL                   0x0
#define PADCTL_CONN_SOC_GPIO13_0_SCR                    SCR_SOC_GPIO13_0
#define PADCTL_CONN_SOC_GPIO13_0_WORD_COUNT                     0x1
#define PADCTL_CONN_SOC_GPIO13_0_RESET_VAL                      _MK_MASK_CONST(0x410)
#define PADCTL_CONN_SOC_GPIO13_0_RESET_MASK                     _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO13_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_READ_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO13_0_WRITE_MASK                     _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO13_0_PM_SHIFT                       _MK_SHIFT_CONST(0)
#define PADCTL_CONN_SOC_GPIO13_0_PM_FIELD                       _MK_FIELD_CONST(0x3, PADCTL_CONN_SOC_GPIO13_0_PM_SHIFT)
#define PADCTL_CONN_SOC_GPIO13_0_PM_RANGE                       1:0
#define PADCTL_CONN_SOC_GPIO13_0_PM_WOFFSET                     0x0
#define PADCTL_CONN_SOC_GPIO13_0_PM_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_PM_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define PADCTL_CONN_SOC_GPIO13_0_PM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_PM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_PM_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_PM_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO13_0_PM_INIT_ENUM                   RSVD0
#define PADCTL_CONN_SOC_GPIO13_0_PM_RSVD0                       _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO13_0_PM_GP                  _MK_ENUM_CONST(1)
#define PADCTL_CONN_SOC_GPIO13_0_PM_RSVD2                       _MK_ENUM_CONST(2)
#define PADCTL_CONN_SOC_GPIO13_0_PM_RSVD3                       _MK_ENUM_CONST(3)

#define PADCTL_CONN_SOC_GPIO13_0_GPIO_SF_SEL_SHIFT                      _MK_SHIFT_CONST(10)
#define PADCTL_CONN_SOC_GPIO13_0_GPIO_SF_SEL_FIELD                      _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO13_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_CONN_SOC_GPIO13_0_GPIO_SF_SEL_RANGE                      10:10
#define PADCTL_CONN_SOC_GPIO13_0_GPIO_SF_SEL_WOFFSET                    0x0
#define PADCTL_CONN_SOC_GPIO13_0_GPIO_SF_SEL_DEFAULT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO13_0_GPIO_SF_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO13_0_GPIO_SF_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_GPIO_SF_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_GPIO_SF_SEL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO13_0_GPIO_SF_SEL_INIT_ENUM                  SFIO
#define PADCTL_CONN_SOC_GPIO13_0_GPIO_SF_SEL_GPIO                       _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO13_0_GPIO_SF_SEL_SFIO                       _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO13_0_TRISTATE_SHIFT                 _MK_SHIFT_CONST(4)
#define PADCTL_CONN_SOC_GPIO13_0_TRISTATE_FIELD                 _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO13_0_TRISTATE_SHIFT)
#define PADCTL_CONN_SOC_GPIO13_0_TRISTATE_RANGE                 4:4
#define PADCTL_CONN_SOC_GPIO13_0_TRISTATE_WOFFSET                       0x0
#define PADCTL_CONN_SOC_GPIO13_0_TRISTATE_DEFAULT                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO13_0_TRISTATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO13_0_TRISTATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_TRISTATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_TRISTATE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_TRISTATE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO13_0_TRISTATE_INIT_ENUM                     TRISTATE
#define PADCTL_CONN_SOC_GPIO13_0_TRISTATE_PASSTHROUGH                   _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO13_0_TRISTATE_TRISTATE                      _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO13_0_PUPD_SHIFT                     _MK_SHIFT_CONST(2)
#define PADCTL_CONN_SOC_GPIO13_0_PUPD_FIELD                     _MK_FIELD_CONST(0x3, PADCTL_CONN_SOC_GPIO13_0_PUPD_SHIFT)
#define PADCTL_CONN_SOC_GPIO13_0_PUPD_RANGE                     3:2
#define PADCTL_CONN_SOC_GPIO13_0_PUPD_WOFFSET                   0x0
#define PADCTL_CONN_SOC_GPIO13_0_PUPD_DEFAULT                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_PUPD_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define PADCTL_CONN_SOC_GPIO13_0_PUPD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_PUPD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_PUPD_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_PUPD_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO13_0_PUPD_INIT_ENUM                 NONE
#define PADCTL_CONN_SOC_GPIO13_0_PUPD_NONE                      _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO13_0_PUPD_PULL_DOWN                 _MK_ENUM_CONST(1)
#define PADCTL_CONN_SOC_GPIO13_0_PUPD_PULL_UP                   _MK_ENUM_CONST(2)
#define PADCTL_CONN_SOC_GPIO13_0_PUPD_RSVD                      _MK_ENUM_CONST(3)

#define PADCTL_CONN_SOC_GPIO13_0_E_INPUT_SHIFT                  _MK_SHIFT_CONST(6)
#define PADCTL_CONN_SOC_GPIO13_0_E_INPUT_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO13_0_E_INPUT_SHIFT)
#define PADCTL_CONN_SOC_GPIO13_0_E_INPUT_RANGE                  6:6
#define PADCTL_CONN_SOC_GPIO13_0_E_INPUT_WOFFSET                        0x0
#define PADCTL_CONN_SOC_GPIO13_0_E_INPUT_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_E_INPUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO13_0_E_INPUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_E_INPUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_E_INPUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_E_INPUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO13_0_E_INPUT_INIT_ENUM                      DISABLE
#define PADCTL_CONN_SOC_GPIO13_0_E_INPUT_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO13_0_E_INPUT_ENABLE                 _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO13_0_E_LPDR_SHIFT                   _MK_SHIFT_CONST(8)
#define PADCTL_CONN_SOC_GPIO13_0_E_LPDR_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO13_0_E_LPDR_SHIFT)
#define PADCTL_CONN_SOC_GPIO13_0_E_LPDR_RANGE                   8:8
#define PADCTL_CONN_SOC_GPIO13_0_E_LPDR_WOFFSET                 0x0
#define PADCTL_CONN_SOC_GPIO13_0_E_LPDR_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_E_LPDR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO13_0_E_LPDR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_E_LPDR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_E_LPDR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_E_LPDR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO13_0_E_LPDR_INIT_ENUM                       DISABLE
#define PADCTL_CONN_SOC_GPIO13_0_E_LPDR_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO13_0_E_LPDR_ENABLE                  _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO13_0_E_SCHMT_SHIFT                  _MK_SHIFT_CONST(12)
#define PADCTL_CONN_SOC_GPIO13_0_E_SCHMT_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO13_0_E_SCHMT_SHIFT)
#define PADCTL_CONN_SOC_GPIO13_0_E_SCHMT_RANGE                  12:12
#define PADCTL_CONN_SOC_GPIO13_0_E_SCHMT_WOFFSET                        0x0
#define PADCTL_CONN_SOC_GPIO13_0_E_SCHMT_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_E_SCHMT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO13_0_E_SCHMT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_E_SCHMT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_E_SCHMT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO13_0_E_SCHMT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO13_0_E_SCHMT_INIT_ENUM                      DISABLE
#define PADCTL_CONN_SOC_GPIO13_0_E_SCHMT_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO13_0_E_SCHMT_ENABLE                 _MK_ENUM_CONST(1)


// Register PADCTL_CONN_CFG2TMC_SOC_GPIO13_0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0                        _MK_ADDR_CONST(0x9c)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_SECURE                         0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_DUAL                   0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_SCR                    SCR_SOC_GPIO13_0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_WORD_COUNT                     0x1
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_RESET_MASK                     _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_READ_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_WRITE_MASK                     _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_CFG_CAL_DRVDN_FIELD                    _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_CFG_CAL_DRVDN_RANGE                    16:12
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_CFG_CAL_DRVDN_WOFFSET                  0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_CFG_CAL_DRVDN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_CFG_CAL_DRVUP_FIELD                    _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_CFG_CAL_DRVUP_RANGE                    24:20
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_CFG_CAL_DRVUP_WOFFSET                  0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_CFG_CAL_DRVUP_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO13_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register PADCTL_CONN_SOC_GPIO14_0
#define PADCTL_CONN_SOC_GPIO14_0                        _MK_ADDR_CONST(0xa0)
#define PADCTL_CONN_SOC_GPIO14_0_SECURE                         0x0
#define PADCTL_CONN_SOC_GPIO14_0_DUAL                   0x0
#define PADCTL_CONN_SOC_GPIO14_0_SCR                    SCR_SOC_GPIO14_0
#define PADCTL_CONN_SOC_GPIO14_0_WORD_COUNT                     0x1
#define PADCTL_CONN_SOC_GPIO14_0_RESET_VAL                      _MK_MASK_CONST(0x454)
#define PADCTL_CONN_SOC_GPIO14_0_RESET_MASK                     _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO14_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO14_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO14_0_READ_MASK                      _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO14_0_WRITE_MASK                     _MK_MASK_CONST(0x155f)
#define PADCTL_CONN_SOC_GPIO14_0_PM_SHIFT                       _MK_SHIFT_CONST(0)
#define PADCTL_CONN_SOC_GPIO14_0_PM_FIELD                       _MK_FIELD_CONST(0x3, PADCTL_CONN_SOC_GPIO14_0_PM_SHIFT)
#define PADCTL_CONN_SOC_GPIO14_0_PM_RANGE                       1:0
#define PADCTL_CONN_SOC_GPIO14_0_PM_WOFFSET                     0x0
#define PADCTL_CONN_SOC_GPIO14_0_PM_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO14_0_PM_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define PADCTL_CONN_SOC_GPIO14_0_PM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO14_0_PM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO14_0_PM_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO14_0_PM_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO14_0_PM_INIT_ENUM                   RSVD0
#define PADCTL_CONN_SOC_GPIO14_0_PM_RSVD0                       _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO14_0_PM_RSVD1                       _MK_ENUM_CONST(1)
#define PADCTL_CONN_SOC_GPIO14_0_PM_RSVD2                       _MK_ENUM_CONST(2)
#define PADCTL_CONN_SOC_GPIO14_0_PM_RSVD3                       _MK_ENUM_CONST(3)

#define PADCTL_CONN_SOC_GPIO14_0_GPIO_SF_SEL_SHIFT                      _MK_SHIFT_CONST(10)
#define PADCTL_CONN_SOC_GPIO14_0_GPIO_SF_SEL_FIELD                      _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO14_0_GPIO_SF_SEL_SHIFT)
#define PADCTL_CONN_SOC_GPIO14_0_GPIO_SF_SEL_RANGE                      10:10
#define PADCTL_CONN_SOC_GPIO14_0_GPIO_SF_SEL_WOFFSET                    0x0
#define PADCTL_CONN_SOC_GPIO14_0_GPIO_SF_SEL_DEFAULT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO14_0_GPIO_SF_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO14_0_GPIO_SF_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO14_0_GPIO_SF_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO14_0_GPIO_SF_SEL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO14_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO14_0_GPIO_SF_SEL_INIT_ENUM                  SFIO
#define PADCTL_CONN_SOC_GPIO14_0_GPIO_SF_SEL_GPIO                       _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO14_0_GPIO_SF_SEL_SFIO                       _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO14_0_TRISTATE_SHIFT                 _MK_SHIFT_CONST(4)
#define PADCTL_CONN_SOC_GPIO14_0_TRISTATE_FIELD                 _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO14_0_TRISTATE_SHIFT)
#define PADCTL_CONN_SOC_GPIO14_0_TRISTATE_RANGE                 4:4
#define PADCTL_CONN_SOC_GPIO14_0_TRISTATE_WOFFSET                       0x0
#define PADCTL_CONN_SOC_GPIO14_0_TRISTATE_DEFAULT                       _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO14_0_TRISTATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO14_0_TRISTATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO14_0_TRISTATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO14_0_TRISTATE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO14_0_TRISTATE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO14_0_TRISTATE_INIT_ENUM                     TRISTATE
#define PADCTL_CONN_SOC_GPIO14_0_TRISTATE_PASSTHROUGH                   _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO14_0_TRISTATE_TRISTATE                      _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO14_0_PUPD_SHIFT                     _MK_SHIFT_CONST(2)
#define PADCTL_CONN_SOC_GPIO14_0_PUPD_FIELD                     _MK_FIELD_CONST(0x3, PADCTL_CONN_SOC_GPIO14_0_PUPD_SHIFT)
#define PADCTL_CONN_SOC_GPIO14_0_PUPD_RANGE                     3:2
#define PADCTL_CONN_SOC_GPIO14_0_PUPD_WOFFSET                   0x0
#define PADCTL_CONN_SOC_GPIO14_0_PUPD_DEFAULT                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO14_0_PUPD_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define PADCTL_CONN_SOC_GPIO14_0_PUPD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO14_0_PUPD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO14_0_PUPD_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO14_0_PUPD_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO14_0_PUPD_INIT_ENUM                 PULL_DOWN
#define PADCTL_CONN_SOC_GPIO14_0_PUPD_NONE                      _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO14_0_PUPD_PULL_DOWN                 _MK_ENUM_CONST(1)
#define PADCTL_CONN_SOC_GPIO14_0_PUPD_PULL_UP                   _MK_ENUM_CONST(2)
#define PADCTL_CONN_SOC_GPIO14_0_PUPD_RSVD                      _MK_ENUM_CONST(3)

#define PADCTL_CONN_SOC_GPIO14_0_E_INPUT_SHIFT                  _MK_SHIFT_CONST(6)
#define PADCTL_CONN_SOC_GPIO14_0_E_INPUT_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO14_0_E_INPUT_SHIFT)
#define PADCTL_CONN_SOC_GPIO14_0_E_INPUT_RANGE                  6:6
#define PADCTL_CONN_SOC_GPIO14_0_E_INPUT_WOFFSET                        0x0
#define PADCTL_CONN_SOC_GPIO14_0_E_INPUT_DEFAULT                        _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO14_0_E_INPUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO14_0_E_INPUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO14_0_E_INPUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO14_0_E_INPUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO14_0_E_INPUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO14_0_E_INPUT_INIT_ENUM                      ENABLE
#define PADCTL_CONN_SOC_GPIO14_0_E_INPUT_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO14_0_E_INPUT_ENABLE                 _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO14_0_E_LPDR_SHIFT                   _MK_SHIFT_CONST(8)
#define PADCTL_CONN_SOC_GPIO14_0_E_LPDR_FIELD                   _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO14_0_E_LPDR_SHIFT)
#define PADCTL_CONN_SOC_GPIO14_0_E_LPDR_RANGE                   8:8
#define PADCTL_CONN_SOC_GPIO14_0_E_LPDR_WOFFSET                 0x0
#define PADCTL_CONN_SOC_GPIO14_0_E_LPDR_DEFAULT                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO14_0_E_LPDR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO14_0_E_LPDR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO14_0_E_LPDR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO14_0_E_LPDR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO14_0_E_LPDR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO14_0_E_LPDR_INIT_ENUM                       DISABLE
#define PADCTL_CONN_SOC_GPIO14_0_E_LPDR_DISABLE                 _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO14_0_E_LPDR_ENABLE                  _MK_ENUM_CONST(1)

#define PADCTL_CONN_SOC_GPIO14_0_E_SCHMT_SHIFT                  _MK_SHIFT_CONST(12)
#define PADCTL_CONN_SOC_GPIO14_0_E_SCHMT_FIELD                  _MK_FIELD_CONST(0x1, PADCTL_CONN_SOC_GPIO14_0_E_SCHMT_SHIFT)
#define PADCTL_CONN_SOC_GPIO14_0_E_SCHMT_RANGE                  12:12
#define PADCTL_CONN_SOC_GPIO14_0_E_SCHMT_WOFFSET                        0x0
#define PADCTL_CONN_SOC_GPIO14_0_E_SCHMT_DEFAULT                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO14_0_E_SCHMT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO14_0_E_SCHMT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO14_0_E_SCHMT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO14_0_E_SCHMT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_SOC_GPIO14_0_E_SCHMT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define PADCTL_CONN_SOC_GPIO14_0_E_SCHMT_INIT_ENUM                      DISABLE
#define PADCTL_CONN_SOC_GPIO14_0_E_SCHMT_DISABLE                        _MK_ENUM_CONST(0)
#define PADCTL_CONN_SOC_GPIO14_0_E_SCHMT_ENABLE                 _MK_ENUM_CONST(1)


// Register PADCTL_CONN_CFG2TMC_SOC_GPIO14_0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0                        _MK_ADDR_CONST(0xa4)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_SECURE                         0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_DUAL                   0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_SCR                    SCR_SOC_GPIO14_0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_WORD_COUNT                     0x1
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_RESET_MASK                     _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_READ_MASK                      _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_WRITE_MASK                     _MK_MASK_CONST(0x1f1f000)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_CFG_CAL_DRVDN_FIELD                    _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_CFG_CAL_DRVDN_SHIFT)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_CFG_CAL_DRVDN_RANGE                    16:12
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_CFG_CAL_DRVDN_WOFFSET                  0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_CFG_CAL_DRVDN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_CFG_CAL_DRVUP_FIELD                    _MK_FIELD_CONST(0x1f, PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_CFG_CAL_DRVUP_SHIFT)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_CFG_CAL_DRVUP_RANGE                    24:20
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_CFG_CAL_DRVUP_WOFFSET                  0x0
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_CFG_CAL_DRVUP_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PADCTL_CONN_CFG2TMC_SOC_GPIO14_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


//
// REGISTER LIST
//
#define LIST_ARPADCTL_CONN_REGS(_op_) \
_op_(PADCTL_CONN_DAP2_DIN_0) \
_op_(PADCTL_CONN_CFG2TMC_DAP2_DIN_0) \
_op_(PADCTL_CONN_DAP2_DOUT_0) \
_op_(PADCTL_CONN_CFG2TMC_DAP2_DOUT_0) \
_op_(PADCTL_CONN_DAP2_FS_0) \
_op_(PADCTL_CONN_CFG2TMC_DAP2_FS_0) \
_op_(PADCTL_CONN_DAP2_SCLK_0) \
_op_(PADCTL_CONN_CFG2TMC_DAP2_SCLK_0) \
_op_(PADCTL_CONN_UART4_CTS_0) \
_op_(PADCTL_CONN_CFG2TMC_UART4_CTS_0) \
_op_(PADCTL_CONN_UART4_RTS_0) \
_op_(PADCTL_CONN_CFG2TMC_UART4_RTS_0) \
_op_(PADCTL_CONN_UART4_RX_0) \
_op_(PADCTL_CONN_CFG2TMC_UART4_RX_0) \
_op_(PADCTL_CONN_UART4_TX_0) \
_op_(PADCTL_CONN_CFG2TMC_UART4_TX_0) \
_op_(PADCTL_CONN_SOC_GPIO03_0) \
_op_(PADCTL_CONN_CFG2TMC_SOC_GPIO03_0) \
_op_(PADCTL_CONN_SOC_GPIO02_0) \
_op_(PADCTL_CONN_CFG2TMC_SOC_GPIO02_0) \
_op_(PADCTL_CONN_SOC_GPIO01_0) \
_op_(PADCTL_CONN_CFG2TMC_SOC_GPIO01_0) \
_op_(PADCTL_CONN_SOC_GPIO00_0) \
_op_(PADCTL_CONN_CFG2TMC_SOC_GPIO00_0) \
_op_(PADCTL_CONN_GEN1_I2C_SCL_0) \
_op_(PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0) \
_op_(PADCTL_CONN_GEN1_I2C_SDA_0) \
_op_(PADCTL_CONN_CFG2TMC_GEN1_I2C_SDA_0) \
_op_(PADCTL_CONN_SOC_GPIO08_0) \
_op_(PADCTL_CONN_CFG2TMC_SOC_GPIO08_0) \
_op_(PADCTL_CONN_SOC_GPIO09_0) \
_op_(PADCTL_CONN_CFG2TMC_SOC_GPIO09_0) \
_op_(PADCTL_CONN_SOC_GPIO10_0) \
_op_(PADCTL_CONN_CFG2TMC_SOC_GPIO10_0) \
_op_(PADCTL_CONN_SOC_GPIO11_0) \
_op_(PADCTL_CONN_CFG2TMC_SOC_GPIO11_0) \
_op_(PADCTL_CONN_SOC_GPIO12_0) \
_op_(PADCTL_CONN_CFG2TMC_SOC_GPIO12_0) \
_op_(PADCTL_CONN_SOC_GPIO13_0) \
_op_(PADCTL_CONN_CFG2TMC_SOC_GPIO13_0) \
_op_(PADCTL_CONN_SOC_GPIO14_0) \
_op_(PADCTL_CONN_CFG2TMC_SOC_GPIO14_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_PADCTL_CONN        0x00000000

//
// ARPADCTL_CONN REGISTER BANKS
//

#define PADCTL_CONN0_FIRST_REG 0x0000 // PADCTL_CONN_DAP2_DIN_0
#define PADCTL_CONN0_LAST_REG 0x00a4 // PADCTL_CONN_CFG2TMC_SOC_GPIO14_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif
#ifndef _MK_FIELD_CONST
  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
#endif

#endif // ifndef ___ARPADCTL_CONN_H_INC_
