#ifndef ARDEV_T_XUSB_DEV_XHCI_H_
#define ARDEV_T_XUSB_DEV_XHCI_H_

// generated by manual_ref_to_h.py from dev_t_xusb_dev_xhci.ref - do not edit

//
// Copyright (c) 2011 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
// 
// 
// 
// 
// 
// 
// 
// 
// 
//                            Tegra XHCI Device Mode Reference Manual
// 
//                         Rahul Jain ( rahjain@nvidia.com)
// 
//                                Nvidia Corporation
// 
//                            C1, Jacaranda, Manyata Embassy Business Park
// 
//                              Outer Ring Road, Bangalore - 560043
// 
// 
// 
//                                     $Id: //dev/stdif/xusb/1.2/manuals/dev_t_xusb_dev_xhci.ref#7 $
//                                   $Date: 2014/08/27 $
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// .ADDR_SPACE DEV_BAR0
// 
// 
// 
// //*****************************************************************************************************
// //*****************************************************************************************************
// //*****************************************************************************************************
// //*****************************************************************************************************
// 
// .TITLE ID Register
// Read only params register
// 
// .FIELD ERSTMAX
// Event Ring Segment Table Max
// Indicates the maximum value supported in the Event Ring Segment Table Base Size, where the maximum size of the Event Ring Segment Table is 2ERST Max
// 


#define XUSB_DEV_XHCI_SPARAM_0                             _MK_ADDR_CONST(0x00000000)
#define XUSB_DEV_XHCI_SPARAM_0_SECURE                      0
#define XUSB_DEV_XHCI_SPARAM_0_WORD_COUNT                  1
#define XUSB_DEV_XHCI_SPARAM_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_SPARAM_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_SPARAM_0_SW_DEFAULT_VAL              _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_SPARAM_0_SW_DEFAULT_MASK             _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_SPARAM_0_READ_MASK                   _MK_MASK_CONST(0x1fffff)
#define XUSB_DEV_XHCI_SPARAM_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_SPARAM_0_CLEAR_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_SPARAM_0_TGL_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_SPARAM_0_RSVD0_SHIFT                  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_SPARAM_0_RSVD0_FIELD                 (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_XHCI_SPARAM_0_RSVD0_SHIFT)
#define XUSB_DEV_XHCI_SPARAM_0_RSVD0_RANGE                 15:0
#define XUSB_DEV_XHCI_SPARAM_0_RSVD0_WOFFSET               0
#define XUSB_DEV_XHCI_SPARAM_0_RSVD0_INIT                  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_SPARAM_0_ERSTMAX_SHIFT                _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_SPARAM_0_ERSTMAX_FIELD               (_MK_SHIFT_CONST(0x1f) << XUSB_DEV_XHCI_SPARAM_0_ERSTMAX_SHIFT)
#define XUSB_DEV_XHCI_SPARAM_0_ERSTMAX_RANGE               20:16
#define XUSB_DEV_XHCI_SPARAM_0_ERSTMAX_WOFFSET             0
#define XUSB_DEV_XHCI_SPARAM_0_ERSTMAX_VALUE               _MK_ENUM_CONST(0x00000002)


// 
// .TITLE Doorbell Register
// Device mode doorbell register
// 
// .FIELD TARGET
// The target field represents the Endpoint ID to which the doorbell is targeted
//   00h: EP 0 Enqueue Pointer Update (Control EP 0)
//   even values: OUT Enqueue Pointer Update
//   odd values:  IN Enqueue Pointer Update
// 
// .FIELD STREAMID
// Only significant for control EPs and is used to represent the control sequence number
// Software is responsible for ensuring that the value written to this field matches the Sequence Number of a SETUP Packet Event
// STREAMID is not used for stream EPs
// 


#define XUSB_DEV_XHCI_DB_0                                 _MK_ADDR_CONST(0x00000004)
#define XUSB_DEV_XHCI_DB_0_SECURE                          0
#define XUSB_DEV_XHCI_DB_0_WORD_COUNT                      1
#define XUSB_DEV_XHCI_DB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_DB_0_RESET_MASK                      _MK_MASK_CONST(0xffffff00)
#define XUSB_DEV_XHCI_DB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_DB_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0xffffff00)
#define XUSB_DEV_XHCI_DB_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_DB_0_WRITE_MASK                      _MK_MASK_CONST(0xffffff00)
#define XUSB_DEV_XHCI_DB_0_CLEAR_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_DB_0_TGL_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_DB_0_RSVD0_SHIFT                      _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_DB_0_RSVD0_FIELD                     (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_DB_0_RSVD0_SHIFT)
#define XUSB_DEV_XHCI_DB_0_RSVD0_RANGE                     7:0
#define XUSB_DEV_XHCI_DB_0_RSVD0_WOFFSET                   0
#define XUSB_DEV_XHCI_DB_0_RSVD0_00                        _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_DB_0_TARGET_SHIFT                     _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_DB_0_TARGET_FIELD                    (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_DB_0_TARGET_SHIFT)
#define XUSB_DEV_XHCI_DB_0_TARGET_RANGE                    15:8
#define XUSB_DEV_XHCI_DB_0_TARGET_WOFFSET                  0
#define XUSB_DEV_XHCI_DB_0_TARGET_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_DB_0_TARGET_DEFAULT_MASK             (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_DB_0_TARGET_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_DB_0_TARGET_SW_DEFAULT_MASK          (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_DB_0_TARGET_INIT                     _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_DB_0_STREAMID_SHIFT                   _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_DB_0_STREAMID_FIELD                  (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_XHCI_DB_0_STREAMID_SHIFT)
#define XUSB_DEV_XHCI_DB_0_STREAMID_RANGE                  31:16
#define XUSB_DEV_XHCI_DB_0_STREAMID_WOFFSET                0
#define XUSB_DEV_XHCI_DB_0_STREAMID_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_DB_0_STREAMID_DEFAULT_MASK           (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_DB_0_STREAMID_SW_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_DB_0_STREAMID_SW_DEFAULT_MASK        (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_DB_0_STREAMID_00                     _MK_ENUM_CONST(0x00000000)


// 
// .TITLE Event Ring Segment Table Size Register
// Specify the size of each event ring segment in terms of number of event TRB slots (each slot is 16 bytes)
// the min value of size in each register is 16 and the max is 4096
// both the segments should be initialized with valid values
// 


#define XUSB_DEV_XHCI_ERSTSZ_0                             _MK_ADDR_CONST(0x00000008)
#define XUSB_DEV_XHCI_ERSTSZ_0_SECURE                      0
#define XUSB_DEV_XHCI_ERSTSZ_0_WORD_COUNT                  1
#define XUSB_DEV_XHCI_ERSTSZ_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ERSTSZ_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ERSTSZ_0_SW_DEFAULT_VAL              _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ERSTSZ_0_SW_DEFAULT_MASK             _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ERSTSZ_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ERSTSZ_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ERSTSZ_0_CLEAR_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ERSTSZ_0_TGL_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ERSTSZ_0_ERST0SZ_SHIFT                _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_ERSTSZ_0_ERST0SZ_FIELD               (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_XHCI_ERSTSZ_0_ERST0SZ_SHIFT)
#define XUSB_DEV_XHCI_ERSTSZ_0_ERST0SZ_RANGE               15:0
#define XUSB_DEV_XHCI_ERSTSZ_0_ERST0SZ_WOFFSET             0
#define XUSB_DEV_XHCI_ERSTSZ_0_ERST0SZ_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ERSTSZ_0_ERST0SZ_DEFAULT_MASK        (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_ERSTSZ_0_ERST0SZ_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ERSTSZ_0_ERST0SZ_SW_DEFAULT_MASK     (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_ERSTSZ_0_ERST0SZ_INIT                _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_ERSTSZ_0_ERST1SZ_SHIFT                _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_ERSTSZ_0_ERST1SZ_FIELD               (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_XHCI_ERSTSZ_0_ERST1SZ_SHIFT)
#define XUSB_DEV_XHCI_ERSTSZ_0_ERST1SZ_RANGE               31:16
#define XUSB_DEV_XHCI_ERSTSZ_0_ERST1SZ_WOFFSET             0
#define XUSB_DEV_XHCI_ERSTSZ_0_ERST1SZ_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ERSTSZ_0_ERST1SZ_DEFAULT_MASK        (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_ERSTSZ_0_ERST1SZ_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ERSTSZ_0_ERST1SZ_SW_DEFAULT_MASK     (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_ERSTSZ_0_ERST1SZ_INIT                _MK_ENUM_CONST(0x00000000)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_ERSTSZ__PRODCHK                                 0 /*       */
// 


#define XUSB_DEV_XHCI_RSVD0_0                              _MK_ADDR_CONST(0x0000000C)
#define XUSB_DEV_XHCI_RSVD0_0_SECURE                       0
#define XUSB_DEV_XHCI_RSVD0_0_WORD_COUNT                   1
#define XUSB_DEV_XHCI_RSVD0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_RSVD0_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_RSVD0_0_SW_DEFAULT_VAL               _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_RSVD0_0_SW_DEFAULT_MASK              _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_RSVD0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_RSVD0_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_RSVD0_0_CLEAR_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_RSVD0_0_TGL_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_RSVD0_0_RSVD0_SHIFT                   _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_RSVD0_0_RSVD0_FIELD                  (_MK_SHIFT_CONST(0xffffffff) << XUSB_DEV_XHCI_RSVD0_0_RSVD0_SHIFT)
#define XUSB_DEV_XHCI_RSVD0_0_RSVD0_RANGE                  31:0
#define XUSB_DEV_XHCI_RSVD0_0_RSVD0_WOFFSET                0
#define XUSB_DEV_XHCI_RSVD0_0_RSVD0_00                     _MK_ENUM_CONST(0x00000000)


// 
// .TITLE Event Ring Segment 0 Base Address Register
// 


#define XUSB_DEV_XHCI_ERST0BALO_0                          _MK_ADDR_CONST(0x00000010)
#define XUSB_DEV_XHCI_ERST0BALO_0_SECURE                   0
#define XUSB_DEV_XHCI_ERST0BALO_0_WORD_COUNT               1
#define XUSB_DEV_XHCI_ERST0BALO_0_RESET_VAL                _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ERST0BALO_0_RESET_MASK               _MK_MASK_CONST(0xfffffff0)
#define XUSB_DEV_XHCI_ERST0BALO_0_SW_DEFAULT_VAL           _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ERST0BALO_0_SW_DEFAULT_MASK          _MK_MASK_CONST(0xfffffff0)
#define XUSB_DEV_XHCI_ERST0BALO_0_READ_MASK                _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ERST0BALO_0_WRITE_MASK               _MK_MASK_CONST(0xfffffff0)
#define XUSB_DEV_XHCI_ERST0BALO_0_CLEAR_MASK               _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ERST0BALO_0_TGL_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ERST0BALO_0_RSVD0_SHIFT               _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_ERST0BALO_0_RSVD0_FIELD              (_MK_SHIFT_CONST(0xf) << XUSB_DEV_XHCI_ERST0BALO_0_RSVD0_SHIFT)
#define XUSB_DEV_XHCI_ERST0BALO_0_RSVD0_RANGE              3:0
#define XUSB_DEV_XHCI_ERST0BALO_0_RSVD0_WOFFSET            0
#define XUSB_DEV_XHCI_ERST0BALO_0_RSVD0_00                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_ERST0BALO_0_ADDRLO_SHIFT              _MK_SHIFT_CONST(4)
#define XUSB_DEV_XHCI_ERST0BALO_0_ADDRLO_FIELD             (_MK_SHIFT_CONST(0xfffffff) << XUSB_DEV_XHCI_ERST0BALO_0_ADDRLO_SHIFT)
#define XUSB_DEV_XHCI_ERST0BALO_0_ADDRLO_RANGE             31:4
#define XUSB_DEV_XHCI_ERST0BALO_0_ADDRLO_WOFFSET           0
#define XUSB_DEV_XHCI_ERST0BALO_0_ADDRLO_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ERST0BALO_0_ADDRLO_DEFAULT_MASK      (_MK_MASK_CONST(0xfffffff)
#define XUSB_DEV_XHCI_ERST0BALO_0_ADDRLO_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ERST0BALO_0_ADDRLO_SW_DEFAULT_MASK   (_MK_MASK_CONST(0xfffffff)
#define XUSB_DEV_XHCI_ERST0BALO_0_ADDRLO_INIT              _MK_ENUM_CONST(0x00000000)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_ERST0BALO__PRODCHK                              0 /*       */
// 


#define XUSB_DEV_XHCI_ERST0BAHI_0                          _MK_ADDR_CONST(0x00000014)
#define XUSB_DEV_XHCI_ERST0BAHI_0_SECURE                   0
#define XUSB_DEV_XHCI_ERST0BAHI_0_WORD_COUNT               1
#define XUSB_DEV_XHCI_ERST0BAHI_0_RESET_VAL                _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ERST0BAHI_0_RESET_MASK               _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ERST0BAHI_0_SW_DEFAULT_VAL           _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ERST0BAHI_0_SW_DEFAULT_MASK          _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ERST0BAHI_0_READ_MASK                _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ERST0BAHI_0_WRITE_MASK               _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ERST0BAHI_0_CLEAR_MASK               _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ERST0BAHI_0_TGL_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ERST0BAHI_0_ADDRHI_SHIFT              _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_ERST0BAHI_0_ADDRHI_FIELD             (_MK_SHIFT_CONST(0xffffffff) << XUSB_DEV_XHCI_ERST0BAHI_0_ADDRHI_SHIFT)
#define XUSB_DEV_XHCI_ERST0BAHI_0_ADDRHI_RANGE             31:0
#define XUSB_DEV_XHCI_ERST0BAHI_0_ADDRHI_WOFFSET           0
#define XUSB_DEV_XHCI_ERST0BAHI_0_ADDRHI_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ERST0BAHI_0_ADDRHI_DEFAULT_MASK      (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ERST0BAHI_0_ADDRHI_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ERST0BAHI_0_ADDRHI_SW_DEFAULT_MASK   (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ERST0BAHI_0_ADDRHI_INIT              _MK_ENUM_CONST(0x00000000)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_ERST0BAHI__PRODCHK                              0 /*       */
// 
// .TITLE Event Ring Segment 1 Base Address Register
// 


#define XUSB_DEV_XHCI_ERST1BALO_0                          _MK_ADDR_CONST(0x00000018)
#define XUSB_DEV_XHCI_ERST1BALO_0_SECURE                   0
#define XUSB_DEV_XHCI_ERST1BALO_0_WORD_COUNT               1
#define XUSB_DEV_XHCI_ERST1BALO_0_RESET_VAL                _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ERST1BALO_0_RESET_MASK               _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ERST1BALO_0_SW_DEFAULT_VAL           _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ERST1BALO_0_SW_DEFAULT_MASK          _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ERST1BALO_0_READ_MASK                _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ERST1BALO_0_WRITE_MASK               _MK_MASK_CONST(0xfffffff0)
#define XUSB_DEV_XHCI_ERST1BALO_0_CLEAR_MASK               _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ERST1BALO_0_TGL_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ERST1BALO_0_RSVD0_SHIFT               _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_ERST1BALO_0_RSVD0_FIELD              (_MK_SHIFT_CONST(0xf) << XUSB_DEV_XHCI_ERST1BALO_0_RSVD0_SHIFT)
#define XUSB_DEV_XHCI_ERST1BALO_0_RSVD0_RANGE              3:0
#define XUSB_DEV_XHCI_ERST1BALO_0_RSVD0_WOFFSET            0
#define XUSB_DEV_XHCI_ERST1BALO_0_RSVD0_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ERST1BALO_0_RSVD0_DEFAULT_MASK       (_MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_ERST1BALO_0_RSVD0_SW_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ERST1BALO_0_RSVD0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_ERST1BALO_0_RSVD0_00                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_ERST1BALO_0_ADDRLO_SHIFT              _MK_SHIFT_CONST(4)
#define XUSB_DEV_XHCI_ERST1BALO_0_ADDRLO_FIELD             (_MK_SHIFT_CONST(0xfffffff) << XUSB_DEV_XHCI_ERST1BALO_0_ADDRLO_SHIFT)
#define XUSB_DEV_XHCI_ERST1BALO_0_ADDRLO_RANGE             31:4
#define XUSB_DEV_XHCI_ERST1BALO_0_ADDRLO_WOFFSET           0
#define XUSB_DEV_XHCI_ERST1BALO_0_ADDRLO_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ERST1BALO_0_ADDRLO_DEFAULT_MASK      (_MK_MASK_CONST(0xfffffff)
#define XUSB_DEV_XHCI_ERST1BALO_0_ADDRLO_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ERST1BALO_0_ADDRLO_SW_DEFAULT_MASK   (_MK_MASK_CONST(0xfffffff)
#define XUSB_DEV_XHCI_ERST1BALO_0_ADDRLO_INIT              _MK_ENUM_CONST(0x00000000)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_ERST1BALO__PRODCHK                              0 /*       */
// 


#define XUSB_DEV_XHCI_ERST1BAHI_0                          _MK_ADDR_CONST(0x0000001C)
#define XUSB_DEV_XHCI_ERST1BAHI_0_SECURE                   0
#define XUSB_DEV_XHCI_ERST1BAHI_0_WORD_COUNT               1
#define XUSB_DEV_XHCI_ERST1BAHI_0_RESET_VAL                _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ERST1BAHI_0_RESET_MASK               _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ERST1BAHI_0_SW_DEFAULT_VAL           _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ERST1BAHI_0_SW_DEFAULT_MASK          _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ERST1BAHI_0_READ_MASK                _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ERST1BAHI_0_WRITE_MASK               _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ERST1BAHI_0_CLEAR_MASK               _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ERST1BAHI_0_TGL_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ERST1BAHI_0_ADDRHI_SHIFT              _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_ERST1BAHI_0_ADDRHI_FIELD             (_MK_SHIFT_CONST(0xffffffff) << XUSB_DEV_XHCI_ERST1BAHI_0_ADDRHI_SHIFT)
#define XUSB_DEV_XHCI_ERST1BAHI_0_ADDRHI_RANGE             31:0
#define XUSB_DEV_XHCI_ERST1BAHI_0_ADDRHI_WOFFSET           0
#define XUSB_DEV_XHCI_ERST1BAHI_0_ADDRHI_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ERST1BAHI_0_ADDRHI_DEFAULT_MASK      (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ERST1BAHI_0_ADDRHI_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ERST1BAHI_0_ADDRHI_SW_DEFAULT_MASK   (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ERST1BAHI_0_ADDRHI_INIT              _MK_ENUM_CONST(0x00000000)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_ERST1BAHI__PRODCHK                              0 /*       */
// 
// .TITLE Event Ring Dequeue Pointer Register
// Reflects the current value of ERDP, SW updates this register after it has popped events
// 
// .FIELD EHB
// EHB is set by HW when an event is posted and is cleared by SW after it has processed all events
// 


#define XUSB_DEV_XHCI_ERDPLO_0                             _MK_ADDR_CONST(0x00000020)
#define XUSB_DEV_XHCI_ERDPLO_0_SECURE                      0
#define XUSB_DEV_XHCI_ERDPLO_0_WORD_COUNT                  1
#define XUSB_DEV_XHCI_ERDPLO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ERDPLO_0_RESET_MASK                  _MK_MASK_CONST(0xfffffff8)
#define XUSB_DEV_XHCI_ERDPLO_0_SW_DEFAULT_VAL              _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ERDPLO_0_SW_DEFAULT_MASK             _MK_MASK_CONST(0xfffffff8)
#define XUSB_DEV_XHCI_ERDPLO_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ERDPLO_0_WRITE_MASK                  _MK_MASK_CONST(0xfffffff8)
#define XUSB_DEV_XHCI_ERDPLO_0_CLEAR_MASK                  _MK_MASK_CONST(0x8)
#define XUSB_DEV_XHCI_ERDPLO_0_TGL_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ERDPLO_0_RSVD0_SHIFT                  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_ERDPLO_0_RSVD0_FIELD                 (_MK_SHIFT_CONST(0x7) << XUSB_DEV_XHCI_ERDPLO_0_RSVD0_SHIFT)
#define XUSB_DEV_XHCI_ERDPLO_0_RSVD0_RANGE                 2:0
#define XUSB_DEV_XHCI_ERDPLO_0_RSVD0_WOFFSET               0
#define XUSB_DEV_XHCI_ERDPLO_0_RSVD0_00                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_ERDPLO_0_EHB_SHIFT                    _MK_SHIFT_CONST(3)
#define XUSB_DEV_XHCI_ERDPLO_0_EHB_FIELD                   (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_ERDPLO_0_EHB_SHIFT)
#define XUSB_DEV_XHCI_ERDPLO_0_EHB_RANGE                   3:3
#define XUSB_DEV_XHCI_ERDPLO_0_EHB_WOFFSET                 0
#define XUSB_DEV_XHCI_ERDPLO_0_EHB_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ERDPLO_0_EHB_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_ERDPLO_0_EHB_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ERDPLO_0_EHB_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_ERDPLO_0_EHB_INIT                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_ERDPLO_0_EHB_CLEAR                   _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_ERDPLO_0_ADDRLO_SHIFT                 _MK_SHIFT_CONST(4)
#define XUSB_DEV_XHCI_ERDPLO_0_ADDRLO_FIELD                (_MK_SHIFT_CONST(0xfffffff) << XUSB_DEV_XHCI_ERDPLO_0_ADDRLO_SHIFT)
#define XUSB_DEV_XHCI_ERDPLO_0_ADDRLO_RANGE                31:4
#define XUSB_DEV_XHCI_ERDPLO_0_ADDRLO_WOFFSET              0
#define XUSB_DEV_XHCI_ERDPLO_0_ADDRLO_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ERDPLO_0_ADDRLO_DEFAULT_MASK         (_MK_MASK_CONST(0xfffffff)
#define XUSB_DEV_XHCI_ERDPLO_0_ADDRLO_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ERDPLO_0_ADDRLO_SW_DEFAULT_MASK      (_MK_MASK_CONST(0xfffffff)
#define XUSB_DEV_XHCI_ERDPLO_0_ADDRLO_INIT                 _MK_ENUM_CONST(0x00000000)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_ERDPLO__PRODCHK                                 0 /*       */
// 


#define XUSB_DEV_XHCI_ERDPHI_0                             _MK_ADDR_CONST(0x00000024)
#define XUSB_DEV_XHCI_ERDPHI_0_SECURE                      0
#define XUSB_DEV_XHCI_ERDPHI_0_WORD_COUNT                  1
#define XUSB_DEV_XHCI_ERDPHI_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ERDPHI_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ERDPHI_0_SW_DEFAULT_VAL              _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ERDPHI_0_SW_DEFAULT_MASK             _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ERDPHI_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ERDPHI_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ERDPHI_0_CLEAR_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ERDPHI_0_TGL_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ERDPHI_0_ADDRHI_SHIFT                 _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_ERDPHI_0_ADDRHI_FIELD                (_MK_SHIFT_CONST(0xffffffff) << XUSB_DEV_XHCI_ERDPHI_0_ADDRHI_SHIFT)
#define XUSB_DEV_XHCI_ERDPHI_0_ADDRHI_RANGE                31:0
#define XUSB_DEV_XHCI_ERDPHI_0_ADDRHI_WOFFSET              0
#define XUSB_DEV_XHCI_ERDPHI_0_ADDRHI_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ERDPHI_0_ADDRHI_DEFAULT_MASK         (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ERDPHI_0_ADDRHI_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ERDPHI_0_ADDRHI_SW_DEFAULT_MASK      (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ERDPHI_0_ADDRHI_INIT                 _MK_ENUM_CONST(0x00000000)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_ERDPHI__PRODCHK                                 0 /*       */
// 
// Reflects the current value of Event Ring Enqueue Pointer, it is updated by HW after posting an event
// SW can write to the register when Control Enable bit is cleared, SW shall also specify the segment index of the segment to be used
// and HW will sample the value written by SW on a posedge of control enable


#define XUSB_DEV_XHCI_EREPLO_0                             _MK_ADDR_CONST(0x00000028)
#define XUSB_DEV_XHCI_EREPLO_0_SECURE                      0
#define XUSB_DEV_XHCI_EREPLO_0_WORD_COUNT                  1
#define XUSB_DEV_XHCI_EREPLO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EREPLO_0_RESET_MASK                  _MK_MASK_CONST(0xfffffff3)
#define XUSB_DEV_XHCI_EREPLO_0_SW_DEFAULT_VAL              _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EREPLO_0_SW_DEFAULT_MASK             _MK_MASK_CONST(0xfffffff3)
#define XUSB_DEV_XHCI_EREPLO_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EREPLO_0_WRITE_MASK                  _MK_MASK_CONST(0xfffffff3)
#define XUSB_DEV_XHCI_EREPLO_0_CLEAR_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EREPLO_0_TGL_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EREPLO_0_ECS_SHIFT                    _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_EREPLO_0_ECS_FIELD                   (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EREPLO_0_ECS_SHIFT)
#define XUSB_DEV_XHCI_EREPLO_0_ECS_RANGE                   0:0
#define XUSB_DEV_XHCI_EREPLO_0_ECS_WOFFSET                 0
#define XUSB_DEV_XHCI_EREPLO_0_ECS_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EREPLO_0_ECS_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EREPLO_0_ECS_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EREPLO_0_ECS_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EREPLO_0_ECS_INIT                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EREPLO_0_SEGI_SHIFT                   _MK_SHIFT_CONST(1)
#define XUSB_DEV_XHCI_EREPLO_0_SEGI_FIELD                  (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EREPLO_0_SEGI_SHIFT)
#define XUSB_DEV_XHCI_EREPLO_0_SEGI_RANGE                  1:1
#define XUSB_DEV_XHCI_EREPLO_0_SEGI_WOFFSET                0
#define XUSB_DEV_XHCI_EREPLO_0_SEGI_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EREPLO_0_SEGI_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EREPLO_0_SEGI_SW_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EREPLO_0_SEGI_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EREPLO_0_SEGI_INIT                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EREPLO_0_SEGI_MAX                    _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EREPLO_0_RSVD0_SHIFT                  _MK_SHIFT_CONST(2)
#define XUSB_DEV_XHCI_EREPLO_0_RSVD0_FIELD                 (_MK_SHIFT_CONST(0x3) << XUSB_DEV_XHCI_EREPLO_0_RSVD0_SHIFT)
#define XUSB_DEV_XHCI_EREPLO_0_RSVD0_RANGE                 3:2
#define XUSB_DEV_XHCI_EREPLO_0_RSVD0_WOFFSET               0
#define XUSB_DEV_XHCI_EREPLO_0_RSVD0_00                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EREPLO_0_ADDRLO_SHIFT                 _MK_SHIFT_CONST(4)
#define XUSB_DEV_XHCI_EREPLO_0_ADDRLO_FIELD                (_MK_SHIFT_CONST(0xfffffff) << XUSB_DEV_XHCI_EREPLO_0_ADDRLO_SHIFT)
#define XUSB_DEV_XHCI_EREPLO_0_ADDRLO_RANGE                31:4
#define XUSB_DEV_XHCI_EREPLO_0_ADDRLO_WOFFSET              0
#define XUSB_DEV_XHCI_EREPLO_0_ADDRLO_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EREPLO_0_ADDRLO_DEFAULT_MASK         (_MK_MASK_CONST(0xfffffff)
#define XUSB_DEV_XHCI_EREPLO_0_ADDRLO_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EREPLO_0_ADDRLO_SW_DEFAULT_MASK      (_MK_MASK_CONST(0xfffffff)
#define XUSB_DEV_XHCI_EREPLO_0_ADDRLO_INIT                 _MK_ENUM_CONST(0x00000000)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_EREPLO__PRODCHK                                 0 /*       */
// 


#define XUSB_DEV_XHCI_EREPHI_0                             _MK_ADDR_CONST(0x0000002C)
#define XUSB_DEV_XHCI_EREPHI_0_SECURE                      0
#define XUSB_DEV_XHCI_EREPHI_0_WORD_COUNT                  1
#define XUSB_DEV_XHCI_EREPHI_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EREPHI_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EREPHI_0_SW_DEFAULT_VAL              _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EREPHI_0_SW_DEFAULT_MASK             _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EREPHI_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EREPHI_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EREPHI_0_CLEAR_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EREPHI_0_TGL_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EREPHI_0_ADDRHI_SHIFT                 _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_EREPHI_0_ADDRHI_FIELD                (_MK_SHIFT_CONST(0xffffffff) << XUSB_DEV_XHCI_EREPHI_0_ADDRHI_SHIFT)
#define XUSB_DEV_XHCI_EREPHI_0_ADDRHI_RANGE                31:0
#define XUSB_DEV_XHCI_EREPHI_0_ADDRHI_WOFFSET              0
#define XUSB_DEV_XHCI_EREPHI_0_ADDRHI_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EREPHI_0_ADDRHI_DEFAULT_MASK         (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EREPHI_0_ADDRHI_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EREPHI_0_ADDRHI_SW_DEFAULT_MASK      (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EREPHI_0_ADDRHI_INIT                 _MK_ENUM_CONST(0x00000000)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_EREPHI__PRODCHK                                 0 /*       */
// 
// 
// Control Register
// 


#define XUSB_DEV_XHCI_CTRL_0                               _MK_ADDR_CONST(0x00000030)
#define XUSB_DEV_XHCI_CTRL_0_SECURE                        0
#define XUSB_DEV_XHCI_CTRL_0_WORD_COUNT                    1
#define XUSB_DEV_XHCI_CTRL_0_RESET_VAL                     _MK_MASK_CONST(0x200)
#define XUSB_DEV_XHCI_CTRL_0_RESET_MASK                    _MK_MASK_CONST(0xff000ff3)
#define XUSB_DEV_XHCI_CTRL_0_SW_DEFAULT_VAL                _MK_MASK_CONST(0x200)
#define XUSB_DEV_XHCI_CTRL_0_SW_DEFAULT_MASK               _MK_MASK_CONST(0xff000ff3)
#define XUSB_DEV_XHCI_CTRL_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_CTRL_0_WRITE_MASK                    _MK_MASK_CONST(0xff000ff3)
#define XUSB_DEV_XHCI_CTRL_0_CLEAR_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CTRL_0_TGL_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CTRL_0_RUN_SHIFT                      _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_CTRL_0_RUN_FIELD                     (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CTRL_0_RUN_SHIFT)
#define XUSB_DEV_XHCI_CTRL_0_RUN_RANGE                     0:0
#define XUSB_DEV_XHCI_CTRL_0_RUN_WOFFSET                   0
#define XUSB_DEV_XHCI_CTRL_0_RUN_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_RUN_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CTRL_0_RUN_SW_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_RUN_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CTRL_0_RUN_STOP                      _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_RUN_RUN                       _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_CTRL_0_LSE_SHIFT                      _MK_SHIFT_CONST(1)
#define XUSB_DEV_XHCI_CTRL_0_LSE_FIELD                     (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CTRL_0_LSE_SHIFT)
#define XUSB_DEV_XHCI_CTRL_0_LSE_RANGE                     1:1
#define XUSB_DEV_XHCI_CTRL_0_LSE_WOFFSET                   0
#define XUSB_DEV_XHCI_CTRL_0_LSE_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_LSE_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CTRL_0_LSE_SW_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_LSE_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CTRL_0_LSE__PROD                     _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_CTRL_0_LSE_DIS                       _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_LSE_EN                        _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_CTRL_0_RSVD1_SHIFT                    _MK_SHIFT_CONST(2)
#define XUSB_DEV_XHCI_CTRL_0_RSVD1_FIELD                   (_MK_SHIFT_CONST(0x3) << XUSB_DEV_XHCI_CTRL_0_RSVD1_SHIFT)
#define XUSB_DEV_XHCI_CTRL_0_RSVD1_RANGE                   3:2
#define XUSB_DEV_XHCI_CTRL_0_RSVD1_WOFFSET                 0
#define XUSB_DEV_XHCI_CTRL_0_RSVD1_00                      _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_IE_SHIFT                       _MK_SHIFT_CONST(4)
#define XUSB_DEV_XHCI_CTRL_0_IE_FIELD                      (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CTRL_0_IE_SHIFT)
#define XUSB_DEV_XHCI_CTRL_0_IE_RANGE                      4:4
#define XUSB_DEV_XHCI_CTRL_0_IE_WOFFSET                    0
#define XUSB_DEV_XHCI_CTRL_0_IE_DEFAULT                    (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_IE_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CTRL_0_IE_SW_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_IE_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CTRL_0_IE__PROD                      _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_CTRL_0_IE_FALSE                      _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_IE_TRUE                       _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_CTRL_0_SMI_EVT_SHIFT                  _MK_SHIFT_CONST(5)
#define XUSB_DEV_XHCI_CTRL_0_SMI_EVT_FIELD                 (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CTRL_0_SMI_EVT_SHIFT)
#define XUSB_DEV_XHCI_CTRL_0_SMI_EVT_RANGE                 5:5
#define XUSB_DEV_XHCI_CTRL_0_SMI_EVT_WOFFSET               0
#define XUSB_DEV_XHCI_CTRL_0_SMI_EVT_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_SMI_EVT_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CTRL_0_SMI_EVT_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_SMI_EVT_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CTRL_0_SMI_EVT_FALSE                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_SMI_EVT_TRUE                  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_CTRL_0_SMI_DSE_SHIFT                  _MK_SHIFT_CONST(6)
#define XUSB_DEV_XHCI_CTRL_0_SMI_DSE_FIELD                 (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CTRL_0_SMI_DSE_SHIFT)
#define XUSB_DEV_XHCI_CTRL_0_SMI_DSE_RANGE                 6:6
#define XUSB_DEV_XHCI_CTRL_0_SMI_DSE_WOFFSET               0
#define XUSB_DEV_XHCI_CTRL_0_SMI_DSE_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_SMI_DSE_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CTRL_0_SMI_DSE_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_SMI_DSE_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CTRL_0_SMI_DSE_FALSE                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_SMI_DSE_TRUE                  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_CTRL_0_EWE_SHIFT                      _MK_SHIFT_CONST(7)
#define XUSB_DEV_XHCI_CTRL_0_EWE_FIELD                     (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CTRL_0_EWE_SHIFT)
#define XUSB_DEV_XHCI_CTRL_0_EWE_RANGE                     7:7
#define XUSB_DEV_XHCI_CTRL_0_EWE_WOFFSET                   0
#define XUSB_DEV_XHCI_CTRL_0_EWE_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_EWE_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CTRL_0_EWE_SW_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_EWE_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CTRL_0_EWE_FALSE                     _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_EWE_TRUE                      _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_CTRL_0_EVENT_RING_HALT_SHIFT          _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_CTRL_0_EVENT_RING_HALT_FIELD         (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CTRL_0_EVENT_RING_HALT_SHIFT)
#define XUSB_DEV_XHCI_CTRL_0_EVENT_RING_HALT_RANGE         8:8
#define XUSB_DEV_XHCI_CTRL_0_EVENT_RING_HALT_WOFFSET       0
#define XUSB_DEV_XHCI_CTRL_0_EVENT_RING_HALT_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_EVENT_RING_HALT_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CTRL_0_EVENT_RING_HALT_SW_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_EVENT_RING_HALT_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CTRL_0_EVENT_RING_HALT_TRUE          _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_CTRL_0_EVENT_RING_HALT_FALSE         _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_FAULT_EN_SHIFT                 _MK_SHIFT_CONST(9)
#define XUSB_DEV_XHCI_CTRL_0_FAULT_EN_FIELD                (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CTRL_0_FAULT_EN_SHIFT)
#define XUSB_DEV_XHCI_CTRL_0_FAULT_EN_RANGE                9:9
#define XUSB_DEV_XHCI_CTRL_0_FAULT_EN_WOFFSET              0
#define XUSB_DEV_XHCI_CTRL_0_FAULT_EN_DEFAULT              (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_CTRL_0_FAULT_EN_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CTRL_0_FAULT_EN_SW_DEFAULT           (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_CTRL_0_FAULT_EN_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CTRL_0_FAULT_EN_FALSE                _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_FAULT_EN_TRUE                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_CTRL_0_FAULT_MASK_DSE_SHIFT           _MK_SHIFT_CONST(10)
#define XUSB_DEV_XHCI_CTRL_0_FAULT_MASK_DSE_FIELD          (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CTRL_0_FAULT_MASK_DSE_SHIFT)
#define XUSB_DEV_XHCI_CTRL_0_FAULT_MASK_DSE_RANGE          10:10
#define XUSB_DEV_XHCI_CTRL_0_FAULT_MASK_DSE_WOFFSET        0
#define XUSB_DEV_XHCI_CTRL_0_FAULT_MASK_DSE_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_FAULT_MASK_DSE_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CTRL_0_FAULT_MASK_DSE_SW_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_FAULT_MASK_DSE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CTRL_0_FAULT_MASK_DSE_FALSE          _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_FAULT_MASK_DSE_TRUE           _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_CTRL_0_FORCE_FAULT_SHIFT              _MK_SHIFT_CONST(11)
#define XUSB_DEV_XHCI_CTRL_0_FORCE_FAULT_FIELD             (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CTRL_0_FORCE_FAULT_SHIFT)
#define XUSB_DEV_XHCI_CTRL_0_FORCE_FAULT_RANGE             11:11
#define XUSB_DEV_XHCI_CTRL_0_FORCE_FAULT_WOFFSET           0
#define XUSB_DEV_XHCI_CTRL_0_FORCE_FAULT_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_FORCE_FAULT_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CTRL_0_FORCE_FAULT_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_FORCE_FAULT_SW_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CTRL_0_FORCE_FAULT_FALSE             _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_FORCE_FAULT_TRUE              _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_CTRL_0_RSVD0_SHIFT                    _MK_SHIFT_CONST(12)
#define XUSB_DEV_XHCI_CTRL_0_RSVD0_FIELD                   (_MK_SHIFT_CONST(0xfff) << XUSB_DEV_XHCI_CTRL_0_RSVD0_SHIFT)
#define XUSB_DEV_XHCI_CTRL_0_RSVD0_RANGE                   23:12
#define XUSB_DEV_XHCI_CTRL_0_RSVD0_WOFFSET                 0
#define XUSB_DEV_XHCI_CTRL_0_RSVD0_00                      _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_DEVADR_SHIFT                   _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_CTRL_0_DEVADR_FIELD                  (_MK_SHIFT_CONST(0x7f) << XUSB_DEV_XHCI_CTRL_0_DEVADR_SHIFT)
#define XUSB_DEV_XHCI_CTRL_0_DEVADR_RANGE                  30:24
#define XUSB_DEV_XHCI_CTRL_0_DEVADR_WOFFSET                0
#define XUSB_DEV_XHCI_CTRL_0_DEVADR_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_DEVADR_DEFAULT_MASK           (_MK_MASK_CONST(0x7f)
#define XUSB_DEV_XHCI_CTRL_0_DEVADR_SW_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_DEVADR_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x7f)
#define XUSB_DEV_XHCI_CTRL_0_DEVADR_INIT                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_ENABLE_SHIFT                   _MK_SHIFT_CONST(31)
#define XUSB_DEV_XHCI_CTRL_0_ENABLE_FIELD                  (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CTRL_0_ENABLE_SHIFT)
#define XUSB_DEV_XHCI_CTRL_0_ENABLE_RANGE                  31:31
#define XUSB_DEV_XHCI_CTRL_0_ENABLE_WOFFSET                0
#define XUSB_DEV_XHCI_CTRL_0_ENABLE_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_ENABLE_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CTRL_0_ENABLE_SW_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_ENABLE_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CTRL_0_ENABLE__PROD                  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_CTRL_0_ENABLE_DIS                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CTRL_0_ENABLE_EN                     _MK_ENUM_CONST(0x00000001)


// 
// Device Mode Run/Stop bit
// Warning: unsupported define: #define T_XUSB_DEV_XHCI_CTRL_RUN__PRODCHK                           0 /*       */
// 
// Generate Event on PORTSC change
// 
// 
// Enable legacy/smi interrupt for pending events
// 
// Enable SMI interrupt for device system errors
// 
// Enable event for MFINDEX rollover from 3FFF to 0
// 
// Halt posting events, can be used to relocate the event ring data structures
// 
// Enable fault reporting from device controller
// fault ctrl for device system error
// 
// 
// Address assigned to the device DUT
// Warning: unsupported define: #define T_XUSB_DEV_XHCI_CTRL_DEVADR__PRODCHK                        0 /*       */
// 
// Device control Enable used to enable device mode operation
// 
// Status Register
// Run Change - set when run bit transitions from 1 to 0
// Interrupt Pending - set by HW when an event is added to the event ring
// Device System Error bit set when error is received on FPCI wrapper


#define XUSB_DEV_XHCI_ST_0                                 _MK_ADDR_CONST(0x00000034)
#define XUSB_DEV_XHCI_ST_0_SECURE                          0
#define XUSB_DEV_XHCI_ST_0_WORD_COUNT                      1
#define XUSB_DEV_XHCI_ST_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ST_0_RESET_MASK                      _MK_MASK_CONST(0x31)
#define XUSB_DEV_XHCI_ST_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ST_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x31)
#define XUSB_DEV_XHCI_ST_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ST_0_WRITE_MASK                      _MK_MASK_CONST(0x31)
#define XUSB_DEV_XHCI_ST_0_CLEAR_MASK                      _MK_MASK_CONST(0x31)
#define XUSB_DEV_XHCI_ST_0_TGL_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ST_0_RC_SHIFT                         _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_ST_0_RC_FIELD                        (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_ST_0_RC_SHIFT)
#define XUSB_DEV_XHCI_ST_0_RC_RANGE                        0:0
#define XUSB_DEV_XHCI_ST_0_RC_WOFFSET                      0
#define XUSB_DEV_XHCI_ST_0_RC_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ST_0_RC_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_ST_0_RC_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ST_0_RC_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_ST_0_RC_NOTPENDING                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_ST_0_RC_PENDING                      _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_ST_0_RC_CLEAR                        _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_ST_0_RSVD0_SHIFT                      _MK_SHIFT_CONST(1)
#define XUSB_DEV_XHCI_ST_0_RSVD0_FIELD                     (_MK_SHIFT_CONST(0x7) << XUSB_DEV_XHCI_ST_0_RSVD0_SHIFT)
#define XUSB_DEV_XHCI_ST_0_RSVD0_RANGE                     3:1
#define XUSB_DEV_XHCI_ST_0_RSVD0_WOFFSET                   0
#define XUSB_DEV_XHCI_ST_0_RSVD0_00                        _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_ST_0_IP_SHIFT                         _MK_SHIFT_CONST(4)
#define XUSB_DEV_XHCI_ST_0_IP_FIELD                        (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_ST_0_IP_SHIFT)
#define XUSB_DEV_XHCI_ST_0_IP_RANGE                        4:4
#define XUSB_DEV_XHCI_ST_0_IP_WOFFSET                      0
#define XUSB_DEV_XHCI_ST_0_IP_DEFAULT                      (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ST_0_IP_DEFAULT_MASK                 (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_ST_0_IP_SW_DEFAULT                   (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ST_0_IP_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_ST_0_IP_NOTPENDING                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_ST_0_IP_PENDING                      _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_ST_0_IP_CLEAR                        _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_ST_0_DSE_SHIFT                        _MK_SHIFT_CONST(5)
#define XUSB_DEV_XHCI_ST_0_DSE_FIELD                       (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_ST_0_DSE_SHIFT)
#define XUSB_DEV_XHCI_ST_0_DSE_RANGE                       5:5
#define XUSB_DEV_XHCI_ST_0_DSE_WOFFSET                     0
#define XUSB_DEV_XHCI_ST_0_DSE_DEFAULT                     (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ST_0_DSE_DEFAULT_MASK                (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_ST_0_DSE_SW_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ST_0_DSE_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_ST_0_DSE_NOTPENDING                  _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_ST_0_DSE_PENDING                     _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_ST_0_DSE_CLEAR                       _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_ST_0_RSVD1_SHIFT                      _MK_SHIFT_CONST(6)
#define XUSB_DEV_XHCI_ST_0_RSVD1_FIELD                     (_MK_SHIFT_CONST(0x3ffffff) << XUSB_DEV_XHCI_ST_0_RSVD1_SHIFT)
#define XUSB_DEV_XHCI_ST_0_RSVD1_RANGE                     31:6
#define XUSB_DEV_XHCI_ST_0_RSVD1_WOFFSET                   0
#define XUSB_DEV_XHCI_ST_0_RSVD1_00                        _MK_ENUM_CONST(0x00000000)


// 
// Interrupt moderation register (as per the xHCI spec)


#define XUSB_DEV_XHCI_RT_IMOD_0                            _MK_ADDR_CONST(0x00000038)
#define XUSB_DEV_XHCI_RT_IMOD_0_SECURE                     0
#define XUSB_DEV_XHCI_RT_IMOD_0_WORD_COUNT                 1
#define XUSB_DEV_XHCI_RT_IMOD_0_RESET_VAL                  _MK_MASK_CONST(0xfa00fa0)
#define XUSB_DEV_XHCI_RT_IMOD_0_RESET_MASK                 _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_RT_IMOD_0_SW_DEFAULT_VAL             _MK_MASK_CONST(0xfa00fa0)
#define XUSB_DEV_XHCI_RT_IMOD_0_SW_DEFAULT_MASK            _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_RT_IMOD_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_RT_IMOD_0_WRITE_MASK                 _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_RT_IMOD_0_CLEAR_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_RT_IMOD_0_TGL_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_RT_IMOD_0_IMODI_SHIFT                 _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_RT_IMOD_0_IMODI_FIELD                (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_XHCI_RT_IMOD_0_IMODI_SHIFT)
#define XUSB_DEV_XHCI_RT_IMOD_0_IMODI_RANGE                15:0
#define XUSB_DEV_XHCI_RT_IMOD_0_IMODI_WOFFSET              0
#define XUSB_DEV_XHCI_RT_IMOD_0_IMODI_DEFAULT              (_MK_MASK_CONST(0x00000FA0)
#define XUSB_DEV_XHCI_RT_IMOD_0_IMODI_DEFAULT_MASK         (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_RT_IMOD_0_IMODI_SW_DEFAULT           (_MK_MASK_CONST(0x00000FA0)
#define XUSB_DEV_XHCI_RT_IMOD_0_IMODI_SW_DEFAULT_MASK      (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_RT_IMOD_0_IMODI_INIT                 _MK_ENUM_CONST(0x00000FA0)
#define XUSB_DEV_XHCI_RT_IMOD_0_IMODC_SHIFT                 _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_RT_IMOD_0_IMODC_FIELD                (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_XHCI_RT_IMOD_0_IMODC_SHIFT)
#define XUSB_DEV_XHCI_RT_IMOD_0_IMODC_RANGE                31:16
#define XUSB_DEV_XHCI_RT_IMOD_0_IMODC_WOFFSET              0
#define XUSB_DEV_XHCI_RT_IMOD_0_IMODC_DEFAULT              (_MK_MASK_CONST(0x00000FA0)
#define XUSB_DEV_XHCI_RT_IMOD_0_IMODC_DEFAULT_MASK         (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_RT_IMOD_0_IMODC_SW_DEFAULT           (_MK_MASK_CONST(0x00000FA0)
#define XUSB_DEV_XHCI_RT_IMOD_0_IMODC_SW_DEFAULT_MASK      (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_RT_IMOD_0_IMODC_INIT                 _MK_ENUM_CONST(0x00000FA0)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_RT_IMOD__PRODCHK                           0 /*       */
// 
// Port Status and Control Register
// Port Status information like port link state(PLS), current connect state(CCS), port speed (PS)
// status change bits CSC/PRC/WRC/PLC/CEC
// control bits for port reset(PR), warm port reset(WPR), directed state transitions (LWS), port enable/disable (PED)


#define XUSB_DEV_XHCI_PORTSC_0                             _MK_ADDR_CONST(0x0000003C)
#define XUSB_DEV_XHCI_PORTSC_0_SECURE                      0
#define XUSB_DEV_XHCI_PORTSC_0_WORD_COUNT                  1
#define XUSB_DEV_XHCI_PORTSC_0_RESET_VAL                   _MK_MASK_CONST(0x80)
#define XUSB_DEV_XHCI_PORTSC_0_RESET_MASK                  _MK_MASK_CONST(0x40ef3fff)
#define XUSB_DEV_XHCI_PORTSC_0_SW_DEFAULT_VAL              _MK_MASK_CONST(0x80)
#define XUSB_DEV_XHCI_PORTSC_0_SW_DEFAULT_MASK             _MK_MASK_CONST(0x40ef3fff)
#define XUSB_DEV_XHCI_PORTSC_0_READ_MASK                   _MK_MASK_CONST(0x70ef7fff)
#define XUSB_DEV_XHCI_PORTSC_0_WRITE_MASK                  _MK_MASK_CONST(0xeb01ef)
#define XUSB_DEV_XHCI_PORTSC_0_CLEAR_MASK                  _MK_MASK_CONST(0xea0000)
#define XUSB_DEV_XHCI_PORTSC_0_TGL_MASK                    _MK_MASK_CONST(0x10000)
#define XUSB_DEV_XHCI_PORTSC_0_CCS_SHIFT                    _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_PORTSC_0_CCS_FIELD                   (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTSC_0_CCS_SHIFT)
#define XUSB_DEV_XHCI_PORTSC_0_CCS_RANGE                   0:0
#define XUSB_DEV_XHCI_PORTSC_0_CCS_WOFFSET                 0
#define XUSB_DEV_XHCI_PORTSC_0_CCS_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_CCS_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_CCS_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_CCS_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_CCS_NOCON                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_CCS_CON                     _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTSC_0_PED_SHIFT                    _MK_SHIFT_CONST(1)
#define XUSB_DEV_XHCI_PORTSC_0_PED_FIELD                   (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTSC_0_PED_SHIFT)
#define XUSB_DEV_XHCI_PORTSC_0_PED_RANGE                   1:1
#define XUSB_DEV_XHCI_PORTSC_0_PED_WOFFSET                 0
#define XUSB_DEV_XHCI_PORTSC_0_PED_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_PED_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_PED_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_PED_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_PED_DIS                     _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_PED_EN                      _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_OVRD_SHIFT     _MK_SHIFT_CONST(2)
#define XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_OVRD_FIELD    (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_OVRD_SHIFT)
#define XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_OVRD_RANGE    2:2
#define XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_OVRD_WOFFSET  0
#define XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_OVRD_DEFAULT  (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_OVRD_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_OVRD_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_OVRD_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_OVRD_INIT     _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_OVRD_VALUE_SHIFT  _MK_SHIFT_CONST(3)
#define XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_OVRD_VALUE_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_OVRD_VALUE_SHIFT)
#define XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_OVRD_VALUE_RANGE 3:3
#define XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_OVRD_VALUE_WOFFSET 0
#define XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_OVRD_VALUE_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_OVRD_VALUE_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_OVRD_VALUE_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_OVRD_VALUE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_OVRD_VALUE_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_PR_SHIFT                     _MK_SHIFT_CONST(4)
#define XUSB_DEV_XHCI_PORTSC_0_PR_FIELD                    (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTSC_0_PR_SHIFT)
#define XUSB_DEV_XHCI_PORTSC_0_PR_RANGE                    4:4
#define XUSB_DEV_XHCI_PORTSC_0_PR_WOFFSET                  0
#define XUSB_DEV_XHCI_PORTSC_0_PR_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_PR_DEFAULT_MASK             (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_PR_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_PR_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_PR_NORST                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_PR_RST                      _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTSC_0_PLS_SHIFT                    _MK_SHIFT_CONST(5)
#define XUSB_DEV_XHCI_PORTSC_0_PLS_FIELD                   (_MK_SHIFT_CONST(0xf) << XUSB_DEV_XHCI_PORTSC_0_PLS_SHIFT)
#define XUSB_DEV_XHCI_PORTSC_0_PLS_RANGE                   8:5
#define XUSB_DEV_XHCI_PORTSC_0_PLS_WOFFSET                 0
#define XUSB_DEV_XHCI_PORTSC_0_PLS_DEFAULT                 (_MK_MASK_CONST(0x00000004)
#define XUSB_DEV_XHCI_PORTSC_0_PLS_DEFAULT_MASK            (_MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_PORTSC_0_PLS_SW_DEFAULT              (_MK_MASK_CONST(0x00000004)
#define XUSB_DEV_XHCI_PORTSC_0_PLS_SW_DEFAULT_MASK         (_MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_PORTSC_0_PLS_U0                      _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_PLS_U1                      _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTSC_0_PLS_U2                      _MK_ENUM_CONST(0x00000002)
#define XUSB_DEV_XHCI_PORTSC_0_PLS_U3                      _MK_ENUM_CONST(0x00000003)
#define XUSB_DEV_XHCI_PORTSC_0_PLS_DISABLED                _MK_ENUM_CONST(0x00000004)
#define XUSB_DEV_XHCI_PORTSC_0_PLS_RXDETECT                _MK_ENUM_CONST(0x00000005)
#define XUSB_DEV_XHCI_PORTSC_0_PLS_INACTIVE                _MK_ENUM_CONST(0x00000006)
#define XUSB_DEV_XHCI_PORTSC_0_PLS_POLLING                 _MK_ENUM_CONST(0x00000007)
#define XUSB_DEV_XHCI_PORTSC_0_PLS_RECOVERY                _MK_ENUM_CONST(0x00000008)
#define XUSB_DEV_XHCI_PORTSC_0_PLS_HOTRESET                _MK_ENUM_CONST(0x00000009)
#define XUSB_DEV_XHCI_PORTSC_0_PLS_COMPLIANCE              _MK_ENUM_CONST(0x0000000A)
#define XUSB_DEV_XHCI_PORTSC_0_PLS_LOOPBACK                _MK_ENUM_CONST(0x0000000B)
#define XUSB_DEV_XHCI_PORTSC_0_PLS_RESUME                  _MK_ENUM_CONST(0x0000000F)
#define XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_VALUE_SHIFT    _MK_SHIFT_CONST(9)
#define XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_VALUE_FIELD   (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_VALUE_SHIFT)
#define XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_VALUE_RANGE   9:9
#define XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_VALUE_WOFFSET 0
#define XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_VALUE_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_VALUE_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_VALUE_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_VALUE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_LANE_POLARITY_VALUE_INIT    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_PS_SHIFT                     _MK_SHIFT_CONST(10)
#define XUSB_DEV_XHCI_PORTSC_0_PS_FIELD                    (_MK_SHIFT_CONST(0xf) << XUSB_DEV_XHCI_PORTSC_0_PS_SHIFT)
#define XUSB_DEV_XHCI_PORTSC_0_PS_RANGE                    13:10
#define XUSB_DEV_XHCI_PORTSC_0_PS_WOFFSET                  0
#define XUSB_DEV_XHCI_PORTSC_0_PS_DEFAULT                  (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_PS_DEFAULT_MASK             (_MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_PORTSC_0_PS_SW_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_PS_SW_DEFAULT_MASK          (_MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_PORTSC_0_PS_UNDEFINED                _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_PS_FS                       _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTSC_0_PS_LS                       _MK_ENUM_CONST(0x00000002)
#define XUSB_DEV_XHCI_PORTSC_0_PS_HS                       _MK_ENUM_CONST(0x00000003)
#define XUSB_DEV_XHCI_PORTSC_0_PS_SS                       _MK_ENUM_CONST(0x00000004)
#define XUSB_DEV_XHCI_PORTSC_0_PS_SSP                      _MK_ENUM_CONST(0x00000005)
#define XUSB_DEV_XHCI_PORTSC_0_RSVD2_SHIFT                  _MK_SHIFT_CONST(14)
#define XUSB_DEV_XHCI_PORTSC_0_RSVD2_FIELD                 (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTSC_0_RSVD2_SHIFT)
#define XUSB_DEV_XHCI_PORTSC_0_RSVD2_RANGE                 14:14
#define XUSB_DEV_XHCI_PORTSC_0_RSVD2_WOFFSET               0
#define XUSB_DEV_XHCI_PORTSC_0_RSVD2_00                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_LWS_SHIFT                    _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_PORTSC_0_LWS_FIELD                   (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTSC_0_LWS_SHIFT)
#define XUSB_DEV_XHCI_PORTSC_0_LWS_RANGE                   16:16
#define XUSB_DEV_XHCI_PORTSC_0_LWS_WOFFSET                 0
#define XUSB_DEV_XHCI_PORTSC_0_LWS_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_LWS_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_LWS_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_LWS_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_LWS_INIT                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_LWS_SET                     _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTSC_0_CSC_SHIFT                    _MK_SHIFT_CONST(17)
#define XUSB_DEV_XHCI_PORTSC_0_CSC_FIELD                   (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTSC_0_CSC_SHIFT)
#define XUSB_DEV_XHCI_PORTSC_0_CSC_RANGE                   17:17
#define XUSB_DEV_XHCI_PORTSC_0_CSC_WOFFSET                 0
#define XUSB_DEV_XHCI_PORTSC_0_CSC_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_CSC_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_CSC_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_CSC_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_CSC_NOT_PENDING             _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_CSC_PENDING                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTSC_0_CSC_CLEAR                   _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTSC_0_RSVD3_SHIFT                  _MK_SHIFT_CONST(18)
#define XUSB_DEV_XHCI_PORTSC_0_RSVD3_FIELD                 (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTSC_0_RSVD3_SHIFT)
#define XUSB_DEV_XHCI_PORTSC_0_RSVD3_RANGE                 18:18
#define XUSB_DEV_XHCI_PORTSC_0_RSVD3_WOFFSET               0
#define XUSB_DEV_XHCI_PORTSC_0_RSVD3_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_RSVD3_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_RSVD3_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_RSVD3_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_RSVD3_00                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_WRC_SHIFT                    _MK_SHIFT_CONST(19)
#define XUSB_DEV_XHCI_PORTSC_0_WRC_FIELD                   (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTSC_0_WRC_SHIFT)
#define XUSB_DEV_XHCI_PORTSC_0_WRC_RANGE                   19:19
#define XUSB_DEV_XHCI_PORTSC_0_WRC_WOFFSET                 0
#define XUSB_DEV_XHCI_PORTSC_0_WRC_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_WRC_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_WRC_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_WRC_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_WRC_NOT_PENDING             _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_WRC_PENDING                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTSC_0_WRC_CLEAR                   _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTSC_0_PRC_SHIFT                    _MK_SHIFT_CONST(21)
#define XUSB_DEV_XHCI_PORTSC_0_PRC_FIELD                   (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTSC_0_PRC_SHIFT)
#define XUSB_DEV_XHCI_PORTSC_0_PRC_RANGE                   21:21
#define XUSB_DEV_XHCI_PORTSC_0_PRC_WOFFSET                 0
#define XUSB_DEV_XHCI_PORTSC_0_PRC_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_PRC_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_PRC_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_PRC_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_PRC_NOT_PENDING             _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_PRC_PENDING                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTSC_0_PRC_CLEAR                   _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTSC_0_PLC_SHIFT                    _MK_SHIFT_CONST(22)
#define XUSB_DEV_XHCI_PORTSC_0_PLC_FIELD                   (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTSC_0_PLC_SHIFT)
#define XUSB_DEV_XHCI_PORTSC_0_PLC_RANGE                   22:22
#define XUSB_DEV_XHCI_PORTSC_0_PLC_WOFFSET                 0
#define XUSB_DEV_XHCI_PORTSC_0_PLC_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_PLC_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_PLC_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_PLC_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_PLC_NOT_PENDING             _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_PLC_PENDING                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTSC_0_PLC_CLEAR                   _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTSC_0_CEC_SHIFT                    _MK_SHIFT_CONST(23)
#define XUSB_DEV_XHCI_PORTSC_0_CEC_FIELD                   (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTSC_0_CEC_SHIFT)
#define XUSB_DEV_XHCI_PORTSC_0_CEC_RANGE                   23:23
#define XUSB_DEV_XHCI_PORTSC_0_CEC_WOFFSET                 0
#define XUSB_DEV_XHCI_PORTSC_0_CEC_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_CEC_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_CEC_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_CEC_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_CEC_NOT_PENDING             _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_CEC_PENDING                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTSC_0_CEC_CLEAR                   _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTSC_0_RSVD4_SHIFT                  _MK_SHIFT_CONST(28)
#define XUSB_DEV_XHCI_PORTSC_0_RSVD4_FIELD                 (_MK_SHIFT_CONST(0x3) << XUSB_DEV_XHCI_PORTSC_0_RSVD4_SHIFT)
#define XUSB_DEV_XHCI_PORTSC_0_RSVD4_RANGE                 29:28
#define XUSB_DEV_XHCI_PORTSC_0_RSVD4_WOFFSET               0
#define XUSB_DEV_XHCI_PORTSC_0_RSVD4_00                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_WPR_SHIFT                    _MK_SHIFT_CONST(30)
#define XUSB_DEV_XHCI_PORTSC_0_WPR_FIELD                   (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTSC_0_WPR_SHIFT)
#define XUSB_DEV_XHCI_PORTSC_0_WPR_RANGE                   30:30
#define XUSB_DEV_XHCI_PORTSC_0_WPR_WOFFSET                 0
#define XUSB_DEV_XHCI_PORTSC_0_WPR_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_WPR_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_WPR_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_WPR_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTSC_0_WPR_NORST                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTSC_0_WPR_RST                     _MK_ENUM_CONST(0x00000001)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_PORTSC__PRODCHK                             0 /*       */
// 
// Endpoint Context Pointer - points to the default control EP, there is one empty slot after the default control EP
// and the remaining EP contexts start from offset 2


#define XUSB_DEV_XHCI_ECPLO_0                              _MK_ADDR_CONST(0x00000040)
#define XUSB_DEV_XHCI_ECPLO_0_SECURE                       0
#define XUSB_DEV_XHCI_ECPLO_0_WORD_COUNT                   1
#define XUSB_DEV_XHCI_ECPLO_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ECPLO_0_RESET_MASK                   _MK_MASK_CONST(0xffffffc0)
#define XUSB_DEV_XHCI_ECPLO_0_SW_DEFAULT_VAL               _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ECPLO_0_SW_DEFAULT_MASK              _MK_MASK_CONST(0xffffffc0)
#define XUSB_DEV_XHCI_ECPLO_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ECPLO_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffc0)
#define XUSB_DEV_XHCI_ECPLO_0_CLEAR_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ECPLO_0_TGL_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ECPLO_0_RSVD0_SHIFT                   _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_ECPLO_0_RSVD0_FIELD                  (_MK_SHIFT_CONST(0x3f) << XUSB_DEV_XHCI_ECPLO_0_RSVD0_SHIFT)
#define XUSB_DEV_XHCI_ECPLO_0_RSVD0_RANGE                  5:0
#define XUSB_DEV_XHCI_ECPLO_0_RSVD0_WOFFSET                0
#define XUSB_DEV_XHCI_ECPLO_0_RSVD0_00                     _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_ECPLO_0_ADDRLO_SHIFT                  _MK_SHIFT_CONST(6)
#define XUSB_DEV_XHCI_ECPLO_0_ADDRLO_FIELD                 (_MK_SHIFT_CONST(0x3ffffff) << XUSB_DEV_XHCI_ECPLO_0_ADDRLO_SHIFT)
#define XUSB_DEV_XHCI_ECPLO_0_ADDRLO_RANGE                 31:6
#define XUSB_DEV_XHCI_ECPLO_0_ADDRLO_WOFFSET               0
#define XUSB_DEV_XHCI_ECPLO_0_ADDRLO_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ECPLO_0_ADDRLO_DEFAULT_MASK          (_MK_MASK_CONST(0x3ffffff)
#define XUSB_DEV_XHCI_ECPLO_0_ADDRLO_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ECPLO_0_ADDRLO_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x3ffffff)
#define XUSB_DEV_XHCI_ECPLO_0_ADDRLO_INIT                  _MK_ENUM_CONST(0x00000000)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_ECPLO__PRODCHK                                 0 /*       */
// 


#define XUSB_DEV_XHCI_ECPHI_0                              _MK_ADDR_CONST(0x00000044)
#define XUSB_DEV_XHCI_ECPHI_0_SECURE                       0
#define XUSB_DEV_XHCI_ECPHI_0_WORD_COUNT                   1
#define XUSB_DEV_XHCI_ECPHI_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ECPHI_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ECPHI_0_SW_DEFAULT_VAL               _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ECPHI_0_SW_DEFAULT_MASK              _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ECPHI_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ECPHI_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ECPHI_0_CLEAR_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ECPHI_0_TGL_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_ECPHI_0_ADDRHI_SHIFT                  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_ECPHI_0_ADDRHI_FIELD                 (_MK_SHIFT_CONST(0xffffffff) << XUSB_DEV_XHCI_ECPHI_0_ADDRHI_SHIFT)
#define XUSB_DEV_XHCI_ECPHI_0_ADDRHI_RANGE                 31:0
#define XUSB_DEV_XHCI_ECPHI_0_ADDRHI_WOFFSET               0
#define XUSB_DEV_XHCI_ECPHI_0_ADDRHI_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ECPHI_0_ADDRHI_DEFAULT_MASK          (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ECPHI_0_ADDRHI_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_ECPHI_0_ADDRHI_SW_DEFAULT_MASK       (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_ECPHI_0_ADDRHI_INIT                  _MK_ENUM_CONST(0x00000000)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_ECPHI__PRODCHK                                 0 /*       */
// 
// Current MFINDEX value


#define XUSB_DEV_XHCI_MFINDEX_0                            _MK_ADDR_CONST(0x00000048)
#define XUSB_DEV_XHCI_MFINDEX_0_SECURE                     0
#define XUSB_DEV_XHCI_MFINDEX_0_WORD_COUNT                 1
#define XUSB_DEV_XHCI_MFINDEX_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_MFINDEX_0_RESET_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_MFINDEX_0_SW_DEFAULT_VAL             _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_MFINDEX_0_SW_DEFAULT_MASK            _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_MFINDEX_0_READ_MASK                  _MK_MASK_CONST(0x3fff)
#define XUSB_DEV_XHCI_MFINDEX_0_WRITE_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_MFINDEX_0_CLEAR_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_MFINDEX_0_TGL_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_MFINDEX_0_UFRAME_SHIFT                _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_MFINDEX_0_UFRAME_FIELD               (_MK_SHIFT_CONST(0x7) << XUSB_DEV_XHCI_MFINDEX_0_UFRAME_SHIFT)
#define XUSB_DEV_XHCI_MFINDEX_0_UFRAME_RANGE               2:0
#define XUSB_DEV_XHCI_MFINDEX_0_UFRAME_WOFFSET             0
#define XUSB_DEV_XHCI_MFINDEX_0_UFRAME_INIT                _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_MFINDEX_0_FRAME_SHIFT                 _MK_SHIFT_CONST(3)
#define XUSB_DEV_XHCI_MFINDEX_0_FRAME_FIELD                (_MK_SHIFT_CONST(0x7ff) << XUSB_DEV_XHCI_MFINDEX_0_FRAME_SHIFT)
#define XUSB_DEV_XHCI_MFINDEX_0_FRAME_RANGE                13:3
#define XUSB_DEV_XHCI_MFINDEX_0_FRAME_WOFFSET              0
#define XUSB_DEV_XHCI_MFINDEX_0_FRAME_INIT                 _MK_ENUM_CONST(0x00000000)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_MFINDEX__PRODCHK                                    0 /*       */
// 
// 
// Port PM Status and Control Register
// High Speed L1 Stats - used by SW to program whether to accept or reject L1 requests
// High Speed L1 remote wake enable to allow port to generate resume signaling during L1
// 25    Vbus Attach Status - Indicates whether Vbus is detected at the port. 0x1 indicates Vbus is present and 0x0 indicates Vbus is not detected.
// This field is reserved for debug capability.    RO    HwInit
// 26    Wake on Connection - Writing this bit to 0x1 enables the port to be sensitive to Vbus connects as system wake-up events.
// This bit is not valid for the Debug Capability. The host PORTSC register is used to control the wake on connect for host ports.    RWS    0x1
// 27    Wake on Disconnection - Writing this bit to 0x1 enables the port to be sensitive to Vbus disconnects as system wake-up events.    RWS    0x1
// 28    SuperSpeed U1 Enable - Enables the port to initiate U1 entry or accept U1 entry requests.
// Software sets this bit when U1 is enabled by the SET_FEATURE device request and software clears this bit when U1 is disabled by the CLEAR_FEATURE device request. This field shall be set to 0x0 by the transition of Port Reset from 0x0 to 0x1.    RWS    0x0
// 29    SuperSpeed U2 Enable - Enables the port to initiate U2 entry or accept U2/L1 entry requests.
// Software sets this bit when U2 is enabled by the SET_FEATURE device request and software clears this bit when U2 is disabled by the CLEAR_FEATURE device request. This field shall be set to 0x0 by the transition of Port Reset from 0x0 to 0x1.    RWS    0x0
// 30    SuperSpeed Function Remote Wake Enable - Enables the port to generate resume signaling. This bit reflects the Function Remote Wake Enable bit captured in the SET_FEATURE device request. This field shall be set to 0x0 by the transition of Port Reset from 0x0 to 0x1.    RWS    0x0
// 31    SuperSpeed Deferred PING Response - CYA to select the response when deferred PING TP is received. Set this bit to 0x0 to enable the response with PING_RESPONSE TP; set this bit to 0x1 to enable the response with ERDY TP.    RWS    0x0
// 
// 
// 


#define XUSB_DEV_XHCI_PORTPM_0                             _MK_ADDR_CONST(0x0000004C)
#define XUSB_DEV_XHCI_PORTPM_0_SECURE                      0
#define XUSB_DEV_XHCI_PORTPM_0_WORD_COUNT                  1
#define XUSB_DEV_XHCI_PORTPM_0_RESET_VAL                   _MK_MASK_CONST(0xcffff01)
#define XUSB_DEV_XHCI_PORTPM_0_RESET_MASK                  _MK_MASK_CONST(0xfdfffffb)
#define XUSB_DEV_XHCI_PORTPM_0_SW_DEFAULT_VAL              _MK_MASK_CONST(0xcffff01)
#define XUSB_DEV_XHCI_PORTPM_0_SW_DEFAULT_MASK             _MK_MASK_CONST(0xfdfffffb)
#define XUSB_DEV_XHCI_PORTPM_0_READ_MASK                   _MK_MASK_CONST(0xfffffffb)
#define XUSB_DEV_XHCI_PORTPM_0_WRITE_MASK                  _MK_MASK_CONST(0xfdfffffb)
#define XUSB_DEV_XHCI_PORTPM_0_CLEAR_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PORTPM_0_TGL_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PORTPM_0_L1S_SHIFT                    _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_PORTPM_0_L1S_FIELD                   (_MK_SHIFT_CONST(0x3) << XUSB_DEV_XHCI_PORTPM_0_L1S_SHIFT)
#define XUSB_DEV_XHCI_PORTPM_0_L1S_RANGE                   1:0
#define XUSB_DEV_XHCI_PORTPM_0_L1S_WOFFSET                 0
#define XUSB_DEV_XHCI_PORTPM_0_L1S_DEFAULT                 (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTPM_0_L1S_DEFAULT_MASK            (_MK_MASK_CONST(0x3)
#define XUSB_DEV_XHCI_PORTPM_0_L1S_SW_DEFAULT              (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTPM_0_L1S_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x3)
#define XUSB_DEV_XHCI_PORTPM_0_L1S_DROP                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTPM_0_L1S_ACCEPT                  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTPM_0_L1S_NYET                    _MK_ENUM_CONST(0x00000002)
#define XUSB_DEV_XHCI_PORTPM_0_L1S_STALL                   _MK_ENUM_CONST(0x00000003)
#define XUSB_DEV_XHCI_PORTPM_0_RWE_SHIFT                    _MK_SHIFT_CONST(3)
#define XUSB_DEV_XHCI_PORTPM_0_RWE_FIELD                   (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTPM_0_RWE_SHIFT)
#define XUSB_DEV_XHCI_PORTPM_0_RWE_RANGE                   3:3
#define XUSB_DEV_XHCI_PORTPM_0_RWE_WOFFSET                 0
#define XUSB_DEV_XHCI_PORTPM_0_RWE_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTPM_0_RWE_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTPM_0_RWE_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTPM_0_RWE_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTPM_0_RWE_DISABLED                _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTPM_0_RWE_ENABLED                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTPM_0_HIRD_SHIFT                   _MK_SHIFT_CONST(4)
#define XUSB_DEV_XHCI_PORTPM_0_HIRD_FIELD                  (_MK_SHIFT_CONST(0xf) << XUSB_DEV_XHCI_PORTPM_0_HIRD_SHIFT)
#define XUSB_DEV_XHCI_PORTPM_0_HIRD_RANGE                  7:4
#define XUSB_DEV_XHCI_PORTPM_0_HIRD_WOFFSET                0
#define XUSB_DEV_XHCI_PORTPM_0_HIRD_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTPM_0_HIRD_DEFAULT_MASK           (_MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_PORTPM_0_HIRD_SW_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTPM_0_HIRD_SW_DEFAULT_MASK        (_MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_PORTPM_0_HIRD_INIT                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTPM_0_U2TIMEOUT_SHIFT              _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_PORTPM_0_U2TIMEOUT_FIELD             (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_PORTPM_0_U2TIMEOUT_SHIFT)
#define XUSB_DEV_XHCI_PORTPM_0_U2TIMEOUT_RANGE             15:8
#define XUSB_DEV_XHCI_PORTPM_0_U2TIMEOUT_WOFFSET           0
#define XUSB_DEV_XHCI_PORTPM_0_U2TIMEOUT_DEFAULT           (_MK_MASK_CONST(0x000000FF)
#define XUSB_DEV_XHCI_PORTPM_0_U2TIMEOUT_DEFAULT_MASK      (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_PORTPM_0_U2TIMEOUT_SW_DEFAULT        (_MK_MASK_CONST(0x000000FF)
#define XUSB_DEV_XHCI_PORTPM_0_U2TIMEOUT_SW_DEFAULT_MASK   (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_PORTPM_0_U2TIMEOUT_INIT              _MK_ENUM_CONST(0x000000FF)
#define XUSB_DEV_XHCI_PORTPM_0_U1TIMEOUT_SHIFT              _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_PORTPM_0_U1TIMEOUT_FIELD             (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_PORTPM_0_U1TIMEOUT_SHIFT)
#define XUSB_DEV_XHCI_PORTPM_0_U1TIMEOUT_RANGE             23:16
#define XUSB_DEV_XHCI_PORTPM_0_U1TIMEOUT_WOFFSET           0
#define XUSB_DEV_XHCI_PORTPM_0_U1TIMEOUT_DEFAULT           (_MK_MASK_CONST(0x000000FF)
#define XUSB_DEV_XHCI_PORTPM_0_U1TIMEOUT_DEFAULT_MASK      (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_PORTPM_0_U1TIMEOUT_SW_DEFAULT        (_MK_MASK_CONST(0x000000FF)
#define XUSB_DEV_XHCI_PORTPM_0_U1TIMEOUT_SW_DEFAULT_MASK   (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_PORTPM_0_U1TIMEOUT_INIT              _MK_ENUM_CONST(0x000000FF)
#define XUSB_DEV_XHCI_PORTPM_0_FLA_SHIFT                    _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_PORTPM_0_FLA_FIELD                   (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTPM_0_FLA_SHIFT)
#define XUSB_DEV_XHCI_PORTPM_0_FLA_RANGE                   24:24
#define XUSB_DEV_XHCI_PORTPM_0_FLA_WOFFSET                 0
#define XUSB_DEV_XHCI_PORTPM_0_FLA_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTPM_0_FLA_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTPM_0_FLA_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTPM_0_FLA_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTPM_0_FLA_INIT                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTPM_0_VBA_SHIFT                    _MK_SHIFT_CONST(25)
#define XUSB_DEV_XHCI_PORTPM_0_VBA_FIELD                   (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTPM_0_VBA_SHIFT)
#define XUSB_DEV_XHCI_PORTPM_0_VBA_RANGE                   25:25
#define XUSB_DEV_XHCI_PORTPM_0_VBA_WOFFSET                 0
#define XUSB_DEV_XHCI_PORTPM_0_VBA_INIT                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTPM_0_WOC_SHIFT                    _MK_SHIFT_CONST(26)
#define XUSB_DEV_XHCI_PORTPM_0_WOC_FIELD                   (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTPM_0_WOC_SHIFT)
#define XUSB_DEV_XHCI_PORTPM_0_WOC_RANGE                   26:26
#define XUSB_DEV_XHCI_PORTPM_0_WOC_WOFFSET                 0
#define XUSB_DEV_XHCI_PORTPM_0_WOC_DEFAULT                 (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTPM_0_WOC_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTPM_0_WOC_SW_DEFAULT              (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTPM_0_WOC_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTPM_0_WOC_INIT                    _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTPM_0_WOD_SHIFT                    _MK_SHIFT_CONST(27)
#define XUSB_DEV_XHCI_PORTPM_0_WOD_FIELD                   (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTPM_0_WOD_SHIFT)
#define XUSB_DEV_XHCI_PORTPM_0_WOD_RANGE                   27:27
#define XUSB_DEV_XHCI_PORTPM_0_WOD_WOFFSET                 0
#define XUSB_DEV_XHCI_PORTPM_0_WOD_DEFAULT                 (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTPM_0_WOD_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTPM_0_WOD_SW_DEFAULT              (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTPM_0_WOD_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTPM_0_WOD_INIT                    _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTPM_0_U1E_SHIFT                    _MK_SHIFT_CONST(28)
#define XUSB_DEV_XHCI_PORTPM_0_U1E_FIELD                   (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTPM_0_U1E_SHIFT)
#define XUSB_DEV_XHCI_PORTPM_0_U1E_RANGE                   28:28
#define XUSB_DEV_XHCI_PORTPM_0_U1E_WOFFSET                 0
#define XUSB_DEV_XHCI_PORTPM_0_U1E_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTPM_0_U1E_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTPM_0_U1E_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTPM_0_U1E_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTPM_0_U1E_INIT                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTPM_0_U2E_SHIFT                    _MK_SHIFT_CONST(29)
#define XUSB_DEV_XHCI_PORTPM_0_U2E_FIELD                   (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTPM_0_U2E_SHIFT)
#define XUSB_DEV_XHCI_PORTPM_0_U2E_RANGE                   29:29
#define XUSB_DEV_XHCI_PORTPM_0_U2E_WOFFSET                 0
#define XUSB_DEV_XHCI_PORTPM_0_U2E_DEFAULT                 (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTPM_0_U2E_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTPM_0_U2E_SW_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTPM_0_U2E_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTPM_0_U2E_INIT                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTPM_0_FRWE_SHIFT                   _MK_SHIFT_CONST(30)
#define XUSB_DEV_XHCI_PORTPM_0_FRWE_FIELD                  (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTPM_0_FRWE_SHIFT)
#define XUSB_DEV_XHCI_PORTPM_0_FRWE_RANGE                  30:30
#define XUSB_DEV_XHCI_PORTPM_0_FRWE_WOFFSET                0
#define XUSB_DEV_XHCI_PORTPM_0_FRWE_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTPM_0_FRWE_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTPM_0_FRWE_SW_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTPM_0_FRWE_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTPM_0_FRWE_INIT                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTPM_0_PNG_CYA_SHIFT                _MK_SHIFT_CONST(31)
#define XUSB_DEV_XHCI_PORTPM_0_PNG_CYA_FIELD               (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTPM_0_PNG_CYA_SHIFT)
#define XUSB_DEV_XHCI_PORTPM_0_PNG_CYA_RANGE               31:31
#define XUSB_DEV_XHCI_PORTPM_0_PNG_CYA_WOFFSET             0
#define XUSB_DEV_XHCI_PORTPM_0_PNG_CYA_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTPM_0_PNG_CYA_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTPM_0_PNG_CYA_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTPM_0_PNG_CYA_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTPM_0_PNG_CYA_INIT                _MK_ENUM_CONST(0x00000000)


// 
// 
// EP HALT register used by SW to program an EP to respond to host request with STALL transaction
// When this bit is set HW preserves certain EP parameters (like ep_state/ep_type etc) - but SW can modify the transfer ring after setting this bit


#define XUSB_DEV_XHCI_EP_HALT_0                            _MK_ADDR_CONST(0x00000050)
#define XUSB_DEV_XHCI_EP_HALT_0_SECURE                     0
#define XUSB_DEV_XHCI_EP_HALT_0_WORD_COUNT                 1
#define XUSB_DEV_XHCI_EP_HALT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EP_HALT_0_RESET_MASK                 _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_HALT_0_SW_DEFAULT_VAL             _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EP_HALT_0_SW_DEFAULT_MASK            _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_HALT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_HALT_0_WRITE_MASK                 _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_HALT_0_CLEAR_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EP_HALT_0_TGL_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EP_HALT_0_DCI_SHIFT                   _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_EP_HALT_0_DCI_FIELD                  (_MK_SHIFT_CONST(0xffffffff) << XUSB_DEV_XHCI_EP_HALT_0_DCI_SHIFT)
#define XUSB_DEV_XHCI_EP_HALT_0_DCI_RANGE                  31:0
#define XUSB_DEV_XHCI_EP_HALT_0_DCI_WOFFSET                0
#define XUSB_DEV_XHCI_EP_HALT_0_DCI_DEFAULT                (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_HALT_0_DCI_DEFAULT_MASK           (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_HALT_0_DCI_SW_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_HALT_0_DCI_SW_DEFAULT_MASK        (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_HALT_0_DCI_NO                     _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_HALT_0_DCI_YES                    _MK_ENUM_CONST(0x00000001)


// 
// 
// EP Pause register used by SW to program the DUT to stop processing the EP and respond host requests with a NRDY/NAK
// When this bit is set HW preserves certain EP parameters (like ep_state/ep_type etc) - but SW can modify the transfer ring after setting this bit


#define XUSB_DEV_XHCI_EP_PAUSE_0                           _MK_ADDR_CONST(0x00000054)
#define XUSB_DEV_XHCI_EP_PAUSE_0_SECURE                    0
#define XUSB_DEV_XHCI_EP_PAUSE_0_WORD_COUNT                1
#define XUSB_DEV_XHCI_EP_PAUSE_0_RESET_VAL                 _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EP_PAUSE_0_RESET_MASK                _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_PAUSE_0_SW_DEFAULT_VAL            _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EP_PAUSE_0_SW_DEFAULT_MASK           _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_PAUSE_0_READ_MASK                 _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_PAUSE_0_WRITE_MASK                _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_PAUSE_0_CLEAR_MASK                _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EP_PAUSE_0_TGL_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EP_PAUSE_0_DCI_SHIFT                  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_EP_PAUSE_0_DCI_FIELD                 (_MK_SHIFT_CONST(0xffffffff) << XUSB_DEV_XHCI_EP_PAUSE_0_DCI_SHIFT)
#define XUSB_DEV_XHCI_EP_PAUSE_0_DCI_RANGE                 31:0
#define XUSB_DEV_XHCI_EP_PAUSE_0_DCI_WOFFSET               0
#define XUSB_DEV_XHCI_EP_PAUSE_0_DCI_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_PAUSE_0_DCI_DEFAULT_MASK          (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_PAUSE_0_DCI_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_PAUSE_0_DCI_SW_DEFAULT_MASK       (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_PAUSE_0_DCI_NO                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_PAUSE_0_DCI_YES                   _MK_ENUM_CONST(0x00000001)


// 
// EP Reload bits are used by SW to direct the Device BI to reload the EP context for that EP
// and update its internal EP related variables like EP state


#define XUSB_DEV_XHCI_EP_RELOAD_0                          _MK_ADDR_CONST(0x00000058)
#define XUSB_DEV_XHCI_EP_RELOAD_0_SECURE                   0
#define XUSB_DEV_XHCI_EP_RELOAD_0_WORD_COUNT               1
#define XUSB_DEV_XHCI_EP_RELOAD_0_RESET_VAL                _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EP_RELOAD_0_RESET_MASK               _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_RELOAD_0_SW_DEFAULT_VAL           _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EP_RELOAD_0_SW_DEFAULT_MASK          _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_RELOAD_0_READ_MASK                _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_RELOAD_0_WRITE_MASK               _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_RELOAD_0_CLEAR_MASK               _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EP_RELOAD_0_TGL_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EP_RELOAD_0_DCI_SHIFT                 _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_EP_RELOAD_0_DCI_FIELD                (_MK_SHIFT_CONST(0xffffffff) << XUSB_DEV_XHCI_EP_RELOAD_0_DCI_SHIFT)
#define XUSB_DEV_XHCI_EP_RELOAD_0_DCI_RANGE                31:0
#define XUSB_DEV_XHCI_EP_RELOAD_0_DCI_WOFFSET              0
#define XUSB_DEV_XHCI_EP_RELOAD_0_DCI_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_RELOAD_0_DCI_DEFAULT_MASK         (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_RELOAD_0_DCI_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_RELOAD_0_DCI_SW_DEFAULT_MASK      (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_RELOAD_0_DCI_NO                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_RELOAD_0_DCI_YES                  _MK_ENUM_CONST(0x00000001)


// 
// EP STCHG is set by HW whenever halt/pause/run bit is cleared by SW, to indicate completion of processing of the SW request
// SW should clear the EP_STCHG bit by writing 1 to it, there is 1 bit for each EP


#define XUSB_DEV_XHCI_EP_STCHG_0                           _MK_ADDR_CONST(0x0000005C)
#define XUSB_DEV_XHCI_EP_STCHG_0_SECURE                    0
#define XUSB_DEV_XHCI_EP_STCHG_0_WORD_COUNT                1
#define XUSB_DEV_XHCI_EP_STCHG_0_RESET_VAL                 _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EP_STCHG_0_RESET_MASK                _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_STCHG_0_SW_DEFAULT_VAL            _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EP_STCHG_0_SW_DEFAULT_MASK           _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_STCHG_0_READ_MASK                 _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_STCHG_0_WRITE_MASK                _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_STCHG_0_CLEAR_MASK                _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_STCHG_0_TGL_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT0_SHIFT                 _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT0_FIELD                (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_OUT0_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT0_RANGE                0:0
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT0_WOFFSET              0
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT0_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT0_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT0_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT0_NO                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT0_YES                  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT0_CLEAR                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN0_SHIFT                  _MK_SHIFT_CONST(1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN0_FIELD                 (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_IN0_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN0_RANGE                 1:1
#define XUSB_DEV_XHCI_EP_STCHG_0_IN0_WOFFSET               0
#define XUSB_DEV_XHCI_EP_STCHG_0_IN0_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN0_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN0_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN0_NO                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN0_YES                   _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN0_CLEAR                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT1_SHIFT                 _MK_SHIFT_CONST(2)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT1_FIELD                (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_OUT1_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT1_RANGE                2:2
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT1_WOFFSET              0
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT1_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT1_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT1_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT1_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT1_NO                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT1_YES                  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT1_CLEAR                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN1_SHIFT                  _MK_SHIFT_CONST(3)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN1_FIELD                 (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_IN1_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN1_RANGE                 3:3
#define XUSB_DEV_XHCI_EP_STCHG_0_IN1_WOFFSET               0
#define XUSB_DEV_XHCI_EP_STCHG_0_IN1_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN1_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN1_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN1_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN1_NO                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN1_YES                   _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN1_CLEAR                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT2_SHIFT                 _MK_SHIFT_CONST(4)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT2_FIELD                (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_OUT2_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT2_RANGE                4:4
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT2_WOFFSET              0
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT2_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT2_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT2_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT2_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT2_NO                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT2_YES                  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT2_CLEAR                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN2_SHIFT                  _MK_SHIFT_CONST(5)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN2_FIELD                 (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_IN2_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN2_RANGE                 5:5
#define XUSB_DEV_XHCI_EP_STCHG_0_IN2_WOFFSET               0
#define XUSB_DEV_XHCI_EP_STCHG_0_IN2_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN2_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN2_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN2_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN2_NO                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN2_YES                   _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN2_CLEAR                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT3_SHIFT                 _MK_SHIFT_CONST(6)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT3_FIELD                (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_OUT3_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT3_RANGE                6:6
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT3_WOFFSET              0
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT3_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT3_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT3_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT3_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT3_NO                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT3_YES                  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT3_CLEAR                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN3_SHIFT                  _MK_SHIFT_CONST(7)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN3_FIELD                 (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_IN3_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN3_RANGE                 7:7
#define XUSB_DEV_XHCI_EP_STCHG_0_IN3_WOFFSET               0
#define XUSB_DEV_XHCI_EP_STCHG_0_IN3_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN3_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN3_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN3_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN3_NO                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN3_YES                   _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN3_CLEAR                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT4_SHIFT                 _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT4_FIELD                (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_OUT4_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT4_RANGE                8:8
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT4_WOFFSET              0
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT4_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT4_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT4_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT4_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT4_NO                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT4_YES                  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT4_CLEAR                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN4_SHIFT                  _MK_SHIFT_CONST(9)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN4_FIELD                 (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_IN4_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN4_RANGE                 9:9
#define XUSB_DEV_XHCI_EP_STCHG_0_IN4_WOFFSET               0
#define XUSB_DEV_XHCI_EP_STCHG_0_IN4_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN4_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN4_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN4_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN4_NO                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN4_YES                   _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN4_CLEAR                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT5_SHIFT                 _MK_SHIFT_CONST(10)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT5_FIELD                (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_OUT5_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT5_RANGE                10:10
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT5_WOFFSET              0
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT5_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT5_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT5_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT5_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT5_NO                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT5_YES                  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT5_CLEAR                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN5_SHIFT                  _MK_SHIFT_CONST(11)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN5_FIELD                 (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_IN5_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN5_RANGE                 11:11
#define XUSB_DEV_XHCI_EP_STCHG_0_IN5_WOFFSET               0
#define XUSB_DEV_XHCI_EP_STCHG_0_IN5_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN5_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN5_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN5_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN5_NO                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN5_YES                   _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN5_CLEAR                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT6_SHIFT                 _MK_SHIFT_CONST(12)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT6_FIELD                (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_OUT6_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT6_RANGE                12:12
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT6_WOFFSET              0
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT6_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT6_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT6_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT6_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT6_NO                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT6_YES                  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT6_CLEAR                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN6_SHIFT                  _MK_SHIFT_CONST(13)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN6_FIELD                 (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_IN6_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN6_RANGE                 13:13
#define XUSB_DEV_XHCI_EP_STCHG_0_IN6_WOFFSET               0
#define XUSB_DEV_XHCI_EP_STCHG_0_IN6_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN6_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN6_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN6_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN6_NO                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN6_YES                   _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN6_CLEAR                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT7_SHIFT                 _MK_SHIFT_CONST(14)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT7_FIELD                (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_OUT7_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT7_RANGE                14:14
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT7_WOFFSET              0
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT7_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT7_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT7_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT7_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT7_NO                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT7_YES                  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT7_CLEAR                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN7_SHIFT                  _MK_SHIFT_CONST(15)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN7_FIELD                 (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_IN7_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN7_RANGE                 15:15
#define XUSB_DEV_XHCI_EP_STCHG_0_IN7_WOFFSET               0
#define XUSB_DEV_XHCI_EP_STCHG_0_IN7_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN7_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN7_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN7_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN7_NO                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN7_YES                   _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN7_CLEAR                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT8_SHIFT                 _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT8_FIELD                (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_OUT8_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT8_RANGE                16:16
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT8_WOFFSET              0
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT8_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT8_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT8_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT8_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT8_NO                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT8_YES                  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT8_CLEAR                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN8_SHIFT                  _MK_SHIFT_CONST(17)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN8_FIELD                 (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_IN8_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN8_RANGE                 17:17
#define XUSB_DEV_XHCI_EP_STCHG_0_IN8_WOFFSET               0
#define XUSB_DEV_XHCI_EP_STCHG_0_IN8_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN8_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN8_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN8_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN8_NO                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN8_YES                   _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN8_CLEAR                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT9_SHIFT                 _MK_SHIFT_CONST(18)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT9_FIELD                (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_OUT9_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT9_RANGE                18:18
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT9_WOFFSET              0
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT9_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT9_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT9_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT9_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT9_NO                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT9_YES                  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT9_CLEAR                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN9_SHIFT                  _MK_SHIFT_CONST(19)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN9_FIELD                 (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_IN9_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN9_RANGE                 19:19
#define XUSB_DEV_XHCI_EP_STCHG_0_IN9_WOFFSET               0
#define XUSB_DEV_XHCI_EP_STCHG_0_IN9_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN9_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN9_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN9_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN9_NO                    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN9_YES                   _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN9_CLEAR                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT10_SHIFT                _MK_SHIFT_CONST(20)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT10_FIELD               (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_OUT10_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT10_RANGE               20:20
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT10_WOFFSET             0
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT10_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT10_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT10_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT10_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT10_NO                  _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT10_YES                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT10_CLEAR               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN10_SHIFT                 _MK_SHIFT_CONST(21)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN10_FIELD                (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_IN10_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN10_RANGE                21:21
#define XUSB_DEV_XHCI_EP_STCHG_0_IN10_WOFFSET              0
#define XUSB_DEV_XHCI_EP_STCHG_0_IN10_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN10_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN10_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN10_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN10_NO                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN10_YES                  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN10_CLEAR                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT11_SHIFT                _MK_SHIFT_CONST(22)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT11_FIELD               (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_OUT11_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT11_RANGE               22:22
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT11_WOFFSET             0
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT11_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT11_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT11_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT11_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT11_NO                  _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT11_YES                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT11_CLEAR               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN11_SHIFT                 _MK_SHIFT_CONST(23)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN11_FIELD                (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_IN11_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN11_RANGE                23:23
#define XUSB_DEV_XHCI_EP_STCHG_0_IN11_WOFFSET              0
#define XUSB_DEV_XHCI_EP_STCHG_0_IN11_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN11_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN11_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN11_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN11_NO                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN11_YES                  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN11_CLEAR                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT12_SHIFT                _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT12_FIELD               (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_OUT12_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT12_RANGE               24:24
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT12_WOFFSET             0
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT12_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT12_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT12_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT12_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT12_NO                  _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT12_YES                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT12_CLEAR               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN12_SHIFT                 _MK_SHIFT_CONST(25)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN12_FIELD                (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_IN12_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN12_RANGE                25:25
#define XUSB_DEV_XHCI_EP_STCHG_0_IN12_WOFFSET              0
#define XUSB_DEV_XHCI_EP_STCHG_0_IN12_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN12_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN12_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN12_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN12_NO                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN12_YES                  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN12_CLEAR                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT13_SHIFT                _MK_SHIFT_CONST(26)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT13_FIELD               (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_OUT13_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT13_RANGE               26:26
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT13_WOFFSET             0
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT13_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT13_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT13_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT13_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT13_NO                  _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT13_YES                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT13_CLEAR               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN13_SHIFT                 _MK_SHIFT_CONST(27)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN13_FIELD                (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_IN13_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN13_RANGE                27:27
#define XUSB_DEV_XHCI_EP_STCHG_0_IN13_WOFFSET              0
#define XUSB_DEV_XHCI_EP_STCHG_0_IN13_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN13_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN13_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN13_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN13_NO                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN13_YES                  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN13_CLEAR                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT14_SHIFT                _MK_SHIFT_CONST(28)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT14_FIELD               (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_OUT14_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT14_RANGE               28:28
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT14_WOFFSET             0
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT14_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT14_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT14_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT14_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT14_NO                  _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT14_YES                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT14_CLEAR               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN14_SHIFT                 _MK_SHIFT_CONST(29)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN14_FIELD                (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_IN14_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN14_RANGE                29:29
#define XUSB_DEV_XHCI_EP_STCHG_0_IN14_WOFFSET              0
#define XUSB_DEV_XHCI_EP_STCHG_0_IN14_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN14_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN14_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN14_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN14_NO                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN14_YES                  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN14_CLEAR                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT15_SHIFT                _MK_SHIFT_CONST(30)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT15_FIELD               (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_OUT15_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT15_RANGE               30:30
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT15_WOFFSET             0
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT15_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT15_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT15_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT15_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT15_NO                  _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT15_YES                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_OUT15_CLEAR               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN15_SHIFT                 _MK_SHIFT_CONST(31)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN15_FIELD                (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STCHG_0_IN15_SHIFT)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN15_RANGE                31:31
#define XUSB_DEV_XHCI_EP_STCHG_0_IN15_WOFFSET              0
#define XUSB_DEV_XHCI_EP_STCHG_0_IN15_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN15_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN15_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN15_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN15_NO                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN15_YES                  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STCHG_0_IN15_CLEAR                _MK_ENUM_CONST(0x00000001)


// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// Flowcontrol threshold values for HSFS NAK - SW needs to enable this if more than 4 IN or 4 OUT EPs are configured
// IDLE timeout for SS - number of microframes an async EP will be in idle state in a thread before it is evicted automatically


#define XUSB_DEV_XHCI_FLOWCNTRL_0                          _MK_ADDR_CONST(0x00000060)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_SECURE                   0
#define XUSB_DEV_XHCI_FLOWCNTRL_0_WORD_COUNT               1
#define XUSB_DEV_XHCI_FLOWCNTRL_0_RESET_VAL                _MK_MASK_CONST(0x80000)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_RESET_MASK               _MK_MASK_CONST(0xffffff)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_SW_DEFAULT_VAL           _MK_MASK_CONST(0x80000)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_SW_DEFAULT_MASK          _MK_MASK_CONST(0xffffff)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_READ_MASK                _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_WRITE_MASK               _MK_MASK_CONST(0xffffff)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_CLEAR_MASK               _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_TGL_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_IN_THRESH_SHIFT           _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_IN_THRESH_FIELD          (_MK_SHIFT_CONST(0x7f) << XUSB_DEV_XHCI_FLOWCNTRL_0_IN_THRESH_SHIFT)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_IN_THRESH_RANGE          6:0
#define XUSB_DEV_XHCI_FLOWCNTRL_0_IN_THRESH_WOFFSET        0
#define XUSB_DEV_XHCI_FLOWCNTRL_0_IN_THRESH_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_IN_THRESH_DEFAULT_MASK   (_MK_MASK_CONST(0x7f)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_IN_THRESH_SW_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_IN_THRESH_SW_DEFAULT_MASK (_MK_MASK_CONST(0x7f)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_IN_THRESH_INIT           _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_IN_EN_SHIFT               _MK_SHIFT_CONST(7)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_IN_EN_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_FLOWCNTRL_0_IN_EN_SHIFT)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_IN_EN_RANGE              7:7
#define XUSB_DEV_XHCI_FLOWCNTRL_0_IN_EN_WOFFSET            0
#define XUSB_DEV_XHCI_FLOWCNTRL_0_IN_EN_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_IN_EN_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_IN_EN_SW_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_IN_EN_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_IN_EN_INIT               _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_OUT_THRESH_SHIFT          _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_OUT_THRESH_FIELD         (_MK_SHIFT_CONST(0x7f) << XUSB_DEV_XHCI_FLOWCNTRL_0_OUT_THRESH_SHIFT)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_OUT_THRESH_RANGE         14:8
#define XUSB_DEV_XHCI_FLOWCNTRL_0_OUT_THRESH_WOFFSET       0
#define XUSB_DEV_XHCI_FLOWCNTRL_0_OUT_THRESH_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_OUT_THRESH_DEFAULT_MASK  (_MK_MASK_CONST(0x7f)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_OUT_THRESH_SW_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_OUT_THRESH_SW_DEFAULT_MASK (_MK_MASK_CONST(0x7f)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_OUT_THRESH_INIT          _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_OUT_EN_SHIFT              _MK_SHIFT_CONST(15)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_OUT_EN_FIELD             (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_FLOWCNTRL_0_OUT_EN_SHIFT)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_OUT_EN_RANGE             15:15
#define XUSB_DEV_XHCI_FLOWCNTRL_0_OUT_EN_WOFFSET           0
#define XUSB_DEV_XHCI_FLOWCNTRL_0_OUT_EN_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_OUT_EN_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_OUT_EN_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_OUT_EN_SW_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_OUT_EN_INIT              _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_IDLE_MITS_SHIFT           _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_IDLE_MITS_FIELD          (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_FLOWCNTRL_0_IDLE_MITS_SHIFT)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_IDLE_MITS_RANGE          23:16
#define XUSB_DEV_XHCI_FLOWCNTRL_0_IDLE_MITS_WOFFSET        0
#define XUSB_DEV_XHCI_FLOWCNTRL_0_IDLE_MITS_DEFAULT        (_MK_MASK_CONST(0x00000008)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_IDLE_MITS_DEFAULT_MASK   (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_IDLE_MITS_SW_DEFAULT     (_MK_MASK_CONST(0x00000008)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_IDLE_MITS_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_IDLE_MITS_INIT           _MK_ENUM_CONST(0x00000008)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_RSVD0_SHIFT               _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_RSVD0_FIELD              (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_FLOWCNTRL_0_RSVD0_SHIFT)
#define XUSB_DEV_XHCI_FLOWCNTRL_0_RSVD0_RANGE              31:24
#define XUSB_DEV_XHCI_FLOWCNTRL_0_RSVD0_WOFFSET            0
#define XUSB_DEV_XHCI_FLOWCNTRL_0_RSVD0_00                 _MK_ENUM_CONST(0x00000000)


// 
// Device notification registers, for SW to direct HW to send a device notification TP
// data should be written and updated before writing 1 to the trigger


#define XUSB_DEV_XHCI_DEVNOTIF_LO_0                        _MK_ADDR_CONST(0x00000064)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_SECURE                 0
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_WORD_COUNT             1
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_RESET_VAL              _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_RESET_MASK             _MK_MASK_CONST(0xfffffff1)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_SW_DEFAULT_VAL         _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_SW_DEFAULT_MASK        _MK_MASK_CONST(0xfffffff1)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_READ_MASK              _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_WRITE_MASK             _MK_MASK_CONST(0xfffffff1)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_CLEAR_MASK             _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_TGL_MASK               _MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_TRIG_SHIFT              _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_TRIG_FIELD             (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_DEVNOTIF_LO_0_TRIG_SHIFT)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_TRIG_RANGE             0:0
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_TRIG_WOFFSET           0
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_TRIG_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_TRIG_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_TRIG_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_TRIG_SW_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_TRIG_INIT              _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_TRIG_SET               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_RSVD0_SHIFT             _MK_SHIFT_CONST(1)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_RSVD0_FIELD            (_MK_SHIFT_CONST(0x7) << XUSB_DEV_XHCI_DEVNOTIF_LO_0_RSVD0_SHIFT)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_RSVD0_RANGE            3:1
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_RSVD0_WOFFSET          0
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_RSVD0_00               _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_TYPE_SHIFT              _MK_SHIFT_CONST(4)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_TYPE_FIELD             (_MK_SHIFT_CONST(0xf) << XUSB_DEV_XHCI_DEVNOTIF_LO_0_TYPE_SHIFT)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_TYPE_RANGE             7:4
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_TYPE_WOFFSET           0
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_TYPE_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_TYPE_DEFAULT_MASK      (_MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_TYPE_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_TYPE_SW_DEFAULT_MASK   (_MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_TYPE_INIT              _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_DATA_SHIFT              _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_DATA_FIELD             (_MK_SHIFT_CONST(0xffffff) << XUSB_DEV_XHCI_DEVNOTIF_LO_0_DATA_SHIFT)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_DATA_RANGE             31:8
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_DATA_WOFFSET           0
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_DATA_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_DATA_DEFAULT_MASK      (_MK_MASK_CONST(0xffffff)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_DATA_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_DATA_SW_DEFAULT_MASK   (_MK_MASK_CONST(0xffffff)
#define XUSB_DEV_XHCI_DEVNOTIF_LO_0_DATA_INIT              _MK_ENUM_CONST(0x00000000)


// 


#define XUSB_DEV_XHCI_DEVNOTIF_HI_0                        _MK_ADDR_CONST(0x00000068)
#define XUSB_DEV_XHCI_DEVNOTIF_HI_0_SECURE                 0
#define XUSB_DEV_XHCI_DEVNOTIF_HI_0_WORD_COUNT             1
#define XUSB_DEV_XHCI_DEVNOTIF_HI_0_RESET_VAL              _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_DEVNOTIF_HI_0_RESET_MASK             _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_DEVNOTIF_HI_0_SW_DEFAULT_VAL         _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_DEVNOTIF_HI_0_SW_DEFAULT_MASK        _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_DEVNOTIF_HI_0_READ_MASK              _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_DEVNOTIF_HI_0_WRITE_MASK             _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_DEVNOTIF_HI_0_CLEAR_MASK             _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_DEVNOTIF_HI_0_TGL_MASK               _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_DEVNOTIF_HI_0_DATA_SHIFT              _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_DEVNOTIF_HI_0_DATA_FIELD             (_MK_SHIFT_CONST(0xffffffff) << XUSB_DEV_XHCI_DEVNOTIF_HI_0_DATA_SHIFT)
#define XUSB_DEV_XHCI_DEVNOTIF_HI_0_DATA_RANGE             31:0
#define XUSB_DEV_XHCI_DEVNOTIF_HI_0_DATA_WOFFSET           0
#define XUSB_DEV_XHCI_DEVNOTIF_HI_0_DATA_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_DEVNOTIF_HI_0_DATA_DEFAULT_MASK      (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_DEVNOTIF_HI_0_DATA_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_DEVNOTIF_HI_0_DATA_SW_DEFAULT_MASK   (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_DEVNOTIF_HI_0_DATA_INIT              _MK_ENUM_CONST(0x00000000)


// 
// PORTHALT register for halt_ltssm related control and status


#define XUSB_DEV_XHCI_PORTHALT_0                           _MK_ADDR_CONST(0x0000006C)
#define XUSB_DEV_XHCI_PORTHALT_0_SECURE                    0
#define XUSB_DEV_XHCI_PORTHALT_0_WORD_COUNT                1
#define XUSB_DEV_XHCI_PORTHALT_0_RESET_VAL                 _MK_MASK_CONST(0x1000001)
#define XUSB_DEV_XHCI_PORTHALT_0_RESET_MASK                _MK_MASK_CONST(0x71f0003)
#define XUSB_DEV_XHCI_PORTHALT_0_SW_DEFAULT_VAL            _MK_MASK_CONST(0x1000001)
#define XUSB_DEV_XHCI_PORTHALT_0_SW_DEFAULT_MASK           _MK_MASK_CONST(0x71f0003)
#define XUSB_DEV_XHCI_PORTHALT_0_READ_MASK                 _MK_MASK_CONST(0x71f0003)
#define XUSB_DEV_XHCI_PORTHALT_0_WRITE_MASK                _MK_MASK_CONST(0x7100003)
#define XUSB_DEV_XHCI_PORTHALT_0_CLEAR_MASK                _MK_MASK_CONST(0x100002)
#define XUSB_DEV_XHCI_PORTHALT_0_TGL_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PORTHALT_0_HALT_LTSSM_SHIFT           _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_PORTHALT_0_HALT_LTSSM_FIELD          (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTHALT_0_HALT_LTSSM_SHIFT)
#define XUSB_DEV_XHCI_PORTHALT_0_HALT_LTSSM_RANGE          0:0
#define XUSB_DEV_XHCI_PORTHALT_0_HALT_LTSSM_WOFFSET        0
#define XUSB_DEV_XHCI_PORTHALT_0_HALT_LTSSM_DEFAULT        (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTHALT_0_HALT_LTSSM_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTHALT_0_HALT_LTSSM_SW_DEFAULT     (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTHALT_0_HALT_LTSSM_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTHALT_0_HALT_LTSSM_INIT           _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTHALT_0_HALT_REJECT_SHIFT          _MK_SHIFT_CONST(1)
#define XUSB_DEV_XHCI_PORTHALT_0_HALT_REJECT_FIELD         (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTHALT_0_HALT_REJECT_SHIFT)
#define XUSB_DEV_XHCI_PORTHALT_0_HALT_REJECT_RANGE         1:1
#define XUSB_DEV_XHCI_PORTHALT_0_HALT_REJECT_WOFFSET       0
#define XUSB_DEV_XHCI_PORTHALT_0_HALT_REJECT_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTHALT_0_HALT_REJECT_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTHALT_0_HALT_REJECT_SW_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTHALT_0_HALT_REJECT_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTHALT_0_HALT_REJECT_FALSE         _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTHALT_0_HALT_REJECT_TRUE          _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTHALT_0_HALT_REJECT_CLEAR         _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_STATE_SHIFT          _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_STATE_FIELD         (_MK_SHIFT_CONST(0xf) << XUSB_DEV_XHCI_PORTHALT_0_STCHG_STATE_SHIFT)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_STATE_RANGE         19:16
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_STATE_WOFFSET       0
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_STATE_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_STATE_DEFAULT_MASK  (_MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_STATE_SW_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_STATE_SW_DEFAULT_MASK (_MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_STATE_U0            _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_REQ_SHIFT            _MK_SHIFT_CONST(20)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_REQ_FIELD           (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTHALT_0_STCHG_REQ_SHIFT)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_REQ_RANGE           20:20
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_REQ_WOFFSET         0
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_REQ_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_REQ_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_REQ_SW_DEFAULT      (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_REQ_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_REQ_NOT_PENDING     _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_REQ_PENDING         _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_REQ_CLEAR           _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_INTR_EN_SHIFT        _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_INTR_EN_FIELD       (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTHALT_0_STCHG_INTR_EN_SHIFT)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_INTR_EN_RANGE       24:24
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_INTR_EN_WOFFSET     0
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_INTR_EN_DEFAULT     (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_INTR_EN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_INTR_EN_SW_DEFAULT  (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_INTR_EN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_INTR_EN_INIT        _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_PME_EN_SHIFT         _MK_SHIFT_CONST(25)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_PME_EN_FIELD        (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTHALT_0_STCHG_PME_EN_SHIFT)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_PME_EN_RANGE        25:25
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_PME_EN_WOFFSET      0
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_PME_EN_DEFAULT      (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_PME_EN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_PME_EN_SW_DEFAULT   (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_PME_EN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_PME_EN_INIT         _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_SMI_EN_SHIFT         _MK_SHIFT_CONST(26)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_SMI_EN_FIELD        (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PORTHALT_0_STCHG_SMI_EN_SHIFT)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_SMI_EN_RANGE        26:26
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_SMI_EN_WOFFSET      0
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_SMI_EN_DEFAULT      (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_SMI_EN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_SMI_EN_SW_DEFAULT   (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_SMI_EN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PORTHALT_0_STCHG_SMI_EN_INIT         _MK_ENUM_CONST(0x00000000)


// 
// Testmode control register, for enabling DUT to enter testmode and send specific patterns


#define XUSB_DEV_XHCI_PORT_TM_0                            _MK_ADDR_CONST(0x00000070)
#define XUSB_DEV_XHCI_PORT_TM_0_SECURE                     0
#define XUSB_DEV_XHCI_PORT_TM_0_WORD_COUNT                 1
#define XUSB_DEV_XHCI_PORT_TM_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PORT_TM_0_RESET_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_PORT_TM_0_SW_DEFAULT_VAL             _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PORT_TM_0_SW_DEFAULT_MASK            _MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_PORT_TM_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_PORT_TM_0_WRITE_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_PORT_TM_0_CLEAR_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PORT_TM_0_TGL_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PORT_TM_0_CTRL_SHIFT                  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_PORT_TM_0_CTRL_FIELD                 (_MK_SHIFT_CONST(0xf) << XUSB_DEV_XHCI_PORT_TM_0_CTRL_SHIFT)
#define XUSB_DEV_XHCI_PORT_TM_0_CTRL_RANGE                 3:0
#define XUSB_DEV_XHCI_PORT_TM_0_CTRL_WOFFSET               0
#define XUSB_DEV_XHCI_PORT_TM_0_CTRL_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORT_TM_0_CTRL_DEFAULT_MASK          (_MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_PORT_TM_0_CTRL_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORT_TM_0_CTRL_SW_DEFAULT_MASK       (_MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_PORT_TM_0_CTRL_DISABLED              _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PORT_TM_0_CTRL_TESTJ                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_PORT_TM_0_CTRL_TESTK                 _MK_ENUM_CONST(0x00000002)
#define XUSB_DEV_XHCI_PORT_TM_0_CTRL_SE0_NAK               _MK_ENUM_CONST(0x00000003)
#define XUSB_DEV_XHCI_PORT_TM_0_CTRL_TEST_PKT              _MK_ENUM_CONST(0x00000004)
#define XUSB_DEV_XHCI_PORT_TM_0_CTRL_TEST_FORCEEN          _MK_ENUM_CONST(0x00000005)


// 
// Per EP bit to indicate whether EP is loaded/active in BI


#define XUSB_DEV_XHCI_EP_THREAD_ACTIVE_0                   _MK_ADDR_CONST(0x00000074)
#define XUSB_DEV_XHCI_EP_THREAD_ACTIVE_0_SECURE            0
#define XUSB_DEV_XHCI_EP_THREAD_ACTIVE_0_WORD_COUNT        1
#define XUSB_DEV_XHCI_EP_THREAD_ACTIVE_0_RESET_VAL         _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EP_THREAD_ACTIVE_0_RESET_MASK        _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_THREAD_ACTIVE_0_SW_DEFAULT_VAL    _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EP_THREAD_ACTIVE_0_SW_DEFAULT_MASK   _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_THREAD_ACTIVE_0_READ_MASK         _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_THREAD_ACTIVE_0_WRITE_MASK        _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EP_THREAD_ACTIVE_0_CLEAR_MASK        _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EP_THREAD_ACTIVE_0_TGL_MASK          _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EP_THREAD_ACTIVE_0_DCI_SHIFT          _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_EP_THREAD_ACTIVE_0_DCI_FIELD         (_MK_SHIFT_CONST(0xffffffff) << XUSB_DEV_XHCI_EP_THREAD_ACTIVE_0_DCI_SHIFT)
#define XUSB_DEV_XHCI_EP_THREAD_ACTIVE_0_DCI_RANGE         31:0
#define XUSB_DEV_XHCI_EP_THREAD_ACTIVE_0_DCI_WOFFSET       0
#define XUSB_DEV_XHCI_EP_THREAD_ACTIVE_0_DCI_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_THREAD_ACTIVE_0_DCI_DEFAULT_MASK  (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_THREAD_ACTIVE_0_DCI_SW_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_THREAD_ACTIVE_0_DCI_SW_DEFAULT_MASK (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_THREAD_ACTIVE_0_DCI_NO            _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_THREAD_ACTIVE_0_DCI_YES           _MK_ENUM_CONST(0x00000001)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_EP_THREAD_ACTIVE__PRODCHK                      0 /*       */
// 
// EP_STOPPED register
// This register has a per endpoit Write 1 to Clear bit to indicate that the Endpoint has hit an error
// condition which needs to be cleared to 0 to stop the endpoint from being processed again


#define XUSB_DEV_XHCI_EP_STOPPED_0                         _MK_ADDR_CONST(0x00000078)
#define XUSB_DEV_XHCI_EP_STOPPED_0_SECURE                  0
#define XUSB_DEV_XHCI_EP_STOPPED_0_WORD_COUNT              1
#define XUSB_DEV_XHCI_EP_STOPPED_0_RESET_VAL               _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EP_STOPPED_0_RESET_MASK              _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_STOPPED_0_SW_DEFAULT_VAL          _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EP_STOPPED_0_SW_DEFAULT_MASK         _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_STOPPED_0_READ_MASK               _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_STOPPED_0_WRITE_MASK              _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_STOPPED_0_CLEAR_MASK              _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_EP_STOPPED_0_TGL_MASK                _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT0_SHIFT               _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT0_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_OUT0_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT0_RANGE              0:0
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT0_WOFFSET            0
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT0_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT0_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT0_SW_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT0_NO                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT0_YES                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT0_CLEAR              _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN0_SHIFT                _MK_SHIFT_CONST(1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN0_FIELD               (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_IN0_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN0_RANGE               1:1
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN0_WOFFSET             0
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN0_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN0_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN0_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN0_NO                  _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN0_YES                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN0_CLEAR               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT1_SHIFT               _MK_SHIFT_CONST(2)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT1_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_OUT1_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT1_RANGE              2:2
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT1_WOFFSET            0
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT1_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT1_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT1_SW_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT1_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT1_NO                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT1_YES                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT1_CLEAR              _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN1_SHIFT                _MK_SHIFT_CONST(3)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN1_FIELD               (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_IN1_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN1_RANGE               3:3
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN1_WOFFSET             0
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN1_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN1_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN1_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN1_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN1_NO                  _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN1_YES                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN1_CLEAR               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT2_SHIFT               _MK_SHIFT_CONST(4)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT2_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_OUT2_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT2_RANGE              4:4
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT2_WOFFSET            0
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT2_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT2_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT2_SW_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT2_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT2_NO                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT2_YES                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT2_CLEAR              _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN2_SHIFT                _MK_SHIFT_CONST(5)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN2_FIELD               (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_IN2_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN2_RANGE               5:5
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN2_WOFFSET             0
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN2_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN2_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN2_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN2_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN2_NO                  _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN2_YES                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN2_CLEAR               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT3_SHIFT               _MK_SHIFT_CONST(6)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT3_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_OUT3_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT3_RANGE              6:6
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT3_WOFFSET            0
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT3_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT3_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT3_SW_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT3_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT3_NO                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT3_YES                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT3_CLEAR              _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN3_SHIFT                _MK_SHIFT_CONST(7)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN3_FIELD               (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_IN3_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN3_RANGE               7:7
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN3_WOFFSET             0
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN3_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN3_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN3_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN3_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN3_NO                  _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN3_YES                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN3_CLEAR               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT4_SHIFT               _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT4_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_OUT4_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT4_RANGE              8:8
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT4_WOFFSET            0
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT4_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT4_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT4_SW_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT4_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT4_NO                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT4_YES                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT4_CLEAR              _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN4_SHIFT                _MK_SHIFT_CONST(9)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN4_FIELD               (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_IN4_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN4_RANGE               9:9
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN4_WOFFSET             0
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN4_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN4_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN4_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN4_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN4_NO                  _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN4_YES                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN4_CLEAR               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT5_SHIFT               _MK_SHIFT_CONST(10)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT5_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_OUT5_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT5_RANGE              10:10
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT5_WOFFSET            0
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT5_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT5_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT5_SW_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT5_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT5_NO                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT5_YES                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT5_CLEAR              _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN5_SHIFT                _MK_SHIFT_CONST(11)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN5_FIELD               (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_IN5_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN5_RANGE               11:11
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN5_WOFFSET             0
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN5_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN5_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN5_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN5_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN5_NO                  _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN5_YES                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN5_CLEAR               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT6_SHIFT               _MK_SHIFT_CONST(12)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT6_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_OUT6_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT6_RANGE              12:12
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT6_WOFFSET            0
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT6_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT6_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT6_SW_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT6_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT6_NO                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT6_YES                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT6_CLEAR              _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN6_SHIFT                _MK_SHIFT_CONST(13)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN6_FIELD               (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_IN6_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN6_RANGE               13:13
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN6_WOFFSET             0
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN6_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN6_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN6_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN6_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN6_NO                  _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN6_YES                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN6_CLEAR               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT7_SHIFT               _MK_SHIFT_CONST(14)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT7_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_OUT7_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT7_RANGE              14:14
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT7_WOFFSET            0
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT7_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT7_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT7_SW_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT7_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT7_NO                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT7_YES                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT7_CLEAR              _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN7_SHIFT                _MK_SHIFT_CONST(15)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN7_FIELD               (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_IN7_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN7_RANGE               15:15
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN7_WOFFSET             0
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN7_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN7_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN7_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN7_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN7_NO                  _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN7_YES                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN7_CLEAR               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT8_SHIFT               _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT8_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_OUT8_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT8_RANGE              16:16
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT8_WOFFSET            0
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT8_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT8_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT8_SW_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT8_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT8_NO                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT8_YES                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT8_CLEAR              _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN8_SHIFT                _MK_SHIFT_CONST(17)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN8_FIELD               (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_IN8_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN8_RANGE               17:17
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN8_WOFFSET             0
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN8_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN8_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN8_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN8_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN8_NO                  _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN8_YES                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN8_CLEAR               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT9_SHIFT               _MK_SHIFT_CONST(18)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT9_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_OUT9_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT9_RANGE              18:18
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT9_WOFFSET            0
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT9_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT9_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT9_SW_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT9_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT9_NO                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT9_YES                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT9_CLEAR              _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN9_SHIFT                _MK_SHIFT_CONST(19)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN9_FIELD               (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_IN9_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN9_RANGE               19:19
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN9_WOFFSET             0
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN9_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN9_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN9_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN9_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN9_NO                  _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN9_YES                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN9_CLEAR               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT10_SHIFT              _MK_SHIFT_CONST(20)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT10_FIELD             (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_OUT10_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT10_RANGE             20:20
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT10_WOFFSET           0
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT10_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT10_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT10_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT10_SW_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT10_NO                _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT10_YES               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT10_CLEAR             _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN10_SHIFT               _MK_SHIFT_CONST(21)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN10_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_IN10_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN10_RANGE              21:21
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN10_WOFFSET            0
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN10_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN10_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN10_SW_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN10_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN10_NO                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN10_YES                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN10_CLEAR              _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT11_SHIFT              _MK_SHIFT_CONST(22)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT11_FIELD             (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_OUT11_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT11_RANGE             22:22
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT11_WOFFSET           0
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT11_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT11_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT11_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT11_SW_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT11_NO                _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT11_YES               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT11_CLEAR             _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN11_SHIFT               _MK_SHIFT_CONST(23)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN11_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_IN11_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN11_RANGE              23:23
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN11_WOFFSET            0
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN11_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN11_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN11_SW_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN11_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN11_NO                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN11_YES                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN11_CLEAR              _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT12_SHIFT              _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT12_FIELD             (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_OUT12_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT12_RANGE             24:24
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT12_WOFFSET           0
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT12_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT12_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT12_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT12_SW_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT12_NO                _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT12_YES               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT12_CLEAR             _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN12_SHIFT               _MK_SHIFT_CONST(25)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN12_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_IN12_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN12_RANGE              25:25
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN12_WOFFSET            0
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN12_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN12_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN12_SW_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN12_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN12_NO                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN12_YES                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN12_CLEAR              _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT13_SHIFT              _MK_SHIFT_CONST(26)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT13_FIELD             (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_OUT13_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT13_RANGE             26:26
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT13_WOFFSET           0
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT13_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT13_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT13_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT13_SW_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT13_NO                _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT13_YES               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT13_CLEAR             _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN13_SHIFT               _MK_SHIFT_CONST(27)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN13_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_IN13_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN13_RANGE              27:27
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN13_WOFFSET            0
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN13_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN13_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN13_SW_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN13_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN13_NO                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN13_YES                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN13_CLEAR              _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT14_SHIFT              _MK_SHIFT_CONST(28)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT14_FIELD             (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_OUT14_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT14_RANGE             28:28
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT14_WOFFSET           0
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT14_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT14_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT14_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT14_SW_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT14_NO                _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT14_YES               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT14_CLEAR             _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN14_SHIFT               _MK_SHIFT_CONST(29)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN14_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_IN14_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN14_RANGE              29:29
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN14_WOFFSET            0
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN14_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN14_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN14_SW_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN14_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN14_NO                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN14_YES                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN14_CLEAR              _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT15_SHIFT              _MK_SHIFT_CONST(30)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT15_FIELD             (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_OUT15_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT15_RANGE             30:30
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT15_WOFFSET           0
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT15_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT15_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT15_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT15_SW_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT15_NO                _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT15_YES               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_OUT15_CLEAR             _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN15_SHIFT               _MK_SHIFT_CONST(31)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN15_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_EP_STOPPED_0_IN15_SHIFT)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN15_RANGE              31:31
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN15_WOFFSET            0
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN15_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN15_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN15_SW_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN15_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN15_NO                 _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN15_YES                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_EP_STOPPED_0_IN15_CLEAR              _MK_ENUM_CONST(0x00000001)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_EP_STOPPED__PRODCHK                             0 /*       */
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 


#define XUSB_DEV_XHCI_STREAMID_CFG_0                       _MK_ADDR_CONST(0x0000007C)
#define XUSB_DEV_XHCI_STREAMID_CFG_0_SECURE                0
#define XUSB_DEV_XHCI_STREAMID_CFG_0_WORD_COUNT            1
#define XUSB_DEV_XHCI_STREAMID_CFG_0_RESET_VAL             _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_STREAMID_CFG_0_RESET_MASK            _MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_STREAMID_CFG_0_SW_DEFAULT_VAL        _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_STREAMID_CFG_0_SW_DEFAULT_MASK       _MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_STREAMID_CFG_0_READ_MASK             _MK_MASK_CONST(0xffff1f01)
#define XUSB_DEV_XHCI_STREAMID_CFG_0_WRITE_MASK            _MK_MASK_CONST(0xffff1f01)
#define XUSB_DEV_XHCI_STREAMID_CFG_0_CLEAR_MASK            _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_STREAMID_CFG_0_TGL_MASK              _MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_STREAMID_CFG_0_TRIGGER_SHIFT          _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_STREAMID_CFG_0_TRIGGER_FIELD         (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_STREAMID_CFG_0_TRIGGER_SHIFT)
#define XUSB_DEV_XHCI_STREAMID_CFG_0_TRIGGER_RANGE         0:0
#define XUSB_DEV_XHCI_STREAMID_CFG_0_TRIGGER_WOFFSET       0
#define XUSB_DEV_XHCI_STREAMID_CFG_0_TRIGGER_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_STREAMID_CFG_0_TRIGGER_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_STREAMID_CFG_0_TRIGGER_SW_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_STREAMID_CFG_0_TRIGGER_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_STREAMID_CFG_0_TRIGGER_NOT_PENDING   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_STREAMID_CFG_0_TRIGGER_PENDING       _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_STREAMID_CFG_0_TRIGGER_SET           _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_STREAMID_CFG_0_DCI_SHIFT              _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_STREAMID_CFG_0_DCI_FIELD             (_MK_SHIFT_CONST(0x1f) << XUSB_DEV_XHCI_STREAMID_CFG_0_DCI_SHIFT)
#define XUSB_DEV_XHCI_STREAMID_CFG_0_DCI_RANGE             12:8
#define XUSB_DEV_XHCI_STREAMID_CFG_0_DCI_WOFFSET           0
#define XUSB_DEV_XHCI_STREAMID_CFG_0_STREAMID_SHIFT         _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_STREAMID_CFG_0_STREAMID_FIELD        (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_XHCI_STREAMID_CFG_0_STREAMID_SHIFT)
#define XUSB_DEV_XHCI_STREAMID_CFG_0_STREAMID_RANGE        31:16
#define XUSB_DEV_XHCI_STREAMID_CFG_0_STREAMID_WOFFSET      0


// 
// 
// SOFTRST signal for device mode


#define XUSB_DEV_XHCI_DEV_SOFTRST_0                        _MK_ADDR_CONST(0x00000084)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_SECURE                 0
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_WORD_COUNT             1
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_RESET_VAL              _MK_MASK_CONST(0x8000)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_RESET_MASK             _MK_MASK_CONST(0xff03)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_SW_DEFAULT_VAL         _MK_MASK_CONST(0x8000)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_SW_DEFAULT_MASK        _MK_MASK_CONST(0xff03)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_READ_MASK              _MK_MASK_CONST(0xff03)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_WRITE_MASK             _MK_MASK_CONST(0xff03)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_CLEAR_MASK             _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_TGL_MASK               _MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_RESET_SHIFT             _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_RESET_FIELD            (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_DEV_SOFTRST_0_RESET_SHIFT)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_RESET_RANGE            0:0
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_RESET_WOFFSET          0
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_RESET_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_RESET_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_RESET_SW_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_RESET_SW_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_RESET_NOT_PENDING      _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_RESET_PENDING          _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_RESET_SET              _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_CYA_DMAIDLE_SHIFT       _MK_SHIFT_CONST(1)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_CYA_DMAIDLE_FIELD      (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_DEV_SOFTRST_0_CYA_DMAIDLE_SHIFT)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_CYA_DMAIDLE_RANGE      1:1
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_CYA_DMAIDLE_WOFFSET    0
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_CYA_DMAIDLE_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_CYA_DMAIDLE_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_CYA_DMAIDLE_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_CYA_DMAIDLE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_CYA_DMAIDLE_INIT       _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_RSTCNT_SHIFT            _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_RSTCNT_FIELD           (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_DEV_SOFTRST_0_RSTCNT_SHIFT)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_RSTCNT_RANGE           15:8
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_RSTCNT_WOFFSET         0
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_RSTCNT_DEFAULT         (_MK_MASK_CONST(0x00000080)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_RSTCNT_DEFAULT_MASK    (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_RSTCNT_SW_DEFAULT      (_MK_MASK_CONST(0x00000080)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_RSTCNT_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_DEV_SOFTRST_0_RSTCNT_INIT            _MK_ENUM_CONST(0x00000080)


// 
// Device mode HSFSPI configuration registers for various internal counters in HW


#define XUSB_DEV_XHCI_HSFSPI_COUNT0_0                      _MK_ADDR_CONST(0x00000100)
#define XUSB_DEV_XHCI_HSFSPI_COUNT0_0_SECURE               0
#define XUSB_DEV_XHCI_HSFSPI_COUNT0_0_WORD_COUNT           1
#define XUSB_DEV_XHCI_HSFSPI_COUNT0_0_RESET_VAL            _MK_MASK_CONST(0x12c)
#define XUSB_DEV_XHCI_HSFSPI_COUNT0_0_RESET_MASK           _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT0_0_SW_DEFAULT_VAL       _MK_MASK_CONST(0x12c)
#define XUSB_DEV_XHCI_HSFSPI_COUNT0_0_SW_DEFAULT_MASK      _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT0_0_READ_MASK            _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT0_0_WRITE_MASK           _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT0_0_CLEAR_MASK           _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT0_0_TGL_MASK             _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT0_0_FS_RESET_MIN_SHIFT    _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT0_0_FS_RESET_MIN_FIELD   (_MK_SHIFT_CONST(0x3fffffff) << XUSB_DEV_XHCI_HSFSPI_COUNT0_0_FS_RESET_MIN_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_COUNT0_0_FS_RESET_MIN_RANGE   29:0
#define XUSB_DEV_XHCI_HSFSPI_COUNT0_0_FS_RESET_MIN_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_COUNT0_0_FS_RESET_MIN_DEFAULT (_MK_MASK_CONST(0x0000012C)
#define XUSB_DEV_XHCI_HSFSPI_COUNT0_0_FS_RESET_MIN_DEFAULT_MASK (_MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT0_0_FS_RESET_MIN_SW_DEFAULT (_MK_MASK_CONST(0x0000012C)
#define XUSB_DEV_XHCI_HSFSPI_COUNT0_0_FS_RESET_MIN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT0_0_FS_RESET_MIN_INIT    _MK_ENUM_CONST(0x0000012C)


// 


#define XUSB_DEV_XHCI_HSFSPI_COUNT1_0                      _MK_ADDR_CONST(0x00000104)
#define XUSB_DEV_XHCI_HSFSPI_COUNT1_0_SECURE               0
#define XUSB_DEV_XHCI_HSFSPI_COUNT1_0_WORD_COUNT           1
#define XUSB_DEV_XHCI_HSFSPI_COUNT1_0_RESET_VAL            _MK_MASK_CONST(0x3395)
#define XUSB_DEV_XHCI_HSFSPI_COUNT1_0_RESET_MASK           _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT1_0_SW_DEFAULT_VAL       _MK_MASK_CONST(0x3395)
#define XUSB_DEV_XHCI_HSFSPI_COUNT1_0_SW_DEFAULT_MASK      _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT1_0_READ_MASK            _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT1_0_WRITE_MASK           _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT1_0_CLEAR_MASK           _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT1_0_TGL_MASK             _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT1_0_HS_RESET_MIN_SHIFT    _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT1_0_HS_RESET_MIN_FIELD   (_MK_SHIFT_CONST(0x3fffffff) << XUSB_DEV_XHCI_HSFSPI_COUNT1_0_HS_RESET_MIN_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_COUNT1_0_HS_RESET_MIN_RANGE   29:0
#define XUSB_DEV_XHCI_HSFSPI_COUNT1_0_HS_RESET_MIN_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_COUNT1_0_HS_RESET_MIN_DEFAULT (_MK_MASK_CONST(0x00003395)
#define XUSB_DEV_XHCI_HSFSPI_COUNT1_0_HS_RESET_MIN_DEFAULT_MASK (_MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT1_0_HS_RESET_MIN_SW_DEFAULT (_MK_MASK_CONST(0x00003395)
#define XUSB_DEV_XHCI_HSFSPI_COUNT1_0_HS_RESET_MIN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT1_0_HS_RESET_MIN_INIT    _MK_ENUM_CONST(0x00003395)


// 


#define XUSB_DEV_XHCI_HSFSPI_COUNT2_0                      _MK_ADDR_CONST(0x00000108)
#define XUSB_DEV_XHCI_HSFSPI_COUNT2_0_SECURE               0
#define XUSB_DEV_XHCI_HSFSPI_COUNT2_0_WORD_COUNT           1
#define XUSB_DEV_XHCI_HSFSPI_COUNT2_0_RESET_VAL            _MK_MASK_CONST(0x2eef)
#define XUSB_DEV_XHCI_HSFSPI_COUNT2_0_RESET_MASK           _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT2_0_SW_DEFAULT_VAL       _MK_MASK_CONST(0x2eef)
#define XUSB_DEV_XHCI_HSFSPI_COUNT2_0_SW_DEFAULT_MASK      _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT2_0_READ_MASK            _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT2_0_WRITE_MASK           _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT2_0_CLEAR_MASK           _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT2_0_TGL_MASK             _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT2_0_HS_RESET_ST_RESET_MIN_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT2_0_HS_RESET_ST_RESET_MIN_FIELD (_MK_SHIFT_CONST(0x3fffffff) << XUSB_DEV_XHCI_HSFSPI_COUNT2_0_HS_RESET_ST_RESET_MIN_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_COUNT2_0_HS_RESET_ST_RESET_MIN_RANGE 29:0
#define XUSB_DEV_XHCI_HSFSPI_COUNT2_0_HS_RESET_ST_RESET_MIN_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_COUNT2_0_HS_RESET_ST_RESET_MIN_DEFAULT (_MK_MASK_CONST(0x0002EEF)
#define XUSB_DEV_XHCI_HSFSPI_COUNT2_0_HS_RESET_ST_RESET_MIN_DEFAULT_MASK (_MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT2_0_HS_RESET_ST_RESET_MIN_SW_DEFAULT (_MK_MASK_CONST(0x0002EEF)
#define XUSB_DEV_XHCI_HSFSPI_COUNT2_0_HS_RESET_ST_RESET_MIN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT2_0_HS_RESET_ST_RESET_MIN_INIT _MK_ENUM_CONST(0x0002EEF)


// 
// 


#define XUSB_DEV_XHCI_HSFSPI_COUNT3_0                      _MK_ADDR_CONST(0x0000010C)
#define XUSB_DEV_XHCI_HSFSPI_COUNT3_0_SECURE               0
#define XUSB_DEV_XHCI_HSFSPI_COUNT3_0_WORD_COUNT           1
#define XUSB_DEV_XHCI_HSFSPI_COUNT3_0_RESET_VAL            _MK_MASK_CONST(0x3a980)
#define XUSB_DEV_XHCI_HSFSPI_COUNT3_0_RESET_MASK           _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT3_0_SW_DEFAULT_VAL       _MK_MASK_CONST(0x3a980)
#define XUSB_DEV_XHCI_HSFSPI_COUNT3_0_SW_DEFAULT_MASK      _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT3_0_READ_MASK            _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT3_0_WRITE_MASK           _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT3_0_CLEAR_MASK           _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT3_0_TGL_MASK             _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT3_0_TX_CHIRP_MID_SHIFT    _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT3_0_TX_CHIRP_MID_FIELD   (_MK_SHIFT_CONST(0x3fffffff) << XUSB_DEV_XHCI_HSFSPI_COUNT3_0_TX_CHIRP_MID_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_COUNT3_0_TX_CHIRP_MID_RANGE   29:0
#define XUSB_DEV_XHCI_HSFSPI_COUNT3_0_TX_CHIRP_MID_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_COUNT3_0_TX_CHIRP_MID_DEFAULT (_MK_MASK_CONST(0x0003A980)
#define XUSB_DEV_XHCI_HSFSPI_COUNT3_0_TX_CHIRP_MID_DEFAULT_MASK (_MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT3_0_TX_CHIRP_MID_SW_DEFAULT (_MK_MASK_CONST(0x0003A980)
#define XUSB_DEV_XHCI_HSFSPI_COUNT3_0_TX_CHIRP_MID_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT3_0_TX_CHIRP_MID_INIT    _MK_ENUM_CONST(0x0003A980)


// 


#define XUSB_DEV_XHCI_HSFSPI_COUNT4_0                      _MK_ADDR_CONST(0x00000110)
#define XUSB_DEV_XHCI_HSFSPI_COUNT4_0_SECURE               0
#define XUSB_DEV_XHCI_HSFSPI_COUNT4_0_WORD_COUNT           1
#define XUSB_DEV_XHCI_HSFSPI_COUNT4_0_RESET_VAL            _MK_MASK_CONST(0x12c0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT4_0_RESET_MASK           _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT4_0_SW_DEFAULT_VAL       _MK_MASK_CONST(0x12c0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT4_0_SW_DEFAULT_MASK      _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT4_0_READ_MASK            _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT4_0_WRITE_MASK           _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT4_0_CLEAR_MASK           _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT4_0_TGL_MASK             _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT4_0_CHIRP_MIN_SHIFT       _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT4_0_CHIRP_MIN_FIELD      (_MK_SHIFT_CONST(0x3fffffff) << XUSB_DEV_XHCI_HSFSPI_COUNT4_0_CHIRP_MIN_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_COUNT4_0_CHIRP_MIN_RANGE      29:0
#define XUSB_DEV_XHCI_HSFSPI_COUNT4_0_CHIRP_MIN_WOFFSET    0
#define XUSB_DEV_XHCI_HSFSPI_COUNT4_0_CHIRP_MIN_DEFAULT    (_MK_MASK_CONST(0x000012C0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT4_0_CHIRP_MIN_DEFAULT_MASK (_MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT4_0_CHIRP_MIN_SW_DEFAULT (_MK_MASK_CONST(0x000012C0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT4_0_CHIRP_MIN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT4_0_CHIRP_MIN_INIT       _MK_ENUM_CONST(0x000012C0)


// 


#define XUSB_DEV_XHCI_HSFSPI_COUNT5_0                      _MK_ADDR_CONST(0x00000114)
#define XUSB_DEV_XHCI_HSFSPI_COUNT5_0_SECURE               0
#define XUSB_DEV_XHCI_HSFSPI_COUNT5_0_WORD_COUNT           1
#define XUSB_DEV_XHCI_HSFSPI_COUNT5_0_RESET_VAL            _MK_MASK_CONST(0x1c20)
#define XUSB_DEV_XHCI_HSFSPI_COUNT5_0_RESET_MASK           _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT5_0_SW_DEFAULT_VAL       _MK_MASK_CONST(0x1c20)
#define XUSB_DEV_XHCI_HSFSPI_COUNT5_0_SW_DEFAULT_MASK      _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT5_0_READ_MASK            _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT5_0_WRITE_MASK           _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT5_0_CLEAR_MASK           _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT5_0_TGL_MASK             _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT5_0_CHIRP_MAX_SHIFT       _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT5_0_CHIRP_MAX_FIELD      (_MK_SHIFT_CONST(0x3fffffff) << XUSB_DEV_XHCI_HSFSPI_COUNT5_0_CHIRP_MAX_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_COUNT5_0_CHIRP_MAX_RANGE      29:0
#define XUSB_DEV_XHCI_HSFSPI_COUNT5_0_CHIRP_MAX_WOFFSET    0
#define XUSB_DEV_XHCI_HSFSPI_COUNT5_0_CHIRP_MAX_DEFAULT    (_MK_MASK_CONST(0x00001C20)
#define XUSB_DEV_XHCI_HSFSPI_COUNT5_0_CHIRP_MAX_DEFAULT_MASK (_MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT5_0_CHIRP_MAX_SW_DEFAULT (_MK_MASK_CONST(0x00001C20)
#define XUSB_DEV_XHCI_HSFSPI_COUNT5_0_CHIRP_MAX_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT5_0_CHIRP_MAX_INIT       _MK_ENUM_CONST(0x00001C20)


// 


#define XUSB_DEV_XHCI_HSFSPI_COUNT6_0                      _MK_ADDR_CONST(0x00000118)
#define XUSB_DEV_XHCI_HSFSPI_COUNT6_0_SECURE               0
#define XUSB_DEV_XHCI_HSFSPI_COUNT6_0_WORD_COUNT           1
#define XUSB_DEV_XHCI_HSFSPI_COUNT6_0_RESET_VAL            _MK_MASK_CONST(0x57ed0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT6_0_RESET_MASK           _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT6_0_SW_DEFAULT_VAL       _MK_MASK_CONST(0x57ed0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT6_0_SW_DEFAULT_MASK      _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT6_0_READ_MASK            _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT6_0_WRITE_MASK           _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT6_0_CLEAR_MASK           _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT6_0_TGL_MASK             _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT6_0_INACTIVITY_TIMEOUT_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT6_0_INACTIVITY_TIMEOUT_FIELD (_MK_SHIFT_CONST(0x3fffffff) << XUSB_DEV_XHCI_HSFSPI_COUNT6_0_INACTIVITY_TIMEOUT_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_COUNT6_0_INACTIVITY_TIMEOUT_RANGE 29:0
#define XUSB_DEV_XHCI_HSFSPI_COUNT6_0_INACTIVITY_TIMEOUT_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_COUNT6_0_INACTIVITY_TIMEOUT_DEFAULT (_MK_MASK_CONST(0x000057ED0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT6_0_INACTIVITY_TIMEOUT_DEFAULT_MASK (_MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT6_0_INACTIVITY_TIMEOUT_SW_DEFAULT (_MK_MASK_CONST(0x000057ED0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT6_0_INACTIVITY_TIMEOUT_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT6_0_INACTIVITY_TIMEOUT_INIT _MK_ENUM_CONST(0x000057ED0)


// 


#define XUSB_DEV_XHCI_HSFSPI_COUNT7_0                      _MK_ADDR_CONST(0x0000011C)
#define XUSB_DEV_XHCI_HSFSPI_COUNT7_0_SECURE               0
#define XUSB_DEV_XHCI_HSFSPI_COUNT7_0_WORD_COUNT           1
#define XUSB_DEV_XHCI_HSFSPI_COUNT7_0_RESET_VAL            _MK_MASK_CONST(0xe0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT7_0_RESET_MASK           _MK_MASK_CONST(0x3fffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT7_0_SW_DEFAULT_VAL       _MK_MASK_CONST(0xe0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT7_0_SW_DEFAULT_MASK      _MK_MASK_CONST(0x3fffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT7_0_READ_MASK            _MK_MASK_CONST(0x3fffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT7_0_WRITE_MASK           _MK_MASK_CONST(0x3fffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT7_0_CLEAR_MASK           _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT7_0_TGL_MASK             _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT7_0_HS_FSM_TIMEOUT_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT7_0_HS_FSM_TIMEOUT_FIELD (_MK_SHIFT_CONST(0x3fffff) << XUSB_DEV_XHCI_HSFSPI_COUNT7_0_HS_FSM_TIMEOUT_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_COUNT7_0_HS_FSM_TIMEOUT_RANGE 21:0
#define XUSB_DEV_XHCI_HSFSPI_COUNT7_0_HS_FSM_TIMEOUT_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_COUNT7_0_HS_FSM_TIMEOUT_DEFAULT (_MK_MASK_CONST(0x000000E0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT7_0_HS_FSM_TIMEOUT_DEFAULT_MASK (_MK_MASK_CONST(0x3fffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT7_0_HS_FSM_TIMEOUT_SW_DEFAULT (_MK_MASK_CONST(0x000000E0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT7_0_HS_FSM_TIMEOUT_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3fffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT7_0_HS_FSM_TIMEOUT_INIT  _MK_ENUM_CONST(0x000000E0)


// 


#define XUSB_DEV_XHCI_HSFSPI_COUNT8_0                      _MK_ADDR_CONST(0x00000120)
#define XUSB_DEV_XHCI_HSFSPI_COUNT8_0_SECURE               0
#define XUSB_DEV_XHCI_HSFSPI_COUNT8_0_WORD_COUNT           1
#define XUSB_DEV_XHCI_HSFSPI_COUNT8_0_RESET_VAL            _MK_MASK_CONST(0xb0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT8_0_RESET_MASK           _MK_MASK_CONST(0x3fffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT8_0_SW_DEFAULT_VAL       _MK_MASK_CONST(0xb0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT8_0_SW_DEFAULT_MASK      _MK_MASK_CONST(0x3fffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT8_0_READ_MASK            _MK_MASK_CONST(0x3fffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT8_0_WRITE_MASK           _MK_MASK_CONST(0x3fffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT8_0_CLEAR_MASK           _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT8_0_TGL_MASK             _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT8_0_FS_FSM_TIMEOUT_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT8_0_FS_FSM_TIMEOUT_FIELD (_MK_SHIFT_CONST(0x3fffff) << XUSB_DEV_XHCI_HSFSPI_COUNT8_0_FS_FSM_TIMEOUT_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_COUNT8_0_FS_FSM_TIMEOUT_RANGE 21:0
#define XUSB_DEV_XHCI_HSFSPI_COUNT8_0_FS_FSM_TIMEOUT_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_COUNT8_0_FS_FSM_TIMEOUT_DEFAULT (_MK_MASK_CONST(0x000000B0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT8_0_FS_FSM_TIMEOUT_DEFAULT_MASK (_MK_MASK_CONST(0x3fffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT8_0_FS_FSM_TIMEOUT_SW_DEFAULT (_MK_MASK_CONST(0x000000B0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT8_0_FS_FSM_TIMEOUT_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3fffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT8_0_FS_FSM_TIMEOUT_INIT  _MK_ENUM_CONST(0x000000B0)


// 


#define XUSB_DEV_XHCI_HSFSPI_COUNT9_0                      _MK_ADDR_CONST(0x00000124)
#define XUSB_DEV_XHCI_HSFSPI_COUNT9_0_SECURE               0
#define XUSB_DEV_XHCI_HSFSPI_COUNT9_0_WORD_COUNT           1
#define XUSB_DEV_XHCI_HSFSPI_COUNT9_0_RESET_VAL            _MK_MASK_CONST(0x124f80)
#define XUSB_DEV_XHCI_HSFSPI_COUNT9_0_RESET_MASK           _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT9_0_SW_DEFAULT_VAL       _MK_MASK_CONST(0x124f80)
#define XUSB_DEV_XHCI_HSFSPI_COUNT9_0_SW_DEFAULT_MASK      _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT9_0_READ_MASK            _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT9_0_WRITE_MASK           _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT9_0_CLEAR_MASK           _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT9_0_TGL_MASK             _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT9_0_U3_RESUME_K_DURATION_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT9_0_U3_RESUME_K_DURATION_FIELD (_MK_SHIFT_CONST(0x3fffffff) << XUSB_DEV_XHCI_HSFSPI_COUNT9_0_U3_RESUME_K_DURATION_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_COUNT9_0_U3_RESUME_K_DURATION_RANGE 29:0
#define XUSB_DEV_XHCI_HSFSPI_COUNT9_0_U3_RESUME_K_DURATION_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_COUNT9_0_U3_RESUME_K_DURATION_DEFAULT (_MK_MASK_CONST(0x00124F80)
#define XUSB_DEV_XHCI_HSFSPI_COUNT9_0_U3_RESUME_K_DURATION_DEFAULT_MASK (_MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT9_0_U3_RESUME_K_DURATION_SW_DEFAULT (_MK_MASK_CONST(0x00124F80)
#define XUSB_DEV_XHCI_HSFSPI_COUNT9_0_U3_RESUME_K_DURATION_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT9_0_U3_RESUME_K_DURATION_INIT _MK_ENUM_CONST(0x00124F80)


// 


#define XUSB_DEV_XHCI_HSFSPI_COUNT10_0                     _MK_ADDR_CONST(0x00000128)
#define XUSB_DEV_XHCI_HSFSPI_COUNT10_0_SECURE              0
#define XUSB_DEV_XHCI_HSFSPI_COUNT10_0_WORD_COUNT          1
#define XUSB_DEV_XHCI_HSFSPI_COUNT10_0_RESET_VAL           _MK_MASK_CONST(0x3a9e)
#define XUSB_DEV_XHCI_HSFSPI_COUNT10_0_RESET_MASK          _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT10_0_SW_DEFAULT_VAL      _MK_MASK_CONST(0x3a9e)
#define XUSB_DEV_XHCI_HSFSPI_COUNT10_0_SW_DEFAULT_MASK     _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT10_0_READ_MASK           _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT10_0_WRITE_MASK          _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT10_0_CLEAR_MASK          _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT10_0_TGL_MASK            _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT10_0_U3_ENTRY_DELAY_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT10_0_U3_ENTRY_DELAY_FIELD (_MK_SHIFT_CONST(0x3fffffff) << XUSB_DEV_XHCI_HSFSPI_COUNT10_0_U3_ENTRY_DELAY_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_COUNT10_0_U3_ENTRY_DELAY_RANGE 29:0
#define XUSB_DEV_XHCI_HSFSPI_COUNT10_0_U3_ENTRY_DELAY_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_COUNT10_0_U3_ENTRY_DELAY_DEFAULT (_MK_MASK_CONST(0x00003A9E)
#define XUSB_DEV_XHCI_HSFSPI_COUNT10_0_U3_ENTRY_DELAY_DEFAULT_MASK (_MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT10_0_U3_ENTRY_DELAY_SW_DEFAULT (_MK_MASK_CONST(0x00003A9E)
#define XUSB_DEV_XHCI_HSFSPI_COUNT10_0_U3_ENTRY_DELAY_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT10_0_U3_ENTRY_DELAY_INIT _MK_ENUM_CONST(0x00003A9E)


// 


#define XUSB_DEV_XHCI_HSFSPI_COUNT11_0                     _MK_ADDR_CONST(0x0000012C)
#define XUSB_DEV_XHCI_HSFSPI_COUNT11_0_SECURE              0
#define XUSB_DEV_XHCI_HSFSPI_COUNT11_0_WORD_COUNT          1
#define XUSB_DEV_XHCI_HSFSPI_COUNT11_0_RESET_VAL           _MK_MASK_CONST(0x1d4ff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT11_0_RESET_MASK          _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT11_0_SW_DEFAULT_VAL      _MK_MASK_CONST(0x1d4ff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT11_0_SW_DEFAULT_MASK     _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT11_0_READ_MASK           _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT11_0_WRITE_MASK          _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT11_0_CLEAR_MASK          _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT11_0_TGL_MASK            _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT11_0_FS_RESET_ST_RESET_MIN_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT11_0_FS_RESET_ST_RESET_MIN_FIELD (_MK_SHIFT_CONST(0x3fffffff) << XUSB_DEV_XHCI_HSFSPI_COUNT11_0_FS_RESET_ST_RESET_MIN_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_COUNT11_0_FS_RESET_ST_RESET_MIN_RANGE 29:0
#define XUSB_DEV_XHCI_HSFSPI_COUNT11_0_FS_RESET_ST_RESET_MIN_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_COUNT11_0_FS_RESET_ST_RESET_MIN_DEFAULT (_MK_MASK_CONST(0x0001D4FF)
#define XUSB_DEV_XHCI_HSFSPI_COUNT11_0_FS_RESET_ST_RESET_MIN_DEFAULT_MASK (_MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT11_0_FS_RESET_ST_RESET_MIN_SW_DEFAULT (_MK_MASK_CONST(0x0001D4FF)
#define XUSB_DEV_XHCI_HSFSPI_COUNT11_0_FS_RESET_ST_RESET_MIN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT11_0_FS_RESET_ST_RESET_MIN_INIT _MK_ENUM_CONST(0x0001D4FF)


// 


#define XUSB_DEV_XHCI_HSFSPI_COUNT12_0                     _MK_ADDR_CONST(0x00000130)
#define XUSB_DEV_XHCI_HSFSPI_COUNT12_0_SECURE              0
#define XUSB_DEV_XHCI_HSFSPI_COUNT12_0_WORD_COUNT          1
#define XUSB_DEV_XHCI_HSFSPI_COUNT12_0_RESET_VAL           _MK_MASK_CONST(0x3d4)
#define XUSB_DEV_XHCI_HSFSPI_COUNT12_0_RESET_MASK          _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT12_0_SW_DEFAULT_VAL      _MK_MASK_CONST(0x3d4)
#define XUSB_DEV_XHCI_HSFSPI_COUNT12_0_SW_DEFAULT_MASK     _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT12_0_READ_MASK           _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT12_0_WRITE_MASK          _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT12_0_CLEAR_MASK          _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT12_0_TGL_MASK            _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT12_0_U2_ENTRY_DELAY_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT12_0_U2_ENTRY_DELAY_FIELD (_MK_SHIFT_CONST(0x3fffffff) << XUSB_DEV_XHCI_HSFSPI_COUNT12_0_U2_ENTRY_DELAY_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_COUNT12_0_U2_ENTRY_DELAY_RANGE 29:0
#define XUSB_DEV_XHCI_HSFSPI_COUNT12_0_U2_ENTRY_DELAY_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_COUNT12_0_U2_ENTRY_DELAY_DEFAULT (_MK_MASK_CONST(0x000003D4)
#define XUSB_DEV_XHCI_HSFSPI_COUNT12_0_U2_ENTRY_DELAY_DEFAULT_MASK (_MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT12_0_U2_ENTRY_DELAY_SW_DEFAULT (_MK_MASK_CONST(0x000003D4)
#define XUSB_DEV_XHCI_HSFSPI_COUNT12_0_U2_ENTRY_DELAY_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT12_0_U2_ENTRY_DELAY_INIT _MK_ENUM_CONST(0x000003D4)


// 


#define XUSB_DEV_XHCI_HSFSPI_COUNT13_0                     _MK_ADDR_CONST(0x00000134)
#define XUSB_DEV_XHCI_HSFSPI_COUNT13_0_SECURE              0
#define XUSB_DEV_XHCI_HSFSPI_COUNT13_0_WORD_COUNT          1
#define XUSB_DEV_XHCI_HSFSPI_COUNT13_0_RESET_VAL           _MK_MASK_CONST(0x1772)
#define XUSB_DEV_XHCI_HSFSPI_COUNT13_0_RESET_MASK          _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT13_0_SW_DEFAULT_VAL      _MK_MASK_CONST(0x1772)
#define XUSB_DEV_XHCI_HSFSPI_COUNT13_0_SW_DEFAULT_MASK     _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT13_0_READ_MASK           _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT13_0_WRITE_MASK          _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT13_0_CLEAR_MASK          _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT13_0_TGL_MASK            _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT13_0_U2_RESUME_K_DURATION_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT13_0_U2_RESUME_K_DURATION_FIELD (_MK_SHIFT_CONST(0x3fffffff) << XUSB_DEV_XHCI_HSFSPI_COUNT13_0_U2_RESUME_K_DURATION_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_COUNT13_0_U2_RESUME_K_DURATION_RANGE 29:0
#define XUSB_DEV_XHCI_HSFSPI_COUNT13_0_U2_RESUME_K_DURATION_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_COUNT13_0_U2_RESUME_K_DURATION_DEFAULT (_MK_MASK_CONST(0x00001772)
#define XUSB_DEV_XHCI_HSFSPI_COUNT13_0_U2_RESUME_K_DURATION_DEFAULT_MASK (_MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT13_0_U2_RESUME_K_DURATION_SW_DEFAULT (_MK_MASK_CONST(0x00001772)
#define XUSB_DEV_XHCI_HSFSPI_COUNT13_0_U2_RESUME_K_DURATION_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT13_0_U2_RESUME_K_DURATION_INIT _MK_ENUM_CONST(0x00001772)
#define XUSB_DEV_XHCI_HSFSPI_COUNT13_0_U2_RESUME_K_DURATION__PROD _MK_ENUM_CONST(0x00002c88)


// 


#define XUSB_DEV_XHCI_HSFSPI_CTRL_0                        _MK_ADDR_CONST(0x00000138)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_SECURE                 0
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_WORD_COUNT             1
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_RESET_VAL              _MK_MASK_CONST(0x7cc00c60)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_RESET_MASK             _MK_MASK_CONST(0x7fffffff)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_SW_DEFAULT_VAL         _MK_MASK_CONST(0x7cc00c60)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_SW_DEFAULT_MASK        _MK_MASK_CONST(0x7fffffff)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_READ_MASK              _MK_MASK_CONST(0x7fffffff)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_WRITE_MASK             _MK_MASK_CONST(0x7fffffff)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_CLEAR_MASK             _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_TGL_MASK               _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_HS_INTERPKT_DELAY_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_HS_INTERPKT_DELAY_FIELD (_MK_SHIFT_CONST(0x3ff) << XUSB_DEV_XHCI_HSFSPI_CTRL_0_HS_INTERPKT_DELAY_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_HS_INTERPKT_DELAY_RANGE 9:0
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_HS_INTERPKT_DELAY_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_HS_INTERPKT_DELAY_DEFAULT (_MK_MASK_CONST(0x00000060)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_HS_INTERPKT_DELAY_DEFAULT_MASK (_MK_MASK_CONST(0x3ff)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_HS_INTERPKT_DELAY_SW_DEFAULT (_MK_MASK_CONST(0x00000060)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_HS_INTERPKT_DELAY_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3ff)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_HS_INTERPKT_DELAY_INIT _MK_ENUM_CONST(0x00000060)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_FS_INTERPKT_DELAY_SHIFT  _MK_SHIFT_CONST(10)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_FS_INTERPKT_DELAY_FIELD (_MK_SHIFT_CONST(0x3ff) << XUSB_DEV_XHCI_HSFSPI_CTRL_0_FS_INTERPKT_DELAY_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_FS_INTERPKT_DELAY_RANGE 19:10
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_FS_INTERPKT_DELAY_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_FS_INTERPKT_DELAY_DEFAULT (_MK_MASK_CONST(0x00000003)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_FS_INTERPKT_DELAY_DEFAULT_MASK (_MK_MASK_CONST(0x3ff)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_FS_INTERPKT_DELAY_SW_DEFAULT (_MK_MASK_CONST(0x00000003)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_FS_INTERPKT_DELAY_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3ff)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_FS_INTERPKT_DELAY_INIT _MK_ENUM_CONST(0x00000003)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_NRZI_DISABLE_SHIFT      _MK_SHIFT_CONST(20)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_NRZI_DISABLE_FIELD     (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_CTRL_0_NRZI_DISABLE_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_NRZI_DISABLE_RANGE     20:20
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_NRZI_DISABLE_WOFFSET   0
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_NRZI_DISABLE_DEFAULT   (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_NRZI_DISABLE_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_NRZI_DISABLE_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_NRZI_DISABLE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_NRZI_DISABLE_INIT      _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_BITSTUFF_DISABLE_SHIFT  _MK_SHIFT_CONST(21)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_BITSTUFF_DISABLE_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_CTRL_0_BITSTUFF_DISABLE_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_BITSTUFF_DISABLE_RANGE 21:21
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_BITSTUFF_DISABLE_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_BITSTUFF_DISABLE_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_BITSTUFF_DISABLE_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_BITSTUFF_DISABLE_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_BITSTUFF_DISABLE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_BITSTUFF_DISABLE_INIT  _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_FS_SE0_WIDTH_SHIFT      _MK_SHIFT_CONST(22)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_FS_SE0_WIDTH_FIELD     (_MK_SHIFT_CONST(0xf) << XUSB_DEV_XHCI_HSFSPI_CTRL_0_FS_SE0_WIDTH_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_FS_SE0_WIDTH_RANGE     25:22
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_FS_SE0_WIDTH_WOFFSET   0
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_FS_SE0_WIDTH_DEFAULT   (_MK_MASK_CONST(0x00000003)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_FS_SE0_WIDTH_DEFAULT_MASK (_MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_FS_SE0_WIDTH_SW_DEFAULT (_MK_MASK_CONST(0x00000003)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_FS_SE0_WIDTH_SW_DEFAULT_MASK (_MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_FS_SE0_WIDTH_INIT      _MK_ENUM_CONST(0x00000003)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_HS_IDLE_BIT_TIME_SHIFT  _MK_SHIFT_CONST(26)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_HS_IDLE_BIT_TIME_FIELD (_MK_SHIFT_CONST(0x1f) << XUSB_DEV_XHCI_HSFSPI_CTRL_0_HS_IDLE_BIT_TIME_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_HS_IDLE_BIT_TIME_RANGE 30:26
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_HS_IDLE_BIT_TIME_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_HS_IDLE_BIT_TIME_DEFAULT (_MK_MASK_CONST(0x0000001F)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_HS_IDLE_BIT_TIME_DEFAULT_MASK (_MK_MASK_CONST(0x1f)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_HS_IDLE_BIT_TIME_SW_DEFAULT (_MK_MASK_CONST(0x0000001F)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_HS_IDLE_BIT_TIME_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1f)
#define XUSB_DEV_XHCI_HSFSPI_CTRL_0_HS_IDLE_BIT_TIME_INIT  _MK_ENUM_CONST(0x0000001F)


// 
// Testmode control register to send specific patterns not defined in spec


#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0               _MK_ADDR_CONST(0x0000013C)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_SECURE        0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_WORD_COUNT    1
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_RESET_VAL     _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_RESET_MASK    _MK_MASK_CONST(0x3)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x3)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_READ_MASK     _MK_MASK_CONST(0x3)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_WRITE_MASK    _MK_MASK_CONST(0x3)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_CLEAR_MASK    _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_TGL_MASK      _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_PATTERN_SELECT_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_PATTERN_SELECT_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_PATTERN_SELECT_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_PATTERN_SELECT_RANGE 0:0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_PATTERN_SELECT_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_PATTERN_SELECT_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_PATTERN_SELECT_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_PATTERN_SELECT_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_PATTERN_SELECT_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_PATTERN_SELECT_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_CYA_ADDR_MATCH_SHIFT  _MK_SHIFT_CONST(1)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_CYA_ADDR_MATCH_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_CYA_ADDR_MATCH_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_CYA_ADDR_MATCH_RANGE 1:1
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_CYA_ADDR_MATCH_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_CYA_ADDR_MATCH_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_CYA_ADDR_MATCH_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_CYA_ADDR_MATCH_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_CYA_ADDR_MATCH_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0_CYA_ADDR_MATCH_INIT _MK_ENUM_CONST(0x00000000)


// 


#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0           _MK_ADDR_CONST(0x00000140)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_SECURE    0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_WORD_COUNT 1
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_RESET_VAL _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_RESET_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_READ_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_WRITE_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_CLEAR_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_TGL_MASK  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE0_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE0_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE0_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE0_RANGE 7:0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE0_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE0_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE0_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE0_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE0_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE0_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE1_SHIFT  _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE1_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE1_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE1_RANGE 15:8
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE1_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE1_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE1_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE1_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE1_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE1_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE2_SHIFT  _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE2_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE2_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE2_RANGE 23:16
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE2_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE2_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE2_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE2_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE2_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE2_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE3_SHIFT  _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE3_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE3_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE3_RANGE 31:24
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE3_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE3_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE3_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE3_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE3_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0_BYTE3_INIT _MK_ENUM_CONST(0x00000000)


// 


#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0           _MK_ADDR_CONST(0x00000144)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_SECURE    0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_WORD_COUNT 1
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_RESET_VAL _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_RESET_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_READ_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_WRITE_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_CLEAR_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_TGL_MASK  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE0_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE0_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE0_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE0_RANGE 7:0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE0_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE0_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE0_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE0_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE0_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE0_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE1_SHIFT  _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE1_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE1_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE1_RANGE 15:8
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE1_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE1_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE1_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE1_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE1_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE1_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE2_SHIFT  _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE2_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE2_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE2_RANGE 23:16
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE2_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE2_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE2_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE2_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE2_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE2_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE3_SHIFT  _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE3_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE3_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE3_RANGE 31:24
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE3_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE3_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE3_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE3_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE3_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0_BYTE3_INIT _MK_ENUM_CONST(0x00000000)


// 


#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0           _MK_ADDR_CONST(0x00000148)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_SECURE    0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_WORD_COUNT 1
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_RESET_VAL _MK_MASK_CONST(0xaaaaaa00)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_RESET_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0xaaaaaa00)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_READ_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_WRITE_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_CLEAR_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_TGL_MASK  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE0_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE0_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE0_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE0_RANGE 7:0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE0_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE0_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE0_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE0_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE0_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE0_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE1_SHIFT  _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE1_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE1_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE1_RANGE 15:8
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE1_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE1_DEFAULT (_MK_MASK_CONST(0x000000AA)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE1_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE1_SW_DEFAULT (_MK_MASK_CONST(0x000000AA)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE1_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE1_INIT _MK_ENUM_CONST(0x000000AA)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE2_SHIFT  _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE2_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE2_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE2_RANGE 23:16
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE2_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE2_DEFAULT (_MK_MASK_CONST(0x000000AA)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE2_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE2_SW_DEFAULT (_MK_MASK_CONST(0x000000AA)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE2_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE2_INIT _MK_ENUM_CONST(0x000000AA)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE3_SHIFT  _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE3_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE3_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE3_RANGE 31:24
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE3_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE3_DEFAULT (_MK_MASK_CONST(0x000000AA)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE3_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE3_SW_DEFAULT (_MK_MASK_CONST(0x000000AA)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE3_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0_BYTE3_INIT _MK_ENUM_CONST(0x000000AA)


// 


#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0           _MK_ADDR_CONST(0x0000014C)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_SECURE    0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_WORD_COUNT 1
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_RESET_VAL _MK_MASK_CONST(0xaaaaaaaa)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_RESET_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0xaaaaaaaa)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_READ_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_WRITE_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_CLEAR_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_TGL_MASK  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE0_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE0_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE0_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE0_RANGE 7:0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE0_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE0_DEFAULT (_MK_MASK_CONST(0x000000AA)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE0_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE0_SW_DEFAULT (_MK_MASK_CONST(0x000000AA)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE0_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE0_INIT _MK_ENUM_CONST(0x000000AA)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE1_SHIFT  _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE1_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE1_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE1_RANGE 15:8
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE1_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE1_DEFAULT (_MK_MASK_CONST(0x000000AA)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE1_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE1_SW_DEFAULT (_MK_MASK_CONST(0x000000AA)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE1_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE1_INIT _MK_ENUM_CONST(0x000000AA)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE2_SHIFT  _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE2_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE2_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE2_RANGE 23:16
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE2_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE2_DEFAULT (_MK_MASK_CONST(0x000000AA)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE2_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE2_SW_DEFAULT (_MK_MASK_CONST(0x000000AA)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE2_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE2_INIT _MK_ENUM_CONST(0x000000AA)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE3_SHIFT  _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE3_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE3_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE3_RANGE 31:24
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE3_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE3_DEFAULT (_MK_MASK_CONST(0x000000AA)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE3_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE3_SW_DEFAULT (_MK_MASK_CONST(0x000000AA)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE3_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0_BYTE3_INIT _MK_ENUM_CONST(0x000000AA)


// 


#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0           _MK_ADDR_CONST(0x00000150)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_SECURE    0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_WORD_COUNT 1
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_RESET_VAL _MK_MASK_CONST(0xeeeeeeaa)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_RESET_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_SW_DEFAULT_VAL _MK_MASK_CONST(0xeeeeeeaa)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_READ_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_WRITE_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_CLEAR_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_TGL_MASK  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE0_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE0_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE0_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE0_RANGE 7:0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE0_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE0_DEFAULT (_MK_MASK_CONST(0x000000AA)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE0_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE0_SW_DEFAULT (_MK_MASK_CONST(0x000000AA)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE0_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE0_INIT _MK_ENUM_CONST(0x000000AA)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE1_SHIFT  _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE1_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE1_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE1_RANGE 15:8
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE1_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE1_DEFAULT (_MK_MASK_CONST(0x000000EE)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE1_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE1_SW_DEFAULT (_MK_MASK_CONST(0x000000EE)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE1_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE1_INIT _MK_ENUM_CONST(0x000000EE)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE2_SHIFT  _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE2_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE2_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE2_RANGE 23:16
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE2_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE2_DEFAULT (_MK_MASK_CONST(0x000000EE)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE2_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE2_SW_DEFAULT (_MK_MASK_CONST(0x000000EE)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE2_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE2_INIT _MK_ENUM_CONST(0x000000EE)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE3_SHIFT  _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE3_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE3_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE3_RANGE 31:24
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE3_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE3_DEFAULT (_MK_MASK_CONST(0x000000EE)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE3_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE3_SW_DEFAULT (_MK_MASK_CONST(0x000000EE)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE3_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0_BYTE3_INIT _MK_ENUM_CONST(0x000000EE)


// 


#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0           _MK_ADDR_CONST(0x00000154)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_SECURE    0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_WORD_COUNT 1
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_RESET_VAL _MK_MASK_CONST(0xeeeeeeee)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_RESET_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_SW_DEFAULT_VAL _MK_MASK_CONST(0xeeeeeeee)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_READ_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_WRITE_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_CLEAR_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_TGL_MASK  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE0_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE0_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE0_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE0_RANGE 7:0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE0_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE0_DEFAULT (_MK_MASK_CONST(0x000000EE)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE0_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE0_SW_DEFAULT (_MK_MASK_CONST(0x000000EE)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE0_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE0_INIT _MK_ENUM_CONST(0x000000EE)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE1_SHIFT  _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE1_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE1_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE1_RANGE 15:8
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE1_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE1_DEFAULT (_MK_MASK_CONST(0x000000EE)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE1_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE1_SW_DEFAULT (_MK_MASK_CONST(0x000000EE)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE1_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE1_INIT _MK_ENUM_CONST(0x000000EE)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE2_SHIFT  _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE2_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE2_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE2_RANGE 23:16
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE2_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE2_DEFAULT (_MK_MASK_CONST(0x000000EE)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE2_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE2_SW_DEFAULT (_MK_MASK_CONST(0x000000EE)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE2_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE2_INIT _MK_ENUM_CONST(0x000000EE)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE3_SHIFT  _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE3_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE3_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE3_RANGE 31:24
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE3_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE3_DEFAULT (_MK_MASK_CONST(0x000000EE)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE3_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE3_SW_DEFAULT (_MK_MASK_CONST(0x000000EE)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE3_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0_BYTE3_INIT _MK_ENUM_CONST(0x000000EE)


// 


#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0           _MK_ADDR_CONST(0x00000158)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_SECURE    0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_WORD_COUNT 1
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_RESET_VAL _MK_MASK_CONST(0xfffffeee)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_RESET_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_SW_DEFAULT_VAL _MK_MASK_CONST(0xfffffeee)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_READ_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_WRITE_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_CLEAR_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_TGL_MASK  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE0_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE0_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE0_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE0_RANGE 7:0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE0_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE0_DEFAULT (_MK_MASK_CONST(0x000000EE)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE0_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE0_SW_DEFAULT (_MK_MASK_CONST(0x000000EE)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE0_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE0_INIT _MK_ENUM_CONST(0x000000EE)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE1_SHIFT  _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE1_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE1_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE1_RANGE 15:8
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE1_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE1_DEFAULT (_MK_MASK_CONST(0x000000FE)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE1_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE1_SW_DEFAULT (_MK_MASK_CONST(0x000000FE)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE1_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE1_INIT _MK_ENUM_CONST(0x000000FE)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE2_SHIFT  _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE2_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE2_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE2_RANGE 23:16
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE2_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE2_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE2_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE2_SW_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE2_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE2_INIT _MK_ENUM_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE3_SHIFT  _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE3_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE3_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE3_RANGE 31:24
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE3_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE3_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE3_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE3_SW_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE3_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0_BYTE3_INIT _MK_ENUM_CONST(0x000000FF)


// 


#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0           _MK_ADDR_CONST(0x0000015C)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_SECURE    0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_WORD_COUNT 1
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_RESET_VAL _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_RESET_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_SW_DEFAULT_VAL _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_READ_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_WRITE_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_CLEAR_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_TGL_MASK  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE0_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE0_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE0_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE0_RANGE 7:0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE0_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE0_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE0_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE0_SW_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE0_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE0_INIT _MK_ENUM_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE1_SHIFT  _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE1_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE1_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE1_RANGE 15:8
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE1_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE1_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE1_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE1_SW_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE1_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE1_INIT _MK_ENUM_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE2_SHIFT  _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE2_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE2_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE2_RANGE 23:16
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE2_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE2_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE2_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE2_SW_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE2_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE2_INIT _MK_ENUM_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE3_SHIFT  _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE3_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE3_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE3_RANGE 31:24
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE3_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE3_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE3_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE3_SW_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE3_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0_BYTE3_INIT _MK_ENUM_CONST(0x000000FF)


// 


#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0           _MK_ADDR_CONST(0x00000160)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_SECURE    0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_WORD_COUNT 1
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_RESET_VAL _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_RESET_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_SW_DEFAULT_VAL _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_READ_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_WRITE_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_CLEAR_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_TGL_MASK  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE0_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE0_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE0_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE0_RANGE 7:0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE0_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE0_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE0_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE0_SW_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE0_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE0_INIT _MK_ENUM_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE1_SHIFT  _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE1_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE1_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE1_RANGE 15:8
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE1_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE1_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE1_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE1_SW_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE1_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE1_INIT _MK_ENUM_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE2_SHIFT  _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE2_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE2_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE2_RANGE 23:16
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE2_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE2_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE2_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE2_SW_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE2_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE2_INIT _MK_ENUM_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE3_SHIFT  _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE3_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE3_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE3_RANGE 31:24
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE3_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE3_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE3_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE3_SW_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE3_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0_BYTE3_INIT _MK_ENUM_CONST(0x000000FF)


// 


#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0           _MK_ADDR_CONST(0x00000164)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_SECURE    0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_WORD_COUNT 1
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_RESET_VAL _MK_MASK_CONST(0xdfbf7fff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_RESET_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_SW_DEFAULT_VAL _MK_MASK_CONST(0xdfbf7fff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_READ_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_WRITE_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_CLEAR_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_TGL_MASK  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE0_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE0_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE0_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE0_RANGE 7:0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE0_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE0_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE0_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE0_SW_DEFAULT (_MK_MASK_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE0_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE0_INIT _MK_ENUM_CONST(0x000000FF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE1_SHIFT  _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE1_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE1_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE1_RANGE 15:8
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE1_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE1_DEFAULT (_MK_MASK_CONST(0x0000007F)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE1_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE1_SW_DEFAULT (_MK_MASK_CONST(0x0000007F)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE1_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE1_INIT _MK_ENUM_CONST(0x0000007F)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE2_SHIFT  _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE2_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE2_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE2_RANGE 23:16
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE2_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE2_DEFAULT (_MK_MASK_CONST(0x000000BF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE2_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE2_SW_DEFAULT (_MK_MASK_CONST(0x000000BF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE2_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE2_INIT _MK_ENUM_CONST(0x000000BF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE3_SHIFT  _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE3_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE3_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE3_RANGE 31:24
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE3_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE3_DEFAULT (_MK_MASK_CONST(0x000000DF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE3_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE3_SW_DEFAULT (_MK_MASK_CONST(0x000000DF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE3_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0_BYTE3_INIT _MK_ENUM_CONST(0x000000DF)


// 


#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0          _MK_ADDR_CONST(0x00000168)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_SECURE   0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_WORD_COUNT 1
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_RESET_VAL _MK_MASK_CONST(0xfdfbf7ef)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_RESET_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_SW_DEFAULT_VAL _MK_MASK_CONST(0xfdfbf7ef)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_READ_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_WRITE_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_CLEAR_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_TGL_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE0_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE0_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE0_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE0_RANGE 7:0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE0_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE0_DEFAULT (_MK_MASK_CONST(0x000000EF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE0_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE0_SW_DEFAULT (_MK_MASK_CONST(0x000000EF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE0_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE0_INIT _MK_ENUM_CONST(0x000000EF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE1_SHIFT  _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE1_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE1_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE1_RANGE 15:8
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE1_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE1_DEFAULT (_MK_MASK_CONST(0x000000F7)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE1_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE1_SW_DEFAULT (_MK_MASK_CONST(0x000000F7)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE1_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE1_INIT _MK_ENUM_CONST(0x000000F7)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE2_SHIFT  _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE2_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE2_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE2_RANGE 23:16
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE2_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE2_DEFAULT (_MK_MASK_CONST(0x000000FB)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE2_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE2_SW_DEFAULT (_MK_MASK_CONST(0x000000FB)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE2_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE2_INIT _MK_ENUM_CONST(0x000000FB)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE3_SHIFT  _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE3_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE3_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE3_RANGE 31:24
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE3_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE3_DEFAULT (_MK_MASK_CONST(0x000000FD)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE3_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE3_SW_DEFAULT (_MK_MASK_CONST(0x000000FD)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE3_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0_BYTE3_INIT _MK_ENUM_CONST(0x000000FD)


// 


#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0          _MK_ADDR_CONST(0x0000016C)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_SECURE   0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_WORD_COUNT 1
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_RESET_VAL _MK_MASK_CONST(0xdfbf7efc)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_RESET_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_SW_DEFAULT_VAL _MK_MASK_CONST(0xdfbf7efc)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_READ_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_WRITE_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_CLEAR_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_TGL_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE0_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE0_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE0_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE0_RANGE 7:0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE0_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE0_DEFAULT (_MK_MASK_CONST(0x000000FC)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE0_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE0_SW_DEFAULT (_MK_MASK_CONST(0x000000FC)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE0_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE0_INIT _MK_ENUM_CONST(0x000000FC)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE1_SHIFT  _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE1_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE1_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE1_RANGE 15:8
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE1_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE1_DEFAULT (_MK_MASK_CONST(0x0000007E)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE1_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE1_SW_DEFAULT (_MK_MASK_CONST(0x0000007E)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE1_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE1_INIT _MK_ENUM_CONST(0x0000007E)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE2_SHIFT  _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE2_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE2_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE2_RANGE 23:16
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE2_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE2_DEFAULT (_MK_MASK_CONST(0x000000BF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE2_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE2_SW_DEFAULT (_MK_MASK_CONST(0x000000BF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE2_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE2_INIT _MK_ENUM_CONST(0x000000BF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE3_SHIFT  _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE3_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE3_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE3_RANGE 31:24
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE3_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE3_DEFAULT (_MK_MASK_CONST(0x000000DF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE3_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE3_SW_DEFAULT (_MK_MASK_CONST(0x000000DF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE3_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0_BYTE3_INIT _MK_ENUM_CONST(0x000000DF)


// 


#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0          _MK_ADDR_CONST(0x00000170)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_SECURE   0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_WORD_COUNT 1
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_RESET_VAL _MK_MASK_CONST(0xfdfbf7ef)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_RESET_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_SW_DEFAULT_VAL _MK_MASK_CONST(0xfdfbf7ef)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_READ_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_WRITE_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_CLEAR_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_TGL_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE0_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE0_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE0_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE0_RANGE 7:0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE0_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE0_DEFAULT (_MK_MASK_CONST(0x000000EF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE0_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE0_SW_DEFAULT (_MK_MASK_CONST(0x000000EF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE0_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE0_INIT _MK_ENUM_CONST(0x000000EF)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE1_SHIFT  _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE1_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE1_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE1_RANGE 15:8
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE1_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE1_DEFAULT (_MK_MASK_CONST(0x000000F7)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE1_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE1_SW_DEFAULT (_MK_MASK_CONST(0x000000F7)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE1_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE1_INIT _MK_ENUM_CONST(0x000000F7)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE2_SHIFT  _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE2_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE2_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE2_RANGE 23:16
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE2_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE2_DEFAULT (_MK_MASK_CONST(0x000000FB)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE2_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE2_SW_DEFAULT (_MK_MASK_CONST(0x000000FB)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE2_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE2_INIT _MK_ENUM_CONST(0x000000FB)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE3_SHIFT  _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE3_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE3_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE3_RANGE 31:24
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE3_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE3_DEFAULT (_MK_MASK_CONST(0x000000FD)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE3_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE3_SW_DEFAULT (_MK_MASK_CONST(0x000000FD)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE3_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0_BYTE3_INIT _MK_ENUM_CONST(0x000000FD)


// 


#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0          _MK_ADDR_CONST(0x00000174)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_SECURE   0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_WORD_COUNT 1
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_RESET_VAL _MK_MASK_CONST(0x7f7f7f7e)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_RESET_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x7f7f7f7e)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_READ_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_WRITE_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_CLEAR_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_TGL_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE0_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE0_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE0_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE0_RANGE 7:0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE0_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE0_DEFAULT (_MK_MASK_CONST(0x0000007E)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE0_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE0_SW_DEFAULT (_MK_MASK_CONST(0x0000007E)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE0_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE0_INIT _MK_ENUM_CONST(0x0000007E)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE1_SHIFT  _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE1_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE1_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE1_RANGE 15:8
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE1_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE1_DEFAULT (_MK_MASK_CONST(0x0000007F)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE1_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE1_SW_DEFAULT (_MK_MASK_CONST(0x0000007F)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE1_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE1_INIT _MK_ENUM_CONST(0x0000007F)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE2_SHIFT  _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE2_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE2_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE2_RANGE 23:16
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE2_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE2_DEFAULT (_MK_MASK_CONST(0x0000007F)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE2_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE2_SW_DEFAULT (_MK_MASK_CONST(0x0000007F)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE2_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE2_INIT _MK_ENUM_CONST(0x0000007F)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE3_SHIFT  _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE3_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE3_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE3_RANGE 31:24
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE3_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE3_DEFAULT (_MK_MASK_CONST(0x0000007F)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE3_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE3_SW_DEFAULT (_MK_MASK_CONST(0x0000007F)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE3_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0_BYTE3_INIT _MK_ENUM_CONST(0x0000007F)


// 


#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0          _MK_ADDR_CONST(0x00000178)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_SECURE   0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_WORD_COUNT 1
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_RESET_VAL _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_RESET_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_READ_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_WRITE_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_CLEAR_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_TGL_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE0_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE0_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE0_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE0_RANGE 7:0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE0_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE0_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE0_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE0_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE0_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE0_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE1_SHIFT  _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE1_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE1_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE1_RANGE 15:8
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE1_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE1_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE1_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE1_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE1_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE1_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE2_SHIFT  _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE2_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE2_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE2_RANGE 23:16
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE2_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE2_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE2_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE2_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE2_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE2_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE3_SHIFT  _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE3_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE3_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE3_RANGE 31:24
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE3_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE3_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE3_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE3_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE3_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0_BYTE3_INIT _MK_ENUM_CONST(0x00000000)


// 


#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0          _MK_ADDR_CONST(0x0000017C)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_SECURE   0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_WORD_COUNT 1
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_RESET_VAL _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_RESET_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_READ_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_WRITE_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_CLEAR_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_TGL_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE0_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE0_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE0_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE0_RANGE 7:0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE0_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE0_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE0_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE0_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE0_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE0_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE1_SHIFT  _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE1_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE1_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE1_RANGE 15:8
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE1_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE1_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE1_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE1_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE1_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE1_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE2_SHIFT  _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE2_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE2_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE2_RANGE 23:16
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE2_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE2_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE2_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE2_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE2_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE2_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE3_SHIFT  _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE3_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE3_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE3_RANGE 31:24
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE3_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE3_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE3_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE3_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE3_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0_BYTE3_INIT _MK_ENUM_CONST(0x00000000)


// 
// Registers for helping in debug of PSM state transitions


#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0             _MK_ADDR_CONST(0x00000180)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_SECURE      0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_WORD_COUNT  1
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_RESET_VAL   _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_RESET_MASK  _MK_MASK_CONST(0xffff03)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffff03)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_READ_MASK   _MK_MASK_CONST(0xffff03)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_WRITE_MASK  _MK_MASK_CONST(0xffff03)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_CLEAR_MASK  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_TGL_MASK    _MK_MASK_CONST(0x2)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_RUN_SHIFT    _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_RUN_FIELD   (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_RUN_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_RUN_RANGE   0:0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_RUN_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_RUN_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_RUN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_RUN_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_RUN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_RUN_STOP    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_RUN_RUN     _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_CLEAR_SHIFT  _MK_SHIFT_CONST(1)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_CLEAR_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_CLEAR_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_CLEAR_RANGE 1:1
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_CLEAR_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_CLEAR_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_CLEAR_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_CLEAR_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_CLEAR_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_CLEAR_NOT_PENDING _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_CLEAR_PENDING _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_CLEAR_TRIGGER _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_START_MAJOR_SHIFT  _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_START_MAJOR_FIELD (_MK_SHIFT_CONST(0xf) << XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_START_MAJOR_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_START_MAJOR_RANGE 11:8
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_START_MAJOR_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_START_MAJOR_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_START_MAJOR_DEFAULT_MASK (_MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_START_MAJOR_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_START_MAJOR_SW_DEFAULT_MASK (_MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_START_MAJOR_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_START_MINOR_SHIFT  _MK_SHIFT_CONST(12)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_START_MINOR_FIELD (_MK_SHIFT_CONST(0xf) << XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_START_MINOR_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_START_MINOR_RANGE 15:12
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_START_MINOR_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_START_MINOR_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_START_MINOR_DEFAULT_MASK (_MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_START_MINOR_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_START_MINOR_SW_DEFAULT_MASK (_MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_START_MINOR_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_END_MAJOR_SHIFT  _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_END_MAJOR_FIELD (_MK_SHIFT_CONST(0xf) << XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_END_MAJOR_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_END_MAJOR_RANGE 19:16
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_END_MAJOR_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_END_MAJOR_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_END_MAJOR_DEFAULT_MASK (_MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_END_MAJOR_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_END_MAJOR_SW_DEFAULT_MASK (_MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_END_MAJOR_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_END_MINOR_SHIFT  _MK_SHIFT_CONST(20)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_END_MINOR_FIELD (_MK_SHIFT_CONST(0xf) << XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_END_MINOR_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_END_MINOR_RANGE 23:20
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_END_MINOR_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_END_MINOR_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_END_MINOR_DEFAULT_MASK (_MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_END_MINOR_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_END_MINOR_SW_DEFAULT_MASK (_MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0_END_MINOR_INIT _MK_ENUM_CONST(0x00000000)


// 


#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0              _MK_ADDR_CONST(0x00000184)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_SECURE       0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_WORD_COUNT   1
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_RESET_VAL    _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_RESET_MASK   _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_READ_MASK    _MK_MASK_CONST(0xfffff)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_WRITE_MASK   _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_CLEAR_MASK   _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_TGL_MASK     _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_START_NONE_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_START_NONE_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_START_NONE_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_START_NONE_RANGE 0:0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_START_NONE_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_DISCONNECTED_NONE_SHIFT  _MK_SHIFT_CONST(1)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_DISCONNECTED_NONE_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_DISCONNECTED_NONE_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_DISCONNECTED_NONE_RANGE 1:1
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_DISCONNECTED_NONE_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_DISABLED_NONE_SHIFT  _MK_SHIFT_CONST(2)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_DISABLED_NONE_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_DISABLED_NONE_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_DISABLED_NONE_RANGE 2:2
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_DISABLED_NONE_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_RESET_HS_TXCHIRPK_SHIFT  _MK_SHIFT_CONST(3)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_RESET_HS_TXCHIRPK_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_RESET_HS_TXCHIRPK_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_RESET_HS_TXCHIRPK_RANGE 3:3
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_RESET_HS_TXCHIRPK_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_RESET_HS_RXCHIRPK_SHIFT  _MK_SHIFT_CONST(4)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_RESET_HS_RXCHIRPK_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_RESET_HS_RXCHIRPK_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_RESET_HS_RXCHIRPK_RANGE 4:4
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_RESET_HS_RXCHIRPK_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_RESET_HS_RXCHIRPJ_SHIFT  _MK_SHIFT_CONST(5)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_RESET_HS_RXCHIRPJ_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_RESET_HS_RXCHIRPJ_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_RESET_HS_RXCHIRPJ_RANGE 5:5
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_RESET_HS_RXCHIRPJ_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_RESET_FS_SHIFT  _MK_SHIFT_CONST(6)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_RESET_FS_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_RESET_FS_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_RESET_FS_RANGE 6:6
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_RESET_FS_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_RESET_HS_PROLOG_SHIFT  _MK_SHIFT_CONST(7)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_RESET_HS_PROLOG_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_RESET_HS_PROLOG_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_RESET_HS_PROLOG_RANGE 7:7
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_RESET_HS_PROLOG_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_HS_U0_SHIFT  _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_HS_U0_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_HS_U0_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_HS_U0_RANGE 8:8
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_HS_U0_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_HS_U2_SHIFT  _MK_SHIFT_CONST(9)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_HS_U2_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_HS_U2_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_HS_U2_RANGE 9:9
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_HS_U2_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_HS_U3_SHIFT  _MK_SHIFT_CONST(10)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_HS_U3_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_HS_U3_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_HS_U3_RANGE 10:10
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_HS_U3_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_HS_RESUME_SHIFT  _MK_SHIFT_CONST(11)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_HS_RESUME_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_HS_RESUME_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_HS_RESUME_RANGE 11:11
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_HS_RESUME_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_FS_U0_SHIFT  _MK_SHIFT_CONST(12)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_FS_U0_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_FS_U0_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_FS_U0_RANGE 12:12
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_FS_U0_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_FS_U2_SHIFT  _MK_SHIFT_CONST(13)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_FS_U2_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_FS_U2_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_FS_U2_RANGE 13:13
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_FS_U2_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_FS_U3_SHIFT  _MK_SHIFT_CONST(14)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_FS_U3_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_FS_U3_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_FS_U3_RANGE 14:14
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_FS_U3_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_FS_RESUME_SHIFT  _MK_SHIFT_CONST(15)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_FS_RESUME_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_FS_RESUME_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_FS_RESUME_RANGE 15:15
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_ENABLED_FS_RESUME_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_TESTMODE_HS_JSTATE_SHIFT  _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_TESTMODE_HS_JSTATE_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_TESTMODE_HS_JSTATE_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_TESTMODE_HS_JSTATE_RANGE 16:16
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_TESTMODE_HS_JSTATE_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_TESTMODE_HS_KSTATE_SHIFT  _MK_SHIFT_CONST(17)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_TESTMODE_HS_KSTATE_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_TESTMODE_HS_KSTATE_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_TESTMODE_HS_KSTATE_RANGE 17:17
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_TESTMODE_HS_KSTATE_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_TESTMODE_HS_NAK_SHIFT  _MK_SHIFT_CONST(18)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_TESTMODE_HS_NAK_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_TESTMODE_HS_NAK_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_TESTMODE_HS_NAK_RANGE 18:18
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_TESTMODE_HS_NAK_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_TESTMODE_HS_PKT_SHIFT  _MK_SHIFT_CONST(19)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_TESTMODE_HS_PKT_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_TESTMODE_HS_PKT_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_TESTMODE_HS_PKT_RANGE 19:19
#define XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0_TESTMODE_HS_PKT_WOFFSET 0


// 


#define XUSB_DEV_XHCI_HSFSPI_COUNT14_0                     _MK_ADDR_CONST(0x0000018C)
#define XUSB_DEV_XHCI_HSFSPI_COUNT14_0_SECURE              0
#define XUSB_DEV_XHCI_HSFSPI_COUNT14_0_WORD_COUNT          1
#define XUSB_DEV_XHCI_HSFSPI_COUNT14_0_RESET_VAL           _MK_MASK_CONST(0x40)
#define XUSB_DEV_XHCI_HSFSPI_COUNT14_0_RESET_MASK          _MK_MASK_CONST(0x3fffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT14_0_SW_DEFAULT_VAL      _MK_MASK_CONST(0x40)
#define XUSB_DEV_XHCI_HSFSPI_COUNT14_0_SW_DEFAULT_MASK     _MK_MASK_CONST(0x3fffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT14_0_READ_MASK           _MK_MASK_CONST(0x3fffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT14_0_WRITE_MASK          _MK_MASK_CONST(0x3fffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT14_0_CLEAR_MASK          _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT14_0_TGL_MASK            _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT14_0_HS_ISO_FSM_TIMEOUT_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT14_0_HS_ISO_FSM_TIMEOUT_FIELD (_MK_SHIFT_CONST(0x3fffff) << XUSB_DEV_XHCI_HSFSPI_COUNT14_0_HS_ISO_FSM_TIMEOUT_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_COUNT14_0_HS_ISO_FSM_TIMEOUT_RANGE 21:0
#define XUSB_DEV_XHCI_HSFSPI_COUNT14_0_HS_ISO_FSM_TIMEOUT_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_COUNT14_0_HS_ISO_FSM_TIMEOUT_DEFAULT (_MK_MASK_CONST(0x00000040)
#define XUSB_DEV_XHCI_HSFSPI_COUNT14_0_HS_ISO_FSM_TIMEOUT_DEFAULT_MASK (_MK_MASK_CONST(0x3fffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT14_0_HS_ISO_FSM_TIMEOUT_SW_DEFAULT (_MK_MASK_CONST(0x00000040)
#define XUSB_DEV_XHCI_HSFSPI_COUNT14_0_HS_ISO_FSM_TIMEOUT_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3fffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT14_0_HS_ISO_FSM_TIMEOUT_INIT _MK_ENUM_CONST(0x00000040)


// 


#define XUSB_DEV_XHCI_HSFSPI_COUNT15_0                     _MK_ADDR_CONST(0x00000190)
#define XUSB_DEV_XHCI_HSFSPI_COUNT15_0_SECURE              0
#define XUSB_DEV_XHCI_HSFSPI_COUNT15_0_WORD_COUNT          1
#define XUSB_DEV_XHCI_HSFSPI_COUNT15_0_RESET_VAL           _MK_MASK_CONST(0xb0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT15_0_RESET_MASK          _MK_MASK_CONST(0x3fffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT15_0_SW_DEFAULT_VAL      _MK_MASK_CONST(0xb0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT15_0_SW_DEFAULT_MASK     _MK_MASK_CONST(0x3fffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT15_0_READ_MASK           _MK_MASK_CONST(0x3fffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT15_0_WRITE_MASK          _MK_MASK_CONST(0x3fffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT15_0_CLEAR_MASK          _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT15_0_TGL_MASK            _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT15_0_FS_ISO_FSM_TIMEOUT_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT15_0_FS_ISO_FSM_TIMEOUT_FIELD (_MK_SHIFT_CONST(0x3fffff) << XUSB_DEV_XHCI_HSFSPI_COUNT15_0_FS_ISO_FSM_TIMEOUT_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_COUNT15_0_FS_ISO_FSM_TIMEOUT_RANGE 21:0
#define XUSB_DEV_XHCI_HSFSPI_COUNT15_0_FS_ISO_FSM_TIMEOUT_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_COUNT15_0_FS_ISO_FSM_TIMEOUT_DEFAULT (_MK_MASK_CONST(0x000000B0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT15_0_FS_ISO_FSM_TIMEOUT_DEFAULT_MASK (_MK_MASK_CONST(0x3fffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT15_0_FS_ISO_FSM_TIMEOUT_SW_DEFAULT (_MK_MASK_CONST(0x000000B0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT15_0_FS_ISO_FSM_TIMEOUT_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3fffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT15_0_FS_ISO_FSM_TIMEOUT_INIT _MK_ENUM_CONST(0x000000B0)


// 


#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0                _MK_ADDR_CONST(0x00000194)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_SECURE         0
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_WORD_COUNT     1
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_RESET_VAL      _MK_MASK_CONST(0x1568c03)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_RESET_MASK     _MK_MASK_CONST(0x1ffffff)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x1568c03)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x1ffffff)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_READ_MASK      _MK_MASK_CONST(0x1ffffff)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_WRITE_MASK     _MK_MASK_CONST(0x1ffffff)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_CLEAR_MASK     _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_TGL_MASK       _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_MCP_MODE_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_MCP_MODE_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_MCP_MODE_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_MCP_MODE_RANGE 0:0
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_MCP_MODE_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_MCP_MODE_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_MCP_MODE_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_MCP_MODE_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_MCP_MODE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_MCP_MODE_INIT  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_T210_A02_MODE_SHIFT  _MK_SHIFT_CONST(1)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_T210_A02_MODE_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_T210_A02_MODE_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_T210_A02_MODE_RANGE 1:1
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_T210_A02_MODE_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_T210_A02_MODE_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_T210_A02_MODE_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_T210_A02_MODE_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_T210_A02_MODE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_T210_A02_MODE_INIT _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USE4SYNCTRANCFG_SHIFT  _MK_SHIFT_CONST(2)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USE4SYNCTRANCFG_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USE4SYNCTRANCFG_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USE4SYNCTRANCFG_RANGE 2:2
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USE4SYNCTRANCFG_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USE4SYNCTRANCFG_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USE4SYNCTRANCFG_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USE4SYNCTRANCFG_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USE4SYNCTRANCFG_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USE4SYNCTRANCFG_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_THREESYNCBITSCFG_SHIFT  _MK_SHIFT_CONST(3)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_THREESYNCBITSCFG_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_THREESYNCBITSCFG_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_THREESYNCBITSCFG_RANGE 3:3
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_THREESYNCBITSCFG_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_THREESYNCBITSCFG_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_THREESYNCBITSCFG_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_THREESYNCBITSCFG_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_THREESYNCBITSCFG_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_THREESYNCBITSCFG_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PHASEADJUSTCFG_SHIFT  _MK_SHIFT_CONST(4)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PHASEADJUSTCFG_FIELD (_MK_SHIFT_CONST(0x3) << XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PHASEADJUSTCFG_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PHASEADJUSTCFG_RANGE 5:4
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PHASEADJUSTCFG_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PHASEADJUSTCFG_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PHASEADJUSTCFG_DEFAULT_MASK (_MK_MASK_CONST(0x3)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PHASEADJUSTCFG_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PHASEADJUSTCFG_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PHASEADJUSTCFG_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PCOUNTINERTIACFG_SHIFT  _MK_SHIFT_CONST(6)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PCOUNTINERTIACFG_FIELD (_MK_SHIFT_CONST(0x3) << XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PCOUNTINERTIACFG_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PCOUNTINERTIACFG_RANGE 7:6
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PCOUNTINERTIACFG_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PCOUNTINERTIACFG_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PCOUNTINERTIACFG_DEFAULT_MASK (_MK_MASK_CONST(0x3)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PCOUNTINERTIACFG_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PCOUNTINERTIACFG_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PCOUNTINERTIACFG_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PASSFEEDBACKCFG_SHIFT  _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PASSFEEDBACKCFG_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PASSFEEDBACKCFG_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PASSFEEDBACKCFG_RANGE 8:8
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PASSFEEDBACKCFG_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PASSFEEDBACKCFG_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PASSFEEDBACKCFG_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PASSFEEDBACKCFG_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PASSFEEDBACKCFG_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PASSFEEDBACKCFG_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PASSCHIRPCFG_SHIFT  _MK_SHIFT_CONST(9)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PASSCHIRPCFG_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PASSCHIRPCFG_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PASSCHIRPCFG_RANGE 9:9
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PASSCHIRPCFG_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PASSCHIRPCFG_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PASSCHIRPCFG_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PASSCHIRPCFG_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PASSCHIRPCFG_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PASSCHIRPCFG_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_SQUELCHEOPDELAYCFG_SHIFT  _MK_SHIFT_CONST(10)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_SQUELCHEOPDELAYCFG_FIELD (_MK_SHIFT_CONST(0x7) << XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_SQUELCHEOPDELAYCFG_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_SQUELCHEOPDELAYCFG_RANGE 12:10
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_SQUELCHEOPDELAYCFG_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_SQUELCHEOPDELAYCFG_DEFAULT (_MK_MASK_CONST(0x00000003)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_SQUELCHEOPDELAYCFG_DEFAULT_MASK (_MK_MASK_CONST(0x7)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_SQUELCHEOPDELAYCFG_SW_DEFAULT (_MK_MASK_CONST(0x00000003)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_SQUELCHEOPDELAYCFG_SW_DEFAULT_MASK (_MK_MASK_CONST(0x7)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_SQUELCHEOPDELAYCFG_INIT _MK_ENUM_CONST(0x00000003)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PCOUNTUPDOWNDIVCFG_SHIFT  _MK_SHIFT_CONST(13)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PCOUNTUPDOWNDIVCFG_FIELD (_MK_SHIFT_CONST(0xf) << XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PCOUNTUPDOWNDIVCFG_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PCOUNTUPDOWNDIVCFG_RANGE 16:13
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PCOUNTUPDOWNDIVCFG_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PCOUNTUPDOWNDIVCFG_DEFAULT (_MK_MASK_CONST(0x00000004)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PCOUNTUPDOWNDIVCFG_DEFAULT_MASK (_MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PCOUNTUPDOWNDIVCFG_SW_DEFAULT (_MK_MASK_CONST(0x00000004)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PCOUNTUPDOWNDIVCFG_SW_DEFAULT_MASK (_MK_MASK_CONST(0xf)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_PCOUNTUPDOWNDIVCFG_INIT _MK_ENUM_CONST(0x00000004)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_REALIGNONNEWPACKETCFG_SHIFT  _MK_SHIFT_CONST(17)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_REALIGNONNEWPACKETCFG_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_REALIGNONNEWPACKETCFG_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_REALIGNONNEWPACKETCFG_RANGE 17:17
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_REALIGNONNEWPACKETCFG_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_REALIGNONNEWPACKETCFG_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_REALIGNONNEWPACKETCFG_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_REALIGNONNEWPACKETCFG_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_REALIGNONNEWPACKETCFG_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_REALIGNONNEWPACKETCFG_INIT _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_ALLOWCONSECUTIVEUPDOWNCFG_SHIFT  _MK_SHIFT_CONST(18)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_ALLOWCONSECUTIVEUPDOWNCFG_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_ALLOWCONSECUTIVEUPDOWNCFG_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_ALLOWCONSECUTIVEUPDOWNCFG_RANGE 18:18
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_ALLOWCONSECUTIVEUPDOWNCFG_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_ALLOWCONSECUTIVEUPDOWNCFG_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_ALLOWCONSECUTIVEUPDOWNCFG_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_ALLOWCONSECUTIVEUPDOWNCFG_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_ALLOWCONSECUTIVEUPDOWNCFG_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_ALLOWCONSECUTIVEUPDOWNCFG_INIT _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_KEEPPATTERNONACTIVECFG_SHIFT  _MK_SHIFT_CONST(19)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_KEEPPATTERNONACTIVECFG_FIELD (_MK_SHIFT_CONST(0x3) << XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_KEEPPATTERNONACTIVECFG_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_KEEPPATTERNONACTIVECFG_RANGE 20:19
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_KEEPPATTERNONACTIVECFG_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_KEEPPATTERNONACTIVECFG_DEFAULT (_MK_MASK_CONST(0x00000002)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_KEEPPATTERNONACTIVECFG_DEFAULT_MASK (_MK_MASK_CONST(0x3)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_KEEPPATTERNONACTIVECFG_SW_DEFAULT (_MK_MASK_CONST(0x00000002)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_KEEPPATTERNONACTIVECFG_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_KEEPPATTERNONACTIVECFG_INIT _MK_ENUM_CONST(0x00000002)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_HSRXLATESQUELCHCFG_SHIFT  _MK_SHIFT_CONST(21)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_HSRXLATESQUELCHCFG_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_HSRXLATESQUELCHCFG_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_HSRXLATESQUELCHCFG_RANGE 21:21
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_HSRXLATESQUELCHCFG_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_HSRXLATESQUELCHCFG_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_HSRXLATESQUELCHCFG_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_HSRXLATESQUELCHCFG_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_HSRXLATESQUELCHCFG_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_HSRXLATESQUELCHCFG_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USEWEIGHTEDEDGESCFG_SHIFT  _MK_SHIFT_CONST(22)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USEWEIGHTEDEDGESCFG_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USEWEIGHTEDEDGESCFG_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USEWEIGHTEDEDGESCFG_RANGE 22:22
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USEWEIGHTEDEDGESCFG_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USEWEIGHTEDEDGESCFG_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USEWEIGHTEDEDGESCFG_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USEWEIGHTEDEDGESCFG_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USEWEIGHTEDEDGESCFG_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USEWEIGHTEDEDGESCFG_INIT _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_THREECYCLEEDGEDETCFG_SHIFT  _MK_SHIFT_CONST(23)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_THREECYCLEEDGEDETCFG_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_THREECYCLEEDGEDETCFG_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_THREECYCLEEDGEDETCFG_RANGE 23:23
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_THREECYCLEEDGEDETCFG_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_THREECYCLEEDGEDETCFG_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_THREECYCLEEDGEDETCFG_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_THREECYCLEEDGEDETCFG_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_THREECYCLEEDGEDETCFG_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_THREECYCLEEDGEDETCFG_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USECOMMONUPDNCNT_SHIFT  _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USECOMMONUPDNCNT_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USECOMMONUPDNCNT_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USECOMMONUPDNCNT_RANGE 24:24
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USECOMMONUPDNCNT_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USECOMMONUPDNCNT_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USECOMMONUPDNCNT_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USECOMMONUPDNCNT_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USECOMMONUPDNCNT_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0_USECOMMONUPDNCNT_INIT _MK_ENUM_CONST(0x00000001)


// 


#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0                       _MK_ADDR_CONST(0x00000198)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_SECURE                0
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_WORD_COUNT            1
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_RESET_VAL             _MK_MASK_CONST(0x11310)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_RESET_MASK            _MK_MASK_CONST(0x13fff)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_SW_DEFAULT_VAL        _MK_MASK_CONST(0x11310)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_SW_DEFAULT_MASK       _MK_MASK_CONST(0x13fff)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_READ_MASK             _MK_MASK_CONST(0x13fff)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_WRITE_MASK            _MK_MASK_CONST(0x13fff)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_CLEAR_MASK            _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_TGL_MASK              _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_BABBLE_TIMEOUT_VAL_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_BABBLE_TIMEOUT_VAL_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_HSFSPI_CTRL1_0_BABBLE_TIMEOUT_VAL_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_BABBLE_TIMEOUT_VAL_RANGE 7:0
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_BABBLE_TIMEOUT_VAL_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_BABBLE_TIMEOUT_VAL_DEFAULT (_MK_MASK_CONST(0x00000010)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_BABBLE_TIMEOUT_VAL_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_BABBLE_TIMEOUT_VAL_SW_DEFAULT (_MK_MASK_CONST(0x00000010)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_BABBLE_TIMEOUT_VAL_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_BABBLE_TIMEOUT_VAL_INIT _MK_ENUM_CONST(0x00000010)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_BABBLE_TIMEOUT_CYA_SHIFT  _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_BABBLE_TIMEOUT_CYA_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_CTRL1_0_BABBLE_TIMEOUT_CYA_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_BABBLE_TIMEOUT_CYA_RANGE 8:8
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_BABBLE_TIMEOUT_CYA_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_BABBLE_TIMEOUT_CYA_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_BABBLE_TIMEOUT_CYA_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_BABBLE_TIMEOUT_CYA_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_BABBLE_TIMEOUT_CYA_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_BABBLE_TIMEOUT_CYA_INIT _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_FS_IDLE_BITTIMES_SHIFT  _MK_SHIFT_CONST(9)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_FS_IDLE_BITTIMES_FIELD (_MK_SHIFT_CONST(0x1f) << XUSB_DEV_XHCI_HSFSPI_CTRL1_0_FS_IDLE_BITTIMES_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_FS_IDLE_BITTIMES_RANGE 13:9
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_FS_IDLE_BITTIMES_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_FS_IDLE_BITTIMES_DEFAULT (_MK_MASK_CONST(0x00000009)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_FS_IDLE_BITTIMES_DEFAULT_MASK (_MK_MASK_CONST(0x1f)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_FS_IDLE_BITTIMES_SW_DEFAULT (_MK_MASK_CONST(0x00000009)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_FS_IDLE_BITTIMES_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1f)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_FS_IDLE_BITTIMES_INIT _MK_ENUM_CONST(0x00000009)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_FILTERED_BUS_IDLE_SHIFT  _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_FILTERED_BUS_IDLE_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_HSFSPI_CTRL1_0_FILTERED_BUS_IDLE_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_FILTERED_BUS_IDLE_RANGE 16:16
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_FILTERED_BUS_IDLE_WOFFSET 0
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_FILTERED_BUS_IDLE_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_FILTERED_BUS_IDLE_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_FILTERED_BUS_IDLE_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_FILTERED_BUS_IDLE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_HSFSPI_CTRL1_0_FILTERED_BUS_IDLE_INIT _MK_ENUM_CONST(0x00000001)


// 
// 


#define XUSB_DEV_XHCI_HSFSPI_COUNT16_0                     _MK_ADDR_CONST(0x0000019C)
#define XUSB_DEV_XHCI_HSFSPI_COUNT16_0_SECURE              0
#define XUSB_DEV_XHCI_HSFSPI_COUNT16_0_WORD_COUNT          1
#define XUSB_DEV_XHCI_HSFSPI_COUNT16_0_RESET_VAL           _MK_MASK_CONST(0x927c0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT16_0_RESET_MASK          _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT16_0_SW_DEFAULT_VAL      _MK_MASK_CONST(0x927c0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT16_0_SW_DEFAULT_MASK     _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT16_0_READ_MASK           _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT16_0_WRITE_MASK          _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT16_0_CLEAR_MASK          _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT16_0_TGL_MASK            _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT16_0_CHIRP_FAIL_SHIFT     _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT16_0_CHIRP_FAIL_FIELD    (_MK_SHIFT_CONST(0x3fffffff) << XUSB_DEV_XHCI_HSFSPI_COUNT16_0_CHIRP_FAIL_SHIFT)
#define XUSB_DEV_XHCI_HSFSPI_COUNT16_0_CHIRP_FAIL_RANGE    29:0
#define XUSB_DEV_XHCI_HSFSPI_COUNT16_0_CHIRP_FAIL_WOFFSET  0
#define XUSB_DEV_XHCI_HSFSPI_COUNT16_0_CHIRP_FAIL_DEFAULT  (_MK_MASK_CONST(0x000927C0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT16_0_CHIRP_FAIL_DEFAULT_MASK (_MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT16_0_CHIRP_FAIL_SW_DEFAULT (_MK_MASK_CONST(0x000927C0)
#define XUSB_DEV_XHCI_HSFSPI_COUNT16_0_CHIRP_FAIL_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_HSFSPI_COUNT16_0_CHIRP_FAIL_INIT     _MK_ENUM_CONST(0x000927C0)


// 
// // Reserve 0x600-0x800 for SSPX CORE registers from Host Mode PCI Config space


#define XUSB_DEV_XHCI_SSPI_HOSTCFG_START_0                 _MK_ADDR_CONST(0x00000600)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_START_0_SECURE          0
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_START_0_WORD_COUNT      1
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_START_0_RESET_VAL       _MK_MASK_CONST(0x1000)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_START_0_RESET_MASK      _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_START_0_SW_DEFAULT_VAL  _MK_MASK_CONST(0x1000)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_START_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_START_0_READ_MASK       _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_START_0_WRITE_MASK      _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_START_0_CLEAR_MASK      _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_START_0_TGL_MASK        _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_START_0_FIELD_SHIFT      _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_START_0_FIELD_FIELD     (_MK_SHIFT_CONST(0xffffffff) << XUSB_DEV_XHCI_SSPI_HOSTCFG_START_0_FIELD_SHIFT)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_START_0_FIELD_RANGE     31:0
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_START_0_FIELD_WOFFSET   0
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_START_0_FIELD_DEFAULT   (_MK_MASK_CONST(0x00001000)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_START_0_FIELD_DEFAULT_MASK (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_START_0_FIELD_SW_DEFAULT (_MK_MASK_CONST(0x00001000)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_START_0_FIELD_SW_DEFAULT_MASK (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_START_0_FIELD_VALUE     _MK_ENUM_CONST(0x00001000)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_SSPI_HOSTCFG_START__PRODCHK                    0 /*       */
// 


#define XUSB_DEV_XHCI_SSPI_HOSTCFG_END_0                   _MK_ADDR_CONST(0x000007FC)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_END_0_SECURE            0
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_END_0_WORD_COUNT        1
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_END_0_RESET_VAL         _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_END_0_RESET_MASK        _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_END_0_SW_DEFAULT_VAL    _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_END_0_SW_DEFAULT_MASK   _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_END_0_READ_MASK         _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_END_0_WRITE_MASK        _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_END_0_CLEAR_MASK        _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_END_0_TGL_MASK          _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_END_0_FIELD_SHIFT        _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_END_0_FIELD_FIELD       (_MK_SHIFT_CONST(0xffffffff) << XUSB_DEV_XHCI_SSPI_HOSTCFG_END_0_FIELD_SHIFT)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_END_0_FIELD_RANGE       31:0
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_END_0_FIELD_WOFFSET     0
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_END_0_FIELD_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_END_0_FIELD_DEFAULT_MASK (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_END_0_FIELD_SW_DEFAULT  (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_END_0_FIELD_SW_DEFAULT_MASK (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_SSPI_HOSTCFG_END_0_FIELD_VALUE       _MK_ENUM_CONST(0x00000000)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_SSPI_HOSTCFG_END__PRODCHK                      0 /*       */
// 
// //*****************************************************************************************************
// //*****************************************************************************************************
// 


#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0       _MK_ADDR_CONST(0x00000800)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_SECURE 0
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_WORD_COUNT 1
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_RESET_VAL _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_RESET_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_READ_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_WRITE_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_CLEAR_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_TGL_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_CYCLESHI_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_CYCLESHI_FIELD (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_CYCLESHI_SHIFT)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_CYCLESHI_RANGE 15:0
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_CYCLESHI_WOFFSET 0
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_CYCLESHI_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_CYCLESHI_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_CYCLESHI_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_CYCLESHI_SW_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_CYCLESHI_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_PKTS_SHIFT  _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_PKTS_FIELD (_MK_SHIFT_CONST(0x7fff) << XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_PKTS_SHIFT)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_PKTS_RANGE 30:16
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_PKTS_WOFFSET 0
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_PKTS_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_PKTS_DEFAULT_MASK (_MK_MASK_CONST(0x7fff)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_PKTS_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_PKTS_SW_DEFAULT_MASK (_MK_MASK_CONST(0x7fff)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_PKTS_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_EN_SHIFT  _MK_SHIFT_CONST(31)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_EN_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_EN_SHIFT)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_EN_RANGE 31:31
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_EN_WOFFSET 0
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_EN_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_EN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_EN_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_EN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0_EN_INIT _MK_ENUM_CONST(0x00000000)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0__PRODCHK                          0 /*       */
// 


#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG1_0       _MK_ADDR_CONST(0x00000804)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG1_0_SECURE 0
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG1_0_WORD_COUNT 1
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG1_0_RESET_VAL _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG1_0_RESET_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG1_0_READ_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG1_0_WRITE_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG1_0_CLEAR_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG1_0_TGL_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG1_0_CYCLESLO_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG1_0_CYCLESLO_FIELD (_MK_SHIFT_CONST(0xffffffff) << XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG1_0_CYCLESLO_SHIFT)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG1_0_CYCLESLO_RANGE 31:0
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG1_0_CYCLESLO_WOFFSET 0
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG1_0_CYCLESLO_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG1_0_CYCLESLO_DEFAULT_MASK (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG1_0_CYCLESLO_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG1_0_CYCLESLO_SW_DEFAULT_MASK (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG1_0_CYCLESLO_INIT _MK_ENUM_CONST(0x00000000)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG1__PRODCHK                          0 /*       */
// 


#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0               _MK_ADDR_CONST(0x00000808)
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_SECURE        0
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_WORD_COUNT    1
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_RESET_VAL     _MK_MASK_CONST(0x14)
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_RESET_MASK    _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x14)
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_READ_MASK     _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_WRITE_MASK    _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_CLEAR_MASK    _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_TGL_MASK      _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_MAXCYCLES_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_MAXCYCLES_FIELD (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_MAXCYCLES_SHIFT)
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_MAXCYCLES_RANGE 15:0
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_MAXCYCLES_WOFFSET 0
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_MAXCYCLES_DEFAULT (_MK_MASK_CONST(0x00000014)
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_MAXCYCLES_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_MAXCYCLES_SW_DEFAULT (_MK_MASK_CONST(0x00000014)
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_MAXCYCLES_SW_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_MAXCYCLES_INIT _MK_ENUM_CONST(0x00000014)
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_MINCYCLES_SHIFT  _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_MINCYCLES_FIELD (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_MINCYCLES_SHIFT)
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_MINCYCLES_RANGE 31:16
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_MINCYCLES_WOFFSET 0
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_MINCYCLES_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_MINCYCLES_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_MINCYCLES_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_MINCYCLES_SW_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0_MINCYCLES_INIT _MK_ENUM_CONST(0x00000000)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_PERFMON_READ_LATENCY__PRODCHK                              0 /*       */
// 
// 
// BOUNDARY_D > BOUNDARY_C > BOUNDARY_B > BOUNDARY_A should be followed, else undefined results are expected
// 


#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0 _MK_ADDR_CONST(0x0000080C)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_SECURE 0
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_WORD_COUNT 1
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_RESET_VAL _MK_MASK_CONST(0x14)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_RESET_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x14)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_READ_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_WRITE_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_CLEAR_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_TGL_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_A_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_A_FIELD (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_A_SHIFT)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_A_RANGE 15:0
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_A_WOFFSET 0
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_A_DEFAULT (_MK_MASK_CONST(0x00000014)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_A_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_A_SW_DEFAULT (_MK_MASK_CONST(0x00000014)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_A_SW_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_A_INIT _MK_ENUM_CONST(0x00000014)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_B_SHIFT  _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_B_FIELD (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_B_SHIFT)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_B_RANGE 31:16
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_B_WOFFSET 0
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_B_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_B_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_B_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_B_SW_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0_B_INIT _MK_ENUM_CONST(0x00000000)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0__PRODCHK                    0 /*       */
// 


#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0 _MK_ADDR_CONST(0x00000810)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_SECURE 0
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_WORD_COUNT 1
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_RESET_VAL _MK_MASK_CONST(0x14)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_RESET_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x14)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_READ_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_WRITE_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_CLEAR_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_TGL_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_C_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_C_FIELD (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_C_SHIFT)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_C_RANGE 15:0
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_C_WOFFSET 0
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_C_DEFAULT (_MK_MASK_CONST(0x00000014)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_C_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_C_SW_DEFAULT (_MK_MASK_CONST(0x00000014)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_C_SW_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_C_INIT _MK_ENUM_CONST(0x00000014)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_D_SHIFT  _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_D_FIELD (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_D_SHIFT)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_D_RANGE 31:16
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_D_WOFFSET 0
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_D_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_D_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_D_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_D_SW_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0_D_INIT _MK_ENUM_CONST(0x00000000)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1__PRODCHK                    0 /*       */
// 
// These registers are updated continously if enabled


#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0 _MK_ADDR_CONST(0x00000814)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_SECURE 0
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_WORD_COUNT 1
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_RESET_VAL _MK_MASK_CONST(0x14)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_RESET_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x14)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_READ_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_WRITE_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_CLEAR_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_TGL_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_0_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_0_FIELD (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_0_SHIFT)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_0_RANGE 15:0
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_0_WOFFSET 0
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_0_DEFAULT (_MK_MASK_CONST(0x00000014)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_0_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_0_SW_DEFAULT (_MK_MASK_CONST(0x00000014)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_0_SW_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_0_INIT _MK_ENUM_CONST(0x00000014)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_1_SHIFT  _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_1_FIELD (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_1_SHIFT)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_1_RANGE 31:16
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_1_WOFFSET 0
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_1_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_1_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_1_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_1_SW_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0_1_INIT _MK_ENUM_CONST(0x00000000)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0__PRODCHK                    0 /*       */
// 


#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0 _MK_ADDR_CONST(0x00000818)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_SECURE 0
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_WORD_COUNT 1
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_RESET_VAL _MK_MASK_CONST(0x14)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_RESET_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x14)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_READ_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_WRITE_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_CLEAR_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_TGL_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_2_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_2_FIELD (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_2_SHIFT)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_2_RANGE 15:0
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_2_WOFFSET 0
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_2_DEFAULT (_MK_MASK_CONST(0x00000014)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_2_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_2_SW_DEFAULT (_MK_MASK_CONST(0x00000014)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_2_SW_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_2_INIT _MK_ENUM_CONST(0x00000014)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_3_SHIFT  _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_3_FIELD (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_3_SHIFT)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_3_RANGE 31:16
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_3_WOFFSET 0
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_3_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_3_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_3_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_3_SW_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0_3_INIT _MK_ENUM_CONST(0x00000000)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1__PRODCHK                    0 /*       */
// 


#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG2_0 _MK_ADDR_CONST(0x0000081C)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG2_0_SECURE 0
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG2_0_WORD_COUNT 1
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG2_0_RESET_VAL _MK_MASK_CONST(0x14)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG2_0_RESET_MASK _MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x14)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG2_0_READ_MASK _MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG2_0_WRITE_MASK _MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG2_0_CLEAR_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG2_0_TGL_MASK _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG2_0_4_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG2_0_4_FIELD (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG2_0_4_SHIFT)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG2_0_4_RANGE 15:0
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG2_0_4_WOFFSET 0
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG2_0_4_DEFAULT (_MK_MASK_CONST(0x00000014)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG2_0_4_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG2_0_4_SW_DEFAULT (_MK_MASK_CONST(0x00000014)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG2_0_4_SW_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG2_0_4_INIT _MK_ENUM_CONST(0x00000014)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG2__PRODCHK                    0 /*       */
// 
// Following Status registers are updated at every uframe boundary ( Frame boundary for FS) when enabled.
// 


#define XUSB_DEV_XHCI_PERFMON_BI_CTRL_0                    _MK_ADDR_CONST(0x00000820)
#define XUSB_DEV_XHCI_PERFMON_BI_CTRL_0_SECURE             0
#define XUSB_DEV_XHCI_PERFMON_BI_CTRL_0_WORD_COUNT         1
#define XUSB_DEV_XHCI_PERFMON_BI_CTRL_0_RESET_VAL          _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_BI_CTRL_0_RESET_MASK         _MK_MASK_CONST(0x80000000)
#define XUSB_DEV_XHCI_PERFMON_BI_CTRL_0_SW_DEFAULT_VAL     _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_BI_CTRL_0_SW_DEFAULT_MASK    _MK_MASK_CONST(0x80000000)
#define XUSB_DEV_XHCI_PERFMON_BI_CTRL_0_READ_MASK          _MK_MASK_CONST(0x80000000)
#define XUSB_DEV_XHCI_PERFMON_BI_CTRL_0_WRITE_MASK         _MK_MASK_CONST(0x80000000)
#define XUSB_DEV_XHCI_PERFMON_BI_CTRL_0_CLEAR_MASK         _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_BI_CTRL_0_TGL_MASK           _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_BI_CTRL_0_EN_SHIFT            _MK_SHIFT_CONST(31)
#define XUSB_DEV_XHCI_PERFMON_BI_CTRL_0_EN_FIELD           (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_PERFMON_BI_CTRL_0_EN_SHIFT)
#define XUSB_DEV_XHCI_PERFMON_BI_CTRL_0_EN_RANGE           31:31
#define XUSB_DEV_XHCI_PERFMON_BI_CTRL_0_EN_WOFFSET         0
#define XUSB_DEV_XHCI_PERFMON_BI_CTRL_0_EN_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_BI_CTRL_0_EN_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PERFMON_BI_CTRL_0_EN_SW_DEFAULT      (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_BI_CTRL_0_EN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_PERFMON_BI_CTRL_0_EN_INIT            _MK_ENUM_CONST(0x00000000)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_PERFMON_BI_CTRL__PRODCHK                           0 /*       */
// 
// Number of requests for EP/TRB made per uframe
// 


#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0                   _MK_ADDR_CONST(0x00000824)
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_SECURE            0
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_WORD_COUNT        1
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_RESET_VAL         _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_RESET_MASK        _MK_MASK_CONST(0x1ffff00)
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_SW_DEFAULT_VAL    _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_SW_DEFAULT_MASK   _MK_MASK_CONST(0x1ffff00)
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_READ_MASK         _MK_MASK_CONST(0x1ffff00)
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_WRITE_MASK        _MK_MASK_CONST(0x1ffff00)
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_CLEAR_MASK        _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_TGL_MASK          _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_EPSYSMEM_SHIFT     _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_EPSYSMEM_FIELD    (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_EPSYSMEM_SHIFT)
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_EPSYSMEM_RANGE    15:8
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_EPSYSMEM_WOFFSET  0
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_EPSYSMEM_DEFAULT  (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_EPSYSMEM_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_EPSYSMEM_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_EPSYSMEM_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_EPSYSMEM_INIT     _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_TRB_SHIFT          _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_TRB_FIELD         (_MK_SHIFT_CONST(0x1ff) << XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_TRB_SHIFT)
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_TRB_RANGE         24:16
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_TRB_WOFFSET       0
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_TRB_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_TRB_DEFAULT_MASK  (_MK_MASK_CONST(0x1ff)
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_TRB_SW_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_TRB_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1ff)
#define XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0_TRB_INIT          _MK_ENUM_CONST(0x00000000)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_PERFMON_BI_EPTRB__PRODCHK                           0 /*       */
// 


#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0                _MK_ADDR_CONST(0x00000828)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_SECURE         0
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_WORD_COUNT     1
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_RESET_VAL      _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_RESET_MASK     _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_READ_MASK      _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_WRITE_MASK     _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_CLEAR_MASK     _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_TGL_MASK       _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_SIZE_SHIFT      _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_SIZE_FIELD     (_MK_SHIFT_CONST(0xffffff) << XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_SIZE_SHIFT)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_SIZE_RANGE     23:0
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_SIZE_WOFFSET   0
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_SIZE_DEFAULT   (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_SIZE_DEFAULT_MASK (_MK_MASK_CONST(0xffffff)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_SIZE_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_SIZE_SW_DEFAULT_MASK (_MK_MASK_CONST(0xffffff)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_SIZE_INIT      _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_REQCOUNT_SHIFT  _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_REQCOUNT_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_REQCOUNT_SHIFT)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_REQCOUNT_RANGE 31:24
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_REQCOUNT_WOFFSET 0
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_REQCOUNT_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_REQCOUNT_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_REQCOUNT_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_REQCOUNT_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0_REQCOUNT_INIT  _MK_ENUM_CONST(0x00000000)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT__PRODCHK                           0 /*       */
// 


#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0                 _MK_ADDR_CONST(0x0000082C)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_SECURE          0
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_WORD_COUNT      1
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_RESET_VAL       _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_RESET_MASK      _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_SW_DEFAULT_VAL  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_READ_MASK       _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_WRITE_MASK      _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_CLEAR_MASK      _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_TGL_MASK        _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_SIZE_SHIFT       _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_SIZE_FIELD      (_MK_SHIFT_CONST(0xffffff) << XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_SIZE_SHIFT)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_SIZE_RANGE      23:0
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_SIZE_WOFFSET    0
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_SIZE_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_SIZE_DEFAULT_MASK (_MK_MASK_CONST(0xffffff)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_SIZE_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_SIZE_SW_DEFAULT_MASK (_MK_MASK_CONST(0xffffff)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_SIZE_INIT       _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_REQCOUNT_SHIFT   _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_REQCOUNT_FIELD  (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_REQCOUNT_SHIFT)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_REQCOUNT_RANGE  31:24
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_REQCOUNT_WOFFSET 0
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_REQCOUNT_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_REQCOUNT_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_REQCOUNT_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_REQCOUNT_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0_REQCOUNT_INIT   _MK_ENUM_CONST(0x00000000)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_PERFMON_BI_DATA_IN__PRODCHK                            0 /*       */
// 
// //*****************************************************************************************************
// //*****************************************************************************************************
// 
// // Clock gating control status register


#define XUSB_DEV_XHCI_BLCG_0                               _MK_ADDR_CONST(0x00000840)
#define XUSB_DEV_XHCI_BLCG_0_SECURE                        0
#define XUSB_DEV_XHCI_BLCG_0_WORD_COUNT                    1
#define XUSB_DEV_XHCI_BLCG_0_RESET_VAL                     _MK_MASK_CONST(0x7ffd)
#define XUSB_DEV_XHCI_BLCG_0_RESET_MASK                    _MK_MASK_CONST(0x7ffd7ffd)
#define XUSB_DEV_XHCI_BLCG_0_SW_DEFAULT_VAL                _MK_MASK_CONST(0x7ffd)
#define XUSB_DEV_XHCI_BLCG_0_SW_DEFAULT_MASK               _MK_MASK_CONST(0x7ffd7ffd)
#define XUSB_DEV_XHCI_BLCG_0_READ_MASK                     _MK_MASK_CONST(0x7ffd7ffd)
#define XUSB_DEV_XHCI_BLCG_0_WRITE_MASK                    _MK_MASK_CONST(0x7ffd7ffd)
#define XUSB_DEV_XHCI_BLCG_0_CLEAR_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_BLCG_0_TGL_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_BLCG_0_AXIAPB_SHIFT                   _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_BLCG_0_AXIAPB_FIELD                  (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_AXIAPB_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_AXIAPB_RANGE                  0:0
#define XUSB_DEV_XHCI_BLCG_0_AXIAPB_WOFFSET                0
#define XUSB_DEV_XHCI_BLCG_0_AXIAPB_DEFAULT                (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_AXIAPB_DEFAULT_MASK           (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_AXIAPB_SW_DEFAULT             (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_AXIAPB_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_AXIAPB_DISABLED               _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_AXIAPB_ENABLED                _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_FE_SHIFT                       _MK_SHIFT_CONST(2)
#define XUSB_DEV_XHCI_BLCG_0_FE_FIELD                      (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_FE_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_FE_RANGE                      2:2
#define XUSB_DEV_XHCI_BLCG_0_FE_WOFFSET                    0
#define XUSB_DEV_XHCI_BLCG_0_FE_DEFAULT                    (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_FE_DEFAULT_MASK               (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_FE_SW_DEFAULT                 (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_FE_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_FE_DISABLED                   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_FE_ENABLED                    _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_CORE_BI_SHIFT                  _MK_SHIFT_CONST(3)
#define XUSB_DEV_XHCI_BLCG_0_CORE_BI_FIELD                 (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_CORE_BI_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_CORE_BI_RANGE                 3:3
#define XUSB_DEV_XHCI_BLCG_0_CORE_BI_WOFFSET               0
#define XUSB_DEV_XHCI_BLCG_0_CORE_BI_DEFAULT               (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_CORE_BI_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_CORE_BI_SW_DEFAULT            (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_CORE_BI_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_CORE_BI_DISABLED              _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_CORE_BI_ENABLED               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_PICLK_BI_SHIFT                 _MK_SHIFT_CONST(4)
#define XUSB_DEV_XHCI_BLCG_0_PICLK_BI_FIELD                (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_PICLK_BI_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_PICLK_BI_RANGE                4:4
#define XUSB_DEV_XHCI_BLCG_0_PICLK_BI_WOFFSET              0
#define XUSB_DEV_XHCI_BLCG_0_PICLK_BI_DEFAULT              (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_PICLK_BI_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_PICLK_BI_SW_DEFAULT           (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_PICLK_BI_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_PICLK_BI_DISABLED             _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_PICLK_BI_ENABLED              _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_HSFS_PI_SHIFT                  _MK_SHIFT_CONST(5)
#define XUSB_DEV_XHCI_BLCG_0_HSFS_PI_FIELD                 (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_HSFS_PI_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_HSFS_PI_RANGE                 5:5
#define XUSB_DEV_XHCI_BLCG_0_HSFS_PI_WOFFSET               0
#define XUSB_DEV_XHCI_BLCG_0_HSFS_PI_DEFAULT               (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_HSFS_PI_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_HSFS_PI_SW_DEFAULT            (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_HSFS_PI_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_HSFS_PI_DISABLED              _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_HSFS_PI_ENABLED               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_NVWRAP_480M_SHIFT              _MK_SHIFT_CONST(6)
#define XUSB_DEV_XHCI_BLCG_0_NVWRAP_480M_FIELD             (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_NVWRAP_480M_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_NVWRAP_480M_RANGE             6:6
#define XUSB_DEV_XHCI_BLCG_0_NVWRAP_480M_WOFFSET           0
#define XUSB_DEV_XHCI_BLCG_0_NVWRAP_480M_DEFAULT           (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_NVWRAP_480M_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_NVWRAP_480M_SW_DEFAULT        (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_NVWRAP_480M_SW_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_NVWRAP_480M_DISABLED          _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_NVWRAP_480M_ENABLED           _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_NVWRAP_48M_SHIFT               _MK_SHIFT_CONST(7)
#define XUSB_DEV_XHCI_BLCG_0_NVWRAP_48M_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_NVWRAP_48M_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_NVWRAP_48M_RANGE              7:7
#define XUSB_DEV_XHCI_BLCG_0_NVWRAP_48M_WOFFSET            0
#define XUSB_DEV_XHCI_BLCG_0_NVWRAP_48M_DEFAULT            (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_NVWRAP_48M_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_NVWRAP_48M_SW_DEFAULT         (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_NVWRAP_48M_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_NVWRAP_48M_DISABLED           _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_NVWRAP_48M_ENABLED            _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_COREPLL_PWRDN_SHIFT            _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_BLCG_0_COREPLL_PWRDN_FIELD           (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_COREPLL_PWRDN_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_COREPLL_PWRDN_RANGE           8:8
#define XUSB_DEV_XHCI_BLCG_0_COREPLL_PWRDN_WOFFSET         0
#define XUSB_DEV_XHCI_BLCG_0_COREPLL_PWRDN_DEFAULT         (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_COREPLL_PWRDN_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_COREPLL_PWRDN_SW_DEFAULT      (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_COREPLL_PWRDN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_COREPLL_PWRDN__PROD           _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_COREPLL_PWRDN_DISABLED        _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_COREPLL_PWRDN_ENABLED         _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_0_PWRDN_SHIFT            _MK_SHIFT_CONST(9)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_0_PWRDN_FIELD           (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_IOPLL_0_PWRDN_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_0_PWRDN_RANGE           9:9
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_0_PWRDN_WOFFSET         0
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_0_PWRDN_DEFAULT         (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_0_PWRDN_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_0_PWRDN_SW_DEFAULT      (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_0_PWRDN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_0_PWRDN_DISABLED        _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_0_PWRDN_ENABLED         _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_1_PWRDN_SHIFT            _MK_SHIFT_CONST(10)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_1_PWRDN_FIELD           (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_IOPLL_1_PWRDN_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_1_PWRDN_RANGE           10:10
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_1_PWRDN_WOFFSET         0
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_1_PWRDN_DEFAULT         (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_1_PWRDN_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_1_PWRDN_SW_DEFAULT      (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_1_PWRDN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_1_PWRDN_DISABLED        _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_1_PWRDN_ENABLED         _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_2_PWRDN_SHIFT            _MK_SHIFT_CONST(11)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_2_PWRDN_FIELD           (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_IOPLL_2_PWRDN_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_2_PWRDN_RANGE           11:11
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_2_PWRDN_WOFFSET         0
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_2_PWRDN_DEFAULT         (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_2_PWRDN_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_2_PWRDN_SW_DEFAULT      (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_2_PWRDN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_2_PWRDN_DISABLED        _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_2_PWRDN_ENABLED         _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_3_PWRDN_SHIFT            _MK_SHIFT_CONST(12)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_3_PWRDN_FIELD           (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_IOPLL_3_PWRDN_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_3_PWRDN_RANGE           12:12
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_3_PWRDN_WOFFSET         0
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_3_PWRDN_DEFAULT         (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_3_PWRDN_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_3_PWRDN_SW_DEFAULT      (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_3_PWRDN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_3_PWRDN_DISABLED        _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_IOPLL_3_PWRDN_ENABLED         _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_SS_PI_SHIFT                    _MK_SHIFT_CONST(13)
#define XUSB_DEV_XHCI_BLCG_0_SS_PI_FIELD                   (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_SS_PI_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_SS_PI_RANGE                   13:13
#define XUSB_DEV_XHCI_BLCG_0_SS_PI_WOFFSET                 0
#define XUSB_DEV_XHCI_BLCG_0_SS_PI_DEFAULT                 (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_SS_PI_DEFAULT_MASK            (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_SS_PI_SW_DEFAULT              (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_SS_PI_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_SS_PI_DISABLED                _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_SS_PI_ENABLED                 _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_SS_PI_500M_SHIFT               _MK_SHIFT_CONST(14)
#define XUSB_DEV_XHCI_BLCG_0_SS_PI_500M_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_SS_PI_500M_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_SS_PI_500M_RANGE              14:14
#define XUSB_DEV_XHCI_BLCG_0_SS_PI_500M_WOFFSET            0
#define XUSB_DEV_XHCI_BLCG_0_SS_PI_500M_DEFAULT            (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_SS_PI_500M_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_SS_PI_500M_SW_DEFAULT         (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_SS_PI_500M_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_SS_PI_500M_DISABLED           _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_SS_PI_500M_ENABLED            _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_AXIAPB_SHIFT              _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_AXIAPB_FIELD             (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_OVRD_AXIAPB_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_AXIAPB_RANGE             16:16
#define XUSB_DEV_XHCI_BLCG_0_OVRD_AXIAPB_WOFFSET           0
#define XUSB_DEV_XHCI_BLCG_0_OVRD_AXIAPB_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_AXIAPB_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_AXIAPB_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_AXIAPB_SW_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_AXIAPB_DISABLED          _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_AXIAPB_ENABLED           _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_FE_SHIFT                  _MK_SHIFT_CONST(18)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_FE_FIELD                 (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_OVRD_FE_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_FE_RANGE                 18:18
#define XUSB_DEV_XHCI_BLCG_0_OVRD_FE_WOFFSET               0
#define XUSB_DEV_XHCI_BLCG_0_OVRD_FE_DEFAULT               (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_FE_DEFAULT_MASK          (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_FE_SW_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_FE_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_FE_DISABLED              _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_FE_ENABLED               _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_CORE_BI_SHIFT             _MK_SHIFT_CONST(19)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_CORE_BI_FIELD            (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_OVRD_CORE_BI_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_CORE_BI_RANGE            19:19
#define XUSB_DEV_XHCI_BLCG_0_OVRD_CORE_BI_WOFFSET          0
#define XUSB_DEV_XHCI_BLCG_0_OVRD_CORE_BI_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_CORE_BI_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_CORE_BI_SW_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_CORE_BI_SW_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_CORE_BI_DISABLED         _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_CORE_BI_ENABLED          _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_PICLK_BI_SHIFT            _MK_SHIFT_CONST(20)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_PICLK_BI_FIELD           (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_OVRD_PICLK_BI_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_PICLK_BI_RANGE           20:20
#define XUSB_DEV_XHCI_BLCG_0_OVRD_PICLK_BI_WOFFSET         0
#define XUSB_DEV_XHCI_BLCG_0_OVRD_PICLK_BI_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_PICLK_BI_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_PICLK_BI_SW_DEFAULT      (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_PICLK_BI_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_PICLK_BI_DISABLED        _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_PICLK_BI_ENABLED         _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_HSFS_PI_SHIFT             _MK_SHIFT_CONST(21)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_HSFS_PI_FIELD            (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_OVRD_HSFS_PI_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_HSFS_PI_RANGE            21:21
#define XUSB_DEV_XHCI_BLCG_0_OVRD_HSFS_PI_WOFFSET          0
#define XUSB_DEV_XHCI_BLCG_0_OVRD_HSFS_PI_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_HSFS_PI_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_HSFS_PI_SW_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_HSFS_PI_SW_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_HSFS_PI_DISABLED         _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_HSFS_PI_ENABLED          _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_NVWRAP_480M_SHIFT         _MK_SHIFT_CONST(22)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_NVWRAP_480M_FIELD        (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_OVRD_NVWRAP_480M_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_NVWRAP_480M_RANGE        22:22
#define XUSB_DEV_XHCI_BLCG_0_OVRD_NVWRAP_480M_WOFFSET      0
#define XUSB_DEV_XHCI_BLCG_0_OVRD_NVWRAP_480M_DEFAULT      (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_NVWRAP_480M_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_NVWRAP_480M_SW_DEFAULT   (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_NVWRAP_480M_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_NVWRAP_480M_DISABLED     _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_NVWRAP_480M_ENABLED      _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_NVWRAP_48M_SHIFT          _MK_SHIFT_CONST(23)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_NVWRAP_48M_FIELD         (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_OVRD_NVWRAP_48M_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_NVWRAP_48M_RANGE         23:23
#define XUSB_DEV_XHCI_BLCG_0_OVRD_NVWRAP_48M_WOFFSET       0
#define XUSB_DEV_XHCI_BLCG_0_OVRD_NVWRAP_48M_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_NVWRAP_48M_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_NVWRAP_48M_SW_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_NVWRAP_48M_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_NVWRAP_48M_DISABLED      _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_NVWRAP_48M_ENABLED       _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_COREPLL_PWRDN_SHIFT       _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_COREPLL_PWRDN_FIELD      (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_OVRD_COREPLL_PWRDN_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_COREPLL_PWRDN_RANGE      24:24
#define XUSB_DEV_XHCI_BLCG_0_OVRD_COREPLL_PWRDN_WOFFSET    0
#define XUSB_DEV_XHCI_BLCG_0_OVRD_COREPLL_PWRDN_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_COREPLL_PWRDN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_COREPLL_PWRDN_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_COREPLL_PWRDN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_COREPLL_PWRDN_DISABLED   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_COREPLL_PWRDN_ENABLED    _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_0_PWRDN_SHIFT       _MK_SHIFT_CONST(25)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_0_PWRDN_FIELD      (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_0_PWRDN_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_0_PWRDN_RANGE      25:25
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_0_PWRDN_WOFFSET    0
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_0_PWRDN_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_0_PWRDN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_0_PWRDN_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_0_PWRDN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_0_PWRDN_DISABLED   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_0_PWRDN_ENABLED    _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_1_PWRDN_SHIFT       _MK_SHIFT_CONST(26)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_1_PWRDN_FIELD      (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_1_PWRDN_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_1_PWRDN_RANGE      26:26
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_1_PWRDN_WOFFSET    0
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_1_PWRDN_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_1_PWRDN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_1_PWRDN_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_1_PWRDN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_1_PWRDN_DISABLED   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_1_PWRDN_ENABLED    _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_2_PWRDN_SHIFT       _MK_SHIFT_CONST(27)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_2_PWRDN_FIELD      (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_2_PWRDN_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_2_PWRDN_RANGE      27:27
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_2_PWRDN_WOFFSET    0
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_2_PWRDN_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_2_PWRDN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_2_PWRDN_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_2_PWRDN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_2_PWRDN_DISABLED   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_2_PWRDN_ENABLED    _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_3_PWRDN_SHIFT       _MK_SHIFT_CONST(28)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_3_PWRDN_FIELD      (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_3_PWRDN_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_3_PWRDN_RANGE      28:28
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_3_PWRDN_WOFFSET    0
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_3_PWRDN_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_3_PWRDN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_3_PWRDN_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_3_PWRDN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_3_PWRDN_DISABLED   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_IOPLL_3_PWRDN_ENABLED    _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_SS_PI_SHIFT               _MK_SHIFT_CONST(29)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_SS_PI_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_OVRD_SS_PI_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_SS_PI_RANGE              29:29
#define XUSB_DEV_XHCI_BLCG_0_OVRD_SS_PI_WOFFSET            0
#define XUSB_DEV_XHCI_BLCG_0_OVRD_SS_PI_DEFAULT            (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_SS_PI_DEFAULT_MASK       (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_SS_PI_SW_DEFAULT         (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_SS_PI_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_SS_PI_DISABLED           _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_SS_PI_ENABLED            _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_SS_PI_500M_SHIFT          _MK_SHIFT_CONST(30)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_SS_PI_500M_FIELD         (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_0_OVRD_SS_PI_500M_SHIFT)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_SS_PI_500M_RANGE         30:30
#define XUSB_DEV_XHCI_BLCG_0_OVRD_SS_PI_500M_WOFFSET       0
#define XUSB_DEV_XHCI_BLCG_0_OVRD_SS_PI_500M_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_SS_PI_500M_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_SS_PI_500M_SW_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_SS_PI_500M_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_SS_PI_500M_DISABLED      _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_0_OVRD_SS_PI_500M_ENABLED       _MK_ENUM_CONST(0x00000001)


// 


#define XUSB_DEV_XHCI_BLCG_STS_0                           _MK_ADDR_CONST(0x00000844)
#define XUSB_DEV_XHCI_BLCG_STS_0_SECURE                    0
#define XUSB_DEV_XHCI_BLCG_STS_0_WORD_COUNT                1
#define XUSB_DEV_XHCI_BLCG_STS_0_RESET_VAL                 _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_BLCG_STS_0_RESET_MASK                _MK_MASK_CONST(0x7ff8)
#define XUSB_DEV_XHCI_BLCG_STS_0_SW_DEFAULT_VAL            _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_BLCG_STS_0_SW_DEFAULT_MASK           _MK_MASK_CONST(0x7ff8)
#define XUSB_DEV_XHCI_BLCG_STS_0_READ_MASK                 _MK_MASK_CONST(0x7ff8)
#define XUSB_DEV_XHCI_BLCG_STS_0_WRITE_MASK                _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_BLCG_STS_0_CLEAR_MASK                _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_BLCG_STS_0_TGL_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_BLCG_STS_0_CORE_BI_SHIFT              _MK_SHIFT_CONST(3)
#define XUSB_DEV_XHCI_BLCG_STS_0_CORE_BI_FIELD             (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_STS_0_CORE_BI_SHIFT)
#define XUSB_DEV_XHCI_BLCG_STS_0_CORE_BI_RANGE             3:3
#define XUSB_DEV_XHCI_BLCG_STS_0_CORE_BI_WOFFSET           0
#define XUSB_DEV_XHCI_BLCG_STS_0_CORE_BI_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_CORE_BI_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_STS_0_CORE_BI_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_CORE_BI_SW_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_STS_0_CORE_BI_DISABLED          _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_CORE_BI_ENABLED           _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_STS_0_PICLK_BI_SHIFT             _MK_SHIFT_CONST(4)
#define XUSB_DEV_XHCI_BLCG_STS_0_PICLK_BI_FIELD            (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_STS_0_PICLK_BI_SHIFT)
#define XUSB_DEV_XHCI_BLCG_STS_0_PICLK_BI_RANGE            4:4
#define XUSB_DEV_XHCI_BLCG_STS_0_PICLK_BI_WOFFSET          0
#define XUSB_DEV_XHCI_BLCG_STS_0_PICLK_BI_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_PICLK_BI_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_STS_0_PICLK_BI_SW_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_PICLK_BI_SW_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_STS_0_PICLK_BI_DISABLED         _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_PICLK_BI_ENABLED          _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_STS_0_HSFS_PI_SHIFT              _MK_SHIFT_CONST(5)
#define XUSB_DEV_XHCI_BLCG_STS_0_HSFS_PI_FIELD             (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_STS_0_HSFS_PI_SHIFT)
#define XUSB_DEV_XHCI_BLCG_STS_0_HSFS_PI_RANGE             5:5
#define XUSB_DEV_XHCI_BLCG_STS_0_HSFS_PI_WOFFSET           0
#define XUSB_DEV_XHCI_BLCG_STS_0_HSFS_PI_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_HSFS_PI_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_STS_0_HSFS_PI_SW_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_HSFS_PI_SW_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_STS_0_HSFS_PI_DISABLED          _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_HSFS_PI_ENABLED           _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_STS_0_NVWRAP_480M_SHIFT          _MK_SHIFT_CONST(6)
#define XUSB_DEV_XHCI_BLCG_STS_0_NVWRAP_480M_FIELD         (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_STS_0_NVWRAP_480M_SHIFT)
#define XUSB_DEV_XHCI_BLCG_STS_0_NVWRAP_480M_RANGE         6:6
#define XUSB_DEV_XHCI_BLCG_STS_0_NVWRAP_480M_WOFFSET       0
#define XUSB_DEV_XHCI_BLCG_STS_0_NVWRAP_480M_DEFAULT       (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_NVWRAP_480M_DEFAULT_MASK  (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_STS_0_NVWRAP_480M_SW_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_NVWRAP_480M_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_STS_0_NVWRAP_480M_DISABLED      _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_NVWRAP_480M_ENABLED       _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_STS_0_NVWRAP_48M_SHIFT           _MK_SHIFT_CONST(7)
#define XUSB_DEV_XHCI_BLCG_STS_0_NVWRAP_48M_FIELD          (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_STS_0_NVWRAP_48M_SHIFT)
#define XUSB_DEV_XHCI_BLCG_STS_0_NVWRAP_48M_RANGE          7:7
#define XUSB_DEV_XHCI_BLCG_STS_0_NVWRAP_48M_WOFFSET        0
#define XUSB_DEV_XHCI_BLCG_STS_0_NVWRAP_48M_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_NVWRAP_48M_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_STS_0_NVWRAP_48M_SW_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_NVWRAP_48M_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_STS_0_NVWRAP_48M_DISABLED       _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_NVWRAP_48M_ENABLED        _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_STS_0_COREPLL_PWRDN_SHIFT        _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_BLCG_STS_0_COREPLL_PWRDN_FIELD       (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_STS_0_COREPLL_PWRDN_SHIFT)
#define XUSB_DEV_XHCI_BLCG_STS_0_COREPLL_PWRDN_RANGE       8:8
#define XUSB_DEV_XHCI_BLCG_STS_0_COREPLL_PWRDN_WOFFSET     0
#define XUSB_DEV_XHCI_BLCG_STS_0_COREPLL_PWRDN_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_COREPLL_PWRDN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_STS_0_COREPLL_PWRDN_SW_DEFAULT  (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_COREPLL_PWRDN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_STS_0_COREPLL_PWRDN_DISABLED    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_COREPLL_PWRDN_ENABLED     _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_0_PWRDN_SHIFT        _MK_SHIFT_CONST(9)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_0_PWRDN_FIELD       (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_0_PWRDN_SHIFT)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_0_PWRDN_RANGE       9:9
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_0_PWRDN_WOFFSET     0
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_0_PWRDN_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_0_PWRDN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_0_PWRDN_SW_DEFAULT  (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_0_PWRDN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_0_PWRDN_DISABLED    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_0_PWRDN_ENABLED     _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_1_PWRDN_SHIFT        _MK_SHIFT_CONST(10)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_1_PWRDN_FIELD       (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_1_PWRDN_SHIFT)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_1_PWRDN_RANGE       10:10
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_1_PWRDN_WOFFSET     0
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_1_PWRDN_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_1_PWRDN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_1_PWRDN_SW_DEFAULT  (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_1_PWRDN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_1_PWRDN_DISABLED    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_1_PWRDN_ENABLED     _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_2_PWRDN_SHIFT        _MK_SHIFT_CONST(11)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_2_PWRDN_FIELD       (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_2_PWRDN_SHIFT)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_2_PWRDN_RANGE       11:11
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_2_PWRDN_WOFFSET     0
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_2_PWRDN_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_2_PWRDN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_2_PWRDN_SW_DEFAULT  (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_2_PWRDN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_2_PWRDN_DISABLED    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_2_PWRDN_ENABLED     _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_3_PWRDN_SHIFT        _MK_SHIFT_CONST(12)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_3_PWRDN_FIELD       (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_3_PWRDN_SHIFT)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_3_PWRDN_RANGE       12:12
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_3_PWRDN_WOFFSET     0
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_3_PWRDN_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_3_PWRDN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_3_PWRDN_SW_DEFAULT  (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_3_PWRDN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_3_PWRDN_DISABLED    _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_IOPLL_3_PWRDN_ENABLED     _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_STS_0_SS_PI_SHIFT                _MK_SHIFT_CONST(13)
#define XUSB_DEV_XHCI_BLCG_STS_0_SS_PI_FIELD               (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_STS_0_SS_PI_SHIFT)
#define XUSB_DEV_XHCI_BLCG_STS_0_SS_PI_RANGE               13:13
#define XUSB_DEV_XHCI_BLCG_STS_0_SS_PI_WOFFSET             0
#define XUSB_DEV_XHCI_BLCG_STS_0_SS_PI_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_SS_PI_DEFAULT_MASK        (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_STS_0_SS_PI_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_SS_PI_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_STS_0_SS_PI_DISABLED            _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_SS_PI_ENABLED             _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_STS_0_SS_PI_500M_SHIFT           _MK_SHIFT_CONST(14)
#define XUSB_DEV_XHCI_BLCG_STS_0_SS_PI_500M_FIELD          (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_STS_0_SS_PI_500M_SHIFT)
#define XUSB_DEV_XHCI_BLCG_STS_0_SS_PI_500M_RANGE          14:14
#define XUSB_DEV_XHCI_BLCG_STS_0_SS_PI_500M_WOFFSET        0
#define XUSB_DEV_XHCI_BLCG_STS_0_SS_PI_500M_DEFAULT        (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_SS_PI_500M_DEFAULT_MASK   (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_STS_0_SS_PI_500M_SW_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_SS_PI_500M_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_STS_0_SS_PI_500M_DISABLED       _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_STS_0_SS_PI_500M_ENABLED        _MK_ENUM_CONST(0x00000001)


// Warning: unsupported define: #define T_XUSB_DEV_XHCI_BLCG_STS__PRODCHK                                       0 /*       */
// 


#define XUSB_DEV_XHCI_BLCG_INTR_0                          _MK_ADDR_CONST(0x00000848)
#define XUSB_DEV_XHCI_BLCG_INTR_0_SECURE                   0
#define XUSB_DEV_XHCI_BLCG_INTR_0_WORD_COUNT               1
#define XUSB_DEV_XHCI_BLCG_INTR_0_RESET_VAL                _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_BLCG_INTR_0_RESET_MASK               _MK_MASK_CONST(0x1f001f01)
#define XUSB_DEV_XHCI_BLCG_INTR_0_SW_DEFAULT_VAL           _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_BLCG_INTR_0_SW_DEFAULT_MASK          _MK_MASK_CONST(0x1f001f01)
#define XUSB_DEV_XHCI_BLCG_INTR_0_READ_MASK                _MK_MASK_CONST(0x1f001f01)
#define XUSB_DEV_XHCI_BLCG_INTR_0_WRITE_MASK               _MK_MASK_CONST(0x1f01)
#define XUSB_DEV_XHCI_BLCG_INTR_0_CLEAR_MASK               _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_BLCG_INTR_0_TGL_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_BLCG_INTR_0_TGT_SHIFT                 _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_BLCG_INTR_0_TGT_FIELD                (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_INTR_0_TGT_SHIFT)
#define XUSB_DEV_XHCI_BLCG_INTR_0_TGT_RANGE                0:0
#define XUSB_DEV_XHCI_BLCG_INTR_0_TGT_WOFFSET              0
#define XUSB_DEV_XHCI_BLCG_INTR_0_TGT_DEFAULT              (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_TGT_DEFAULT_MASK         (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_INTR_0_TGT_SW_DEFAULT           (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_TGT_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_INTR_0_TGT_SMI                  _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_TGT_PME                  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_INTR_0_COREPLL_PWRDN_SHIFT       _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_BLCG_INTR_0_COREPLL_PWRDN_FIELD      (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_INTR_0_COREPLL_PWRDN_SHIFT)
#define XUSB_DEV_XHCI_BLCG_INTR_0_COREPLL_PWRDN_RANGE      8:8
#define XUSB_DEV_XHCI_BLCG_INTR_0_COREPLL_PWRDN_WOFFSET    0
#define XUSB_DEV_XHCI_BLCG_INTR_0_COREPLL_PWRDN_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_COREPLL_PWRDN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_INTR_0_COREPLL_PWRDN_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_COREPLL_PWRDN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_INTR_0_COREPLL_PWRDN_DISABLED   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_COREPLL_PWRDN_ENABLED    _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_0_PWRDN_SHIFT       _MK_SHIFT_CONST(9)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_0_PWRDN_FIELD      (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_0_PWRDN_SHIFT)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_0_PWRDN_RANGE      9:9
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_0_PWRDN_WOFFSET    0
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_0_PWRDN_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_0_PWRDN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_0_PWRDN_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_0_PWRDN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_0_PWRDN_DISABLED   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_0_PWRDN_ENABLED    _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_1_PWRDN_SHIFT       _MK_SHIFT_CONST(10)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_1_PWRDN_FIELD      (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_1_PWRDN_SHIFT)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_1_PWRDN_RANGE      10:10
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_1_PWRDN_WOFFSET    0
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_1_PWRDN_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_1_PWRDN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_1_PWRDN_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_1_PWRDN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_1_PWRDN_DISABLED   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_1_PWRDN_ENABLED    _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_2_PWRDN_SHIFT       _MK_SHIFT_CONST(11)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_2_PWRDN_FIELD      (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_2_PWRDN_SHIFT)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_2_PWRDN_RANGE      11:11
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_2_PWRDN_WOFFSET    0
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_2_PWRDN_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_2_PWRDN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_2_PWRDN_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_2_PWRDN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_2_PWRDN_DISABLED   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_2_PWRDN_ENABLED    _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_3_PWRDN_SHIFT       _MK_SHIFT_CONST(12)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_3_PWRDN_FIELD      (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_3_PWRDN_SHIFT)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_3_PWRDN_RANGE      12:12
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_3_PWRDN_WOFFSET    0
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_3_PWRDN_DEFAULT    (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_3_PWRDN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_3_PWRDN_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_3_PWRDN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_3_PWRDN_DISABLED   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_IOPLL_3_PWRDN_ENABLED    _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_COREPLL_PWRDN_SHIFT   _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_COREPLL_PWRDN_FIELD  (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_INTR_0_STS_COREPLL_PWRDN_SHIFT)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_COREPLL_PWRDN_RANGE  24:24
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_COREPLL_PWRDN_WOFFSET 0
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_COREPLL_PWRDN_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_COREPLL_PWRDN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_COREPLL_PWRDN_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_COREPLL_PWRDN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_COREPLL_PWRDN_DISABLED _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_COREPLL_PWRDN_ENABLED _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_0_PWRDN_SHIFT   _MK_SHIFT_CONST(25)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_0_PWRDN_FIELD  (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_0_PWRDN_SHIFT)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_0_PWRDN_RANGE  25:25
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_0_PWRDN_WOFFSET 0
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_0_PWRDN_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_0_PWRDN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_0_PWRDN_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_0_PWRDN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_0_PWRDN_DISABLED _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_0_PWRDN_ENABLED _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_1_PWRDN_SHIFT   _MK_SHIFT_CONST(26)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_1_PWRDN_FIELD  (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_1_PWRDN_SHIFT)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_1_PWRDN_RANGE  26:26
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_1_PWRDN_WOFFSET 0
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_1_PWRDN_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_1_PWRDN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_1_PWRDN_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_1_PWRDN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_1_PWRDN_DISABLED _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_1_PWRDN_ENABLED _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_2_PWRDN_SHIFT   _MK_SHIFT_CONST(27)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_2_PWRDN_FIELD  (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_2_PWRDN_SHIFT)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_2_PWRDN_RANGE  27:27
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_2_PWRDN_WOFFSET 0
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_2_PWRDN_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_2_PWRDN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_2_PWRDN_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_2_PWRDN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_2_PWRDN_DISABLED _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_2_PWRDN_ENABLED _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_3_PWRDN_SHIFT   _MK_SHIFT_CONST(28)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_3_PWRDN_FIELD  (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_3_PWRDN_SHIFT)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_3_PWRDN_RANGE  28:28
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_3_PWRDN_WOFFSET 0
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_3_PWRDN_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_3_PWRDN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_3_PWRDN_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_3_PWRDN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_3_PWRDN_DISABLED _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_BLCG_INTR_0_STS_IOPLL_3_PWRDN_ENABLED _MK_ENUM_CONST(0x00000001)


// 
// 
// 
// //*****************************************************************************************************
// //*****************************************************************************************************
// // Dev BI registers
// // ISOCH_SKIP_SIA - if there is no host request for an EP which has TD pending with SIA=1, BI will generate a missed service if this config is 1
// // MAX_ALOM - Controls the number of back to back accesses that DMA Engines issue with ALOM bit (At-Least One More) set
// // UPSTREAM_* - Controls PCIE Attributes for upstream requests
// // CNT_250NS - 250NS counter duration for Interrupt Moderation
// // LOCAL_ROTATE - Enabled Perf mode in Thread logic where it doesnt evict and Endpoint if there are no other endpoints waiting
// // TRBFETCH_IDT_IN - CYA to allow IDT TRBs for an OUT Endpoint
// // TRBFETCH_NUMSKIP - Number of Isoch TDs to skip in case of missed service
// // TRBFETCH_RINGEND_CHK - Setting this to 1, makes TRB Fetch always fetch one extra TRB to check for End of Ring.
// // ASYNC_EP_IDLE - CYA to include Async EPs Idle condition for U1/U2. If this bit is 1, Async EPs Idle is based on PP bit indication by host.
// //               - If it is 0, Async EPs will always flag idle
// 


#define XUSB_DEV_XHCI_CFG_DEVBI_0                          _MK_ADDR_CONST(0x00000850)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_SECURE                   0
#define XUSB_DEV_XHCI_CFG_DEVBI_0_WORD_COUNT               1
#define XUSB_DEV_XHCI_CFG_DEVBI_0_RESET_VAL                _MK_MASK_CONST(0x302638c3)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_RESET_MASK               _MK_MASK_CONST(0x7fff79ff)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_SW_DEFAULT_VAL           _MK_MASK_CONST(0x302638c3)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_SW_DEFAULT_MASK          _MK_MASK_CONST(0x7fff79ff)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_READ_MASK                _MK_MASK_CONST(0x7fff79ff)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_WRITE_MASK               _MK_MASK_CONST(0x7fff79ff)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_CLEAR_MASK               _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TGL_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_WR_MAX_ALOM_SHIFT     _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_WR_MAX_ALOM_FIELD    (_MK_SHIFT_CONST(0x1f) << XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_WR_MAX_ALOM_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_WR_MAX_ALOM_RANGE    4:0
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_WR_MAX_ALOM_WOFFSET  0
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_WR_MAX_ALOM_DEFAULT  (_MK_MASK_CONST(0x00000003)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_WR_MAX_ALOM_DEFAULT_MASK (_MK_MASK_CONST(0x1f)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_WR_MAX_ALOM_SW_DEFAULT (_MK_MASK_CONST(0x00000003)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_WR_MAX_ALOM_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1f)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_WR_MAX_ALOM_INIT     _MK_ENUM_CONST(0x00000003)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_UPSTREAM_RDPASSPW_SHIFT  _MK_SHIFT_CONST(5)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_UPSTREAM_RDPASSPW_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_UPSTREAM_RDPASSPW_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_UPSTREAM_RDPASSPW_RANGE 5:5
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_UPSTREAM_RDPASSPW_WOFFSET 0
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_UPSTREAM_RDPASSPW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_UPSTREAM_RDPASSPW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_UPSTREAM_RDPASSPW_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_UPSTREAM_RDPASSPW_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_UPSTREAM_RDPASSPW_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_UPSTREAM_RO_SHIFT  _MK_SHIFT_CONST(6)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_UPSTREAM_RO_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_UPSTREAM_RO_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_UPSTREAM_RO_RANGE 6:6
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_UPSTREAM_RO_WOFFSET 0
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_UPSTREAM_RO_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_UPSTREAM_RO_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_UPSTREAM_RO_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_UPSTREAM_RO_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_UPSTREAM_RO_INIT  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_WR_UPSTREAM_RO_SHIFT  _MK_SHIFT_CONST(7)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_WR_UPSTREAM_RO_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_WR_UPSTREAM_RO_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_WR_UPSTREAM_RO_RANGE 7:7
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_WR_UPSTREAM_RO_WOFFSET 0
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_WR_UPSTREAM_RO_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_WR_UPSTREAM_RO_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_WR_UPSTREAM_RO_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_WR_UPSTREAM_RO_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_WR_UPSTREAM_RO_INIT  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_IDT_IN_SHIFT     _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_IDT_IN_FIELD    (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_IDT_IN_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_IDT_IN_RANGE    8:8
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_IDT_IN_WOFFSET  0
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_IDT_IN_DEFAULT  (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_IDT_IN_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_IDT_IN_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_IDT_IN_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_IDT_IN_INIT     _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_RINGEND_CHK_SHIFT  _MK_SHIFT_CONST(11)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_RINGEND_CHK_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_RINGEND_CHK_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_RINGEND_CHK_RANGE 11:11
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_RINGEND_CHK_WOFFSET 0
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_RINGEND_CHK_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_RINGEND_CHK_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_RINGEND_CHK_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_RINGEND_CHK_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_RINGEND_CHK_EN  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_LOCAL_ROTATE_SHIFT        _MK_SHIFT_CONST(12)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_LOCAL_ROTATE_FIELD       (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_DEVBI_0_LOCAL_ROTATE_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_LOCAL_ROTATE_RANGE       12:12
#define XUSB_DEV_XHCI_CFG_DEVBI_0_LOCAL_ROTATE_WOFFSET     0
#define XUSB_DEV_XHCI_CFG_DEVBI_0_LOCAL_ROTATE_DEFAULT     (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_LOCAL_ROTATE_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_LOCAL_ROTATE_SW_DEFAULT  (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_LOCAL_ROTATE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_LOCAL_ROTATE_INIT        _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_LOCAL_ROTATE_EN          _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_LOCAL_ROTATE_DIS         _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_ASYNC_EP_IDLE_SHIFT       _MK_SHIFT_CONST(13)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_ASYNC_EP_IDLE_FIELD      (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_DEVBI_0_ASYNC_EP_IDLE_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_ASYNC_EP_IDLE_RANGE      13:13
#define XUSB_DEV_XHCI_CFG_DEVBI_0_ASYNC_EP_IDLE_WOFFSET    0
#define XUSB_DEV_XHCI_CFG_DEVBI_0_ASYNC_EP_IDLE_DEFAULT    (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_ASYNC_EP_IDLE_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_ASYNC_EP_IDLE_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_ASYNC_EP_IDLE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_ASYNC_EP_IDLE_INIT       _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_RDPASSPW_SHIFT   _MK_SHIFT_CONST(14)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_RDPASSPW_FIELD  (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_RDPASSPW_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_RDPASSPW_RANGE  14:14
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_RDPASSPW_WOFFSET 0
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_RDPASSPW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_RDPASSPW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_RDPASSPW_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_RDPASSPW_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_TRBFETCH_RDPASSPW_INIT   _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_CNT_250NS_SHIFT           _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_CNT_250NS_FIELD          (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_CFG_DEVBI_0_CNT_250NS_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_CNT_250NS_RANGE          23:16
#define XUSB_DEV_XHCI_CFG_DEVBI_0_CNT_250NS_WOFFSET        0
#define XUSB_DEV_XHCI_CFG_DEVBI_0_CNT_250NS_DEFAULT        (_MK_MASK_CONST(0x00000026)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_CNT_250NS_DEFAULT_MASK   (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_CNT_250NS_SW_DEFAULT     (_MK_MASK_CONST(0x00000026)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_CNT_250NS_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_CNT_250NS_INIT           _MK_ENUM_CONST(0x00000026)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_MAX_ALOM_SHIFT     _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_MAX_ALOM_FIELD    (_MK_SHIFT_CONST(0x1f) << XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_MAX_ALOM_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_MAX_ALOM_RANGE    28:24
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_MAX_ALOM_WOFFSET  0
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_MAX_ALOM_DEFAULT  (_MK_MASK_CONST(0x00000010)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_MAX_ALOM_DEFAULT_MASK (_MK_MASK_CONST(0x1f)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_MAX_ALOM_SW_DEFAULT (_MK_MASK_CONST(0x00000010)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_MAX_ALOM_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1f)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_DMA_RD_MAX_ALOM_INIT     _MK_ENUM_CONST(0x00000010)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_ISOCH_SKIP_SIA_SHIFT      _MK_SHIFT_CONST(29)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_ISOCH_SKIP_SIA_FIELD     (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_DEVBI_0_ISOCH_SKIP_SIA_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_ISOCH_SKIP_SIA_RANGE     29:29
#define XUSB_DEV_XHCI_CFG_DEVBI_0_ISOCH_SKIP_SIA_WOFFSET   0
#define XUSB_DEV_XHCI_CFG_DEVBI_0_ISOCH_SKIP_SIA_DEFAULT   (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_ISOCH_SKIP_SIA_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_ISOCH_SKIP_SIA_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_ISOCH_SKIP_SIA_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_ISOCH_SKIP_SIA_INIT      _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_OVERRUN_EVT_DEQPTR0_SHIFT  _MK_SHIFT_CONST(30)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_OVERRUN_EVT_DEQPTR0_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_DEVBI_0_OVERRUN_EVT_DEQPTR0_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_OVERRUN_EVT_DEQPTR0_RANGE 30:30
#define XUSB_DEV_XHCI_CFG_DEVBI_0_OVERRUN_EVT_DEQPTR0_WOFFSET 0
#define XUSB_DEV_XHCI_CFG_DEVBI_0_OVERRUN_EVT_DEQPTR0_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_OVERRUN_EVT_DEQPTR0_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_OVERRUN_EVT_DEQPTR0_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_OVERRUN_EVT_DEQPTR0_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_0_OVERRUN_EVT_DEQPTR0_INIT _MK_ENUM_CONST(0x00000000)


// 
// 
// 
// 
// 


#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0                 _MK_ADDR_CONST(0x00000854)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_SECURE          0
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_WORD_COUNT      1
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_RESET_VAL       _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_RESET_MASK      _MK_MASK_CONST(0xffff1f07)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_SW_DEFAULT_VAL  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xffff1f07)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_READ_MASK       _MK_MASK_CONST(0xffff1f07)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_WRITE_MASK      _MK_MASK_CONST(0xffff1f07)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_CLEAR_MASK      _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_TGL_MASK        _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_TC_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_TC_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_TC_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_TC_RANGE 0:0
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_TC_WOFFSET 0
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_TC_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_TC_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_TC_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_TC_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_TC_INIT  _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_NS_SHIFT  _MK_SHIFT_CONST(1)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_NS_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_NS_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_NS_RANGE 1:1
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_NS_WOFFSET 0
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_NS_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_NS_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_NS_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_NS_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_NS_INIT  _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_RO_SHIFT  _MK_SHIFT_CONST(2)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_RO_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_RO_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_RO_RANGE 2:2
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_RO_WOFFSET 0
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_RO_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_RO_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_RO_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_RO_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EVENTQ_RO_INIT  _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_TC_SHIFT  _MK_SHIFT_CONST(8)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_TC_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_TC_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_TC_RANGE 8:8
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_TC_WOFFSET 0
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_TC_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_TC_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_TC_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_TC_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_TC_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_NS_SHIFT  _MK_SHIFT_CONST(9)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_NS_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_NS_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_NS_RANGE 9:9
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_NS_WOFFSET 0
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_NS_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_NS_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_NS_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_NS_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_NS_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_RO_SHIFT  _MK_SHIFT_CONST(10)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_RO_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_RO_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_RO_RANGE 10:10
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_RO_WOFFSET 0
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_RO_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_RO_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_RO_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_RO_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_RO_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_RDPASSPW_SHIFT  _MK_SHIFT_CONST(11)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_RDPASSPW_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_RDPASSPW_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_RDPASSPW_RANGE 11:11
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_RDPASSPW_WOFFSET 0
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_RDPASSPW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_RDPASSPW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_RDPASSPW_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_RDPASSPW_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_EPLOGIC_RDPASSPW_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_WR_USE_WR_ACKS_SHIFT  _MK_SHIFT_CONST(12)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_WR_USE_WR_ACKS_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_WR_USE_WR_ACKS_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_WR_USE_WR_ACKS_RANGE 12:12
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_WR_USE_WR_ACKS_WOFFSET 0
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_WR_USE_WR_ACKS_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_WR_USE_WR_ACKS_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_WR_USE_WR_ACKS_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_WR_USE_WR_ACKS_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_WR_USE_WR_ACKS_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_RD_LIMIT_SHIFT  _MK_SHIFT_CONST(16)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_RD_LIMIT_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_RD_LIMIT_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_RD_LIMIT_RANGE 23:16
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_RD_LIMIT_WOFFSET 0
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_RD_LIMIT_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_RD_LIMIT_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_RD_LIMIT_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_RD_LIMIT_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_RD_LIMIT_INIT _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_WR_LIMIT_SHIFT  _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_WR_LIMIT_FIELD (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_WR_LIMIT_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_WR_LIMIT_RANGE 31:24
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_WR_LIMIT_WOFFSET 0
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_WR_LIMIT_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_WR_LIMIT_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_WR_LIMIT_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_WR_LIMIT_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0_DMA_WR_LIMIT_INIT _MK_ENUM_CONST(0x00000000)


// 
// // Transaction timeout duration while waiting for ACK from host


#define XUSB_DEV_XHCI_CFG_DEV_SSPI_XFER_0                  _MK_ADDR_CONST(0x00000858)
#define XUSB_DEV_XHCI_CFG_DEV_SSPI_XFER_0_SECURE           0
#define XUSB_DEV_XHCI_CFG_DEV_SSPI_XFER_0_WORD_COUNT       1
#define XUSB_DEV_XHCI_CFG_DEV_SSPI_XFER_0_RESET_VAL        _MK_MASK_CONST(0xf00)
#define XUSB_DEV_XHCI_CFG_DEV_SSPI_XFER_0_RESET_MASK       _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_CFG_DEV_SSPI_XFER_0_SW_DEFAULT_VAL   _MK_MASK_CONST(0xf00)
#define XUSB_DEV_XHCI_CFG_DEV_SSPI_XFER_0_SW_DEFAULT_MASK  _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_CFG_DEV_SSPI_XFER_0_READ_MASK        _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_CFG_DEV_SSPI_XFER_0_WRITE_MASK       _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_CFG_DEV_SSPI_XFER_0_CLEAR_MASK       _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_DEV_SSPI_XFER_0_TGL_MASK         _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_DEV_SSPI_XFER_0_ACKTIMEOUT_SHIFT  _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_CFG_DEV_SSPI_XFER_0_ACKTIMEOUT_FIELD (_MK_SHIFT_CONST(0xffffffff) << XUSB_DEV_XHCI_CFG_DEV_SSPI_XFER_0_ACKTIMEOUT_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEV_SSPI_XFER_0_ACKTIMEOUT_RANGE 31:0
#define XUSB_DEV_XHCI_CFG_DEV_SSPI_XFER_0_ACKTIMEOUT_WOFFSET 0
#define XUSB_DEV_XHCI_CFG_DEV_SSPI_XFER_0_ACKTIMEOUT_DEFAULT (_MK_MASK_CONST(0x00000F00)
#define XUSB_DEV_XHCI_CFG_DEV_SSPI_XFER_0_ACKTIMEOUT_DEFAULT_MASK (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_CFG_DEV_SSPI_XFER_0_ACKTIMEOUT_SW_DEFAULT (_MK_MASK_CONST(0x00000F00)
#define XUSB_DEV_XHCI_CFG_DEV_SSPI_XFER_0_ACKTIMEOUT_SW_DEFAULT_MASK (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_CFG_DEV_SSPI_XFER_0_ACKTIMEOUT__PROD _MK_ENUM_CONST(0x0000F000)
#define XUSB_DEV_XHCI_CFG_DEV_SSPI_XFER_0_ACKTIMEOUT_INIT  _MK_ENUM_CONST(0x00000F00)


// 
// // CYA bits for DEV_FE


#define XUSB_DEV_XHCI_CFG_DEV_FE_0                         _MK_ADDR_CONST(0x0000085C)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_SECURE                  0
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_WORD_COUNT              1
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_RESET_VAL               _MK_MASK_CONST(0x1a004b0c)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_RESET_MASK              _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_SW_DEFAULT_VAL          _MK_MASK_CONST(0x1a004b0c)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_SW_DEFAULT_MASK         _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_READ_MASK               _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_WRITE_MASK              _MK_MASK_CONST(0x3fffffff)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_CLEAR_MASK              _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_TGL_MASK                _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTREGSEL_SHIFT         _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTREGSEL_FIELD        (_MK_SHIFT_CONST(0x3) << XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTREGSEL_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTREGSEL_RANGE        1:0
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTREGSEL_WOFFSET      0
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTREGSEL_DEFAULT      (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTREGSEL_DEFAULT_MASK (_MK_MASK_CONST(0x3)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTREGSEL_SW_DEFAULT   (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTREGSEL_SW_DEFAULT_MASK (_MK_MASK_CONST(0x3)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTREGSEL_INIT         _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTREGSEL_SS           _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTREGSEL_HSFS         _MK_ENUM_CONST(0x00000002)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_SEQNUM_INIT_SHIFT        _MK_SHIFT_CONST(2)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_SEQNUM_INIT_FIELD       (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_DEV_FE_0_SEQNUM_INIT_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_SEQNUM_INIT_RANGE       2:2
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_SEQNUM_INIT_WOFFSET     0
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_SEQNUM_INIT_DEFAULT     (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_SEQNUM_INIT_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_SEQNUM_INIT_SW_DEFAULT  (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_SEQNUM_INIT_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_SEQNUM_INIT_INIT        _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTRST_HW_SHIFT         _MK_SHIFT_CONST(3)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTRST_HW_FIELD        (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTRST_HW_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTRST_HW_RANGE        3:3
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTRST_HW_WOFFSET      0
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTRST_HW_DEFAULT      (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTRST_HW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTRST_HW_SW_DEFAULT   (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTRST_HW_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTRST_HW_INIT         _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_MFCOUNT_MIN_SHIFT        _MK_SHIFT_CONST(4)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_MFCOUNT_MIN_FIELD       (_MK_SHIFT_CONST(0xfffff) << XUSB_DEV_XHCI_CFG_DEV_FE_0_MFCOUNT_MIN_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_MFCOUNT_MIN_RANGE       23:4
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_MFCOUNT_MIN_WOFFSET     0
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_MFCOUNT_MIN_DEFAULT     (_MK_MASK_CONST(0x000004B0)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_MFCOUNT_MIN_DEFAULT_MASK (_MK_MASK_CONST(0xfffff)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_MFCOUNT_MIN_SW_DEFAULT  (_MK_MASK_CONST(0x000004B0)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_MFCOUNT_MIN_SW_DEFAULT_MASK (_MK_MASK_CONST(0xfffff)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_MFCOUNT_MIN_INIT        _MK_ENUM_CONST(0x000004B0)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_CTX_RESTORE_SHIFT        _MK_SHIFT_CONST(24)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_CTX_RESTORE_FIELD       (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_DEV_FE_0_CTX_RESTORE_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_CTX_RESTORE_RANGE       24:24
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_CTX_RESTORE_WOFFSET     0
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_CTX_RESTORE_DEFAULT     (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_CTX_RESTORE_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_CTX_RESTORE_SW_DEFAULT  (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_CTX_RESTORE_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_CTX_RESTORE_INIT        _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTDISCON_RST_HW_SHIFT  _MK_SHIFT_CONST(25)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTDISCON_RST_HW_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTDISCON_RST_HW_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTDISCON_RST_HW_RANGE 25:25
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTDISCON_RST_HW_WOFFSET 0
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTDISCON_RST_HW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTDISCON_RST_HW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTDISCON_RST_HW_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTDISCON_RST_HW_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_PORTDISCON_RST_HW_INIT  _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_EN_STALL_EVENT_SHIFT     _MK_SHIFT_CONST(26)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_EN_STALL_EVENT_FIELD    (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_DEV_FE_0_EN_STALL_EVENT_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_EN_STALL_EVENT_RANGE    26:26
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_EN_STALL_EVENT_WOFFSET  0
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_EN_STALL_EVENT_DEFAULT  (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_EN_STALL_EVENT_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_EN_STALL_EVENT_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_EN_STALL_EVENT_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_EN_STALL_EVENT_INIT     _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_FEATURE_LPM_SHIFT        _MK_SHIFT_CONST(27)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_FEATURE_LPM_FIELD       (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_DEV_FE_0_FEATURE_LPM_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_FEATURE_LPM_RANGE       27:27
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_FEATURE_LPM_WOFFSET     0
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_FEATURE_LPM_DEFAULT     (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_FEATURE_LPM_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_FEATURE_LPM_SW_DEFAULT  (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_FEATURE_LPM_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_FEATURE_LPM_EN          _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_FEATURE_LPM_DIS         _MK_ENUM_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_EN_PRIME_EVENT_SHIFT     _MK_SHIFT_CONST(28)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_EN_PRIME_EVENT_FIELD    (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_DEV_FE_0_EN_PRIME_EVENT_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_EN_PRIME_EVENT_RANGE    28:28
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_EN_PRIME_EVENT_WOFFSET  0
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_EN_PRIME_EVENT_DEFAULT  (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_EN_PRIME_EVENT_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_EN_PRIME_EVENT_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_EN_PRIME_EVENT_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_EN_PRIME_EVENT_INIT     _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_INFINITE_SS_RETRY_SHIFT  _MK_SHIFT_CONST(29)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_INFINITE_SS_RETRY_FIELD (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_DEV_FE_0_INFINITE_SS_RETRY_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_INFINITE_SS_RETRY_RANGE 29:29
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_INFINITE_SS_RETRY_WOFFSET 0
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_INFINITE_SS_RETRY_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_INFINITE_SS_RETRY_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_INFINITE_SS_RETRY_SW_DEFAULT (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_INFINITE_SS_RETRY_SW_DEFAULT_MASK (_MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_INFINITE_SS_RETRY_EN    _MK_ENUM_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEV_FE_0_INFINITE_SS_RETRY_DIS   _MK_ENUM_CONST(0x00000000)


// 
// // IDLE bits for each device mode block


#define XUSB_DEV_XHCI_CFG_IDLE_0                           _MK_ADDR_CONST(0x00000860)
#define XUSB_DEV_XHCI_CFG_IDLE_0_SECURE                    0
#define XUSB_DEV_XHCI_CFG_IDLE_0_WORD_COUNT                1
#define XUSB_DEV_XHCI_CFG_IDLE_0_RESET_VAL                 _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_IDLE_0_RESET_MASK                _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_IDLE_0_SW_DEFAULT_VAL            _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_IDLE_0_SW_DEFAULT_MASK           _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_IDLE_0_READ_MASK                 _MK_MASK_CONST(0x1f)
#define XUSB_DEV_XHCI_CFG_IDLE_0_WRITE_MASK                _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_IDLE_0_CLEAR_MASK                _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_IDLE_0_TGL_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_IDLE_0_DEV_BI_SHIFT               _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_CFG_IDLE_0_DEV_BI_FIELD              (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_IDLE_0_DEV_BI_SHIFT)
#define XUSB_DEV_XHCI_CFG_IDLE_0_DEV_BI_RANGE              0:0
#define XUSB_DEV_XHCI_CFG_IDLE_0_DEV_BI_WOFFSET            0
#define XUSB_DEV_XHCI_CFG_IDLE_0_DEV_HSFS_PI_SHIFT          _MK_SHIFT_CONST(1)
#define XUSB_DEV_XHCI_CFG_IDLE_0_DEV_HSFS_PI_FIELD         (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_IDLE_0_DEV_HSFS_PI_SHIFT)
#define XUSB_DEV_XHCI_CFG_IDLE_0_DEV_HSFS_PI_RANGE         1:1
#define XUSB_DEV_XHCI_CFG_IDLE_0_DEV_HSFS_PI_WOFFSET       0
#define XUSB_DEV_XHCI_CFG_IDLE_0_DEV_HS_NVWRAP_SHIFT        _MK_SHIFT_CONST(2)
#define XUSB_DEV_XHCI_CFG_IDLE_0_DEV_HS_NVWRAP_FIELD       (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_IDLE_0_DEV_HS_NVWRAP_SHIFT)
#define XUSB_DEV_XHCI_CFG_IDLE_0_DEV_HS_NVWRAP_RANGE       2:2
#define XUSB_DEV_XHCI_CFG_IDLE_0_DEV_HS_NVWRAP_WOFFSET     0
#define XUSB_DEV_XHCI_CFG_IDLE_0_DEV_FS_NVWRAP_SHIFT        _MK_SHIFT_CONST(3)
#define XUSB_DEV_XHCI_CFG_IDLE_0_DEV_FS_NVWRAP_FIELD       (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_IDLE_0_DEV_FS_NVWRAP_SHIFT)
#define XUSB_DEV_XHCI_CFG_IDLE_0_DEV_FS_NVWRAP_RANGE       3:3
#define XUSB_DEV_XHCI_CFG_IDLE_0_DEV_FS_NVWRAP_WOFFSET     0
#define XUSB_DEV_XHCI_CFG_IDLE_0_DEV_SS_PI_SHIFT            _MK_SHIFT_CONST(4)
#define XUSB_DEV_XHCI_CFG_IDLE_0_DEV_SS_PI_FIELD           (_MK_SHIFT_CONST(0x1) << XUSB_DEV_XHCI_CFG_IDLE_0_DEV_SS_PI_SHIFT)
#define XUSB_DEV_XHCI_CFG_IDLE_0_DEV_SS_PI_RANGE           4:4
#define XUSB_DEV_XHCI_CFG_IDLE_0_DEV_SS_PI_WOFFSET         0


// 
// // programmable tERDYTimeout (in terms of number of pi clk cycles)


#define XUSB_DEV_XHCI_CFG_SSXFER_0                         _MK_ADDR_CONST(0x00000864)
#define XUSB_DEV_XHCI_CFG_SSXFER_0_SECURE                  0
#define XUSB_DEV_XHCI_CFG_SSXFER_0_WORD_COUNT              1
#define XUSB_DEV_XHCI_CFG_SSXFER_0_RESET_VAL               _MK_MASK_CONST(0x3938700)
#define XUSB_DEV_XHCI_CFG_SSXFER_0_RESET_MASK              _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_CFG_SSXFER_0_SW_DEFAULT_VAL          _MK_MASK_CONST(0x3938700)
#define XUSB_DEV_XHCI_CFG_SSXFER_0_SW_DEFAULT_MASK         _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_CFG_SSXFER_0_READ_MASK               _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_CFG_SSXFER_0_WRITE_MASK              _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_CFG_SSXFER_0_CLEAR_MASK              _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_SSXFER_0_TGL_MASK                _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_SSXFER_0_ERDYTIMER_SHIFT          _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_CFG_SSXFER_0_ERDYTIMER_FIELD         (_MK_SHIFT_CONST(0xffffffff) << XUSB_DEV_XHCI_CFG_SSXFER_0_ERDYTIMER_SHIFT)
#define XUSB_DEV_XHCI_CFG_SSXFER_0_ERDYTIMER_RANGE         31:0
#define XUSB_DEV_XHCI_CFG_SSXFER_0_ERDYTIMER_WOFFSET       0
#define XUSB_DEV_XHCI_CFG_SSXFER_0_ERDYTIMER_DEFAULT       (_MK_MASK_CONST(0x03938700)
#define XUSB_DEV_XHCI_CFG_SSXFER_0_ERDYTIMER_DEFAULT_MASK  (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_CFG_SSXFER_0_ERDYTIMER_SW_DEFAULT    (_MK_MASK_CONST(0x03938700)
#define XUSB_DEV_XHCI_CFG_SSXFER_0_ERDYTIMER_SW_DEFAULT_MASK (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_CFG_SSXFER_0_ERDYTIMER_INIT          _MK_ENUM_CONST(0x03938700)


// 
// // programmable tERDYTimeout (in terms of number of uframes)


#define XUSB_DEV_XHCI_CFG_SSXFER1_0                        _MK_ADDR_CONST(0x00000868)
#define XUSB_DEV_XHCI_CFG_SSXFER1_0_SECURE                 0
#define XUSB_DEV_XHCI_CFG_SSXFER1_0_WORD_COUNT             1
#define XUSB_DEV_XHCI_CFG_SSXFER1_0_RESET_VAL              _MK_MASK_CONST(0x2)
#define XUSB_DEV_XHCI_CFG_SSXFER1_0_RESET_MASK             _MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_CFG_SSXFER1_0_SW_DEFAULT_VAL         _MK_MASK_CONST(0x2)
#define XUSB_DEV_XHCI_CFG_SSXFER1_0_SW_DEFAULT_MASK        _MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_CFG_SSXFER1_0_READ_MASK              _MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_CFG_SSXFER1_0_WRITE_MASK             _MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_CFG_SSXFER1_0_CLEAR_MASK             _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_SSXFER1_0_TGL_MASK               _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_SSXFER1_0_PINGTIMER_SHIFT         _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_CFG_SSXFER1_0_PINGTIMER_FIELD        (_MK_SHIFT_CONST(0xffff) << XUSB_DEV_XHCI_CFG_SSXFER1_0_PINGTIMER_SHIFT)
#define XUSB_DEV_XHCI_CFG_SSXFER1_0_PINGTIMER_RANGE        15:0
#define XUSB_DEV_XHCI_CFG_SSXFER1_0_PINGTIMER_WOFFSET      0
#define XUSB_DEV_XHCI_CFG_SSXFER1_0_PINGTIMER_DEFAULT      (_MK_MASK_CONST(0x00000002)
#define XUSB_DEV_XHCI_CFG_SSXFER1_0_PINGTIMER_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_CFG_SSXFER1_0_PINGTIMER_SW_DEFAULT   (_MK_MASK_CONST(0x00000002)
#define XUSB_DEV_XHCI_CFG_SSXFER1_0_PINGTIMER_SW_DEFAULT_MASK (_MK_MASK_CONST(0xffff)
#define XUSB_DEV_XHCI_CFG_SSXFER1_0_PINGTIMER_INIT         _MK_ENUM_CONST(0x00000002)


// 


#define XUSB_DEV_XHCI_CFG_DEVBI1_0                         _MK_ADDR_CONST(0x0000086C)
#define XUSB_DEV_XHCI_CFG_DEVBI1_0_SECURE                  0
#define XUSB_DEV_XHCI_CFG_DEVBI1_0_WORD_COUNT              1
#define XUSB_DEV_XHCI_CFG_DEVBI1_0_RESET_VAL               _MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI1_0_RESET_MASK              _MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_CFG_DEVBI1_0_SW_DEFAULT_VAL          _MK_MASK_CONST(0x1)
#define XUSB_DEV_XHCI_CFG_DEVBI1_0_SW_DEFAULT_MASK         _MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_CFG_DEVBI1_0_READ_MASK               _MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_CFG_DEVBI1_0_WRITE_MASK              _MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_CFG_DEVBI1_0_CLEAR_MASK              _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_DEVBI1_0_TGL_MASK                _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_DEVBI1_0_TRBFETCH_NUMSKIP_SHIFT   _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_CFG_DEVBI1_0_TRBFETCH_NUMSKIP_FIELD  (_MK_SHIFT_CONST(0xff) << XUSB_DEV_XHCI_CFG_DEVBI1_0_TRBFETCH_NUMSKIP_SHIFT)
#define XUSB_DEV_XHCI_CFG_DEVBI1_0_TRBFETCH_NUMSKIP_RANGE  7:0
#define XUSB_DEV_XHCI_CFG_DEVBI1_0_TRBFETCH_NUMSKIP_WOFFSET 0
#define XUSB_DEV_XHCI_CFG_DEVBI1_0_TRBFETCH_NUMSKIP_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEVBI1_0_TRBFETCH_NUMSKIP_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_CFG_DEVBI1_0_TRBFETCH_NUMSKIP_SW_DEFAULT (_MK_MASK_CONST(0x00000001)
#define XUSB_DEV_XHCI_CFG_DEVBI1_0_TRBFETCH_NUMSKIP_SW_DEFAULT_MASK (_MK_MASK_CONST(0xff)
#define XUSB_DEV_XHCI_CFG_DEVBI1_0_TRBFETCH_NUMSKIP_INIT   _MK_ENUM_CONST(0x00000001)


// 
// 


#define XUSB_DEV_XHCI_CFG_SPARE0_0                         _MK_ADDR_CONST(0x00000870)
#define XUSB_DEV_XHCI_CFG_SPARE0_0_SECURE                  0
#define XUSB_DEV_XHCI_CFG_SPARE0_0_WORD_COUNT              1
#define XUSB_DEV_XHCI_CFG_SPARE0_0_RESET_VAL               _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_SPARE0_0_RESET_MASK              _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_CFG_SPARE0_0_SW_DEFAULT_VAL          _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_SPARE0_0_SW_DEFAULT_MASK         _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_CFG_SPARE0_0_READ_MASK               _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_CFG_SPARE0_0_WRITE_MASK              _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_CFG_SPARE0_0_CLEAR_MASK              _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_SPARE0_0_TGL_MASK                _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_SPARE0_0_REG_SHIFT                _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_CFG_SPARE0_0_REG_FIELD               (_MK_SHIFT_CONST(0xffffffff) << XUSB_DEV_XHCI_CFG_SPARE0_0_REG_SHIFT)
#define XUSB_DEV_XHCI_CFG_SPARE0_0_REG_RANGE               31:0
#define XUSB_DEV_XHCI_CFG_SPARE0_0_REG_WOFFSET             0
#define XUSB_DEV_XHCI_CFG_SPARE0_0_REG_DEFAULT             (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_SPARE0_0_REG_DEFAULT_MASK        (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_CFG_SPARE0_0_REG_SW_DEFAULT          (_MK_MASK_CONST(0x00000000)
#define XUSB_DEV_XHCI_CFG_SPARE0_0_REG_SW_DEFAULT_MASK     (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_CFG_SPARE0_0_REG_INIT                _MK_ENUM_CONST(0x00000000)


// 


#define XUSB_DEV_XHCI_CFG_SPARE1_0                         _MK_ADDR_CONST(0x00000874)
#define XUSB_DEV_XHCI_CFG_SPARE1_0_SECURE                  0
#define XUSB_DEV_XHCI_CFG_SPARE1_0_WORD_COUNT              1
#define XUSB_DEV_XHCI_CFG_SPARE1_0_RESET_VAL               _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_CFG_SPARE1_0_RESET_MASK              _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_CFG_SPARE1_0_SW_DEFAULT_VAL          _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_CFG_SPARE1_0_SW_DEFAULT_MASK         _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_CFG_SPARE1_0_READ_MASK               _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_CFG_SPARE1_0_WRITE_MASK              _MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_CFG_SPARE1_0_CLEAR_MASK              _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_SPARE1_0_TGL_MASK                _MK_MASK_CONST(0x0)
#define XUSB_DEV_XHCI_CFG_SPARE1_0_REG_SHIFT                _MK_SHIFT_CONST(0)
#define XUSB_DEV_XHCI_CFG_SPARE1_0_REG_FIELD               (_MK_SHIFT_CONST(0xffffffff) << XUSB_DEV_XHCI_CFG_SPARE1_0_REG_SHIFT)
#define XUSB_DEV_XHCI_CFG_SPARE1_0_REG_RANGE               31:0
#define XUSB_DEV_XHCI_CFG_SPARE1_0_REG_WOFFSET             0
#define XUSB_DEV_XHCI_CFG_SPARE1_0_REG_DEFAULT             (_MK_MASK_CONST(0xFFFFFFFF)
#define XUSB_DEV_XHCI_CFG_SPARE1_0_REG_DEFAULT_MASK        (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_CFG_SPARE1_0_REG_SW_DEFAULT          (_MK_MASK_CONST(0xFFFFFFFF)
#define XUSB_DEV_XHCI_CFG_SPARE1_0_REG_SW_DEFAULT_MASK     (_MK_MASK_CONST(0xffffffff)
#define XUSB_DEV_XHCI_CFG_SPARE1_0_REG_INIT                _MK_ENUM_CONST(0xFFFFFFFF)


// 
// 
// 
// 
// 
// 
// 
// 
// 
// 
// 

// REGISTER LIST

#define LIST_XUSB_DEV_XHCI_REGS(_op_) \
  _op_(XUSB_DEV_XHCI_SPARAM_0) \
  _op_(XUSB_DEV_XHCI_DB_0) \
  _op_(XUSB_DEV_XHCI_ERSTSZ_0) \
  _op_(XUSB_DEV_XHCI_RSVD0_0) \
  _op_(XUSB_DEV_XHCI_ERST0BALO_0) \
  _op_(XUSB_DEV_XHCI_ERST0BAHI_0) \
  _op_(XUSB_DEV_XHCI_ERST1BALO_0) \
  _op_(XUSB_DEV_XHCI_ERST1BAHI_0) \
  _op_(XUSB_DEV_XHCI_ERDPLO_0) \
  _op_(XUSB_DEV_XHCI_ERDPHI_0) \
  _op_(XUSB_DEV_XHCI_EREPLO_0) \
  _op_(XUSB_DEV_XHCI_EREPHI_0) \
  _op_(XUSB_DEV_XHCI_CTRL_0) \
  _op_(XUSB_DEV_XHCI_ST_0) \
  _op_(XUSB_DEV_XHCI_RT_IMOD_0) \
  _op_(XUSB_DEV_XHCI_PORTSC_0) \
  _op_(XUSB_DEV_XHCI_ECPLO_0) \
  _op_(XUSB_DEV_XHCI_ECPHI_0) \
  _op_(XUSB_DEV_XHCI_MFINDEX_0) \
  _op_(XUSB_DEV_XHCI_PORTPM_0) \
  _op_(XUSB_DEV_XHCI_EP_HALT_0) \
  _op_(XUSB_DEV_XHCI_EP_PAUSE_0) \
  _op_(XUSB_DEV_XHCI_EP_RELOAD_0) \
  _op_(XUSB_DEV_XHCI_EP_STCHG_0) \
  _op_(XUSB_DEV_XHCI_FLOWCNTRL_0) \
  _op_(XUSB_DEV_XHCI_DEVNOTIF_LO_0) \
  _op_(XUSB_DEV_XHCI_DEVNOTIF_HI_0) \
  _op_(XUSB_DEV_XHCI_PORTHALT_0) \
  _op_(XUSB_DEV_XHCI_PORT_TM_0) \
  _op_(XUSB_DEV_XHCI_EP_THREAD_ACTIVE_0) \
  _op_(XUSB_DEV_XHCI_EP_STOPPED_0) \
  _op_(XUSB_DEV_XHCI_STREAMID_CFG_0) \
  _op_(XUSB_DEV_XHCI_DEV_SOFTRST_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_COUNT0_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_COUNT1_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_COUNT2_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_COUNT3_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_COUNT4_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_COUNT5_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_COUNT6_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_COUNT7_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_COUNT8_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_COUNT9_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_COUNT10_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_COUNT11_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_COUNT12_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_COUNT13_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_CTRL_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_TESTMODE_CTRL_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN0_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN1_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN2_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN3_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN4_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN5_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN6_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN7_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN8_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN9_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN10_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN11_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN12_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN13_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN14_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_TESTMODE_PATTERN15_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_CTRL_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_PVTPORTDBG_STS_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_COUNT14_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_COUNT15_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_NVWRAP_DESER_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_CTRL1_0) \
  _op_(XUSB_DEV_XHCI_HSFSPI_COUNT16_0) \
  _op_(XUSB_DEV_XHCI_SSPI_HOSTCFG_START_0) \
  _op_(XUSB_DEV_XHCI_SSPI_HOSTCFG_END_0) \
  _op_(XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG0_0) \
  _op_(XUSB_DEV_XHCI_PERFMON_READ_CUMLATENCY_REG1_0) \
  _op_(XUSB_DEV_XHCI_PERFMON_READ_LATENCY_0) \
  _op_(XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG0_0) \
  _op_(XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BOUNDARY_REG1_0) \
  _op_(XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG0_0) \
  _op_(XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG1_0) \
  _op_(XUSB_DEV_XHCI_PERFMON_READ_HISTOGRAM_BUCKET_REG2_0) \
  _op_(XUSB_DEV_XHCI_PERFMON_BI_CTRL_0) \
  _op_(XUSB_DEV_XHCI_PERFMON_BI_EPTRB_0) \
  _op_(XUSB_DEV_XHCI_PERFMON_BI_DATA_OUT_0) \
  _op_(XUSB_DEV_XHCI_PERFMON_BI_DATA_IN_0) \
  _op_(XUSB_DEV_XHCI_BLCG_0) \
  _op_(XUSB_DEV_XHCI_BLCG_STS_0) \
  _op_(XUSB_DEV_XHCI_BLCG_INTR_0) \
  _op_(XUSB_DEV_XHCI_CFG_DEVBI_0) \
  _op_(XUSB_DEV_XHCI_CFG_DEVBI_UPSTREAM_0) \
  _op_(XUSB_DEV_XHCI_CFG_DEV_SSPI_XFER_0) \
  _op_(XUSB_DEV_XHCI_CFG_DEV_FE_0) \
  _op_(XUSB_DEV_XHCI_CFG_IDLE_0) \
  _op_(XUSB_DEV_XHCI_CFG_SSXFER_0) \
  _op_(XUSB_DEV_XHCI_CFG_SSXFER1_0) \
  _op_(XUSB_DEV_XHCI_CFG_DEVBI1_0) \
  _op_(XUSB_DEV_XHCI_CFG_SPARE0_0) \
  _op_(XUSB_DEV_XHCI_CFG_SPARE1_0) 


#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif

#endif
