/*
 * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * NVIDIA Corporation and its licensors retain all intellectual property
 * and proprietary rights in and to this software, related documentation
 * and any modifications thereto.  Any use, reproduction, disclosure or
 * distribution of this software and related documentation without an express
 * license agreement from NVIDIA Corporation is strictly prohibited.
 */

#ifndef __TEGRABL_DP_DPCD_H__
#define __TEGRABL_DP_DPCD_H__

/* DPCD definitions - from DP spec */
#define DPCD_REV                 (0x00000000)
#define DPCD_REV_MAJOR_SHIFT             (4)
#define DPCD_REV_MAJOR_MASK              (0xf << 4)
#define DPCD_REV_MINOR_SHIFT             (0)
#define DPCD_REV_MINOR_MASK              (0xf)
#define DPCD_MAX_LINK_BANDWIDTH          (0x00000001)
#define DPCD_MAX_LINK_BANDWIDTH_VAL_1_62_GPBS    (0x00000006)
#define DPCD_MAX_LINK_BANDWIDTH_VAL_2_70_GPBS    (0x0000000a)
#define DPCD_MAX_LINK_BANDWIDTH_VAL_5_40_GPBS    (0x00000014)
#define DPCD_MAX_LANE_COUNT              (0x00000002)
#define DPCD_MAX_LANE_COUNT_MASK         (0x1f)
#define DPCD_MAX_LANE_COUNT_LANE_1           (0x00000001)
#define DPCD_MAX_LANE_COUNT_LANE_2           (0x00000002)
#define DPCD_MAX_LANE_COUNT_LANE_4           (0x00000004)
#define DPCD_MAX_LANE_COUNT_TPS3_SUPPORTED_YES   (0x00000001 << 6)
#define DPCD_MAX_DOWNSPREAD_TPS4_SUPPORTED_YES  (0x00000001 << 7)
#define DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_NO  (0x00000000 << 7)
#define DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES (0x00000001 << 7)
#define DPCD_MAX_DOWNSPREAD              (0x00000003)
#define DPCD_MAX_DOWNSPREAD_VAL_NONE         (0x00000000)
#define DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT      (0x00000001)
#define DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_F    (0x00000000 << 6)
#define DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_T    (0x00000001 << 6)
#define DPCD_EDP_CONFIG_CAP              (0x0000000D)
#define DPCD_EDP_CONFIG_CAP_ASC_RESET_NO     (0x00000000)
#define DPCD_EDP_CONFIG_CAP_ASC_RESET_YES        (0x00000001)
#define DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_NO    (0x00000000 << 1)
#define DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES   (0x00000001 << 1)
#define DPCD_EDP_CONFIG_CAP_DISPLAY_CONTROL_CAP_YES  (0x00000001 << 3)
#define DPCD_TRAINING_AUX_RD_INTERVAL        (0x0000000E)
#define DPCD_TRAINING_AUX_RD_INTERVAL_MASK   (0x3f)
#define DPCD_LINK_BANDWIDTH_SET          (0x00000100)
#define DPCD_LANE_COUNT_SET              (0x00000101)
#define DPCD_LANE_COUNT_SET_MASK         (0x1f)
#define DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_F    (0x00000000 << 7)
#define DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_T    (0x00000001 << 7)
#define DPCD_TRAINING_PATTERN_SET            (0x00000102)
#define DPCD_TRAINING_PATTERN_SET_TPS_MASK       0x3
#define DPCD_TRAINING_PATTERN_SET_TPS_NONE       (0x00000000)
#define DPCD_TRAINING_PATTERN_SET_TPS_TP1        (0x00000001)
#define DPCD_TRAINING_PATTERN_SET_TPS_TP2        (0x00000002)
#define DPCD_TRAINING_PATTERN_SET_TPS_TP3        (0x00000003)
#define DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F  (0x00000000 << 5)
#define DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T  (0x00000001 << 5)
#define DPCD_TRAINING_LANE0_SET          (0x00000103)
#define DPCD_TRAINING_LANE1_SET          (0x00000104)
#define DPCD_TRAINING_LANE2_SET          (0x00000105)
#define DPCD_TRAINING_LANE3_SET          (0x00000106)
#define DPCD_TRAINING_LANEX_SET_DC_SHIFT     0
#define DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_T (0x00000001 << 2)
#define DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_F (0x00000000 << 2)
#define DPCD_TRAINING_LANEX_SET_PE_SHIFT     3
#define DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T (0x00000001 << 5)
#define DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_F (0x00000000 << 5)
#define DPCD_DOWNSPREAD_CTRL             (0x00000107)
#define DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_NONE     (0x00000000 << 4)
#define DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_LT_0_5   (0x00000001 << 4)
#define DPCD_MAIN_LINK_CHANNEL_CODING_SET        (0x00000108)
#define DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_8B10B 1
#define DPCD_EDP_CONFIG_SET              (0x0000010A)
#define DPCD_EDP_CONFIG_SET_ASC_RESET_DISABLE    (0x00000000)
#define DPCD_EDP_CONFIG_SET_ASC_RESET_ENABLE     (0x00000001)
#define DPCD_EDP_CONFIG_SET_FRAMING_CHANGE_DISABLE   (0x00000000 << 1)
#define DPCD_EDP_CONFIG_SET_FRAMING_CHANGE_ENABLE    (0x00000001 << 1)
#define DPCD_TRAINING_LANE0_1_SET2           (0x0000010F)
#define DPCD_TRAINING_LANE2_3_SET2           (0x00000110)
#define DPCD_LANEX_SET2_PC2_SHIFT            0
#define DPCD_LANEX_SET2_PC2_MAX_REACHED_T        (0x00000001 << 2)
#define DPCD_LANEX_SET2_PC2_MAX_REACHED_F        (0x00000000 << 2)
#define DPCD_LANEXPLUS1_SET2_PC2_SHIFT       4
#define DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_T   (0x00000001 << 6)
#define DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_F   (0x00000000 << 6)
#define DPCD_SINK_COUNT              (0x00000200)
#define DPCD_DEVICE_SERVICE_IRQ_VECTOR       (0x00000201)
#define DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST_NO  (0x00000000 << 1)
#define DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST_YES (0x00000001 << 1)
#define DPCD_DEVICE_SERVICE_IRQ_VECTOR_CP_NO     (0x00000000 << 2)
#define DPCD_DEVICE_SERVICE_IRQ_VECTOR_CP_YES    (0x00000001 << 2)
#define DPCD_LANE0_1_STATUS              (0x00000202)
#define DPCD_LANE2_3_STATUS              (0x00000203)
#define DPCD_STATUS_LANEX_CR_DONE_SHIFT      0
#define DPCD_STATUS_LANEX_CR_DONE_NO         (0x00000000)
#define DPCD_STATUS_LANEX_CR_DONE_YES        (0x00000001)
#define DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT      1
#define DPCD_STATUS_LANEX_CHN_EQ_DONE_NO     (0x00000000 << 1)
#define DPCD_STATUS_LANEX_CHN_EQ_DONE_YES        (0x00000001 << 1)
#define DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHIFT    2
#define DPCD_STATUS_LANEX_SYMBOL_LOCKED_NO       (0x00000000 << 2)
#define DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES      (0x00000001 << 2)
#define DPCD_STATUS_LANEXPLUS1_CR_DONE_SHIFT     4
#define DPCD_STATUS_LANEXPLUS1_CR_DONE_NO        (0x00000000 << 4)
#define DPCD_STATUS_LANEXPLUS1_CR_DONE_YES       (0x00000001 << 4)
#define DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT 5
#define DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_NO    (0x00000000 << 5)
#define DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES   (0x00000001 << 5)
#define DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT   6
#define DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_NO  (0x00000000 << 6)
#define DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES (0x00000001 << 6)
#define DPCD_LANE_ALIGN_STATUS_UPDATED       (0x00000204)
#define DPCD_LANE_ALIGN_STATUS_INTERLANE_ALIGN_DONE_NO   (0x00000000)
#define DPCD_LANE_ALIGN_STATUS_INTERLANE_ALIGN_DONE_YES  (0x00000001)
#define DPCD_LANE0_1_ADJUST_REQ          (0x00000206)
#define DPCD_LANE2_3_ADJUST_REQ          (0x00000207)
#define DPCD_ADJUST_REQ_LANEX_DC_SHIFT       0
#define DPCD_ADJUST_REQ_LANEX_DC_MASK        0x3
#define DPCD_ADJUST_REQ_LANEX_PE_SHIFT       2
#define DPCD_ADJUST_REQ_LANEX_PE_MASK        (0x3 << 2)
#define DPCD_ADJUST_REQ_LANEXPLUS1_DC_SHIFT      4
#define DPCD_ADJUST_REQ_LANEXPLUS1_DC_MASK       (0x3 << 4)
#define DPCD_ADJUST_REQ_LANEXPLUS1_PE_SHIFT      6
#define DPCD_ADJUST_REQ_LANEXPLUS1_PE_MASK       (0x3 << 6)
#define DPCD_ADJUST_REQ_POST_CURSOR2         (0x0000020C)
#define DPCD_ADJUST_REQ_POST_CURSOR2_LANE_MASK   0x3
#define DPCD_ADJUST_REQ_POST_CURSOR2_LANE_SHIFT(i)   (i*2)
#define DPCD_TEST_REQUEST                (0x00000218)
#define DPCD_TEST_REQUEST_TEST_LT            (1 << 0)
#define DPCD_TEST_REQUEST_TEST_PATTERN       (1 << 1)
#define DPCD_TEST_REQUEST_TEST_EDID_READ     (1 << 2)
#define DPCD_TEST_RESPONSE               (0x00000260)
#define DPCD_TEST_RESPONSE_ACK           (1 << 0)
#define DPCD_TEST_RESPONSE_NACK          (1 << 1)
#define DPCD_TEST_EDID_CHECKSUM_WR       (1 << 2)
#define DPCD_TEST_EDID_CHECKSUM          (0x00000261)
#define DPCD_SOURCE_IEEE_OUI             (0x00000300)
#define IEEE_OUI                 (0x00044b)
#define DPCD_SINK_IEEE_OUI               (0x00000400)
#define DPCD_BRANCH_IEEE_OUI             (0x00000500)
#define DPCD_SET_POWER               (0x00000600)
#define DPCD_SET_POWER_VAL_RESERVED          (0x00000000)
#define DPCD_SET_POWER_VAL_D0_NORMAL         (0x00000001)
#define DPCD_SET_POWER_VAL_D3_PWRDWN         (0x00000002)
#define DPCD_FEATURE_ENUM_LIST           (0x00002210)
#define DPCD_FEATURE_ENUM_LIST_VSC_EXT_COLORIMETRY   (1 << 3)
#define DPCD_HDCP_BKSV_OFFSET            (0x00068000)
#define DPCD_HDCP_RPRIME_OFFSET          (0x00068005)
#define DPCD_HDCP_AKSV_OFFSET            (0x00068007)
#define DPCD_HDCP_AN_OFFSET              (0x0006800C)
#define DPCD_HDCP_VPRIME_OFFSET          (0x00068014)
#define DPCD_HDCP_BCAPS_OFFSET           (0x00068028)
#define DPCD_HDCP_BSTATUS_OFFSET         (0x00068029)
#define DPCD_HDCP_BINFO_OFFSET           (0x0006802A)
#define DPCD_HDCP_KSV_FIFO_OFFSET            (0x0006802C)
#define DPCD_HDCP_AINFO_OFFSET           (0x0006803B)

#endif
