/*
 * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
 *
 * NVIDIA CORPORATION and its licensors retain all intellectual property
 * and proprietary rights in and to this software, related documentation
 * and any modifications thereto.  Any use, reproduction, disclosure or
 * distribution of this software and related documentation without an express
 * license agreement from NVIDIA CORPORATION is strictly prohibited
 */

#ifndef TEGRABL_NVME_ERR_AUX_H
#define TEGRABL_NVME_ERR_AUX_H

#define TEGRABL_ERR_NVME_BDEV_OPEN			0x01U
#define TEGRABL_ERR_NVME_BDEV_CLOSE			0x02U
#define TEGRABL_ERR_NVME_BDEV_READ_BLOCK	0x03U
#define TEGRABL_ERR_NVME_BDEV_WRITE_BLOCK	0x04U
#define TEGRABL_ERR_NVME_REGISTER_REGION	0x05U
#define TEGRABL_ERR_NVME_CTLR_INIT			0x06U
#define TEGRABL_ERR_NVME_PRPS				0x07U

#endif
