//
// Copyright (c) 2018 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ___ARXUSB_PADCTL_H_INC_
#define ___ARXUSB_PADCTL_H_INC_
#define NV_MOBILE_ARXUSB_PADCTL_H_UNIT_OF_OFFSET 1B


// Register XUSB_PADCTL_BOOT_MEDIA_0
#define XUSB_PADCTL_BOOT_MEDIA_0                        _MK_ADDR_CONST(0x0)
#define XUSB_PADCTL_BOOT_MEDIA_0_SECURE                         0x0
#define XUSB_PADCTL_BOOT_MEDIA_0_DUAL                   0x0
#define XUSB_PADCTL_BOOT_MEDIA_0_SCR                    0
#define XUSB_PADCTL_BOOT_MEDIA_0_WORD_COUNT                     0x1
#define XUSB_PADCTL_BOOT_MEDIA_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_BOOT_MEDIA_0_RESET_MASK                     _MK_MASK_CONST(0x1f)
#define XUSB_PADCTL_BOOT_MEDIA_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_BOOT_MEDIA_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_BOOT_MEDIA_0_READ_MASK                      _MK_MASK_CONST(0x1f)
#define XUSB_PADCTL_BOOT_MEDIA_0_WRITE_MASK                     _MK_MASK_CONST(0x1f)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_MEDIA_ENABLE_SHIFT                        _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_MEDIA_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_BOOT_MEDIA_0_BOOT_MEDIA_ENABLE_SHIFT)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_MEDIA_ENABLE_RANGE                        0:0
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_MEDIA_ENABLE_WOFFSET                      0x0
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_MEDIA_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_MEDIA_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_MEDIA_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_MEDIA_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_MEDIA_ENABLE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_MEDIA_ENABLE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_MEDIA_ENABLE_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_MEDIA_ENABLE_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_SHIFT                        _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_SHIFT)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_RANGE                        4:1
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_WOFFSET                      0x0
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_USB2_OTG0                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_USB2_OTG1                    _MK_ENUM_CONST(1)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_USB2_OTG2                    _MK_ENUM_CONST(2)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_USB2_OTG3                    _MK_ENUM_CONST(3)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_USB2_OTG4                    _MK_ENUM_CONST(4)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_USB2_OTG5                    _MK_ENUM_CONST(5)
#define XUSB_PADCTL_BOOT_MEDIA_0_BOOT_PORT_USB2_OTG6                    _MK_ENUM_CONST(6)


// Register XUSB_PADCTL_USB2_PAD_MUX_0
#define XUSB_PADCTL_USB2_PAD_MUX_0                      _MK_ADDR_CONST(0x4)
#define XUSB_PADCTL_USB2_PAD_MUX_0_SECURE                       0x0
#define XUSB_PADCTL_USB2_PAD_MUX_0_DUAL                         0x0
#define XUSB_PADCTL_USB2_PAD_MUX_0_SCR                  0
#define XUSB_PADCTL_USB2_PAD_MUX_0_WORD_COUNT                   0x1
#define XUSB_PADCTL_USB2_PAD_MUX_0_RESET_VAL                    _MK_MASK_CONST(0x55)
#define XUSB_PADCTL_USB2_PAD_MUX_0_RESET_MASK                   _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_USB2_PAD_MUX_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_READ_MASK                    _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_USB2_PAD_MUX_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT0_SHIFT                     _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT0_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT0_SHIFT)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT0_RANGE                     1:0
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT0_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT0_DEFAULT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT0_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT0_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT0_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT0_XUSB                      _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT0_SWD                       _MK_ENUM_CONST(2)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT0_UART                      _MK_ENUM_CONST(3)

#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT1_SHIFT                     _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT1_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT1_SHIFT)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT1_RANGE                     3:2
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT1_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT1_DEFAULT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT1_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT1_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT1_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT1_XUSB                      _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT1_SWD                       _MK_ENUM_CONST(2)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT1_UART                      _MK_ENUM_CONST(3)

#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT2_SHIFT                     _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT2_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT2_SHIFT)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT2_RANGE                     5:4
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT2_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT2_DEFAULT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT2_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT2_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT2_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT2_XUSB                      _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT2_SWD                       _MK_ENUM_CONST(2)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT2_UART                      _MK_ENUM_CONST(3)

#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT3_SHIFT                     _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT3_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT3_SHIFT)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT3_RANGE                     7:6
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT3_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT3_DEFAULT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT3_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT3_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT3_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT3_XUSB                      _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT3_SWD                       _MK_ENUM_CONST(2)
#define XUSB_PADCTL_USB2_PAD_MUX_0_USB2_OTG_PAD_PORT3_UART                      _MK_ENUM_CONST(3)


// Register XUSB_PADCTL_USB2_PORT_CAP_0
#define XUSB_PADCTL_USB2_PORT_CAP_0                     _MK_ADDR_CONST(0x8)
#define XUSB_PADCTL_USB2_PORT_CAP_0_SECURE                      0x0
#define XUSB_PADCTL_USB2_PORT_CAP_0_DUAL                        0x0
#define XUSB_PADCTL_USB2_PORT_CAP_0_SCR                         0
#define XUSB_PADCTL_USB2_PORT_CAP_0_WORD_COUNT                  0x1
#define XUSB_PADCTL_USB2_PORT_CAP_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_RESET_MASK                  _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_USB2_PORT_CAP_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_READ_MASK                   _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_USB2_PORT_CAP_0_WRITE_MASK                  _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_SHIFT                     _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_SHIFT)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_RANGE                     1:0
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_DISABLED                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_HOST_ONLY                 _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_DEVICE_ONLY                       _MK_ENUM_CONST(2)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_CAP_OTG_CAP                   _MK_ENUM_CONST(3)

#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_INTERNAL_SHIFT                        _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_INTERNAL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_INTERNAL_SHIFT)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_INTERNAL_RANGE                        2:2
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_INTERNAL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_INTERNAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_INTERNAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_INTERNAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_INTERNAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_INTERNAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_INTERNAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_INTERNAL_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_INTERNAL_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_REVERSE_ID_SHIFT                      _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_REVERSE_ID_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_REVERSE_ID_SHIFT)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_REVERSE_ID_RANGE                      3:3
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_REVERSE_ID_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_REVERSE_ID_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_REVERSE_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_REVERSE_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_REVERSE_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_REVERSE_ID_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_REVERSE_ID_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_REVERSE_ID_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT0_REVERSE_ID_YES                        _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_SHIFT                     _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_SHIFT)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_RANGE                     5:4
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_DISABLED                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_HOST_ONLY                 _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_DEVICE_ONLY                       _MK_ENUM_CONST(2)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_CAP_OTG_CAP                   _MK_ENUM_CONST(3)

#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_INTERNAL_SHIFT                        _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_INTERNAL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_INTERNAL_SHIFT)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_INTERNAL_RANGE                        6:6
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_INTERNAL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_INTERNAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_INTERNAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_INTERNAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_INTERNAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_INTERNAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_INTERNAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_INTERNAL_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_INTERNAL_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_REVERSE_ID_SHIFT                      _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_REVERSE_ID_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_REVERSE_ID_SHIFT)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_REVERSE_ID_RANGE                      7:7
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_REVERSE_ID_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_REVERSE_ID_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_REVERSE_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_REVERSE_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_REVERSE_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_REVERSE_ID_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_REVERSE_ID_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_REVERSE_ID_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT1_REVERSE_ID_YES                        _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_SHIFT                     _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_SHIFT)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_RANGE                     9:8
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_DISABLED                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_HOST_ONLY                 _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_DEVICE_ONLY                       _MK_ENUM_CONST(2)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_CAP_OTG_CAP                   _MK_ENUM_CONST(3)

#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_INTERNAL_SHIFT                        _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_INTERNAL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_INTERNAL_SHIFT)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_INTERNAL_RANGE                        10:10
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_INTERNAL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_INTERNAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_INTERNAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_INTERNAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_INTERNAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_INTERNAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_INTERNAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_INTERNAL_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_INTERNAL_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_REVERSE_ID_SHIFT                      _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_REVERSE_ID_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_REVERSE_ID_SHIFT)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_REVERSE_ID_RANGE                      11:11
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_REVERSE_ID_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_REVERSE_ID_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_REVERSE_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_REVERSE_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_REVERSE_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_REVERSE_ID_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_REVERSE_ID_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_REVERSE_ID_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT2_REVERSE_ID_YES                        _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_SHIFT                     _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_SHIFT)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_RANGE                     13:12
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_DISABLED                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_HOST_ONLY                 _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_DEVICE_ONLY                       _MK_ENUM_CONST(2)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_CAP_OTG_CAP                   _MK_ENUM_CONST(3)

#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_INTERNAL_SHIFT                        _MK_SHIFT_CONST(14)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_INTERNAL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_INTERNAL_SHIFT)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_INTERNAL_RANGE                        14:14
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_INTERNAL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_INTERNAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_INTERNAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_INTERNAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_INTERNAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_INTERNAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_INTERNAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_INTERNAL_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_INTERNAL_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_REVERSE_ID_SHIFT                      _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_REVERSE_ID_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_REVERSE_ID_SHIFT)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_REVERSE_ID_RANGE                      15:15
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_REVERSE_ID_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_REVERSE_ID_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_REVERSE_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_REVERSE_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_REVERSE_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_REVERSE_ID_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_REVERSE_ID_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_REVERSE_ID_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_PORT_CAP_0_PORT3_REVERSE_ID_YES                        _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_SS_PORT_CAP_0
#define XUSB_PADCTL_SS_PORT_CAP_0                       _MK_ADDR_CONST(0xc)
#define XUSB_PADCTL_SS_PORT_CAP_0_SECURE                        0x0
#define XUSB_PADCTL_SS_PORT_CAP_0_DUAL                  0x0
#define XUSB_PADCTL_SS_PORT_CAP_0_SCR                   0
#define XUSB_PADCTL_SS_PORT_CAP_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_SS_PORT_CAP_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_SS_PORT_CAP_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_READ_MASK                     _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_SS_PORT_CAP_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_SHIFT                       _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_FIELD                       _MK_FIELD_CONST(0x3, XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_SHIFT)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_RANGE                       1:0
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_WOFFSET                     0x0
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_DISABLED                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_HOST_ONLY                   _MK_ENUM_CONST(1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_DEVICE_ONLY                 _MK_ENUM_CONST(2)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_CAP_OTG_CAP                     _MK_ENUM_CONST(3)

#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_INTERNAL_SHIFT                  _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_INTERNAL_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_SS_PORT_CAP_0_PORT0_INTERNAL_SHIFT)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_INTERNAL_RANGE                  2:2
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_INTERNAL_WOFFSET                        0x0
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_INTERNAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_INTERNAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_INTERNAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_INTERNAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_INTERNAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_INTERNAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_INTERNAL_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_INTERNAL_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_REVERSE_ID_SHIFT                        _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_REVERSE_ID_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_SS_PORT_CAP_0_PORT0_REVERSE_ID_SHIFT)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_REVERSE_ID_RANGE                        3:3
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_REVERSE_ID_WOFFSET                      0x0
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_REVERSE_ID_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_REVERSE_ID_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_REVERSE_ID_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_REVERSE_ID_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_REVERSE_ID_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_REVERSE_ID_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_REVERSE_ID_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT0_REVERSE_ID_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_SHIFT                       _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_FIELD                       _MK_FIELD_CONST(0x3, XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_SHIFT)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_RANGE                       5:4
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_WOFFSET                     0x0
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_DISABLED                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_HOST_ONLY                   _MK_ENUM_CONST(1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_DEVICE_ONLY                 _MK_ENUM_CONST(2)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_CAP_OTG_CAP                     _MK_ENUM_CONST(3)

#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_INTERNAL_SHIFT                  _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_INTERNAL_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_SS_PORT_CAP_0_PORT1_INTERNAL_SHIFT)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_INTERNAL_RANGE                  6:6
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_INTERNAL_WOFFSET                        0x0
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_INTERNAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_INTERNAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_INTERNAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_INTERNAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_INTERNAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_INTERNAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_INTERNAL_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_INTERNAL_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_REVERSE_ID_SHIFT                        _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_REVERSE_ID_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_SS_PORT_CAP_0_PORT1_REVERSE_ID_SHIFT)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_REVERSE_ID_RANGE                        7:7
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_REVERSE_ID_WOFFSET                      0x0
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_REVERSE_ID_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_REVERSE_ID_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_REVERSE_ID_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_REVERSE_ID_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_REVERSE_ID_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_REVERSE_ID_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_REVERSE_ID_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT1_REVERSE_ID_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_SHIFT                       _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_FIELD                       _MK_FIELD_CONST(0x3, XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_SHIFT)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_RANGE                       9:8
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_WOFFSET                     0x0
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_DISABLED                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_HOST_ONLY                   _MK_ENUM_CONST(1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_DEVICE_ONLY                 _MK_ENUM_CONST(2)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_CAP_OTG_CAP                     _MK_ENUM_CONST(3)

#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_INTERNAL_SHIFT                  _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_INTERNAL_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_SS_PORT_CAP_0_PORT2_INTERNAL_SHIFT)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_INTERNAL_RANGE                  10:10
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_INTERNAL_WOFFSET                        0x0
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_INTERNAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_INTERNAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_INTERNAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_INTERNAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_INTERNAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_INTERNAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_INTERNAL_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_INTERNAL_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_REVERSE_ID_SHIFT                        _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_REVERSE_ID_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_SS_PORT_CAP_0_PORT2_REVERSE_ID_SHIFT)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_REVERSE_ID_RANGE                        11:11
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_REVERSE_ID_WOFFSET                      0x0
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_REVERSE_ID_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_REVERSE_ID_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_REVERSE_ID_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_REVERSE_ID_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_REVERSE_ID_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_REVERSE_ID_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_REVERSE_ID_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT2_REVERSE_ID_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_SHIFT                       _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_FIELD                       _MK_FIELD_CONST(0x3, XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_SHIFT)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_RANGE                       13:12
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_WOFFSET                     0x0
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_DISABLED                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_HOST_ONLY                   _MK_ENUM_CONST(1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_DEVICE_ONLY                 _MK_ENUM_CONST(2)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_CAP_OTG_CAP                     _MK_ENUM_CONST(3)

#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_INTERNAL_SHIFT                  _MK_SHIFT_CONST(14)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_INTERNAL_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_SS_PORT_CAP_0_PORT3_INTERNAL_SHIFT)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_INTERNAL_RANGE                  14:14
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_INTERNAL_WOFFSET                        0x0
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_INTERNAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_INTERNAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_INTERNAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_INTERNAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_INTERNAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_INTERNAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_INTERNAL_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_INTERNAL_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_REVERSE_ID_SHIFT                        _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_REVERSE_ID_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_SS_PORT_CAP_0_PORT3_REVERSE_ID_SHIFT)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_REVERSE_ID_RANGE                        15:15
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_REVERSE_ID_WOFFSET                      0x0
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_REVERSE_ID_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_REVERSE_ID_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_REVERSE_ID_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_REVERSE_ID_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_REVERSE_ID_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_REVERSE_ID_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_REVERSE_ID_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CAP_0_PORT3_REVERSE_ID_YES                  _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_USB2_OC_MAP_0
#define XUSB_PADCTL_USB2_OC_MAP_0                       _MK_ADDR_CONST(0x10)
#define XUSB_PADCTL_USB2_OC_MAP_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OC_MAP_0_DUAL                  0x0
#define XUSB_PADCTL_USB2_OC_MAP_0_SCR                   0
#define XUSB_PADCTL_USB2_OC_MAP_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OC_MAP_0_RESET_VAL                     _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_USB2_OC_MAP_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_USB2_OC_MAP_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OC_MAP_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OC_MAP_0_READ_MASK                     _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_USB2_OC_MAP_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_SHIFT                    _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_FIELD                    _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_SHIFT)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_RANGE                    3:0
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_DEFAULT                  _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED0                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED1                     _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED2                     _MK_ENUM_CONST(2)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED3                     _MK_ENUM_CONST(3)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED_VBUS_PAD0                    _MK_ENUM_CONST(4)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED_VBUS_PAD1                    _MK_ENUM_CONST(5)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED_VBUS_PAD2                    _MK_ENUM_CONST(6)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED_VBUS_PAD3                    _MK_ENUM_CONST(7)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT0_OC_PIN_OC_DETECTION_DISABLED                    _MK_ENUM_CONST(15)

#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_SHIFT                    _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_FIELD                    _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_SHIFT)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_RANGE                    7:4
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_DEFAULT                  _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED0                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED1                     _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED2                     _MK_ENUM_CONST(2)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED3                     _MK_ENUM_CONST(3)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED_VBUS_PAD0                    _MK_ENUM_CONST(4)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED_VBUS_PAD1                    _MK_ENUM_CONST(5)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED_VBUS_PAD2                    _MK_ENUM_CONST(6)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED_VBUS_PAD3                    _MK_ENUM_CONST(7)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT1_OC_PIN_OC_DETECTION_DISABLED                    _MK_ENUM_CONST(15)

#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_SHIFT                    _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_FIELD                    _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_SHIFT)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_RANGE                    11:8
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_DEFAULT                  _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED0                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED1                     _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED2                     _MK_ENUM_CONST(2)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED3                     _MK_ENUM_CONST(3)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED_VBUS_PAD0                    _MK_ENUM_CONST(4)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED_VBUS_PAD1                    _MK_ENUM_CONST(5)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED_VBUS_PAD2                    _MK_ENUM_CONST(6)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED_VBUS_PAD3                    _MK_ENUM_CONST(7)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT2_OC_PIN_OC_DETECTION_DISABLED                    _MK_ENUM_CONST(15)

#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_SHIFT                    _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_FIELD                    _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_SHIFT)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_RANGE                    15:12
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_DEFAULT                  _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED0                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED1                     _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED2                     _MK_ENUM_CONST(2)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED3                     _MK_ENUM_CONST(3)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED_VBUS_PAD0                    _MK_ENUM_CONST(4)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED_VBUS_PAD1                    _MK_ENUM_CONST(5)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED_VBUS_PAD2                    _MK_ENUM_CONST(6)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED_VBUS_PAD3                    _MK_ENUM_CONST(7)
#define XUSB_PADCTL_USB2_OC_MAP_0_PORT3_OC_PIN_OC_DETECTION_DISABLED                    _MK_ENUM_CONST(15)


// Register XUSB_PADCTL_SS_OC_MAP_0
#define XUSB_PADCTL_SS_OC_MAP_0                 _MK_ADDR_CONST(0x14)
#define XUSB_PADCTL_SS_OC_MAP_0_SECURE                  0x0
#define XUSB_PADCTL_SS_OC_MAP_0_DUAL                    0x0
#define XUSB_PADCTL_SS_OC_MAP_0_SCR                     0
#define XUSB_PADCTL_SS_OC_MAP_0_WORD_COUNT                      0x1
#define XUSB_PADCTL_SS_OC_MAP_0_RESET_VAL                       _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_SS_OC_MAP_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_SS_OC_MAP_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_OC_MAP_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_OC_MAP_0_READ_MASK                       _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_SS_OC_MAP_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_SHIFT                      _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_FIELD                      _MK_FIELD_CONST(0xf, XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_SHIFT)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_RANGE                      3:0
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_WOFFSET                    0x0
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_DEFAULT                    _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED0                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED1                       _MK_ENUM_CONST(1)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED2                       _MK_ENUM_CONST(2)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED3                       _MK_ENUM_CONST(3)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED_VBUS_PAD0                      _MK_ENUM_CONST(4)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED_VBUS_PAD1                      _MK_ENUM_CONST(5)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED_VBUS_PAD2                      _MK_ENUM_CONST(6)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_OC_DETECTED_VBUS_PAD3                      _MK_ENUM_CONST(7)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT0_OC_PIN_OC_DETECTION_DISABLED                      _MK_ENUM_CONST(15)

#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_SHIFT                      _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_FIELD                      _MK_FIELD_CONST(0xf, XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_SHIFT)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_RANGE                      7:4
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_WOFFSET                    0x0
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_DEFAULT                    _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED0                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED1                       _MK_ENUM_CONST(1)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED2                       _MK_ENUM_CONST(2)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED3                       _MK_ENUM_CONST(3)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED_VBUS_PAD0                      _MK_ENUM_CONST(4)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED_VBUS_PAD1                      _MK_ENUM_CONST(5)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED_VBUS_PAD2                      _MK_ENUM_CONST(6)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_OC_DETECTED_VBUS_PAD3                      _MK_ENUM_CONST(7)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT1_OC_PIN_OC_DETECTION_DISABLED                      _MK_ENUM_CONST(15)

#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_SHIFT                      _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_FIELD                      _MK_FIELD_CONST(0xf, XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_SHIFT)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_RANGE                      11:8
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_WOFFSET                    0x0
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_DEFAULT                    _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED0                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED1                       _MK_ENUM_CONST(1)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED2                       _MK_ENUM_CONST(2)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED3                       _MK_ENUM_CONST(3)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED_VBUS_PAD0                      _MK_ENUM_CONST(4)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED_VBUS_PAD1                      _MK_ENUM_CONST(5)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED_VBUS_PAD2                      _MK_ENUM_CONST(6)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_OC_DETECTED_VBUS_PAD3                      _MK_ENUM_CONST(7)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT2_OC_PIN_OC_DETECTION_DISABLED                      _MK_ENUM_CONST(15)

#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_SHIFT                      _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_FIELD                      _MK_FIELD_CONST(0xf, XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_SHIFT)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_RANGE                      15:12
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_WOFFSET                    0x0
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_DEFAULT                    _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED0                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED1                       _MK_ENUM_CONST(1)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED2                       _MK_ENUM_CONST(2)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED3                       _MK_ENUM_CONST(3)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED_VBUS_PAD0                      _MK_ENUM_CONST(4)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED_VBUS_PAD1                      _MK_ENUM_CONST(5)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED_VBUS_PAD2                      _MK_ENUM_CONST(6)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_OC_DETECTED_VBUS_PAD3                      _MK_ENUM_CONST(7)
#define XUSB_PADCTL_SS_OC_MAP_0_PORT3_OC_PIN_OC_DETECTION_DISABLED                      _MK_ENUM_CONST(15)


// Register XUSB_PADCTL_VBUS_OC_MAP_0
#define XUSB_PADCTL_VBUS_OC_MAP_0                       _MK_ADDR_CONST(0x18)
#define XUSB_PADCTL_VBUS_OC_MAP_0_SECURE                        0x0
#define XUSB_PADCTL_VBUS_OC_MAP_0_DUAL                  0x0
#define XUSB_PADCTL_VBUS_OC_MAP_0_SCR                   0
#define XUSB_PADCTL_VBUS_OC_MAP_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_VBUS_OC_MAP_0_RESET_VAL                     _MK_MASK_CONST(0xf7bde)
#define XUSB_PADCTL_VBUS_OC_MAP_0_RESET_MASK                    _MK_MASK_CONST(0xfffff)
#define XUSB_PADCTL_VBUS_OC_MAP_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_READ_MASK                     _MK_MASK_CONST(0xfffff)
#define XUSB_PADCTL_VBUS_OC_MAP_0_WRITE_MASK                    _MK_MASK_CONST(0xfffff)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_SHIFT                    _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_SHIFT)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_RANGE                    0:0
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_WOFFSET                  0x0
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_SHIFT                     _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_FIELD                     _MK_FIELD_CONST(0xf, XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_SHIFT)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_RANGE                     4:1
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_WOFFSET                   0x0
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_DEFAULT                   _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_OC_DETECTED0                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_OC_DETECTED1                      _MK_ENUM_CONST(1)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_OC_DETECTED2                      _MK_ENUM_CONST(2)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_OC_DETECTED3                      _MK_ENUM_CONST(3)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_OC_DETECTED_VBUS_PAD0                     _MK_ENUM_CONST(4)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_OC_DETECTED_VBUS_PAD1                     _MK_ENUM_CONST(5)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_OC_DETECTED_VBUS_PAD2                     _MK_ENUM_CONST(6)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_OC_DETECTED_VBUS_PAD3                     _MK_ENUM_CONST(7)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE0_OC_MAP_OC_DETECTION_DISABLED                     _MK_ENUM_CONST(15)

#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_SHIFT                    _MK_SHIFT_CONST(5)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_SHIFT)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_RANGE                    5:5
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_WOFFSET                  0x0
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_SHIFT                     _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_FIELD                     _MK_FIELD_CONST(0xf, XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_SHIFT)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_RANGE                     9:6
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_WOFFSET                   0x0
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_DEFAULT                   _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_OC_DETECTED0                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_OC_DETECTED1                      _MK_ENUM_CONST(1)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_OC_DETECTED2                      _MK_ENUM_CONST(2)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_OC_DETECTED3                      _MK_ENUM_CONST(3)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_OC_DETECTED_VBUS_PAD0                     _MK_ENUM_CONST(4)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_OC_DETECTED_VBUS_PAD1                     _MK_ENUM_CONST(5)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_OC_DETECTED_VBUS_PAD2                     _MK_ENUM_CONST(6)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_OC_DETECTED_VBUS_PAD3                     _MK_ENUM_CONST(7)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE1_OC_MAP_OC_DETECTION_DISABLED                     _MK_ENUM_CONST(15)

#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_SHIFT                    _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_SHIFT)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_RANGE                    10:10
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_WOFFSET                  0x0
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_SHIFT                     _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_FIELD                     _MK_FIELD_CONST(0xf, XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_SHIFT)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_RANGE                     14:11
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_WOFFSET                   0x0
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_DEFAULT                   _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_OC_DETECTED0                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_OC_DETECTED1                      _MK_ENUM_CONST(1)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_OC_DETECTED2                      _MK_ENUM_CONST(2)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_OC_DETECTED3                      _MK_ENUM_CONST(3)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_OC_DETECTED_VBUS_PAD0                     _MK_ENUM_CONST(4)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_OC_DETECTED_VBUS_PAD1                     _MK_ENUM_CONST(5)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_OC_DETECTED_VBUS_PAD2                     _MK_ENUM_CONST(6)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_OC_DETECTED_VBUS_PAD3                     _MK_ENUM_CONST(7)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE2_OC_MAP_OC_DETECTION_DISABLED                     _MK_ENUM_CONST(15)

#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_SHIFT                    _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_SHIFT)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_RANGE                    15:15
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_WOFFSET                  0x0
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_SHIFT                     _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_FIELD                     _MK_FIELD_CONST(0xf, XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_SHIFT)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_RANGE                     19:16
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_WOFFSET                   0x0
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_DEFAULT                   _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_OC_DETECTED0                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_OC_DETECTED1                      _MK_ENUM_CONST(1)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_OC_DETECTED2                      _MK_ENUM_CONST(2)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_OC_DETECTED3                      _MK_ENUM_CONST(3)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_OC_DETECTED_VBUS_PAD0                     _MK_ENUM_CONST(4)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_OC_DETECTED_VBUS_PAD1                     _MK_ENUM_CONST(5)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_OC_DETECTED_VBUS_PAD2                     _MK_ENUM_CONST(6)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_OC_DETECTED_VBUS_PAD3                     _MK_ENUM_CONST(7)
#define XUSB_PADCTL_VBUS_OC_MAP_0_VBUS_ENABLE3_OC_MAP_OC_DETECTION_DISABLED                     _MK_ENUM_CONST(15)


// Register XUSB_PADCTL_OC_DET_0
#define XUSB_PADCTL_OC_DET_0                    _MK_ADDR_CONST(0x1c)
#define XUSB_PADCTL_OC_DET_0_SECURE                     0x0
#define XUSB_PADCTL_OC_DET_0_DUAL                       0x0
#define XUSB_PADCTL_OC_DET_0_SCR                        0
#define XUSB_PADCTL_OC_DET_0_WORD_COUNT                         0x1
#define XUSB_PADCTL_OC_DET_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_RESET_MASK                         _MK_MASK_CONST(0xff0ff0f)
#define XUSB_PADCTL_OC_DET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_READ_MASK                  _MK_MASK_CONST(0xff0ff0f)
#define XUSB_PADCTL_OC_DET_0_WRITE_MASK                         _MK_MASK_CONST(0xff0ff0f)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED0_SHIFT                     _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED0_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED0_SHIFT)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED0_RANGE                     0:0
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED0_WOFFSET                   0x0
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED0_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED0_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED0_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED0_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED0_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED1_SHIFT                     _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED1_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED1_SHIFT)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED1_RANGE                     1:1
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED1_WOFFSET                   0x0
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED1_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED1_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED1_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED1_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED1_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED2_SHIFT                     _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED2_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED2_SHIFT)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED2_RANGE                     2:2
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED2_WOFFSET                   0x0
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED2_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED2_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED2_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED2_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED2_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED3_SHIFT                     _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED3_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED3_SHIFT)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED3_RANGE                     3:3
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED3_WOFFSET                   0x0
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED3_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED3_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED3_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED3_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_SET_OC_DETECTED3_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED0_SHIFT                 _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED0_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED0_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED0_RANGE                 8:8
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED0_WOFFSET                       0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED0_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED0_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED0_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED0_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED0_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED1_SHIFT                 _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED1_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED1_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED1_RANGE                 9:9
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED1_WOFFSET                       0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED1_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED1_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED1_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED1_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED1_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED2_SHIFT                 _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED2_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED2_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED2_RANGE                 10:10
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED2_WOFFSET                       0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED2_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED2_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED2_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED2_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED2_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED3_SHIFT                 _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED3_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED3_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED3_RANGE                 11:11
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED3_WOFFSET                       0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED3_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED3_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED3_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED3_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED3_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD0_SHIFT                        _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD0_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD0_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD0_RANGE                        12:12
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD0_WOFFSET                      0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD0_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD0_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD0_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD0_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD0_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD1_SHIFT                        _MK_SHIFT_CONST(13)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD1_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD1_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD1_RANGE                        13:13
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD1_WOFFSET                      0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD1_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD1_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD1_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD2_SHIFT                        _MK_SHIFT_CONST(14)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD2_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD2_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD2_RANGE                        14:14
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD2_WOFFSET                      0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD2_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD2_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD2_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD3_SHIFT                        _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD3_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD3_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD3_RANGE                        15:15
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD3_WOFFSET                      0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD3_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD3_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_VBUS_PAD3_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE0_SHIFT                        _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE0_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE0_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE0_RANGE                        20:20
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE0_WOFFSET                      0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE0_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE0_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE0_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE0_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE0_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE1_SHIFT                        _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE1_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE1_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE1_RANGE                        21:21
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE1_WOFFSET                      0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE1_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE1_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE1_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE2_SHIFT                        _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE2_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE2_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE2_RANGE                        22:22
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE2_WOFFSET                      0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE2_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE2_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE2_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE3_SHIFT                        _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE3_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE3_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE3_RANGE                        23:23
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE3_WOFFSET                      0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE3_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE3_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE3_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD0_SHIFT                        _MK_SHIFT_CONST(24)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD0_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD0_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD0_RANGE                        24:24
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD0_WOFFSET                      0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD0_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD0_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD0_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD0_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD0_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD1_SHIFT                        _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD1_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD1_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD1_RANGE                        25:25
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD1_WOFFSET                      0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD1_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD1_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD1_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD2_SHIFT                        _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD2_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD2_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD2_RANGE                        26:26
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD2_WOFFSET                      0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD2_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD2_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD2_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD3_SHIFT                        _MK_SHIFT_CONST(27)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD3_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD3_SHIFT)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD3_RANGE                        27:27
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD3_WOFFSET                      0x0
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD3_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD3_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_OC_DET_0_OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD3_YES                  _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_ELPG_PROGRAM_0_0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0                    _MK_ADDR_CONST(0x20)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SECURE                     0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_DUAL                       0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SCR                        0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_WORD_COUNT                         0x1
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_RESET_MASK                         _MK_MASK_CONST(0x1e3c78f)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_READ_MASK                  _MK_MASK_CONST(0x1e3c78f)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_WRITE_MASK                         _MK_MASK_CONST(0x1e3c78f)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKE_INTERRUPT_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKE_INTERRUPT_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKE_INTERRUPT_ENABLE_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKE_INTERRUPT_ENABLE_RANGE                     0:0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKE_INTERRUPT_ENABLE_WOFFSET                   0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKE_INTERRUPT_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKE_INTERRUPT_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKE_INTERRUPT_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKE_INTERRUPT_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKE_INTERRUPT_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKE_INTERRUPT_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKE_INTERRUPT_ENABLE_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKE_INTERRUPT_ENABLE_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKE_INTERRUPT_ENABLE_SHIFT                     _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKE_INTERRUPT_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKE_INTERRUPT_ENABLE_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKE_INTERRUPT_ENABLE_RANGE                     1:1
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKE_INTERRUPT_ENABLE_WOFFSET                   0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKE_INTERRUPT_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKE_INTERRUPT_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKE_INTERRUPT_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKE_INTERRUPT_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKE_INTERRUPT_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKE_INTERRUPT_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKE_INTERRUPT_ENABLE_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKE_INTERRUPT_ENABLE_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKE_INTERRUPT_ENABLE_SHIFT                     _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKE_INTERRUPT_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKE_INTERRUPT_ENABLE_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKE_INTERRUPT_ENABLE_RANGE                     2:2
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKE_INTERRUPT_ENABLE_WOFFSET                   0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKE_INTERRUPT_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKE_INTERRUPT_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKE_INTERRUPT_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKE_INTERRUPT_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKE_INTERRUPT_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKE_INTERRUPT_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKE_INTERRUPT_ENABLE_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKE_INTERRUPT_ENABLE_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKE_INTERRUPT_ENABLE_SHIFT                     _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKE_INTERRUPT_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKE_INTERRUPT_ENABLE_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKE_INTERRUPT_ENABLE_RANGE                     3:3
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKE_INTERRUPT_ENABLE_WOFFSET                   0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKE_INTERRUPT_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKE_INTERRUPT_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKE_INTERRUPT_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKE_INTERRUPT_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKE_INTERRUPT_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKE_INTERRUPT_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKE_INTERRUPT_ENABLE_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKE_INTERRUPT_ENABLE_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKEUP_EVENT_SHIFT                      _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKEUP_EVENT_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKEUP_EVENT_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKEUP_EVENT_RANGE                      7:7
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKEUP_EVENT_WOFFSET                    0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKEUP_EVENT_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKEUP_EVENT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKEUP_EVENT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKEUP_EVENT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKEUP_EVENT_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKEUP_EVENT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKEUP_EVENT_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT0_WAKEUP_EVENT_YES                        _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKEUP_EVENT_SHIFT                      _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKEUP_EVENT_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKEUP_EVENT_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKEUP_EVENT_RANGE                      8:8
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKEUP_EVENT_WOFFSET                    0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKEUP_EVENT_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKEUP_EVENT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKEUP_EVENT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKEUP_EVENT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKEUP_EVENT_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKEUP_EVENT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKEUP_EVENT_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT1_WAKEUP_EVENT_YES                        _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKEUP_EVENT_SHIFT                      _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKEUP_EVENT_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKEUP_EVENT_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKEUP_EVENT_RANGE                      9:9
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKEUP_EVENT_WOFFSET                    0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKEUP_EVENT_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKEUP_EVENT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKEUP_EVENT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKEUP_EVENT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKEUP_EVENT_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKEUP_EVENT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKEUP_EVENT_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT2_WAKEUP_EVENT_YES                        _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKEUP_EVENT_SHIFT                      _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKEUP_EVENT_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKEUP_EVENT_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKEUP_EVENT_RANGE                      10:10
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKEUP_EVENT_WOFFSET                    0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKEUP_EVENT_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKEUP_EVENT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKEUP_EVENT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKEUP_EVENT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKEUP_EVENT_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKEUP_EVENT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKEUP_EVENT_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_USB2_PORT3_WAKEUP_EVENT_YES                        _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKE_INTERRUPT_ENABLE_SHIFT                       _MK_SHIFT_CONST(14)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKE_INTERRUPT_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKE_INTERRUPT_ENABLE_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKE_INTERRUPT_ENABLE_RANGE                       14:14
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKE_INTERRUPT_ENABLE_WOFFSET                     0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKE_INTERRUPT_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKE_INTERRUPT_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKE_INTERRUPT_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKE_INTERRUPT_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKE_INTERRUPT_ENABLE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKE_INTERRUPT_ENABLE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKE_INTERRUPT_ENABLE_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKE_INTERRUPT_ENABLE_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKE_INTERRUPT_ENABLE_SHIFT                       _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKE_INTERRUPT_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKE_INTERRUPT_ENABLE_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKE_INTERRUPT_ENABLE_RANGE                       15:15
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKE_INTERRUPT_ENABLE_WOFFSET                     0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKE_INTERRUPT_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKE_INTERRUPT_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKE_INTERRUPT_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKE_INTERRUPT_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKE_INTERRUPT_ENABLE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKE_INTERRUPT_ENABLE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKE_INTERRUPT_ENABLE_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKE_INTERRUPT_ENABLE_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKE_INTERRUPT_ENABLE_SHIFT                       _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKE_INTERRUPT_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKE_INTERRUPT_ENABLE_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKE_INTERRUPT_ENABLE_RANGE                       16:16
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKE_INTERRUPT_ENABLE_WOFFSET                     0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKE_INTERRUPT_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKE_INTERRUPT_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKE_INTERRUPT_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKE_INTERRUPT_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKE_INTERRUPT_ENABLE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKE_INTERRUPT_ENABLE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKE_INTERRUPT_ENABLE_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKE_INTERRUPT_ENABLE_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKE_INTERRUPT_ENABLE_SHIFT                       _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKE_INTERRUPT_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKE_INTERRUPT_ENABLE_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKE_INTERRUPT_ENABLE_RANGE                       17:17
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKE_INTERRUPT_ENABLE_WOFFSET                     0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKE_INTERRUPT_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKE_INTERRUPT_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKE_INTERRUPT_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKE_INTERRUPT_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKE_INTERRUPT_ENABLE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKE_INTERRUPT_ENABLE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKE_INTERRUPT_ENABLE_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKE_INTERRUPT_ENABLE_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKEUP_EVENT_SHIFT                        _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKEUP_EVENT_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKEUP_EVENT_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKEUP_EVENT_RANGE                        21:21
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKEUP_EVENT_WOFFSET                      0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKEUP_EVENT_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKEUP_EVENT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKEUP_EVENT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKEUP_EVENT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKEUP_EVENT_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKEUP_EVENT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKEUP_EVENT_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT0_WAKEUP_EVENT_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKEUP_EVENT_SHIFT                        _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKEUP_EVENT_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKEUP_EVENT_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKEUP_EVENT_RANGE                        22:22
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKEUP_EVENT_WOFFSET                      0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKEUP_EVENT_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKEUP_EVENT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKEUP_EVENT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKEUP_EVENT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKEUP_EVENT_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKEUP_EVENT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKEUP_EVENT_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT1_WAKEUP_EVENT_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKEUP_EVENT_SHIFT                        _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKEUP_EVENT_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKEUP_EVENT_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKEUP_EVENT_RANGE                        23:23
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKEUP_EVENT_WOFFSET                      0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKEUP_EVENT_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKEUP_EVENT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKEUP_EVENT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKEUP_EVENT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKEUP_EVENT_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKEUP_EVENT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKEUP_EVENT_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT2_WAKEUP_EVENT_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKEUP_EVENT_SHIFT                        _MK_SHIFT_CONST(24)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKEUP_EVENT_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKEUP_EVENT_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKEUP_EVENT_RANGE                        24:24
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKEUP_EVENT_WOFFSET                      0x0
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKEUP_EVENT_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKEUP_EVENT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKEUP_EVENT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKEUP_EVENT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKEUP_EVENT_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKEUP_EVENT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKEUP_EVENT_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_0_0_SS_PORT3_WAKEUP_EVENT_YES                  _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_ELPG_PROGRAM_1_0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0                    _MK_ADDR_CONST(0x24)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SECURE                     0x0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_DUAL                       0x0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SCR                        0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_WORD_COUNT                         0x1
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_RESET_VAL                  _MK_MASK_CONST(0xfff)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_RESET_MASK                         _MK_MASK_CONST(0xfff)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_READ_MASK                  _MK_MASK_CONST(0xfff)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_WRITE_MASK                         _MK_MASK_CONST(0xfff)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_SHIFT                   _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_RANGE                   0:0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_WOFFSET                 0x0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_EARLY_SHIFT                     _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_EARLY_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_EARLY_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_EARLY_RANGE                     1:1
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_EARLY_WOFFSET                   0x0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_EARLY_DEFAULT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_EARLY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_EARLY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_EARLY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_EARLY_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_EARLY_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_EARLY_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_CLAMP_EN_EARLY_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_VCORE_DOWN_SHIFT                 _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_VCORE_DOWN_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_VCORE_DOWN_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_VCORE_DOWN_RANGE                 2:2
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_VCORE_DOWN_WOFFSET                       0x0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_VCORE_DOWN_DEFAULT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_VCORE_DOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_VCORE_DOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_VCORE_DOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_VCORE_DOWN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_VCORE_DOWN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_VCORE_DOWN_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP0_ELPG_VCORE_DOWN_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_SHIFT                   _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_RANGE                   3:3
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_WOFFSET                 0x0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_EARLY_SHIFT                     _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_EARLY_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_EARLY_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_EARLY_RANGE                     4:4
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_EARLY_WOFFSET                   0x0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_EARLY_DEFAULT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_EARLY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_EARLY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_EARLY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_EARLY_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_EARLY_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_EARLY_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_CLAMP_EN_EARLY_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_VCORE_DOWN_SHIFT                 _MK_SHIFT_CONST(5)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_VCORE_DOWN_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_VCORE_DOWN_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_VCORE_DOWN_RANGE                 5:5
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_VCORE_DOWN_WOFFSET                       0x0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_VCORE_DOWN_DEFAULT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_VCORE_DOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_VCORE_DOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_VCORE_DOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_VCORE_DOWN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_VCORE_DOWN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_VCORE_DOWN_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP1_ELPG_VCORE_DOWN_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_SHIFT                   _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_RANGE                   6:6
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_WOFFSET                 0x0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_EARLY_SHIFT                     _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_EARLY_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_EARLY_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_EARLY_RANGE                     7:7
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_EARLY_WOFFSET                   0x0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_EARLY_DEFAULT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_EARLY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_EARLY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_EARLY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_EARLY_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_EARLY_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_EARLY_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_CLAMP_EN_EARLY_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_VCORE_DOWN_SHIFT                 _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_VCORE_DOWN_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_VCORE_DOWN_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_VCORE_DOWN_RANGE                 8:8
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_VCORE_DOWN_WOFFSET                       0x0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_VCORE_DOWN_DEFAULT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_VCORE_DOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_VCORE_DOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_VCORE_DOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_VCORE_DOWN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_VCORE_DOWN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_VCORE_DOWN_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP2_ELPG_VCORE_DOWN_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_SHIFT                   _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_RANGE                   9:9
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_WOFFSET                 0x0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_EARLY_SHIFT                     _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_EARLY_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_EARLY_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_EARLY_RANGE                     10:10
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_EARLY_WOFFSET                   0x0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_EARLY_DEFAULT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_EARLY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_EARLY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_EARLY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_EARLY_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_EARLY_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_EARLY_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_CLAMP_EN_EARLY_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_VCORE_DOWN_SHIFT                 _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_VCORE_DOWN_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_VCORE_DOWN_SHIFT)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_VCORE_DOWN_RANGE                 11:11
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_VCORE_DOWN_WOFFSET                       0x0
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_VCORE_DOWN_DEFAULT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_VCORE_DOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_VCORE_DOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_VCORE_DOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_VCORE_DOWN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_VCORE_DOWN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_VCORE_DOWN_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_ELPG_PROGRAM_1_0_SSP3_ELPG_VCORE_DOWN_YES                   _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_PM_SPARE_0
#define XUSB_PADCTL_PM_SPARE_0                  _MK_ADDR_CONST(0x28)
#define XUSB_PADCTL_PM_SPARE_0_SECURE                   0x0
#define XUSB_PADCTL_PM_SPARE_0_DUAL                     0x0
#define XUSB_PADCTL_PM_SPARE_0_SCR                      0
#define XUSB_PADCTL_PM_SPARE_0_WORD_COUNT                       0x1
#define XUSB_PADCTL_PM_SPARE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_RESET_MASK                       _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_PM_SPARE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_READ_MASK                        _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_PM_SPARE_0_WRITE_MASK                       _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT0_SHIFT                  _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT0_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT0_SHIFT)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT0_RANGE                  0:0
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT0_WOFFSET                        0x0
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT0_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT0_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT0_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT1_SHIFT                  _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT1_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT1_SHIFT)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT1_RANGE                  1:1
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT1_WOFFSET                        0x0
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT1_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT1_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT1_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT2_SHIFT                  _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT2_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT2_SHIFT)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT2_RANGE                  2:2
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT2_WOFFSET                        0x0
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT2_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT2_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT2_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT3_SHIFT                  _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT3_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT3_SHIFT)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT3_RANGE                  3:3
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT3_WOFFSET                        0x0
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT3_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT3_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_PM_SPARE_0_OTG_PM_SPARE_BIT3_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register XUSB_PADCTL_SS_PORT_CFG_0
#define XUSB_PADCTL_SS_PORT_CFG_0                       _MK_ADDR_CONST(0x2c)
#define XUSB_PADCTL_SS_PORT_CFG_0_SECURE                        0x0
#define XUSB_PADCTL_SS_PORT_CFG_0_DUAL                  0x0
#define XUSB_PADCTL_SS_PORT_CFG_0_SCR                   0
#define XUSB_PADCTL_SS_PORT_CFG_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_SS_PORT_CFG_0_RESET_VAL                     _MK_MASK_CONST(0x1111)
#define XUSB_PADCTL_SS_PORT_CFG_0_RESET_MASK                    _MK_MASK_CONST(0x3333)
#define XUSB_PADCTL_SS_PORT_CFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CFG_0_READ_MASK                     _MK_MASK_CONST(0x3333)
#define XUSB_PADCTL_SS_PORT_CFG_0_WRITE_MASK                    _MK_MASK_CONST(0x3333)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT0_SPEED_SUPPORT_SHIFT                     _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT0_SPEED_SUPPORT_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_SS_PORT_CFG_0_PORT0_SPEED_SUPPORT_SHIFT)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT0_SPEED_SUPPORT_RANGE                     1:0
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT0_SPEED_SUPPORT_WOFFSET                   0x0
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT0_SPEED_SUPPORT_DEFAULT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT0_SPEED_SUPPORT_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT0_SPEED_SUPPORT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT0_SPEED_SUPPORT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT0_SPEED_SUPPORT_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT0_SPEED_SUPPORT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT0_SPEED_SUPPORT_GEN1_5G                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT0_SPEED_SUPPORT_GEN2_10G                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_SS_PORT_CFG_0_PORT1_SPEED_SUPPORT_SHIFT                     _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT1_SPEED_SUPPORT_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_SS_PORT_CFG_0_PORT1_SPEED_SUPPORT_SHIFT)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT1_SPEED_SUPPORT_RANGE                     5:4
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT1_SPEED_SUPPORT_WOFFSET                   0x0
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT1_SPEED_SUPPORT_DEFAULT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT1_SPEED_SUPPORT_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT1_SPEED_SUPPORT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT1_SPEED_SUPPORT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT1_SPEED_SUPPORT_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT1_SPEED_SUPPORT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT1_SPEED_SUPPORT_GEN1_5G                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT1_SPEED_SUPPORT_GEN2_10G                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_SS_PORT_CFG_0_PORT2_SPEED_SUPPORT_SHIFT                     _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT2_SPEED_SUPPORT_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_SS_PORT_CFG_0_PORT2_SPEED_SUPPORT_SHIFT)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT2_SPEED_SUPPORT_RANGE                     9:8
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT2_SPEED_SUPPORT_WOFFSET                   0x0
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT2_SPEED_SUPPORT_DEFAULT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT2_SPEED_SUPPORT_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT2_SPEED_SUPPORT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT2_SPEED_SUPPORT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT2_SPEED_SUPPORT_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT2_SPEED_SUPPORT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT2_SPEED_SUPPORT_GEN1_5G                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT2_SPEED_SUPPORT_GEN2_10G                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_SS_PORT_CFG_0_PORT3_SPEED_SUPPORT_SHIFT                     _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT3_SPEED_SUPPORT_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_SS_PORT_CFG_0_PORT3_SPEED_SUPPORT_SHIFT)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT3_SPEED_SUPPORT_RANGE                     13:12
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT3_SPEED_SUPPORT_WOFFSET                   0x0
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT3_SPEED_SUPPORT_DEFAULT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT3_SPEED_SUPPORT_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT3_SPEED_SUPPORT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT3_SPEED_SUPPORT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT3_SPEED_SUPPORT_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT3_SPEED_SUPPORT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT3_SPEED_SUPPORT_GEN1_5G                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_SS_PORT_CFG_0_PORT3_SPEED_SUPPORT_GEN2_10G                  _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_USB2_VBUS_ID_MAP_0
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0                  _MK_ADDR_CONST(0x30)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_SECURE                   0x0
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_DUAL                     0x0
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_SCR                      0
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_WORD_COUNT                       0x1
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_RESET_MASK                       _MK_MASK_CONST(0x7777)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_READ_MASK                        _MK_MASK_CONST(0x7777)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_WRITE_MASK                       _MK_MASK_CONST(0x7777)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT0_VBUS_ID_NUM_SHIFT                  _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT0_VBUS_ID_NUM_FIELD                  _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT0_VBUS_ID_NUM_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT0_VBUS_ID_NUM_RANGE                  2:0
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT0_VBUS_ID_NUM_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT0_VBUS_ID_NUM_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT0_VBUS_ID_NUM_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT0_VBUS_ID_NUM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT0_VBUS_ID_NUM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT0_VBUS_ID_NUM_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT0_VBUS_ID_NUM_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT1_VBUS_ID_NUM_SHIFT                  _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT1_VBUS_ID_NUM_FIELD                  _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT1_VBUS_ID_NUM_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT1_VBUS_ID_NUM_RANGE                  6:4
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT1_VBUS_ID_NUM_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT1_VBUS_ID_NUM_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT1_VBUS_ID_NUM_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT1_VBUS_ID_NUM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT1_VBUS_ID_NUM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT1_VBUS_ID_NUM_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT1_VBUS_ID_NUM_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT2_VBUS_ID_NUM_SHIFT                  _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT2_VBUS_ID_NUM_FIELD                  _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT2_VBUS_ID_NUM_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT2_VBUS_ID_NUM_RANGE                  10:8
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT2_VBUS_ID_NUM_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT2_VBUS_ID_NUM_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT2_VBUS_ID_NUM_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT2_VBUS_ID_NUM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT2_VBUS_ID_NUM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT2_VBUS_ID_NUM_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT2_VBUS_ID_NUM_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT3_VBUS_ID_NUM_SHIFT                  _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT3_VBUS_ID_NUM_FIELD                  _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT3_VBUS_ID_NUM_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT3_VBUS_ID_NUM_RANGE                  14:12
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT3_VBUS_ID_NUM_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT3_VBUS_ID_NUM_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT3_VBUS_ID_NUM_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT3_VBUS_ID_NUM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT3_VBUS_ID_NUM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT3_VBUS_ID_NUM_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_MAP_0_PORT3_VBUS_ID_NUM_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register XUSB_PADCTL_SS_VBUS_ID_MAP_0
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0                    _MK_ADDR_CONST(0x34)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_SECURE                     0x0
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_DUAL                       0x0
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_SCR                        0
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_WORD_COUNT                         0x1
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_RESET_MASK                         _MK_MASK_CONST(0x7777)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_READ_MASK                  _MK_MASK_CONST(0x7777)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_WRITE_MASK                         _MK_MASK_CONST(0x7777)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT0_VBUS_ID_NUM_SHIFT                    _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT0_VBUS_ID_NUM_FIELD                    _MK_FIELD_CONST(0x7, XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT0_VBUS_ID_NUM_SHIFT)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT0_VBUS_ID_NUM_RANGE                    2:0
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT0_VBUS_ID_NUM_WOFFSET                  0x0
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT0_VBUS_ID_NUM_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT0_VBUS_ID_NUM_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT0_VBUS_ID_NUM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT0_VBUS_ID_NUM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT0_VBUS_ID_NUM_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT0_VBUS_ID_NUM_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT1_VBUS_ID_NUM_SHIFT                    _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT1_VBUS_ID_NUM_FIELD                    _MK_FIELD_CONST(0x7, XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT1_VBUS_ID_NUM_SHIFT)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT1_VBUS_ID_NUM_RANGE                    6:4
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT1_VBUS_ID_NUM_WOFFSET                  0x0
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT1_VBUS_ID_NUM_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT1_VBUS_ID_NUM_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT1_VBUS_ID_NUM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT1_VBUS_ID_NUM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT1_VBUS_ID_NUM_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT1_VBUS_ID_NUM_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT2_VBUS_ID_NUM_SHIFT                    _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT2_VBUS_ID_NUM_FIELD                    _MK_FIELD_CONST(0x7, XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT2_VBUS_ID_NUM_SHIFT)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT2_VBUS_ID_NUM_RANGE                    10:8
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT2_VBUS_ID_NUM_WOFFSET                  0x0
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT2_VBUS_ID_NUM_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT2_VBUS_ID_NUM_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT2_VBUS_ID_NUM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT2_VBUS_ID_NUM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT2_VBUS_ID_NUM_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT2_VBUS_ID_NUM_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT3_VBUS_ID_NUM_SHIFT                    _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT3_VBUS_ID_NUM_FIELD                    _MK_FIELD_CONST(0x7, XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT3_VBUS_ID_NUM_SHIFT)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT3_VBUS_ID_NUM_RANGE                    14:12
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT3_VBUS_ID_NUM_WOFFSET                  0x0
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT3_VBUS_ID_NUM_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT3_VBUS_ID_NUM_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT3_VBUS_ID_NUM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT3_VBUS_ID_NUM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT3_VBUS_ID_NUM_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_SS_VBUS_ID_MAP_0_PORT3_VBUS_ID_NUM_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Reserved address 0x38

// Reserved address 0x3c

// Reserved address 0x40

// Reserved address 0x44

// Reserved address 0x48

// Reserved address 0x4c

// Reserved address 0x50

// Reserved address 0x54

// Reserved address 0x58

// Reserved address 0x5c

// Reserved address 0x60

// Reserved address 0x64

// Reserved address 0x68

// Reserved address 0x6c

// Reserved address 0x70

// Reserved address 0x74

// Reserved address 0x78

// Reserved address 0x7c

// Register XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0                    _MK_ADDR_CONST(0x80)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SECURE                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DUAL                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SCR                        0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_WORD_COUNT                         0x1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_RESET_MASK                         _MK_MASK_CONST(0xfffc3fff)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_READ_MASK                  _MK_MASK_CONST(0xfffc3fff)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_WRITE_MASK                         _MK_MASK_CONST(0xffb83fdd)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_PD_CHG_SHIFT                       _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_PD_CHG_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_PD_CHG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_PD_CHG_RANGE                       0:0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_PD_CHG_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_PD_CHG_DEFAULT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_PD_CHG_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_PD_CHG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_PD_CHG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_PD_CHG_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_PD_CHG_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_PD_CHG_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_PD_CHG_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_SHIFT                     _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_RANGE                     1:1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_ST_CHNG_SHIFT                     _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_ST_CHNG_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_ST_CHNG_RANGE                     2:2
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_ST_CHNG_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_ST_CHNG_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_ST_CHNG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_ST_CHNG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_ST_CHNG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_ST_CHNG_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_ST_CHNG_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_ST_CHNG_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_ST_CHNG_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_CHNG_INTR_EN_SHIFT                        _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_CHNG_INTR_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_CHNG_INTR_EN_RANGE                        3:3
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_CHNG_INTR_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_CHNG_INTR_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_CHNG_INTR_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_CHNG_INTR_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_CHNG_INTR_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_CHNG_INTR_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_CHNG_INTR_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_CHNG_INTR_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_CHNG_INTR_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_FILTER_EN_SHIFT                   _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_FILTER_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_FILTER_EN_RANGE                   4:4
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_FILTER_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_FILTER_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_FILTER_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_FILTER_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_FILTER_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_FILTER_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_FILTER_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_FILTER_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDCD_DET_FILTER_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_SHIFT                     _MK_SHIFT_CONST(5)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_RANGE                     5:5
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_ST_CHNG_SHIFT                     _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_ST_CHNG_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_ST_CHNG_RANGE                     6:6
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_ST_CHNG_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_ST_CHNG_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_ST_CHNG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_ST_CHNG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_ST_CHNG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_ST_CHNG_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_ST_CHNG_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_ST_CHNG_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_ST_CHNG_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_CHNG_INTR_EN_SHIFT                        _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_CHNG_INTR_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_CHNG_INTR_EN_RANGE                        7:7
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_CHNG_INTR_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_CHNG_INTR_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_CHNG_INTR_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_CHNG_INTR_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_CHNG_INTR_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_CHNG_INTR_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_CHNG_INTR_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_CHNG_INTR_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_CHNG_INTR_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_FILTER_EN_SHIFT                   _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_FILTER_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_FILTER_EN_RANGE                   8:8
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_FILTER_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_FILTER_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_FILTER_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_FILTER_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_FILTER_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_FILTER_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_FILTER_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_FILTER_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_VDAT_DET_FILTER_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SINK_EN_SHIFT                   _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SINK_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SINK_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SINK_EN_RANGE                   9:9
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SINK_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SINK_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SINK_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SINK_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SINK_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SRC_EN_SHIFT                    _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SRC_EN_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SRC_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SRC_EN_RANGE                    10:10
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SRC_EN_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SRC_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SRC_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SRC_EN_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_SRC_EN_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SINK_EN_SHIFT                   _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SINK_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SINK_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SINK_EN_RANGE                   11:11
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SINK_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SINK_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SINK_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SINK_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SINK_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SRC_EN_SHIFT                    _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SRC_EN_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SRC_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SRC_EN_RANGE                    12:12
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SRC_EN_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SRC_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SRC_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SRC_EN_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ON_SRC_EN_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_I_SRC_EN_SHIFT                  _MK_SHIFT_CONST(13)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_I_SRC_EN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_I_SRC_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_I_SRC_EN_RANGE                  13:13
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_I_SRC_EN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_I_SRC_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_I_SRC_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_I_SRC_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_I_SRC_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_I_SRC_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_I_SRC_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_I_SRC_EN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_OP_I_SRC_EN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_SHIFT                  _MK_SHIFT_CONST(18)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_RANGE                  18:18
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_ST_CHNG_SHIFT                  _MK_SHIFT_CONST(19)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_ST_CHNG_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_ST_CHNG_RANGE                  19:19
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_ST_CHNG_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_ST_CHNG_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_ST_CHNG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_ST_CHNG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_ST_CHNG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_ST_CHNG_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_ST_CHNG_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_ST_CHNG_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_ST_CHNG_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_CHNG_INTR_EN_SHIFT                     _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_CHNG_INTR_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_CHNG_INTR_EN_RANGE                     20:20
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_CHNG_INTR_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_CHNG_INTR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_CHNG_INTR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_CHNG_INTR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_CHNG_INTR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_CHNG_INTR_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_CHNG_INTR_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_CHNG_INTR_EN_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_CHNG_INTR_EN_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_FILTER_EN_SHIFT                        _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_FILTER_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_FILTER_EN_RANGE                        21:21
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_FILTER_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_FILTER_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_FILTER_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_FILTER_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_FILTER_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_FILTER_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_FILTER_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_FILTER_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIP_FILTER_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_SHIFT                  _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_RANGE                  22:22
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_ST_CHNG_SHIFT                  _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_ST_CHNG_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_ST_CHNG_RANGE                  23:23
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_ST_CHNG_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_ST_CHNG_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_ST_CHNG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_ST_CHNG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_ST_CHNG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_ST_CHNG_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_ST_CHNG_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_ST_CHNG_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_ST_CHNG_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_CHNG_INTR_EN_SHIFT                     _MK_SHIFT_CONST(24)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_CHNG_INTR_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_CHNG_INTR_EN_RANGE                     24:24
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_CHNG_INTR_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_CHNG_INTR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_CHNG_INTR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_CHNG_INTR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_CHNG_INTR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_CHNG_INTR_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_CHNG_INTR_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_CHNG_INTR_EN_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_CHNG_INTR_EN_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_FILTER_EN_SHIFT                        _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_FILTER_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_FILTER_EN_RANGE                        25:25
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_FILTER_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_FILTER_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_FILTER_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_FILTER_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_FILTER_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_FILTER_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_FILTER_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_FILTER_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_ZIN_FILTER_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_DETECTED_SHIFT                 _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_DETECTED_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_DETECTED_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_DETECTED_RANGE                 26:26
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_DETECTED_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_DETECTED_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_DETECTED_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_DETECTED_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_DETECTED_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_DETECTED_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_DETECTED_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_DETECTED_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_DETECTED_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_INTR_EN_SHIFT                  _MK_SHIFT_CONST(27)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_INTR_EN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_INTR_EN_RANGE                  27:27
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_INTR_EN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_INTR_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_INTR_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_INTR_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_INTR_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_INTR_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_INTR_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_INTR_EN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_DCD_INTR_EN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECT_EN_SHIFT                        _MK_SHIFT_CONST(28)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECT_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECT_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECT_EN_RANGE                        28:28
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECT_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECT_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECT_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECT_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECT_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECTED_SHIFT                 _MK_SHIFT_CONST(29)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECTED_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECTED_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECTED_RANGE                 29:29
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECTED_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECTED_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECTED_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECTED_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECTED_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECTED_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECTED_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECTED_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_DETECTED_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_INTR_EN_SHIFT                  _MK_SHIFT_CONST(30)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_INTR_EN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_INTR_EN_RANGE                  30:30
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_INTR_EN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_INTR_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_INTR_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_INTR_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_INTR_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_INTR_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_INTR_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_INTR_EN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_SRP_INTR_EN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_GENERATE_SRP_SHIFT                 _MK_SHIFT_CONST(31)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_GENERATE_SRP_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_GENERATE_SRP_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_GENERATE_SRP_RANGE                 31:31
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_GENERATE_SRP_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_GENERATE_SRP_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_GENERATE_SRP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_GENERATE_SRP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_GENERATE_SRP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_GENERATE_SRP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_GENERATE_SRP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_GENERATE_SRP_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0_GENERATE_SRP_YES                   _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0                    _MK_ADDR_CONST(0x84)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_SECURE                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_DUAL                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_SCR                        0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_WORD_COUNT                         0x1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_RESET_VAL                  _MK_MASK_CONST(0x40)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_RESET_MASK                         _MK_MASK_CONST(0xff1fdf)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_READ_MASK                  _MK_MASK_CONST(0xff1fdf)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_WRITE_MASK                         _MK_MASK_CONST(0xff1fd0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P0_DET_SHIFT                       _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P0_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P0_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P0_DET_RANGE                       0:0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P0_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P0_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P0_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P0_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P0_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P0_DET_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P0_DET_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P0_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P0_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P7_DET_SHIFT                       _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P7_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P7_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P7_DET_RANGE                       1:1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P7_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P7_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P7_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P7_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P7_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P7_DET_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P7_DET_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P7_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VON_DIV2P7_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P0_DET_SHIFT                       _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P0_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P0_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P0_DET_RANGE                       2:2
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P0_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P0_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P0_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P0_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P0_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P0_DET_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P0_DET_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P0_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P0_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P7_DET_SHIFT                       _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P7_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P7_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P7_DET_RANGE                       3:3
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P7_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P7_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P7_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P7_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P7_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P7_DET_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P7_DET_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P7_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VOP_DIV2P7_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_DIV_DET_EN_SHIFT                   _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_DIV_DET_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_DIV_DET_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_DIV_DET_EN_RANGE                   4:4
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_DIV_DET_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_DIV_DET_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_DIV_DET_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_DIV_DET_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_DIV_DET_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_DIV_DET_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_DIV_DET_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_DIV_DET_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_DIV_DET_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_PD_VREG_SHIFT                      _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_PD_VREG_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_PD_VREG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_PD_VREG_RANGE                      6:6
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_PD_VREG_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_PD_VREG_DEFAULT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_PD_VREG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_PD_VREG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_PD_VREG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_PD_VREG_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_PD_VREG_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_LEV_SHIFT                     _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_LEV_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_LEV_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_LEV_RANGE                     8:7
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_LEV_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_LEV_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_LEV_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_LEV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_LEV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_LEV_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_LEV_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DYN_DLY_SHIFT                 _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DYN_DLY_FIELD                 _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DYN_DLY_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DYN_DLY_RANGE                 10:9
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DYN_DLY_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DYN_DLY_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DYN_DLY_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DYN_DLY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DYN_DLY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DYN_DLY_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DYN_DLY_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DIR_SHIFT                     _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DIR_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DIR_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DIR_RANGE                     12:11
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DIR_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DIR_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DIR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DIR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DIR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DIR_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_VREG_DIR_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_SHIFT                       _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_RANGE                       16:16
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_VAL_RANGE                   17:17
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPD_OVRD_VAL_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_SHIFT                       _MK_SHIFT_CONST(18)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_RANGE                       18:18
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(19)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_VAL_RANGE                   19:19
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBOP_RPU_OVRD_VAL_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_SHIFT                       _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_RANGE                       20:20
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_VAL_RANGE                   21:21
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPD_OVRD_VAL_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_SHIFT                       _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_RANGE                       22:22
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_VAL_RANGE                   23:23
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0_USBON_RPU_OVRD_VAL_YES                     _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0                       _MK_ADDR_CONST(0x88)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_DUAL                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_RESET_VAL                     _MK_MASK_CONST(0x26cc88e0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_RESET_MASK                    _MK_MASK_CONST(0x3fffffff)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_READ_MASK                     _MK_MASK_CONST(0x3fffffff)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_WRITE_MASK                    _MK_MASK_CONST(0x3fffffff)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_CURR_LEVEL_SHIFT                   _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_CURR_LEVEL_FIELD                   _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_CURR_LEVEL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_CURR_LEVEL_RANGE                   5:0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_CURR_LEVEL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_CURR_LEVEL_DEFAULT                 _MK_MASK_CONST(0x20)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_CURR_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_CURR_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_CURR_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_CURR_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_CURR_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_SLEW_SHIFT                 _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_SLEW_FIELD                 _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_SLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_SLEW_RANGE                 8:6
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_SLEW_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_SLEW_DEFAULT                       _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_SLEW_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_SLEW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_SLEW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_SLEW_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_HS_SLEW_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_RSLEW_SHIFT                        _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_RSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_RSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_RSLEW_RANGE                        12:9
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_RSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_RSLEW_DEFAULT                      _MK_MASK_CONST(0x4)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_RSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_RSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_RSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_RSLEW_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_RSLEW_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_FSLEW_SHIFT                        _MK_SHIFT_CONST(13)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_FSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_FSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_FSLEW_RANGE                        16:13
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_FSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_FSLEW_DEFAULT                      _MK_MASK_CONST(0x4)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_FSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_FSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_FSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_FSLEW_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_FS_FSLEW_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_RSLEW_SHIFT                        _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_RSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_RSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_RSLEW_RANGE                        20:17
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_RSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_RSLEW_DEFAULT                      _MK_MASK_CONST(0x6)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_RSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_RSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_RSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_RSLEW_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_RSLEW_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_FSLEW_SHIFT                        _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_FSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_FSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_FSLEW_RANGE                        24:21
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_FSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_FSLEW_DEFAULT                      _MK_MASK_CONST(0x6)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_FSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_FSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_FSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_FSLEW_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_LS_FSLEW_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_TERM_SEL_SHIFT                        _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_TERM_SEL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_TERM_SEL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_TERM_SEL_RANGE                        25:25
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_TERM_SEL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_TERM_SEL_DEFAULT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_TERM_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_TERM_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_TERM_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_TERM_SEL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_TERM_SEL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_SHIFT                      _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_RANGE                      26:26
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_DEFAULT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_SHIFT                     _MK_SHIFT_CONST(27)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_RANGE                     27:27
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_OVRD_EN_SHIFT                     _MK_SHIFT_CONST(28)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_OVRD_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_OVRD_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_OVRD_EN_RANGE                     28:28
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_OVRD_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_OVRD_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_OVRD_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_OVRD_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_OVRD_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_OVRD_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD2_OVRD_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_ZI_SHIFT                   _MK_SHIFT_CONST(29)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_ZI_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_ZI_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_ZI_RANGE                   29:29
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_ZI_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_ZI_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_ZI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_ZI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_ZI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_ZI_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_ZI_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0_PD_ZI__PROD                   _MK_ENUM_CONST(0)


// Register XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0                       _MK_ADDR_CONST(0x8c)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_DUAL                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RESET_VAL                     _MK_MASK_CONST(0x20101044)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RESET_MASK                    _MK_MASK_CONST(0x7fff9fff)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_READ_MASK                     _MK_MASK_CONST(0x7fff9fff)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_WRITE_MASK                    _MK_MASK_CONST(0x7dff9fff)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_SHIFT                    _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_RANGE                    0:0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_SHIFT                    _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_RANGE                    1:1
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DR_SHIFT                   _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DR_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DR_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DR_RANGE                   2:2
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DR_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DR_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_TERM_RANGE_ADJ_SHIFT                  _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_TERM_RANGE_ADJ_FIELD                  _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_TERM_RANGE_ADJ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_TERM_RANGE_ADJ_RANGE                  6:3
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_TERM_RANGE_ADJ_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_TERM_RANGE_ADJ_DEFAULT                        _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_TERM_RANGE_ADJ_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_TERM_RANGE_ADJ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_TERM_RANGE_ADJ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_TERM_RANGE_ADJ_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_TERM_RANGE_ADJ_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SPARE_SHIFT                   _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SPARE_FIELD                   _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SPARE_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SPARE_RANGE                   10:7
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SPARE_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SPARE_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SPARE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_SPARE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_COUP_EN_SHIFT                      _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_COUP_EN_FIELD                      _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_COUP_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_COUP_EN_RANGE                      12:11
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_COUP_EN_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_COUP_EN_DEFAULT                    _MK_MASK_CONST(0x2)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_COUP_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_COUP_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_COUP_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_COUP_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_COUP_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_VAL_SHIFT                        _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_VAL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_VAL_RANGE                        15:15
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_VAL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_VAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_CHRP_OVRD_VAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_VAL_SHIFT                        _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_VAL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_VAL_RANGE                        16:16
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_VAL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_VAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PD_DISC_OVRD_VAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PTERM_RANGE_ADJ_SHIFT                 _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PTERM_RANGE_ADJ_FIELD                 _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PTERM_RANGE_ADJ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PTERM_RANGE_ADJ_RANGE                 20:17
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PTERM_RANGE_ADJ_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PTERM_RANGE_ADJ_DEFAULT                       _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PTERM_RANGE_ADJ_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PTERM_RANGE_ADJ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PTERM_RANGE_ADJ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PTERM_RANGE_ADJ_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_PTERM_RANGE_ADJ_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_EN_SHIFT                     _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_EN_RANGE                     21:21
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SHIFT                    _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_VAL_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_VAL_RANGE                    22:22
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_VAL_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_HS_LOOPBACK_OVRD_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_OVRD_SHIFT                 _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_OVRD_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_OVRD_RANGE                 23:23
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_OVRD_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_OVRD_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_OVRD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_OVRD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_OVRD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_OVRD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_OVRD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_LOW_SHIFT                  _MK_SHIFT_CONST(24)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_LOW_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_LOW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_LOW_RANGE                  24:24
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_LOW_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_LOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_LOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_LOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_LOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_LOW_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_SWITCH_LOW_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_STATUS_HIGH_SHIFT                 _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_STATUS_HIGH_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_STATUS_HIGH_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_STATUS_HIGH_RANGE                 25:25
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_STATUS_HIGH_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_STATUS_HIGH_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_STATUS_HIGH_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_STATUS_HIGH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_STATUS_HIGH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_STATUS_HIGH_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPU_STATUS_HIGH_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPD_CTRL_SHIFT                        _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPD_CTRL_FIELD                        _MK_FIELD_CONST(0x1f, XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPD_CTRL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPD_CTRL_RANGE                        30:26
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPD_CTRL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPD_CTRL_DEFAULT                      _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPD_CTRL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPD_CTRL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPD_CTRL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPD_CTRL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0_RPD_CTRL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0                       _MK_ADDR_CONST(0x90)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_DUAL                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RESET_MASK                    _MK_MASK_CONST(0xf3f3fff3)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_READ_MASK                     _MK_MASK_CONST(0xf3f3fff3)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_WRITE_MASK                    _MK_MASK_CONST(0xf3f3fff3)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_AUTO_SWITCH_EN_SHIFT                      _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_AUTO_SWITCH_EN_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_AUTO_SWITCH_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_AUTO_SWITCH_EN_RANGE                      0:0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_AUTO_SWITCH_EN_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_AUTO_SWITCH_EN_DEFAULT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_AUTO_SWITCH_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_AUTO_SWITCH_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_AUTO_SWITCH_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_AUTO_SWITCH_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_AUTO_SWITCH_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_HIGH_FIXED_SHIFT                  _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_HIGH_FIXED_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_HIGH_FIXED_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_HIGH_FIXED_RANGE                  1:1
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_HIGH_FIXED_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_HIGH_FIXED_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_HIGH_FIXED_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_HIGH_FIXED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_HIGH_FIXED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_HIGH_FIXED_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_RPU_HIGH_FIXED_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_SHIFT                       _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_FIELD                       _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_RANGE                       9:4
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_SHIFT                       _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_FIELD                       _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_RANGE                       15:10
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_OVRD_SHIFT                  _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_OVRD_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_OVRD_RANGE                  16:16
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_OVRD_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_OVRD_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_OVRD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_OVRD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_OVRD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_OVRD_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_PCTRL_TRK_OVRD_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_OVRD_SHIFT                  _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_OVRD_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_OVRD_RANGE                  17:17
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_OVRD_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_OVRD_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_OVRD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_OVRD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_OVRD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_OVRD_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_TRK_OVRD_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_SW_SHIFT                        _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_SW_FIELD                        _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_SW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_SW_RANGE                        25:20
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_SW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_SW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_SW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_SW_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_TCTRL_SW_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SPARE_AO_SHIFT                        _MK_SHIFT_CONST(28)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SPARE_AO_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SPARE_AO_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SPARE_AO_RANGE                        31:28
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SPARE_AO_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SPARE_AO_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SPARE_AO_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SPARE_AO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SPARE_AO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SPARE_AO_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0_SPARE_AO_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0                       _MK_ADDR_CONST(0x94)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_DUAL                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_RESET_MASK                    _MK_MASK_CONST(0x1cf)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_READ_MASK                     _MK_MASK_CONST(0x1cf)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_WRITE_MASK                    _MK_MASK_CONST(0x1cf)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_DIN_DLY_SEL_SHIFT                  _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_DIN_DLY_SEL_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_DIN_DLY_SEL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_DIN_DLY_SEL_RANGE                  0:0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_DIN_DLY_SEL_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_DIN_DLY_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_DIN_DLY_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_DIN_DLY_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_DIN_DLY_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_DIN_DLY_SEL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_DIN_DLY_SEL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_TXEQ_SHIFT                 _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_TXEQ_FIELD                 _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_TXEQ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_TXEQ_RANGE                 3:1
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_TXEQ_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_TXEQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_TXEQ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_TXEQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_TXEQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_TXEQ_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_TXEQ_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_RXEQ_SHIFT                 _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_RXEQ_FIELD                 _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_RXEQ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_RXEQ_RANGE                 8:6
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_RXEQ_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_RXEQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_RXEQ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_RXEQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_RXEQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_RXEQ_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0_HS_RXEQ_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Reserved address 0x98

// Reserved address 0x9c

// Reserved address 0xa0

// Reserved address 0xa4

// Reserved address 0xa8

// Reserved address 0xac

// Reserved address 0xb0

// Reserved address 0xb4

// Reserved address 0xb8

// Reserved address 0xbc

// Register XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0                    _MK_ADDR_CONST(0xc0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SECURE                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DUAL                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SCR                        0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_WORD_COUNT                         0x1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_RESET_MASK                         _MK_MASK_CONST(0xfffc3fff)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_READ_MASK                  _MK_MASK_CONST(0xfffc3fff)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_WRITE_MASK                         _MK_MASK_CONST(0xffb83fdd)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_PD_CHG_SHIFT                       _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_PD_CHG_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_PD_CHG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_PD_CHG_RANGE                       0:0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_PD_CHG_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_PD_CHG_DEFAULT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_PD_CHG_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_PD_CHG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_PD_CHG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_PD_CHG_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_PD_CHG_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_PD_CHG_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_PD_CHG_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_SHIFT                     _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_RANGE                     1:1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_ST_CHNG_SHIFT                     _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_ST_CHNG_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_ST_CHNG_RANGE                     2:2
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_ST_CHNG_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_ST_CHNG_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_ST_CHNG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_ST_CHNG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_ST_CHNG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_ST_CHNG_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_ST_CHNG_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_ST_CHNG_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_ST_CHNG_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_CHNG_INTR_EN_SHIFT                        _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_CHNG_INTR_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_CHNG_INTR_EN_RANGE                        3:3
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_CHNG_INTR_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_CHNG_INTR_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_CHNG_INTR_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_CHNG_INTR_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_CHNG_INTR_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_CHNG_INTR_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_CHNG_INTR_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_CHNG_INTR_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_CHNG_INTR_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_FILTER_EN_SHIFT                   _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_FILTER_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_FILTER_EN_RANGE                   4:4
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_FILTER_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_FILTER_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_FILTER_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_FILTER_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_FILTER_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_FILTER_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_FILTER_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_FILTER_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDCD_DET_FILTER_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_SHIFT                     _MK_SHIFT_CONST(5)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_RANGE                     5:5
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_ST_CHNG_SHIFT                     _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_ST_CHNG_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_ST_CHNG_RANGE                     6:6
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_ST_CHNG_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_ST_CHNG_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_ST_CHNG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_ST_CHNG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_ST_CHNG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_ST_CHNG_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_ST_CHNG_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_ST_CHNG_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_ST_CHNG_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_CHNG_INTR_EN_SHIFT                        _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_CHNG_INTR_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_CHNG_INTR_EN_RANGE                        7:7
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_CHNG_INTR_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_CHNG_INTR_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_CHNG_INTR_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_CHNG_INTR_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_CHNG_INTR_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_CHNG_INTR_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_CHNG_INTR_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_CHNG_INTR_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_CHNG_INTR_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_FILTER_EN_SHIFT                   _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_FILTER_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_FILTER_EN_RANGE                   8:8
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_FILTER_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_FILTER_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_FILTER_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_FILTER_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_FILTER_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_FILTER_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_FILTER_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_FILTER_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_VDAT_DET_FILTER_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SINK_EN_SHIFT                   _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SINK_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SINK_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SINK_EN_RANGE                   9:9
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SINK_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SINK_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SINK_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SINK_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SINK_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SRC_EN_SHIFT                    _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SRC_EN_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SRC_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SRC_EN_RANGE                    10:10
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SRC_EN_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SRC_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SRC_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SRC_EN_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_SRC_EN_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SINK_EN_SHIFT                   _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SINK_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SINK_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SINK_EN_RANGE                   11:11
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SINK_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SINK_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SINK_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SINK_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SINK_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SRC_EN_SHIFT                    _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SRC_EN_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SRC_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SRC_EN_RANGE                    12:12
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SRC_EN_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SRC_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SRC_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SRC_EN_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ON_SRC_EN_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_I_SRC_EN_SHIFT                  _MK_SHIFT_CONST(13)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_I_SRC_EN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_I_SRC_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_I_SRC_EN_RANGE                  13:13
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_I_SRC_EN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_I_SRC_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_I_SRC_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_I_SRC_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_I_SRC_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_I_SRC_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_I_SRC_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_I_SRC_EN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_OP_I_SRC_EN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_SHIFT                  _MK_SHIFT_CONST(18)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_RANGE                  18:18
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_ST_CHNG_SHIFT                  _MK_SHIFT_CONST(19)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_ST_CHNG_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_ST_CHNG_RANGE                  19:19
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_ST_CHNG_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_ST_CHNG_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_ST_CHNG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_ST_CHNG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_ST_CHNG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_ST_CHNG_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_ST_CHNG_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_ST_CHNG_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_ST_CHNG_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_CHNG_INTR_EN_SHIFT                     _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_CHNG_INTR_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_CHNG_INTR_EN_RANGE                     20:20
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_CHNG_INTR_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_CHNG_INTR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_CHNG_INTR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_CHNG_INTR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_CHNG_INTR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_CHNG_INTR_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_CHNG_INTR_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_CHNG_INTR_EN_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_CHNG_INTR_EN_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_FILTER_EN_SHIFT                        _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_FILTER_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_FILTER_EN_RANGE                        21:21
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_FILTER_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_FILTER_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_FILTER_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_FILTER_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_FILTER_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_FILTER_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_FILTER_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_FILTER_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIP_FILTER_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_SHIFT                  _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_RANGE                  22:22
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_ST_CHNG_SHIFT                  _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_ST_CHNG_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_ST_CHNG_RANGE                  23:23
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_ST_CHNG_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_ST_CHNG_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_ST_CHNG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_ST_CHNG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_ST_CHNG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_ST_CHNG_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_ST_CHNG_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_ST_CHNG_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_ST_CHNG_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_CHNG_INTR_EN_SHIFT                     _MK_SHIFT_CONST(24)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_CHNG_INTR_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_CHNG_INTR_EN_RANGE                     24:24
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_CHNG_INTR_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_CHNG_INTR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_CHNG_INTR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_CHNG_INTR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_CHNG_INTR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_CHNG_INTR_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_CHNG_INTR_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_CHNG_INTR_EN_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_CHNG_INTR_EN_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_FILTER_EN_SHIFT                        _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_FILTER_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_FILTER_EN_RANGE                        25:25
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_FILTER_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_FILTER_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_FILTER_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_FILTER_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_FILTER_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_FILTER_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_FILTER_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_FILTER_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_ZIN_FILTER_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_DETECTED_SHIFT                 _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_DETECTED_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_DETECTED_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_DETECTED_RANGE                 26:26
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_DETECTED_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_DETECTED_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_DETECTED_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_DETECTED_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_DETECTED_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_DETECTED_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_DETECTED_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_DETECTED_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_DETECTED_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_INTR_EN_SHIFT                  _MK_SHIFT_CONST(27)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_INTR_EN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_INTR_EN_RANGE                  27:27
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_INTR_EN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_INTR_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_INTR_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_INTR_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_INTR_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_INTR_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_INTR_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_INTR_EN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_DCD_INTR_EN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECT_EN_SHIFT                        _MK_SHIFT_CONST(28)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECT_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECT_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECT_EN_RANGE                        28:28
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECT_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECT_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECT_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECT_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECT_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECTED_SHIFT                 _MK_SHIFT_CONST(29)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECTED_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECTED_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECTED_RANGE                 29:29
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECTED_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECTED_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECTED_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECTED_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECTED_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECTED_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECTED_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECTED_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_DETECTED_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_INTR_EN_SHIFT                  _MK_SHIFT_CONST(30)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_INTR_EN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_INTR_EN_RANGE                  30:30
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_INTR_EN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_INTR_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_INTR_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_INTR_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_INTR_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_INTR_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_INTR_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_INTR_EN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_SRP_INTR_EN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_GENERATE_SRP_SHIFT                 _MK_SHIFT_CONST(31)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_GENERATE_SRP_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_GENERATE_SRP_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_GENERATE_SRP_RANGE                 31:31
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_GENERATE_SRP_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_GENERATE_SRP_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_GENERATE_SRP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_GENERATE_SRP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_GENERATE_SRP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_GENERATE_SRP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_GENERATE_SRP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_GENERATE_SRP_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0_GENERATE_SRP_YES                   _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0                    _MK_ADDR_CONST(0xc4)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_SECURE                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_DUAL                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_SCR                        0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_WORD_COUNT                         0x1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_RESET_VAL                  _MK_MASK_CONST(0x40)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_RESET_MASK                         _MK_MASK_CONST(0xff1fdf)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_READ_MASK                  _MK_MASK_CONST(0xff1fdf)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_WRITE_MASK                         _MK_MASK_CONST(0xff1fd0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P0_DET_SHIFT                       _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P0_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P0_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P0_DET_RANGE                       0:0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P0_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P0_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P0_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P0_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P0_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P0_DET_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P0_DET_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P0_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P0_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P7_DET_SHIFT                       _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P7_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P7_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P7_DET_RANGE                       1:1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P7_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P7_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P7_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P7_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P7_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P7_DET_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P7_DET_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P7_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VON_DIV2P7_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P0_DET_SHIFT                       _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P0_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P0_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P0_DET_RANGE                       2:2
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P0_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P0_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P0_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P0_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P0_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P0_DET_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P0_DET_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P0_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P0_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P7_DET_SHIFT                       _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P7_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P7_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P7_DET_RANGE                       3:3
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P7_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P7_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P7_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P7_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P7_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P7_DET_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P7_DET_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P7_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VOP_DIV2P7_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_DIV_DET_EN_SHIFT                   _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_DIV_DET_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_DIV_DET_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_DIV_DET_EN_RANGE                   4:4
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_DIV_DET_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_DIV_DET_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_DIV_DET_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_DIV_DET_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_DIV_DET_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_DIV_DET_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_DIV_DET_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_DIV_DET_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_DIV_DET_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_PD_VREG_SHIFT                      _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_PD_VREG_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_PD_VREG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_PD_VREG_RANGE                      6:6
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_PD_VREG_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_PD_VREG_DEFAULT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_PD_VREG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_PD_VREG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_PD_VREG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_PD_VREG_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_PD_VREG_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_LEV_SHIFT                     _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_LEV_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_LEV_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_LEV_RANGE                     8:7
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_LEV_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_LEV_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_LEV_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_LEV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_LEV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_LEV_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_LEV_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DYN_DLY_SHIFT                 _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DYN_DLY_FIELD                 _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DYN_DLY_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DYN_DLY_RANGE                 10:9
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DYN_DLY_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DYN_DLY_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DYN_DLY_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DYN_DLY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DYN_DLY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DYN_DLY_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DYN_DLY_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DIR_SHIFT                     _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DIR_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DIR_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DIR_RANGE                     12:11
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DIR_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DIR_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DIR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DIR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DIR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DIR_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_VREG_DIR_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_SHIFT                       _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_RANGE                       16:16
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_VAL_RANGE                   17:17
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPD_OVRD_VAL_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_SHIFT                       _MK_SHIFT_CONST(18)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_RANGE                       18:18
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(19)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_VAL_RANGE                   19:19
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBOP_RPU_OVRD_VAL_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_SHIFT                       _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_RANGE                       20:20
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_VAL_RANGE                   21:21
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPD_OVRD_VAL_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_SHIFT                       _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_RANGE                       22:22
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_VAL_RANGE                   23:23
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0_USBON_RPU_OVRD_VAL_YES                     _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0                       _MK_ADDR_CONST(0xc8)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_DUAL                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_RESET_VAL                     _MK_MASK_CONST(0x26cc88e0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_RESET_MASK                    _MK_MASK_CONST(0x3fffffff)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_READ_MASK                     _MK_MASK_CONST(0x3fffffff)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_WRITE_MASK                    _MK_MASK_CONST(0x3fffffff)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_CURR_LEVEL_SHIFT                   _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_CURR_LEVEL_FIELD                   _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_CURR_LEVEL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_CURR_LEVEL_RANGE                   5:0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_CURR_LEVEL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_CURR_LEVEL_DEFAULT                 _MK_MASK_CONST(0x20)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_CURR_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_CURR_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_CURR_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_CURR_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_CURR_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_SLEW_SHIFT                 _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_SLEW_FIELD                 _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_SLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_SLEW_RANGE                 8:6
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_SLEW_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_SLEW_DEFAULT                       _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_SLEW_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_SLEW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_SLEW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_SLEW_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_HS_SLEW_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_RSLEW_SHIFT                        _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_RSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_RSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_RSLEW_RANGE                        12:9
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_RSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_RSLEW_DEFAULT                      _MK_MASK_CONST(0x4)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_RSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_RSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_RSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_RSLEW_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_RSLEW_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_FSLEW_SHIFT                        _MK_SHIFT_CONST(13)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_FSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_FSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_FSLEW_RANGE                        16:13
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_FSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_FSLEW_DEFAULT                      _MK_MASK_CONST(0x4)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_FSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_FSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_FSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_FSLEW_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_FS_FSLEW_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_RSLEW_SHIFT                        _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_RSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_RSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_RSLEW_RANGE                        20:17
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_RSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_RSLEW_DEFAULT                      _MK_MASK_CONST(0x6)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_RSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_RSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_RSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_RSLEW_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_RSLEW_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_FSLEW_SHIFT                        _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_FSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_FSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_FSLEW_RANGE                        24:21
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_FSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_FSLEW_DEFAULT                      _MK_MASK_CONST(0x6)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_FSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_FSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_FSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_FSLEW_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_LS_FSLEW_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_TERM_SEL_SHIFT                        _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_TERM_SEL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_TERM_SEL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_TERM_SEL_RANGE                        25:25
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_TERM_SEL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_TERM_SEL_DEFAULT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_TERM_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_TERM_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_TERM_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_TERM_SEL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_TERM_SEL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_SHIFT                      _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_RANGE                      26:26
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_DEFAULT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_SHIFT                     _MK_SHIFT_CONST(27)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_RANGE                     27:27
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_OVRD_EN_SHIFT                     _MK_SHIFT_CONST(28)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_OVRD_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_OVRD_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_OVRD_EN_RANGE                     28:28
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_OVRD_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_OVRD_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_OVRD_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_OVRD_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_OVRD_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_OVRD_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD2_OVRD_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_ZI_SHIFT                   _MK_SHIFT_CONST(29)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_ZI_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_ZI_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_ZI_RANGE                   29:29
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_ZI_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_ZI_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_ZI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_ZI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_ZI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_ZI_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_ZI_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0_PD_ZI__PROD                   _MK_ENUM_CONST(0)


// Register XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0                       _MK_ADDR_CONST(0xcc)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_DUAL                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RESET_VAL                     _MK_MASK_CONST(0x20101044)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RESET_MASK                    _MK_MASK_CONST(0x7fff9fff)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_READ_MASK                     _MK_MASK_CONST(0x7fff9fff)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_WRITE_MASK                    _MK_MASK_CONST(0x7dff9fff)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_SHIFT                    _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_RANGE                    0:0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_SHIFT                    _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_RANGE                    1:1
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DR_SHIFT                   _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DR_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DR_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DR_RANGE                   2:2
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DR_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DR_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_TERM_RANGE_ADJ_SHIFT                  _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_TERM_RANGE_ADJ_FIELD                  _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_TERM_RANGE_ADJ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_TERM_RANGE_ADJ_RANGE                  6:3
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_TERM_RANGE_ADJ_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_TERM_RANGE_ADJ_DEFAULT                        _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_TERM_RANGE_ADJ_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_TERM_RANGE_ADJ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_TERM_RANGE_ADJ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_TERM_RANGE_ADJ_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_TERM_RANGE_ADJ_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SPARE_SHIFT                   _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SPARE_FIELD                   _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SPARE_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SPARE_RANGE                   10:7
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SPARE_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SPARE_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SPARE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_SPARE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_COUP_EN_SHIFT                      _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_COUP_EN_FIELD                      _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_COUP_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_COUP_EN_RANGE                      12:11
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_COUP_EN_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_COUP_EN_DEFAULT                    _MK_MASK_CONST(0x2)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_COUP_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_COUP_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_COUP_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_COUP_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_COUP_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_VAL_SHIFT                        _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_VAL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_VAL_RANGE                        15:15
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_VAL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_VAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_CHRP_OVRD_VAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_VAL_SHIFT                        _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_VAL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_VAL_RANGE                        16:16
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_VAL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_VAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PD_DISC_OVRD_VAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PTERM_RANGE_ADJ_SHIFT                 _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PTERM_RANGE_ADJ_FIELD                 _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PTERM_RANGE_ADJ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PTERM_RANGE_ADJ_RANGE                 20:17
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PTERM_RANGE_ADJ_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PTERM_RANGE_ADJ_DEFAULT                       _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PTERM_RANGE_ADJ_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PTERM_RANGE_ADJ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PTERM_RANGE_ADJ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PTERM_RANGE_ADJ_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_PTERM_RANGE_ADJ_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_EN_SHIFT                     _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_EN_RANGE                     21:21
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SHIFT                    _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_VAL_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_VAL_RANGE                    22:22
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_VAL_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_HS_LOOPBACK_OVRD_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_OVRD_SHIFT                 _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_OVRD_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_OVRD_RANGE                 23:23
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_OVRD_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_OVRD_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_OVRD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_OVRD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_OVRD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_OVRD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_OVRD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_LOW_SHIFT                  _MK_SHIFT_CONST(24)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_LOW_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_LOW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_LOW_RANGE                  24:24
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_LOW_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_LOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_LOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_LOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_LOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_LOW_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_SWITCH_LOW_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_STATUS_HIGH_SHIFT                 _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_STATUS_HIGH_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_STATUS_HIGH_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_STATUS_HIGH_RANGE                 25:25
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_STATUS_HIGH_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_STATUS_HIGH_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_STATUS_HIGH_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_STATUS_HIGH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_STATUS_HIGH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_STATUS_HIGH_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPU_STATUS_HIGH_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPD_CTRL_SHIFT                        _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPD_CTRL_FIELD                        _MK_FIELD_CONST(0x1f, XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPD_CTRL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPD_CTRL_RANGE                        30:26
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPD_CTRL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPD_CTRL_DEFAULT                      _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPD_CTRL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPD_CTRL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPD_CTRL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPD_CTRL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0_RPD_CTRL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0                       _MK_ADDR_CONST(0xd0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_DUAL                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RESET_MASK                    _MK_MASK_CONST(0xf3f3fff3)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_READ_MASK                     _MK_MASK_CONST(0xf3f3fff3)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_WRITE_MASK                    _MK_MASK_CONST(0xf3f3fff3)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_AUTO_SWITCH_EN_SHIFT                      _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_AUTO_SWITCH_EN_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_AUTO_SWITCH_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_AUTO_SWITCH_EN_RANGE                      0:0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_AUTO_SWITCH_EN_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_AUTO_SWITCH_EN_DEFAULT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_AUTO_SWITCH_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_AUTO_SWITCH_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_AUTO_SWITCH_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_AUTO_SWITCH_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_AUTO_SWITCH_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_HIGH_FIXED_SHIFT                  _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_HIGH_FIXED_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_HIGH_FIXED_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_HIGH_FIXED_RANGE                  1:1
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_HIGH_FIXED_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_HIGH_FIXED_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_HIGH_FIXED_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_HIGH_FIXED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_HIGH_FIXED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_HIGH_FIXED_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_RPU_HIGH_FIXED_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_SHIFT                       _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_FIELD                       _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_RANGE                       9:4
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_SHIFT                       _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_FIELD                       _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_RANGE                       15:10
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_OVRD_SHIFT                  _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_OVRD_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_OVRD_RANGE                  16:16
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_OVRD_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_OVRD_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_OVRD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_OVRD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_OVRD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_OVRD_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_PCTRL_TRK_OVRD_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_OVRD_SHIFT                  _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_OVRD_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_OVRD_RANGE                  17:17
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_OVRD_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_OVRD_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_OVRD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_OVRD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_OVRD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_OVRD_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_TRK_OVRD_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_SW_SHIFT                        _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_SW_FIELD                        _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_SW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_SW_RANGE                        25:20
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_SW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_SW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_SW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_SW_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_TCTRL_SW_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SPARE_AO_SHIFT                        _MK_SHIFT_CONST(28)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SPARE_AO_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SPARE_AO_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SPARE_AO_RANGE                        31:28
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SPARE_AO_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SPARE_AO_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SPARE_AO_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SPARE_AO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SPARE_AO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SPARE_AO_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0_SPARE_AO_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0                       _MK_ADDR_CONST(0xd4)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_DUAL                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_RESET_MASK                    _MK_MASK_CONST(0x1cf)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_READ_MASK                     _MK_MASK_CONST(0x1cf)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_WRITE_MASK                    _MK_MASK_CONST(0x1cf)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_DIN_DLY_SEL_SHIFT                  _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_DIN_DLY_SEL_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_DIN_DLY_SEL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_DIN_DLY_SEL_RANGE                  0:0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_DIN_DLY_SEL_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_DIN_DLY_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_DIN_DLY_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_DIN_DLY_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_DIN_DLY_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_DIN_DLY_SEL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_DIN_DLY_SEL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_TXEQ_SHIFT                 _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_TXEQ_FIELD                 _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_TXEQ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_TXEQ_RANGE                 3:1
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_TXEQ_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_TXEQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_TXEQ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_TXEQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_TXEQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_TXEQ_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_TXEQ_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_RXEQ_SHIFT                 _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_RXEQ_FIELD                 _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_RXEQ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_RXEQ_RANGE                 8:6
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_RXEQ_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_RXEQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_RXEQ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_RXEQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_RXEQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_RXEQ_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0_HS_RXEQ_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Reserved address 0xd8

// Reserved address 0xdc

// Reserved address 0xe0

// Reserved address 0xe4

// Reserved address 0xe8

// Reserved address 0xec

// Reserved address 0xf0

// Reserved address 0xf4

// Reserved address 0xf8

// Reserved address 0xfc

// Register XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0                    _MK_ADDR_CONST(0x100)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SECURE                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DUAL                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SCR                        0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_WORD_COUNT                         0x1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_RESET_MASK                         _MK_MASK_CONST(0xfffc3fff)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_READ_MASK                  _MK_MASK_CONST(0xfffc3fff)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_WRITE_MASK                         _MK_MASK_CONST(0xffb83fdd)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_PD_CHG_SHIFT                       _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_PD_CHG_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_PD_CHG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_PD_CHG_RANGE                       0:0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_PD_CHG_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_PD_CHG_DEFAULT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_PD_CHG_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_PD_CHG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_PD_CHG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_PD_CHG_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_PD_CHG_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_PD_CHG_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_PD_CHG_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_SHIFT                     _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_RANGE                     1:1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_ST_CHNG_SHIFT                     _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_ST_CHNG_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_ST_CHNG_RANGE                     2:2
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_ST_CHNG_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_ST_CHNG_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_ST_CHNG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_ST_CHNG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_ST_CHNG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_ST_CHNG_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_ST_CHNG_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_ST_CHNG_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_ST_CHNG_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_CHNG_INTR_EN_SHIFT                        _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_CHNG_INTR_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_CHNG_INTR_EN_RANGE                        3:3
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_CHNG_INTR_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_CHNG_INTR_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_CHNG_INTR_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_CHNG_INTR_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_CHNG_INTR_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_CHNG_INTR_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_CHNG_INTR_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_CHNG_INTR_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_CHNG_INTR_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_FILTER_EN_SHIFT                   _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_FILTER_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_FILTER_EN_RANGE                   4:4
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_FILTER_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_FILTER_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_FILTER_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_FILTER_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_FILTER_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_FILTER_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_FILTER_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_FILTER_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDCD_DET_FILTER_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_SHIFT                     _MK_SHIFT_CONST(5)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_RANGE                     5:5
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_ST_CHNG_SHIFT                     _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_ST_CHNG_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_ST_CHNG_RANGE                     6:6
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_ST_CHNG_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_ST_CHNG_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_ST_CHNG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_ST_CHNG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_ST_CHNG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_ST_CHNG_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_ST_CHNG_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_ST_CHNG_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_ST_CHNG_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_CHNG_INTR_EN_SHIFT                        _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_CHNG_INTR_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_CHNG_INTR_EN_RANGE                        7:7
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_CHNG_INTR_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_CHNG_INTR_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_CHNG_INTR_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_CHNG_INTR_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_CHNG_INTR_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_CHNG_INTR_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_CHNG_INTR_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_CHNG_INTR_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_CHNG_INTR_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_FILTER_EN_SHIFT                   _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_FILTER_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_FILTER_EN_RANGE                   8:8
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_FILTER_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_FILTER_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_FILTER_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_FILTER_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_FILTER_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_FILTER_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_FILTER_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_FILTER_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_VDAT_DET_FILTER_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SINK_EN_SHIFT                   _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SINK_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SINK_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SINK_EN_RANGE                   9:9
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SINK_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SINK_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SINK_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SINK_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SINK_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SRC_EN_SHIFT                    _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SRC_EN_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SRC_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SRC_EN_RANGE                    10:10
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SRC_EN_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SRC_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SRC_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SRC_EN_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_SRC_EN_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SINK_EN_SHIFT                   _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SINK_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SINK_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SINK_EN_RANGE                   11:11
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SINK_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SINK_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SINK_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SINK_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SINK_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SRC_EN_SHIFT                    _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SRC_EN_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SRC_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SRC_EN_RANGE                    12:12
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SRC_EN_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SRC_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SRC_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SRC_EN_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ON_SRC_EN_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_I_SRC_EN_SHIFT                  _MK_SHIFT_CONST(13)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_I_SRC_EN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_I_SRC_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_I_SRC_EN_RANGE                  13:13
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_I_SRC_EN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_I_SRC_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_I_SRC_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_I_SRC_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_I_SRC_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_I_SRC_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_I_SRC_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_I_SRC_EN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_OP_I_SRC_EN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_SHIFT                  _MK_SHIFT_CONST(18)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_RANGE                  18:18
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_ST_CHNG_SHIFT                  _MK_SHIFT_CONST(19)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_ST_CHNG_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_ST_CHNG_RANGE                  19:19
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_ST_CHNG_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_ST_CHNG_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_ST_CHNG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_ST_CHNG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_ST_CHNG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_ST_CHNG_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_ST_CHNG_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_ST_CHNG_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_ST_CHNG_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_CHNG_INTR_EN_SHIFT                     _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_CHNG_INTR_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_CHNG_INTR_EN_RANGE                     20:20
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_CHNG_INTR_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_CHNG_INTR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_CHNG_INTR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_CHNG_INTR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_CHNG_INTR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_CHNG_INTR_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_CHNG_INTR_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_CHNG_INTR_EN_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_CHNG_INTR_EN_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_FILTER_EN_SHIFT                        _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_FILTER_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_FILTER_EN_RANGE                        21:21
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_FILTER_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_FILTER_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_FILTER_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_FILTER_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_FILTER_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_FILTER_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_FILTER_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_FILTER_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIP_FILTER_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_SHIFT                  _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_RANGE                  22:22
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_ST_CHNG_SHIFT                  _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_ST_CHNG_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_ST_CHNG_RANGE                  23:23
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_ST_CHNG_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_ST_CHNG_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_ST_CHNG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_ST_CHNG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_ST_CHNG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_ST_CHNG_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_ST_CHNG_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_ST_CHNG_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_ST_CHNG_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_CHNG_INTR_EN_SHIFT                     _MK_SHIFT_CONST(24)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_CHNG_INTR_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_CHNG_INTR_EN_RANGE                     24:24
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_CHNG_INTR_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_CHNG_INTR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_CHNG_INTR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_CHNG_INTR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_CHNG_INTR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_CHNG_INTR_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_CHNG_INTR_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_CHNG_INTR_EN_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_CHNG_INTR_EN_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_FILTER_EN_SHIFT                        _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_FILTER_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_FILTER_EN_RANGE                        25:25
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_FILTER_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_FILTER_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_FILTER_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_FILTER_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_FILTER_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_FILTER_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_FILTER_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_FILTER_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_ZIN_FILTER_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_DETECTED_SHIFT                 _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_DETECTED_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_DETECTED_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_DETECTED_RANGE                 26:26
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_DETECTED_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_DETECTED_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_DETECTED_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_DETECTED_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_DETECTED_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_DETECTED_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_DETECTED_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_DETECTED_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_DETECTED_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_INTR_EN_SHIFT                  _MK_SHIFT_CONST(27)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_INTR_EN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_INTR_EN_RANGE                  27:27
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_INTR_EN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_INTR_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_INTR_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_INTR_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_INTR_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_INTR_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_INTR_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_INTR_EN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_DCD_INTR_EN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECT_EN_SHIFT                        _MK_SHIFT_CONST(28)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECT_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECT_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECT_EN_RANGE                        28:28
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECT_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECT_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECT_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECT_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECT_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECTED_SHIFT                 _MK_SHIFT_CONST(29)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECTED_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECTED_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECTED_RANGE                 29:29
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECTED_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECTED_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECTED_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECTED_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECTED_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECTED_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECTED_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECTED_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_DETECTED_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_INTR_EN_SHIFT                  _MK_SHIFT_CONST(30)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_INTR_EN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_INTR_EN_RANGE                  30:30
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_INTR_EN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_INTR_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_INTR_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_INTR_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_INTR_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_INTR_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_INTR_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_INTR_EN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_SRP_INTR_EN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_GENERATE_SRP_SHIFT                 _MK_SHIFT_CONST(31)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_GENERATE_SRP_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_GENERATE_SRP_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_GENERATE_SRP_RANGE                 31:31
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_GENERATE_SRP_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_GENERATE_SRP_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_GENERATE_SRP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_GENERATE_SRP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_GENERATE_SRP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_GENERATE_SRP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_GENERATE_SRP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_GENERATE_SRP_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0_GENERATE_SRP_YES                   _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0                    _MK_ADDR_CONST(0x104)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_SECURE                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_DUAL                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_SCR                        0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_WORD_COUNT                         0x1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_RESET_VAL                  _MK_MASK_CONST(0x40)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_RESET_MASK                         _MK_MASK_CONST(0xff1fdf)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_READ_MASK                  _MK_MASK_CONST(0xff1fdf)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_WRITE_MASK                         _MK_MASK_CONST(0xff1fd0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P0_DET_SHIFT                       _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P0_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P0_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P0_DET_RANGE                       0:0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P0_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P0_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P0_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P0_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P0_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P0_DET_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P0_DET_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P0_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P0_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P7_DET_SHIFT                       _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P7_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P7_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P7_DET_RANGE                       1:1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P7_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P7_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P7_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P7_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P7_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P7_DET_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P7_DET_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P7_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VON_DIV2P7_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P0_DET_SHIFT                       _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P0_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P0_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P0_DET_RANGE                       2:2
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P0_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P0_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P0_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P0_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P0_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P0_DET_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P0_DET_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P0_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P0_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P7_DET_SHIFT                       _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P7_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P7_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P7_DET_RANGE                       3:3
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P7_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P7_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P7_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P7_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P7_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P7_DET_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P7_DET_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P7_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VOP_DIV2P7_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_DIV_DET_EN_SHIFT                   _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_DIV_DET_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_DIV_DET_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_DIV_DET_EN_RANGE                   4:4
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_DIV_DET_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_DIV_DET_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_DIV_DET_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_DIV_DET_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_DIV_DET_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_DIV_DET_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_DIV_DET_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_DIV_DET_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_DIV_DET_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_PD_VREG_SHIFT                      _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_PD_VREG_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_PD_VREG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_PD_VREG_RANGE                      6:6
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_PD_VREG_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_PD_VREG_DEFAULT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_PD_VREG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_PD_VREG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_PD_VREG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_PD_VREG_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_PD_VREG_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_LEV_SHIFT                     _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_LEV_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_LEV_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_LEV_RANGE                     8:7
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_LEV_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_LEV_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_LEV_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_LEV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_LEV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_LEV_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_LEV_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DYN_DLY_SHIFT                 _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DYN_DLY_FIELD                 _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DYN_DLY_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DYN_DLY_RANGE                 10:9
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DYN_DLY_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DYN_DLY_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DYN_DLY_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DYN_DLY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DYN_DLY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DYN_DLY_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DYN_DLY_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DIR_SHIFT                     _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DIR_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DIR_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DIR_RANGE                     12:11
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DIR_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DIR_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DIR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DIR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DIR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DIR_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_VREG_DIR_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_SHIFT                       _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_RANGE                       16:16
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_VAL_RANGE                   17:17
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPD_OVRD_VAL_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_SHIFT                       _MK_SHIFT_CONST(18)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_RANGE                       18:18
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(19)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_VAL_RANGE                   19:19
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBOP_RPU_OVRD_VAL_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_SHIFT                       _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_RANGE                       20:20
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_VAL_RANGE                   21:21
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPD_OVRD_VAL_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_SHIFT                       _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_RANGE                       22:22
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_VAL_RANGE                   23:23
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0_USBON_RPU_OVRD_VAL_YES                     _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0                       _MK_ADDR_CONST(0x108)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_DUAL                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_RESET_VAL                     _MK_MASK_CONST(0x26cc88e0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_RESET_MASK                    _MK_MASK_CONST(0x3fffffff)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_READ_MASK                     _MK_MASK_CONST(0x3fffffff)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_WRITE_MASK                    _MK_MASK_CONST(0x3fffffff)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_CURR_LEVEL_SHIFT                   _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_CURR_LEVEL_FIELD                   _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_CURR_LEVEL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_CURR_LEVEL_RANGE                   5:0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_CURR_LEVEL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_CURR_LEVEL_DEFAULT                 _MK_MASK_CONST(0x20)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_CURR_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_CURR_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_CURR_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_CURR_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_CURR_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_SLEW_SHIFT                 _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_SLEW_FIELD                 _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_SLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_SLEW_RANGE                 8:6
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_SLEW_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_SLEW_DEFAULT                       _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_SLEW_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_SLEW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_SLEW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_SLEW_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_HS_SLEW_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_RSLEW_SHIFT                        _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_RSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_RSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_RSLEW_RANGE                        12:9
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_RSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_RSLEW_DEFAULT                      _MK_MASK_CONST(0x4)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_RSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_RSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_RSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_RSLEW_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_RSLEW_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_FSLEW_SHIFT                        _MK_SHIFT_CONST(13)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_FSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_FSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_FSLEW_RANGE                        16:13
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_FSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_FSLEW_DEFAULT                      _MK_MASK_CONST(0x4)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_FSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_FSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_FSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_FSLEW_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_FS_FSLEW_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_RSLEW_SHIFT                        _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_RSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_RSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_RSLEW_RANGE                        20:17
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_RSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_RSLEW_DEFAULT                      _MK_MASK_CONST(0x6)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_RSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_RSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_RSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_RSLEW_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_RSLEW_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_FSLEW_SHIFT                        _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_FSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_FSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_FSLEW_RANGE                        24:21
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_FSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_FSLEW_DEFAULT                      _MK_MASK_CONST(0x6)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_FSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_FSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_FSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_FSLEW_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_LS_FSLEW_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_TERM_SEL_SHIFT                        _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_TERM_SEL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_TERM_SEL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_TERM_SEL_RANGE                        25:25
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_TERM_SEL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_TERM_SEL_DEFAULT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_TERM_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_TERM_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_TERM_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_TERM_SEL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_TERM_SEL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_SHIFT                      _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_RANGE                      26:26
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_DEFAULT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_SHIFT                     _MK_SHIFT_CONST(27)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_RANGE                     27:27
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_OVRD_EN_SHIFT                     _MK_SHIFT_CONST(28)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_OVRD_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_OVRD_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_OVRD_EN_RANGE                     28:28
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_OVRD_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_OVRD_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_OVRD_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_OVRD_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_OVRD_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_OVRD_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD2_OVRD_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_ZI_SHIFT                   _MK_SHIFT_CONST(29)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_ZI_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_ZI_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_ZI_RANGE                   29:29
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_ZI_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_ZI_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_ZI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_ZI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_ZI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_ZI_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_ZI_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0_PD_ZI__PROD                   _MK_ENUM_CONST(0)


// Register XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0                       _MK_ADDR_CONST(0x10c)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_DUAL                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RESET_VAL                     _MK_MASK_CONST(0x20101044)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RESET_MASK                    _MK_MASK_CONST(0x7fff9fff)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_READ_MASK                     _MK_MASK_CONST(0x7fff9fff)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_WRITE_MASK                    _MK_MASK_CONST(0x7dff9fff)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_SHIFT                    _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_RANGE                    0:0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_SHIFT                    _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_RANGE                    1:1
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DR_SHIFT                   _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DR_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DR_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DR_RANGE                   2:2
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DR_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DR_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_TERM_RANGE_ADJ_SHIFT                  _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_TERM_RANGE_ADJ_FIELD                  _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_TERM_RANGE_ADJ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_TERM_RANGE_ADJ_RANGE                  6:3
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_TERM_RANGE_ADJ_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_TERM_RANGE_ADJ_DEFAULT                        _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_TERM_RANGE_ADJ_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_TERM_RANGE_ADJ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_TERM_RANGE_ADJ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_TERM_RANGE_ADJ_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_TERM_RANGE_ADJ_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SPARE_SHIFT                   _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SPARE_FIELD                   _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SPARE_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SPARE_RANGE                   10:7
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SPARE_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SPARE_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SPARE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_SPARE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_COUP_EN_SHIFT                      _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_COUP_EN_FIELD                      _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_COUP_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_COUP_EN_RANGE                      12:11
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_COUP_EN_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_COUP_EN_DEFAULT                    _MK_MASK_CONST(0x2)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_COUP_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_COUP_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_COUP_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_COUP_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_COUP_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_VAL_SHIFT                        _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_VAL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_VAL_RANGE                        15:15
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_VAL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_VAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_CHRP_OVRD_VAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_VAL_SHIFT                        _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_VAL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_VAL_RANGE                        16:16
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_VAL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_VAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PD_DISC_OVRD_VAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PTERM_RANGE_ADJ_SHIFT                 _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PTERM_RANGE_ADJ_FIELD                 _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PTERM_RANGE_ADJ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PTERM_RANGE_ADJ_RANGE                 20:17
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PTERM_RANGE_ADJ_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PTERM_RANGE_ADJ_DEFAULT                       _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PTERM_RANGE_ADJ_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PTERM_RANGE_ADJ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PTERM_RANGE_ADJ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PTERM_RANGE_ADJ_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_PTERM_RANGE_ADJ_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_EN_SHIFT                     _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_EN_RANGE                     21:21
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SHIFT                    _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_VAL_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_VAL_RANGE                    22:22
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_VAL_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_HS_LOOPBACK_OVRD_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_OVRD_SHIFT                 _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_OVRD_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_OVRD_RANGE                 23:23
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_OVRD_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_OVRD_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_OVRD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_OVRD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_OVRD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_OVRD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_OVRD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_LOW_SHIFT                  _MK_SHIFT_CONST(24)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_LOW_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_LOW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_LOW_RANGE                  24:24
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_LOW_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_LOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_LOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_LOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_LOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_LOW_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_SWITCH_LOW_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_STATUS_HIGH_SHIFT                 _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_STATUS_HIGH_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_STATUS_HIGH_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_STATUS_HIGH_RANGE                 25:25
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_STATUS_HIGH_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_STATUS_HIGH_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_STATUS_HIGH_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_STATUS_HIGH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_STATUS_HIGH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_STATUS_HIGH_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPU_STATUS_HIGH_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPD_CTRL_SHIFT                        _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPD_CTRL_FIELD                        _MK_FIELD_CONST(0x1f, XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPD_CTRL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPD_CTRL_RANGE                        30:26
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPD_CTRL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPD_CTRL_DEFAULT                      _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPD_CTRL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPD_CTRL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPD_CTRL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPD_CTRL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0_RPD_CTRL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0                       _MK_ADDR_CONST(0x110)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_DUAL                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RESET_MASK                    _MK_MASK_CONST(0xf3f3fff3)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_READ_MASK                     _MK_MASK_CONST(0xf3f3fff3)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_WRITE_MASK                    _MK_MASK_CONST(0xf3f3fff3)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_AUTO_SWITCH_EN_SHIFT                      _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_AUTO_SWITCH_EN_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_AUTO_SWITCH_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_AUTO_SWITCH_EN_RANGE                      0:0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_AUTO_SWITCH_EN_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_AUTO_SWITCH_EN_DEFAULT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_AUTO_SWITCH_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_AUTO_SWITCH_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_AUTO_SWITCH_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_AUTO_SWITCH_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_AUTO_SWITCH_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_HIGH_FIXED_SHIFT                  _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_HIGH_FIXED_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_HIGH_FIXED_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_HIGH_FIXED_RANGE                  1:1
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_HIGH_FIXED_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_HIGH_FIXED_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_HIGH_FIXED_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_HIGH_FIXED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_HIGH_FIXED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_HIGH_FIXED_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_RPU_HIGH_FIXED_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_SHIFT                       _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_FIELD                       _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_RANGE                       9:4
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_SHIFT                       _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_FIELD                       _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_RANGE                       15:10
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_OVRD_SHIFT                  _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_OVRD_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_OVRD_RANGE                  16:16
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_OVRD_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_OVRD_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_OVRD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_OVRD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_OVRD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_OVRD_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_PCTRL_TRK_OVRD_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_OVRD_SHIFT                  _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_OVRD_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_OVRD_RANGE                  17:17
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_OVRD_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_OVRD_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_OVRD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_OVRD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_OVRD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_OVRD_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_TRK_OVRD_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_SW_SHIFT                        _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_SW_FIELD                        _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_SW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_SW_RANGE                        25:20
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_SW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_SW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_SW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_SW_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_TCTRL_SW_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SPARE_AO_SHIFT                        _MK_SHIFT_CONST(28)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SPARE_AO_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SPARE_AO_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SPARE_AO_RANGE                        31:28
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SPARE_AO_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SPARE_AO_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SPARE_AO_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SPARE_AO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SPARE_AO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SPARE_AO_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0_SPARE_AO_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0                       _MK_ADDR_CONST(0x114)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_DUAL                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_RESET_MASK                    _MK_MASK_CONST(0x1cf)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_READ_MASK                     _MK_MASK_CONST(0x1cf)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_WRITE_MASK                    _MK_MASK_CONST(0x1cf)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_DIN_DLY_SEL_SHIFT                  _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_DIN_DLY_SEL_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_DIN_DLY_SEL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_DIN_DLY_SEL_RANGE                  0:0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_DIN_DLY_SEL_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_DIN_DLY_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_DIN_DLY_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_DIN_DLY_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_DIN_DLY_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_DIN_DLY_SEL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_DIN_DLY_SEL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_TXEQ_SHIFT                 _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_TXEQ_FIELD                 _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_TXEQ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_TXEQ_RANGE                 3:1
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_TXEQ_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_TXEQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_TXEQ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_TXEQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_TXEQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_TXEQ_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_TXEQ_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_RXEQ_SHIFT                 _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_RXEQ_FIELD                 _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_RXEQ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_RXEQ_RANGE                 8:6
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_RXEQ_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_RXEQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_RXEQ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_RXEQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_RXEQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_RXEQ_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0_HS_RXEQ_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Reserved address 0x118

// Reserved address 0x11c

// Reserved address 0x120

// Reserved address 0x124

// Reserved address 0x128

// Reserved address 0x12c

// Reserved address 0x130

// Reserved address 0x134

// Reserved address 0x138

// Reserved address 0x13c

// Register XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0                    _MK_ADDR_CONST(0x140)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SECURE                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DUAL                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SCR                        0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_WORD_COUNT                         0x1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_RESET_MASK                         _MK_MASK_CONST(0xfffc3fff)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_READ_MASK                  _MK_MASK_CONST(0xfffc3fff)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_WRITE_MASK                         _MK_MASK_CONST(0xffb83fdd)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_PD_CHG_SHIFT                       _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_PD_CHG_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_PD_CHG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_PD_CHG_RANGE                       0:0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_PD_CHG_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_PD_CHG_DEFAULT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_PD_CHG_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_PD_CHG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_PD_CHG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_PD_CHG_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_PD_CHG_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_PD_CHG_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_PD_CHG_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_SHIFT                     _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_RANGE                     1:1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_ST_CHNG_SHIFT                     _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_ST_CHNG_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_ST_CHNG_RANGE                     2:2
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_ST_CHNG_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_ST_CHNG_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_ST_CHNG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_ST_CHNG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_ST_CHNG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_ST_CHNG_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_ST_CHNG_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_ST_CHNG_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_ST_CHNG_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_CHNG_INTR_EN_SHIFT                        _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_CHNG_INTR_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_CHNG_INTR_EN_RANGE                        3:3
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_CHNG_INTR_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_CHNG_INTR_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_CHNG_INTR_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_CHNG_INTR_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_CHNG_INTR_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_CHNG_INTR_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_CHNG_INTR_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_CHNG_INTR_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_CHNG_INTR_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_FILTER_EN_SHIFT                   _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_FILTER_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_FILTER_EN_RANGE                   4:4
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_FILTER_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_FILTER_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_FILTER_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_FILTER_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_FILTER_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_FILTER_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_FILTER_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_FILTER_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDCD_DET_FILTER_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_SHIFT                     _MK_SHIFT_CONST(5)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_RANGE                     5:5
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_ST_CHNG_SHIFT                     _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_ST_CHNG_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_ST_CHNG_RANGE                     6:6
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_ST_CHNG_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_ST_CHNG_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_ST_CHNG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_ST_CHNG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_ST_CHNG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_ST_CHNG_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_ST_CHNG_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_ST_CHNG_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_ST_CHNG_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_CHNG_INTR_EN_SHIFT                        _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_CHNG_INTR_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_CHNG_INTR_EN_RANGE                        7:7
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_CHNG_INTR_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_CHNG_INTR_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_CHNG_INTR_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_CHNG_INTR_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_CHNG_INTR_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_CHNG_INTR_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_CHNG_INTR_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_CHNG_INTR_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_CHNG_INTR_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_FILTER_EN_SHIFT                   _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_FILTER_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_FILTER_EN_RANGE                   8:8
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_FILTER_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_FILTER_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_FILTER_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_FILTER_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_FILTER_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_FILTER_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_FILTER_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_FILTER_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_VDAT_DET_FILTER_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SINK_EN_SHIFT                   _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SINK_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SINK_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SINK_EN_RANGE                   9:9
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SINK_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SINK_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SINK_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SINK_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SINK_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SRC_EN_SHIFT                    _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SRC_EN_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SRC_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SRC_EN_RANGE                    10:10
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SRC_EN_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SRC_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SRC_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SRC_EN_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_SRC_EN_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SINK_EN_SHIFT                   _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SINK_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SINK_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SINK_EN_RANGE                   11:11
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SINK_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SINK_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SINK_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SINK_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SINK_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SRC_EN_SHIFT                    _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SRC_EN_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SRC_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SRC_EN_RANGE                    12:12
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SRC_EN_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SRC_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SRC_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SRC_EN_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ON_SRC_EN_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_I_SRC_EN_SHIFT                  _MK_SHIFT_CONST(13)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_I_SRC_EN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_I_SRC_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_I_SRC_EN_RANGE                  13:13
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_I_SRC_EN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_I_SRC_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_I_SRC_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_I_SRC_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_I_SRC_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_I_SRC_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_I_SRC_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_I_SRC_EN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_OP_I_SRC_EN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_SHIFT                  _MK_SHIFT_CONST(18)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_RANGE                  18:18
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_ST_CHNG_SHIFT                  _MK_SHIFT_CONST(19)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_ST_CHNG_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_ST_CHNG_RANGE                  19:19
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_ST_CHNG_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_ST_CHNG_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_ST_CHNG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_ST_CHNG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_ST_CHNG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_ST_CHNG_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_ST_CHNG_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_ST_CHNG_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_ST_CHNG_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_CHNG_INTR_EN_SHIFT                     _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_CHNG_INTR_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_CHNG_INTR_EN_RANGE                     20:20
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_CHNG_INTR_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_CHNG_INTR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_CHNG_INTR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_CHNG_INTR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_CHNG_INTR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_CHNG_INTR_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_CHNG_INTR_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_CHNG_INTR_EN_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_CHNG_INTR_EN_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_FILTER_EN_SHIFT                        _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_FILTER_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_FILTER_EN_RANGE                        21:21
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_FILTER_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_FILTER_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_FILTER_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_FILTER_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_FILTER_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_FILTER_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_FILTER_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_FILTER_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIP_FILTER_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_SHIFT                  _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_RANGE                  22:22
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_ST_CHNG_SHIFT                  _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_ST_CHNG_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_ST_CHNG_RANGE                  23:23
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_ST_CHNG_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_ST_CHNG_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_ST_CHNG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_ST_CHNG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_ST_CHNG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_ST_CHNG_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_ST_CHNG_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_ST_CHNG_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_ST_CHNG_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_CHNG_INTR_EN_SHIFT                     _MK_SHIFT_CONST(24)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_CHNG_INTR_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_CHNG_INTR_EN_RANGE                     24:24
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_CHNG_INTR_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_CHNG_INTR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_CHNG_INTR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_CHNG_INTR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_CHNG_INTR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_CHNG_INTR_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_CHNG_INTR_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_CHNG_INTR_EN_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_CHNG_INTR_EN_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_FILTER_EN_SHIFT                        _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_FILTER_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_FILTER_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_FILTER_EN_RANGE                        25:25
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_FILTER_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_FILTER_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_FILTER_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_FILTER_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_FILTER_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_FILTER_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_FILTER_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_FILTER_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_ZIN_FILTER_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_DETECTED_SHIFT                 _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_DETECTED_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_DETECTED_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_DETECTED_RANGE                 26:26
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_DETECTED_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_DETECTED_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_DETECTED_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_DETECTED_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_DETECTED_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_DETECTED_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_DETECTED_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_DETECTED_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_DETECTED_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_INTR_EN_SHIFT                  _MK_SHIFT_CONST(27)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_INTR_EN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_INTR_EN_RANGE                  27:27
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_INTR_EN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_INTR_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_INTR_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_INTR_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_INTR_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_INTR_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_INTR_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_INTR_EN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_DCD_INTR_EN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECT_EN_SHIFT                        _MK_SHIFT_CONST(28)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECT_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECT_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECT_EN_RANGE                        28:28
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECT_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECT_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECT_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECT_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECT_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECTED_SHIFT                 _MK_SHIFT_CONST(29)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECTED_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECTED_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECTED_RANGE                 29:29
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECTED_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECTED_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECTED_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECTED_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECTED_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECTED_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECTED_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECTED_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_DETECTED_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_INTR_EN_SHIFT                  _MK_SHIFT_CONST(30)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_INTR_EN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_INTR_EN_RANGE                  30:30
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_INTR_EN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_INTR_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_INTR_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_INTR_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_INTR_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_INTR_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_INTR_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_INTR_EN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_SRP_INTR_EN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_GENERATE_SRP_SHIFT                 _MK_SHIFT_CONST(31)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_GENERATE_SRP_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_GENERATE_SRP_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_GENERATE_SRP_RANGE                 31:31
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_GENERATE_SRP_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_GENERATE_SRP_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_GENERATE_SRP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_GENERATE_SRP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_GENERATE_SRP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_GENERATE_SRP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_GENERATE_SRP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_GENERATE_SRP_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0_GENERATE_SRP_YES                   _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0                    _MK_ADDR_CONST(0x144)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_SECURE                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_DUAL                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_SCR                        0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_WORD_COUNT                         0x1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_RESET_VAL                  _MK_MASK_CONST(0x40)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_RESET_MASK                         _MK_MASK_CONST(0xff1fdf)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_READ_MASK                  _MK_MASK_CONST(0xff1fdf)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_WRITE_MASK                         _MK_MASK_CONST(0xff1fd0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P0_DET_SHIFT                       _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P0_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P0_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P0_DET_RANGE                       0:0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P0_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P0_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P0_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P0_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P0_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P0_DET_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P0_DET_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P0_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P0_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P7_DET_SHIFT                       _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P7_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P7_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P7_DET_RANGE                       1:1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P7_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P7_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P7_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P7_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P7_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P7_DET_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P7_DET_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P7_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VON_DIV2P7_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P0_DET_SHIFT                       _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P0_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P0_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P0_DET_RANGE                       2:2
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P0_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P0_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P0_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P0_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P0_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P0_DET_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P0_DET_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P0_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P0_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P7_DET_SHIFT                       _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P7_DET_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P7_DET_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P7_DET_RANGE                       3:3
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P7_DET_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P7_DET_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P7_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P7_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P7_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P7_DET_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P7_DET_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P7_DET_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VOP_DIV2P7_DET_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_DIV_DET_EN_SHIFT                   _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_DIV_DET_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_DIV_DET_EN_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_DIV_DET_EN_RANGE                   4:4
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_DIV_DET_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_DIV_DET_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_DIV_DET_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_DIV_DET_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_DIV_DET_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_DIV_DET_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_DIV_DET_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_DIV_DET_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_DIV_DET_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_PD_VREG_SHIFT                      _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_PD_VREG_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_PD_VREG_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_PD_VREG_RANGE                      6:6
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_PD_VREG_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_PD_VREG_DEFAULT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_PD_VREG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_PD_VREG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_PD_VREG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_PD_VREG_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_PD_VREG_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_LEV_SHIFT                     _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_LEV_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_LEV_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_LEV_RANGE                     8:7
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_LEV_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_LEV_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_LEV_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_LEV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_LEV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_LEV_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_LEV_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DYN_DLY_SHIFT                 _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DYN_DLY_FIELD                 _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DYN_DLY_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DYN_DLY_RANGE                 10:9
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DYN_DLY_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DYN_DLY_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DYN_DLY_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DYN_DLY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DYN_DLY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DYN_DLY_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DYN_DLY_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DIR_SHIFT                     _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DIR_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DIR_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DIR_RANGE                     12:11
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DIR_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DIR_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DIR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DIR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DIR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DIR_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_VREG_DIR_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_SHIFT                       _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_RANGE                       16:16
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_VAL_RANGE                   17:17
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPD_OVRD_VAL_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_SHIFT                       _MK_SHIFT_CONST(18)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_RANGE                       18:18
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(19)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_VAL_RANGE                   19:19
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBOP_RPU_OVRD_VAL_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_SHIFT                       _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_RANGE                       20:20
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_VAL_RANGE                   21:21
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPD_OVRD_VAL_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_SHIFT                       _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_RANGE                       22:22
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_VAL_SHIFT                   _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_VAL_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_VAL_RANGE                   23:23
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_VAL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_VAL_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0_USBON_RPU_OVRD_VAL_YES                     _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0                       _MK_ADDR_CONST(0x148)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_DUAL                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_RESET_VAL                     _MK_MASK_CONST(0x26cc88e0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_RESET_MASK                    _MK_MASK_CONST(0x3fffffff)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_READ_MASK                     _MK_MASK_CONST(0x3fffffff)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_WRITE_MASK                    _MK_MASK_CONST(0x3fffffff)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_CURR_LEVEL_SHIFT                   _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_CURR_LEVEL_FIELD                   _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_CURR_LEVEL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_CURR_LEVEL_RANGE                   5:0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_CURR_LEVEL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_CURR_LEVEL_DEFAULT                 _MK_MASK_CONST(0x20)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_CURR_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_CURR_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_CURR_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_CURR_LEVEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_CURR_LEVEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_SLEW_SHIFT                 _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_SLEW_FIELD                 _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_SLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_SLEW_RANGE                 8:6
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_SLEW_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_SLEW_DEFAULT                       _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_SLEW_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_SLEW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_SLEW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_SLEW_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_HS_SLEW_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_RSLEW_SHIFT                        _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_RSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_RSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_RSLEW_RANGE                        12:9
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_RSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_RSLEW_DEFAULT                      _MK_MASK_CONST(0x4)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_RSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_RSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_RSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_RSLEW_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_RSLEW_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_FSLEW_SHIFT                        _MK_SHIFT_CONST(13)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_FSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_FSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_FSLEW_RANGE                        16:13
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_FSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_FSLEW_DEFAULT                      _MK_MASK_CONST(0x4)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_FSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_FSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_FSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_FSLEW_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_FS_FSLEW_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_RSLEW_SHIFT                        _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_RSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_RSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_RSLEW_RANGE                        20:17
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_RSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_RSLEW_DEFAULT                      _MK_MASK_CONST(0x6)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_RSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_RSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_RSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_RSLEW_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_RSLEW_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_FSLEW_SHIFT                        _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_FSLEW_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_FSLEW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_FSLEW_RANGE                        24:21
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_FSLEW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_FSLEW_DEFAULT                      _MK_MASK_CONST(0x6)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_FSLEW_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_FSLEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_FSLEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_FSLEW_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_LS_FSLEW_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_TERM_SEL_SHIFT                        _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_TERM_SEL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_TERM_SEL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_TERM_SEL_RANGE                        25:25
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_TERM_SEL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_TERM_SEL_DEFAULT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_TERM_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_TERM_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_TERM_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_TERM_SEL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_TERM_SEL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_SHIFT                      _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_RANGE                      26:26
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_DEFAULT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_SHIFT                     _MK_SHIFT_CONST(27)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_RANGE                     27:27
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_OVRD_EN_SHIFT                     _MK_SHIFT_CONST(28)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_OVRD_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_OVRD_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_OVRD_EN_RANGE                     28:28
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_OVRD_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_OVRD_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_OVRD_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_OVRD_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_OVRD_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_OVRD_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD2_OVRD_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_ZI_SHIFT                   _MK_SHIFT_CONST(29)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_ZI_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_ZI_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_ZI_RANGE                   29:29
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_ZI_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_ZI_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_ZI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_ZI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_ZI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_ZI_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_ZI_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0_PD_ZI__PROD                   _MK_ENUM_CONST(0)


// Register XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0                       _MK_ADDR_CONST(0x14c)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_DUAL                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RESET_VAL                     _MK_MASK_CONST(0x20101044)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RESET_MASK                    _MK_MASK_CONST(0x7fff9fff)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_READ_MASK                     _MK_MASK_CONST(0x7fff9fff)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_WRITE_MASK                    _MK_MASK_CONST(0x7dff9fff)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_SHIFT                    _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_RANGE                    0:0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_SHIFT                    _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_RANGE                    1:1
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DR_SHIFT                   _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DR_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DR_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DR_RANGE                   2:2
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DR_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DR_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_TERM_RANGE_ADJ_SHIFT                  _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_TERM_RANGE_ADJ_FIELD                  _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_TERM_RANGE_ADJ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_TERM_RANGE_ADJ_RANGE                  6:3
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_TERM_RANGE_ADJ_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_TERM_RANGE_ADJ_DEFAULT                        _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_TERM_RANGE_ADJ_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_TERM_RANGE_ADJ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_TERM_RANGE_ADJ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_TERM_RANGE_ADJ_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_TERM_RANGE_ADJ_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SPARE_SHIFT                   _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SPARE_FIELD                   _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SPARE_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SPARE_RANGE                   10:7
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SPARE_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SPARE_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SPARE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_SPARE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_COUP_EN_SHIFT                      _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_COUP_EN_FIELD                      _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_COUP_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_COUP_EN_RANGE                      12:11
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_COUP_EN_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_COUP_EN_DEFAULT                    _MK_MASK_CONST(0x2)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_COUP_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_COUP_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_COUP_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_COUP_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_COUP_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_VAL_SHIFT                        _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_VAL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_VAL_RANGE                        15:15
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_VAL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_VAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_CHRP_OVRD_VAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_VAL_SHIFT                        _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_VAL_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_VAL_RANGE                        16:16
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_VAL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_VAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PD_DISC_OVRD_VAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PTERM_RANGE_ADJ_SHIFT                 _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PTERM_RANGE_ADJ_FIELD                 _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PTERM_RANGE_ADJ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PTERM_RANGE_ADJ_RANGE                 20:17
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PTERM_RANGE_ADJ_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PTERM_RANGE_ADJ_DEFAULT                       _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PTERM_RANGE_ADJ_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PTERM_RANGE_ADJ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PTERM_RANGE_ADJ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PTERM_RANGE_ADJ_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_PTERM_RANGE_ADJ_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_EN_SHIFT                     _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_EN_RANGE                     21:21
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SHIFT                    _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_VAL_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_VAL_RANGE                    22:22
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_VAL_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_HS_LOOPBACK_OVRD_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_OVRD_SHIFT                 _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_OVRD_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_OVRD_RANGE                 23:23
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_OVRD_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_OVRD_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_OVRD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_OVRD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_OVRD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_OVRD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_OVRD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_LOW_SHIFT                  _MK_SHIFT_CONST(24)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_LOW_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_LOW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_LOW_RANGE                  24:24
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_LOW_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_LOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_LOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_LOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_LOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_LOW_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_SWITCH_LOW_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_STATUS_HIGH_SHIFT                 _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_STATUS_HIGH_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_STATUS_HIGH_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_STATUS_HIGH_RANGE                 25:25
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_STATUS_HIGH_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_STATUS_HIGH_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_STATUS_HIGH_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_STATUS_HIGH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_STATUS_HIGH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_STATUS_HIGH_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPU_STATUS_HIGH_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPD_CTRL_SHIFT                        _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPD_CTRL_FIELD                        _MK_FIELD_CONST(0x1f, XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPD_CTRL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPD_CTRL_RANGE                        30:26
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPD_CTRL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPD_CTRL_DEFAULT                      _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPD_CTRL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPD_CTRL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPD_CTRL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPD_CTRL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0_RPD_CTRL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0                       _MK_ADDR_CONST(0x150)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_DUAL                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RESET_MASK                    _MK_MASK_CONST(0xf3f3fff3)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_READ_MASK                     _MK_MASK_CONST(0xf3f3fff3)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_WRITE_MASK                    _MK_MASK_CONST(0xf3f3fff3)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_AUTO_SWITCH_EN_SHIFT                      _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_AUTO_SWITCH_EN_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_AUTO_SWITCH_EN_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_AUTO_SWITCH_EN_RANGE                      0:0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_AUTO_SWITCH_EN_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_AUTO_SWITCH_EN_DEFAULT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_AUTO_SWITCH_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_AUTO_SWITCH_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_AUTO_SWITCH_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_AUTO_SWITCH_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_AUTO_SWITCH_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_HIGH_FIXED_SHIFT                  _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_HIGH_FIXED_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_HIGH_FIXED_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_HIGH_FIXED_RANGE                  1:1
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_HIGH_FIXED_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_HIGH_FIXED_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_HIGH_FIXED_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_HIGH_FIXED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_HIGH_FIXED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_HIGH_FIXED_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_RPU_HIGH_FIXED_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_SHIFT                       _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_FIELD                       _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_RANGE                       9:4
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_SHIFT                       _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_FIELD                       _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_RANGE                       15:10
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_OVRD_SHIFT                  _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_OVRD_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_OVRD_RANGE                  16:16
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_OVRD_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_OVRD_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_OVRD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_OVRD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_OVRD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_OVRD_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_PCTRL_TRK_OVRD_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_OVRD_SHIFT                  _MK_SHIFT_CONST(17)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_OVRD_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_OVRD_RANGE                  17:17
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_OVRD_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_OVRD_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_OVRD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_OVRD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_OVRD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_OVRD_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_TRK_OVRD_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_SW_SHIFT                        _MK_SHIFT_CONST(20)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_SW_FIELD                        _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_SW_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_SW_RANGE                        25:20
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_SW_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_SW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_SW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_SW_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_TCTRL_SW_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SPARE_AO_SHIFT                        _MK_SHIFT_CONST(28)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SPARE_AO_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SPARE_AO_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SPARE_AO_RANGE                        31:28
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SPARE_AO_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SPARE_AO_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SPARE_AO_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SPARE_AO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SPARE_AO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SPARE_AO_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0_SPARE_AO_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0                       _MK_ADDR_CONST(0x154)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_DUAL                  0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_SCR                   0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_RESET_MASK                    _MK_MASK_CONST(0x1cf)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_READ_MASK                     _MK_MASK_CONST(0x1cf)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_WRITE_MASK                    _MK_MASK_CONST(0x1cf)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_DIN_DLY_SEL_SHIFT                  _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_DIN_DLY_SEL_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_DIN_DLY_SEL_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_DIN_DLY_SEL_RANGE                  0:0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_DIN_DLY_SEL_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_DIN_DLY_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_DIN_DLY_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_DIN_DLY_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_DIN_DLY_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_DIN_DLY_SEL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_DIN_DLY_SEL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_TXEQ_SHIFT                 _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_TXEQ_FIELD                 _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_TXEQ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_TXEQ_RANGE                 3:1
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_TXEQ_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_TXEQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_TXEQ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_TXEQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_TXEQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_TXEQ_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_TXEQ_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_RXEQ_SHIFT                 _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_RXEQ_FIELD                 _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_RXEQ_SHIFT)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_RXEQ_RANGE                 8:6
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_RXEQ_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_RXEQ_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_RXEQ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_RXEQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_RXEQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_RXEQ_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0_HS_RXEQ_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Reserved address 0x158

// Reserved address 0x15c

// Reserved address 0x160

// Reserved address 0x164

// Reserved address 0x168

// Reserved address 0x16c

// Reserved address 0x170

// Reserved address 0x174

// Reserved address 0x178

// Reserved address 0x17c

// Reserved address 0x180

// Reserved address 0x184

// Reserved address 0x188

// Reserved address 0x18c

// Reserved address 0x190

// Reserved address 0x194

// Reserved address 0x198

// Reserved address 0x19c

// Reserved address 0x1a0

// Reserved address 0x1a4

// Reserved address 0x1a8

// Reserved address 0x1ac

// Reserved address 0x1b0

// Reserved address 0x1b4

// Reserved address 0x1b8

// Reserved address 0x1bc

// Reserved address 0x1c0

// Reserved address 0x1c4

// Reserved address 0x1c8

// Reserved address 0x1cc

// Reserved address 0x1d0

// Reserved address 0x1d4

// Reserved address 0x1d8

// Reserved address 0x1dc

// Reserved address 0x1e0

// Reserved address 0x1e4

// Reserved address 0x1e8

// Reserved address 0x1ec

// Reserved address 0x1f0

// Reserved address 0x1f4

// Reserved address 0x1f8

// Reserved address 0x1fc

// Reserved address 0x200

// Reserved address 0x204

// Reserved address 0x208

// Reserved address 0x20c

// Reserved address 0x210

// Reserved address 0x214

// Reserved address 0x218

// Reserved address 0x21c

// Reserved address 0x220

// Reserved address 0x224

// Reserved address 0x228

// Reserved address 0x22c

// Reserved address 0x230

// Reserved address 0x234

// Reserved address 0x238

// Reserved address 0x23c

// Reserved address 0x240

// Reserved address 0x244

// Reserved address 0x248

// Reserved address 0x24c

// Reserved address 0x250

// Reserved address 0x254

// Reserved address 0x258

// Reserved address 0x25c

// Reserved address 0x260

// Reserved address 0x264

// Reserved address 0x268

// Reserved address 0x26c

// Reserved address 0x270

// Reserved address 0x274

// Reserved address 0x278

// Reserved address 0x27c

// Register XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0                 _MK_ADDR_CONST(0x280)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_SECURE                  0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_DUAL                    0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_SCR                     0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_WORD_COUNT                      0x1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_RESET_VAL                       _MK_MASK_CONST(0x5000)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_RESET_MASK                      _MK_MASK_CONST(0x1ffff)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_READ_MASK                       _MK_MASK_CONST(0x1ffff)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_WRITE_MASK                      _MK_MASK_CONST(0x1ffff)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_TDCD_DBNC_SHIFT                 _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_TDCD_DBNC_FIELD                 _MK_FIELD_CONST(0x7ff, XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_TDCD_DBNC_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_TDCD_DBNC_RANGE                 10:0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_TDCD_DBNC_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_TDCD_DBNC_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_TDCD_DBNC_DEFAULT_MASK                  _MK_MASK_CONST(0x7ff)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_TDCD_DBNC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_TDCD_DBNC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_TDCD_DBNC_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_TDCD_DBNC_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_IDDIG_DBNC_SHIFT                        _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_IDDIG_DBNC_FIELD                        _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_IDDIG_DBNC_SHIFT)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_IDDIG_DBNC_RANGE                        16:11
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_IDDIG_DBNC_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_IDDIG_DBNC_DEFAULT                      _MK_MASK_CONST(0xa)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_IDDIG_DBNC_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_IDDIG_DBNC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_IDDIG_DBNC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_IDDIG_DBNC_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0_IDDIG_DBNC_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0                       _MK_ADDR_CONST(0x284)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_DUAL                  0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SCR                   0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_RESET_VAL                     _MK_MASK_CONST(0x60e0b10)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_RESET_MASK                    _MK_MASK_CONST(0x1fff8fff)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_READ_MASK                     _MK_MASK_CONST(0x1fff8fff)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_WRITE_MASK                    _MK_MASK_CONST(0x1fff8fff)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_SQUELCH_LEVEL_SHIFT                        _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_SQUELCH_LEVEL_FIELD                        _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_SQUELCH_LEVEL_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_SQUELCH_LEVEL_RANGE                        2:0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_SQUELCH_LEVEL_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_SQUELCH_LEVEL_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_SQUELCH_LEVEL_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_SQUELCH_LEVEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_SQUELCH_LEVEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_SQUELCH_LEVEL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_SQUELCH_LEVEL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_DISCON_LEVEL_SHIFT                 _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_DISCON_LEVEL_FIELD                 _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_DISCON_LEVEL_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_DISCON_LEVEL_RANGE                 5:3
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_DISCON_LEVEL_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_DISCON_LEVEL_DEFAULT                       _MK_MASK_CONST(0x2)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_DISCON_LEVEL_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_DISCON_LEVEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_DISCON_LEVEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_DISCON_LEVEL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_DISCON_LEVEL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_CHIRP_LEVEL_SHIFT                  _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_CHIRP_LEVEL_FIELD                  _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_CHIRP_LEVEL_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_CHIRP_LEVEL_RANGE                  7:6
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_CHIRP_LEVEL_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_CHIRP_LEVEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_CHIRP_LEVEL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_CHIRP_LEVEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_CHIRP_LEVEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_CHIRP_LEVEL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_HS_CHIRP_LEVEL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TERM_OFFSET_SHIFT                     _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TERM_OFFSET_FIELD                     _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TERM_OFFSET_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TERM_OFFSET_RANGE                     10:8
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TERM_OFFSET_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TERM_OFFSET_DEFAULT                   _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TERM_OFFSET_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TERM_OFFSET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TERM_OFFSET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TERM_OFFSET_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TERM_OFFSET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_PD_SHIFT                      _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_PD_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_PD_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_PD_RANGE                      11:11
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_PD_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_PD_DEFAULT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_PD_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_PD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_VREF_CTRL_SHIFT                       _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_VREF_CTRL_FIELD                       _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_VREF_CTRL_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_VREF_CTRL_RANGE                       17:15
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_VREF_CTRL_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_VREF_CTRL_DEFAULT                     _MK_MASK_CONST(0x4)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_VREF_CTRL_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_VREF_CTRL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_VREF_CTRL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_VREF_CTRL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_VREF_CTRL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TEMP_COEF_SHIFT                       _MK_SHIFT_CONST(18)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TEMP_COEF_FIELD                       _MK_FIELD_CONST(0x7, XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TEMP_COEF_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TEMP_COEF_RANGE                       20:18
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TEMP_COEF_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TEMP_COEF_DEFAULT                     _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TEMP_COEF_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TEMP_COEF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TEMP_COEF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TEMP_COEF_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_TEMP_COEF_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_CHG_DIV_SHIFT                 _MK_SHIFT_CONST(21)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_CHG_DIV_FIELD                 _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_CHG_DIV_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_CHG_DIV_RANGE                 24:21
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_CHG_DIV_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_CHG_DIV_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_CHG_DIV_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_CHG_DIV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_CHG_DIV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_CHG_DIV_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_CHG_DIV_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SPARE_SHIFT                   _MK_SHIFT_CONST(25)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SPARE_FIELD                   _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SPARE_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SPARE_RANGE                   28:25
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SPARE_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SPARE_DEFAULT                 _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SPARE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0_SPARE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0                       _MK_ADDR_CONST(0x288)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_SECURE                        0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_DUAL                  0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_SCR                   0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_RESET_VAL                     _MK_MASK_CONST(0x4820000)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_WRITE_MASK                    _MK_MASK_CONST(0xeffff000)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TCTRL_SHIFT                   _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TCTRL_FIELD                   _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TCTRL_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TCTRL_RANGE                   5:0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TCTRL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TCTRL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TCTRL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TCTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TCTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TCTRL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TCTRL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PCTRL_SHIFT                   _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PCTRL_FIELD                   _MK_FIELD_CONST(0x3f, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PCTRL_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PCTRL_RANGE                   11:6
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PCTRL_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PCTRL_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PCTRL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PCTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PCTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PCTRL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PCTRL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_TIMER_SHIFT                 _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_TIMER_FIELD                 _MK_FIELD_CONST(0x7f, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_TIMER_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_TIMER_RANGE                 18:12
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_TIMER_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_TIMER_DEFAULT                       _MK_MASK_CONST(0x20)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_TIMER_DEFAULT_MASK                  _MK_MASK_CONST(0x7f)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_TIMER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_TIMER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_TIMER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_TIMER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_TIMER__PROD                 _MK_ENUM_CONST(30)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_RESET_TIMER_SHIFT                    _MK_SHIFT_CONST(19)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_RESET_TIMER_FIELD                    _MK_FIELD_CONST(0x7f, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_RESET_TIMER_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_RESET_TIMER_RANGE                    25:19
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_RESET_TIMER_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_RESET_TIMER_DEFAULT                  _MK_MASK_CONST(0x10)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_RESET_TIMER_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_RESET_TIMER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_RESET_TIMER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_RESET_TIMER_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_RESET_TIMER_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_RESET_TIMER__PROD                    _MK_ENUM_CONST(10)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PD_TRK_SHIFT                  _MK_SHIFT_CONST(26)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PD_TRK_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PD_TRK_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PD_TRK_RANGE                  26:26
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PD_TRK_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PD_TRK_DEFAULT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PD_TRK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PD_TRK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PD_TRK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PD_TRK_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_PD_TRK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_SHIFT                       _MK_SHIFT_CONST(27)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_RANGE                       27:27
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_START_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_SHIFT                        _MK_SHIFT_CONST(28)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_RANGE                        28:28
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_DONE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_SW_OVRD_SHIFT                     _MK_SHIFT_CONST(29)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_SW_OVRD_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_SW_OVRD_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_SW_OVRD_RANGE                     29:29
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_SW_OVRD_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_SW_OVRD_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_SW_OVRD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_SW_OVRD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_SW_OVRD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_SW_OVRD_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_SW_OVRD_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_FORCE_TRK_CLK_EN_SHIFT                        _MK_SHIFT_CONST(30)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_FORCE_TRK_CLK_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_FORCE_TRK_CLK_EN_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_FORCE_TRK_CLK_EN_RANGE                        30:30
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_FORCE_TRK_CLK_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_FORCE_TRK_CLK_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_FORCE_TRK_CLK_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_FORCE_TRK_CLK_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_FORCE_TRK_CLK_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_FORCE_TRK_CLK_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_FORCE_TRK_CLK_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_COMPLETED_SHIFT                   _MK_SHIFT_CONST(31)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_COMPLETED_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_COMPLETED_SHIFT)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_COMPLETED_RANGE                   31:31
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_COMPLETED_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_COMPLETED_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_COMPLETED_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_COMPLETED_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_COMPLETED_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_COMPLETED_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0_TRK_COMPLETED_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Reserved address 0x28c

// Reserved address 0x290

// Reserved address 0x294

// Reserved address 0x298

// Reserved address 0x29c

// Reserved address 0x2a0

// Reserved address 0x2a4

// Reserved address 0x2a8

// Reserved address 0x2ac

// Reserved address 0x2b0

// Reserved address 0x2b4

// Reserved address 0x2b8

// Reserved address 0x2bc

// Reserved address 0x2c0

// Reserved address 0x2c4

// Reserved address 0x2c8

// Reserved address 0x2cc

// Reserved address 0x2d0

// Reserved address 0x2d4

// Reserved address 0x2d8

// Reserved address 0x2dc

// Reserved address 0x2e0

// Reserved address 0x2e4

// Reserved address 0x2e8

// Reserved address 0x2ec

// Reserved address 0x2f0

// Reserved address 0x2f4

// Reserved address 0x2f8

// Reserved address 0x2fc

// Reserved address 0x300

// Reserved address 0x304

// Reserved address 0x308

// Reserved address 0x30c

// Reserved address 0x310

// Reserved address 0x314

// Reserved address 0x318

// Reserved address 0x31c

// Reserved address 0x320

// Reserved address 0x324

// Reserved address 0x328

// Reserved address 0x32c

// Reserved address 0x330

// Reserved address 0x334

// Reserved address 0x338

// Reserved address 0x33c

// Reserved address 0x340

// Reserved address 0x344

// Reserved address 0x348

// Reserved address 0x34c

// Reserved address 0x350

// Reserved address 0x354

// Reserved address 0x358

// Reserved address 0x35c

// Register XUSB_PADCTL_USB2_VBUS_ID_0
#define XUSB_PADCTL_USB2_VBUS_ID_0                      _MK_ADDR_CONST(0x360)
#define XUSB_PADCTL_USB2_VBUS_ID_0_SECURE                       0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_DUAL                         0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_SCR                  0
#define XUSB_PADCTL_USB2_VBUS_ID_0_WORD_COUNT                   0x1
#define XUSB_PADCTL_USB2_VBUS_ID_0_RESET_VAL                    _MK_MASK_CONST(0x211000)
#define XUSB_PADCTL_USB2_VBUS_ID_0_RESET_MASK                   _MK_MASK_CONST(0x1ffffff)
#define XUSB_PADCTL_USB2_VBUS_ID_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_READ_MASK                    _MK_MASK_CONST(0x1ffffff)
#define XUSB_PADCTL_USB2_VBUS_ID_0_WRITE_MASK                   _MK_MASK_CONST(0x1bffc36)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_SHIFT                      _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_RANGE                      0:0
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_YES                        _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_ST_CHNG_SHIFT                      _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_ST_CHNG_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_ST_CHNG_RANGE                      1:1
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_ST_CHNG_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_ST_CHNG_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_ST_CHNG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_ST_CHNG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_ST_CHNG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_ST_CHNG_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_ST_CHNG_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_ST_CHNG_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_ST_CHNG_YES                        _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_SHIFT                 _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_RANGE                 2:2
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_SHIFT                     _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_RANGE                     3:3
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_ST_CHNG_SHIFT                     _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_ST_CHNG_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_ST_CHNG_RANGE                     4:4
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_ST_CHNG_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_ST_CHNG_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_ST_CHNG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_ST_CHNG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_ST_CHNG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_ST_CHNG_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_ST_CHNG_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_ST_CHNG_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_ST_CHNG_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_CHNG_INTR_EN_SHIFT                        _MK_SHIFT_CONST(5)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_CHNG_INTR_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_CHNG_INTR_EN_RANGE                        5:5
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_CHNG_INTR_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_CHNG_INTR_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_CHNG_INTR_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_CHNG_INTR_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_CHNG_INTR_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_CHNG_INTR_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_CHNG_INTR_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_CHNG_INTR_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_VALID_CHNG_INTR_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_SHIFT                  _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_RANGE                  6:6
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_A_SHIFT                        _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_A_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_A_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_A_RANGE                        7:7
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_A_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_A_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_A_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_A_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_A_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_A_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_A_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_A_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_A_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_B_SHIFT                        _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_B_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_B_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_B_RANGE                        8:8
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_B_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_B_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_B_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_B_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_B_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_B_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_C_SHIFT                        _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_C_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_C_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_C_RANGE                        9:9
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_C_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_C_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_C_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_C_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_C_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_C_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_C_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_C_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_C_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_ST_CHNG_SHIFT                  _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_ST_CHNG_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_ST_CHNG_RANGE                  10:10
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_ST_CHNG_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_ST_CHNG_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_ST_CHNG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_ST_CHNG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_ST_CHNG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_ST_CHNG_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_ST_CHNG_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_ST_CHNG_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_ST_CHNG_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_CHNG_INTR_EN_SHIFT                     _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_CHNG_INTR_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_CHNG_INTR_EN_RANGE                     11:11
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_CHNG_INTR_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_CHNG_INTR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_CHNG_INTR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_CHNG_INTR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_CHNG_INTR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_CHNG_INTR_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_CHNG_INTR_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_CHNG_INTR_EN_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_IDDIG_CHNG_INTR_EN_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_SOURCE_SELECT_SHIFT                     _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_SOURCE_SELECT_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_SOURCE_SELECT_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_SOURCE_SELECT_RANGE                     13:12
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_SOURCE_SELECT_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_SOURCE_SELECT_DEFAULT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_SOURCE_SELECT_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_SOURCE_SELECT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_SOURCE_SELECT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_SOURCE_SELECT_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_SOURCE_SELECT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_SOURCE_SELECT_VGPIO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_SOURCE_SELECT_VBUS_OVERRIDE                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_OVERRIDE_SHIFT                  _MK_SHIFT_CONST(14)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_OVERRIDE_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_OVERRIDE_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_OVERRIDE_RANGE                  14:14
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_OVERRIDE_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_OVERRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_OVERRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_OVERRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_OVERRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_OVERRIDE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_OVERRIDE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_OVERRIDE_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_OVERRIDE_YES                    _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_OVERRIDE_VBUS_ON                        _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_OVERRIDE_VBUS_OFF                       _MK_ENUM_CONST(0)

#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_OVERRIDE_SHIFT                   _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_OVERRIDE_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_OVERRIDE_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_OVERRIDE_RANGE                   15:15
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_OVERRIDE_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_OVERRIDE_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_OVERRIDE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_OVERRIDE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_OVERRIDE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_OVERRIDE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_OVERRIDE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_OVERRIDE_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_OVERRIDE_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_SOURCE_SELECT_SHIFT                       _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_SOURCE_SELECT_FIELD                       _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_VBUS_ID_0_ID_SOURCE_SELECT_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_SOURCE_SELECT_RANGE                       17:16
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_SOURCE_SELECT_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_SOURCE_SELECT_DEFAULT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_SOURCE_SELECT_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_SOURCE_SELECT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_SOURCE_SELECT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_SOURCE_SELECT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_SOURCE_SELECT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_SOURCE_SELECT_VGPIO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_SOURCE_SELECT_ID_OVERRIDE                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_OVERRIDE_SHIFT                    _MK_SHIFT_CONST(18)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_OVERRIDE_FIELD                    _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_VBUS_ID_0_ID_OVERRIDE_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_OVERRIDE_RANGE                    21:18
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_OVERRIDE_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_OVERRIDE_DEFAULT                  _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_OVERRIDE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_OVERRIDE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_OVERRIDE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_OVERRIDE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_OVERRIDE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_OVERRIDE_ID_GND                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_OVERRIDE_ID_A                     _MK_ENUM_CONST(4)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_OVERRIDE_ID_B                     _MK_ENUM_CONST(2)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_OVERRIDE_ID_C                     _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_ID_OVERRIDE_ID_FLOAT                 _MK_ENUM_CONST(8)

#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_SHIFT                    _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_RANGE                    22:22
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_ST_CHNG_SHIFT                    _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_ST_CHNG_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_ST_CHNG_RANGE                    23:23
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_ST_CHNG_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_ST_CHNG_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_ST_CHNG_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_ST_CHNG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_ST_CHNG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_ST_CHNG_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_ST_CHNG_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_ST_CHNG_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_ST_CHNG_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_CHNG_INTR_EN_SHIFT                       _MK_SHIFT_CONST(24)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_CHNG_INTR_EN_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_CHNG_INTR_EN_RANGE                       24:24
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_CHNG_INTR_EN_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_CHNG_INTR_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_CHNG_INTR_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_CHNG_INTR_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_CHNG_INTR_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_CHNG_INTR_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_CHNG_INTR_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_CHNG_INTR_EN_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_0_VBUS_WAKEUP_CHNG_INTR_EN_YES                 _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_USB2_VBUS_ID
#define XUSB_PADCTL_USB2_VBUS_ID                        _MK_ADDR_CONST(0x360)
#define XUSB_PADCTL_USB2_VBUS_ID_SECURE                         0x0
#define XUSB_PADCTL_USB2_VBUS_ID_DUAL                   0x0
#define XUSB_PADCTL_USB2_VBUS_ID_SCR                    0
#define XUSB_PADCTL_USB2_VBUS_ID_WORD_COUNT                     0x1
#define XUSB_PADCTL_USB2_VBUS_ID_RESET_VAL                      _MK_MASK_CONST(0x211000)
#define XUSB_PADCTL_USB2_VBUS_ID_RESET_MASK                     _MK_MASK_CONST(0x1ffffff)
#define XUSB_PADCTL_USB2_VBUS_ID_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_READ_MASK                      _MK_MASK_CONST(0x1ffffff)
#define XUSB_PADCTL_USB2_VBUS_ID_WRITE_MASK                     _MK_MASK_CONST(0x1bffc36)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_SHIFT                        _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_RANGE                        0:0
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_ST_CHNG_SHIFT                        _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_ST_CHNG_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_ST_CHNG_RANGE                        1:1
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_ST_CHNG_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_ST_CHNG_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_ST_CHNG_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_ST_CHNG_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_ST_CHNG_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_ST_CHNG_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_ST_CHNG_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_ST_CHNG_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_ST_CHNG_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_SHIFT                   _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_RANGE                   2:2
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_SHIFT                       _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_RANGE                       3:3
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_ST_CHNG_SHIFT                       _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_ST_CHNG_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_ST_CHNG_RANGE                       4:4
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_ST_CHNG_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_ST_CHNG_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_ST_CHNG_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_ST_CHNG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_ST_CHNG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_ST_CHNG_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_ST_CHNG_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_ST_CHNG_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_ST_CHNG_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_CHNG_INTR_EN_SHIFT                  _MK_SHIFT_CONST(5)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_CHNG_INTR_EN_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_CHNG_INTR_EN_RANGE                  5:5
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_CHNG_INTR_EN_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_CHNG_INTR_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_CHNG_INTR_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_CHNG_INTR_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_CHNG_INTR_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_CHNG_INTR_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_CHNG_INTR_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_CHNG_INTR_EN_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_VALID_CHNG_INTR_EN_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_SHIFT                    _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_IDDIG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_RANGE                    6:6
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_A_SHIFT                  _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_A_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_IDDIG_A_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_A_RANGE                  7:7
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_A_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_A_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_A_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_A_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_A_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_A_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_A_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_A_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_A_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_B_SHIFT                  _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_B_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_IDDIG_B_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_B_RANGE                  8:8
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_B_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_B_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_B_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_B_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_B_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_B_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_B_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_B_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_B_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_C_SHIFT                  _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_C_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_IDDIG_C_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_C_RANGE                  9:9
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_C_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_C_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_C_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_C_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_C_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_C_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_C_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_C_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_C_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_ST_CHNG_SHIFT                    _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_ST_CHNG_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_IDDIG_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_ST_CHNG_RANGE                    10:10
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_ST_CHNG_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_ST_CHNG_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_ST_CHNG_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_ST_CHNG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_ST_CHNG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_ST_CHNG_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_ST_CHNG_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_ST_CHNG_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_ST_CHNG_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_CHNG_INTR_EN_SHIFT                       _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_CHNG_INTR_EN_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_IDDIG_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_CHNG_INTR_EN_RANGE                       11:11
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_CHNG_INTR_EN_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_CHNG_INTR_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_CHNG_INTR_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_CHNG_INTR_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_CHNG_INTR_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_CHNG_INTR_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_CHNG_INTR_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_CHNG_INTR_EN_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_IDDIG_CHNG_INTR_EN_YES                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_SOURCE_SELECT_SHIFT                       _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_SOURCE_SELECT_FIELD                       _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_VBUS_ID_VBUS_SOURCE_SELECT_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_SOURCE_SELECT_RANGE                       13:12
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_SOURCE_SELECT_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_SOURCE_SELECT_DEFAULT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_SOURCE_SELECT_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_SOURCE_SELECT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_SOURCE_SELECT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_SOURCE_SELECT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_SOURCE_SELECT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_SOURCE_SELECT_VGPIO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_SOURCE_SELECT_VBUS_OVERRIDE                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_OVERRIDE_SHIFT                    _MK_SHIFT_CONST(14)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_OVERRIDE_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_VBUS_OVERRIDE_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_OVERRIDE_RANGE                    14:14
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_OVERRIDE_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_OVERRIDE_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_OVERRIDE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_OVERRIDE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_OVERRIDE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_OVERRIDE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_OVERRIDE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_OVERRIDE_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_OVERRIDE_YES                      _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_OVERRIDE_VBUS_ON                  _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_OVERRIDE_VBUS_OFF                 _MK_ENUM_CONST(0)

#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_OVERRIDE_SHIFT                     _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_OVERRIDE_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_OVERRIDE_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_OVERRIDE_RANGE                     15:15
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_OVERRIDE_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_OVERRIDE_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_OVERRIDE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_OVERRIDE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_OVERRIDE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_OVERRIDE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_OVERRIDE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_OVERRIDE_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_OVERRIDE_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_ID_SOURCE_SELECT_SHIFT                 _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_VBUS_ID_ID_SOURCE_SELECT_FIELD                 _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_VBUS_ID_ID_SOURCE_SELECT_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_ID_SOURCE_SELECT_RANGE                 17:16
#define XUSB_PADCTL_USB2_VBUS_ID_ID_SOURCE_SELECT_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_VBUS_ID_ID_SOURCE_SELECT_DEFAULT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_ID_SOURCE_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_VBUS_ID_ID_SOURCE_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_ID_SOURCE_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_ID_SOURCE_SELECT_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_ID_SOURCE_SELECT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_ID_SOURCE_SELECT_VGPIO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_ID_SOURCE_SELECT_ID_OVERRIDE                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_ID_OVERRIDE_SHIFT                      _MK_SHIFT_CONST(18)
#define XUSB_PADCTL_USB2_VBUS_ID_ID_OVERRIDE_FIELD                      _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_VBUS_ID_ID_OVERRIDE_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_ID_OVERRIDE_RANGE                      21:18
#define XUSB_PADCTL_USB2_VBUS_ID_ID_OVERRIDE_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_VBUS_ID_ID_OVERRIDE_DEFAULT                    _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_USB2_VBUS_ID_ID_OVERRIDE_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_VBUS_ID_ID_OVERRIDE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_ID_OVERRIDE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_ID_OVERRIDE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_ID_OVERRIDE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_ID_OVERRIDE_ID_GND                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_ID_OVERRIDE_ID_A                       _MK_ENUM_CONST(4)
#define XUSB_PADCTL_USB2_VBUS_ID_ID_OVERRIDE_ID_B                       _MK_ENUM_CONST(2)
#define XUSB_PADCTL_USB2_VBUS_ID_ID_OVERRIDE_ID_C                       _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_VBUS_ID_ID_OVERRIDE_ID_FLOAT                   _MK_ENUM_CONST(8)

#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_SHIFT                      _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_RANGE                      22:22
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_YES                        _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_ST_CHNG_SHIFT                      _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_ST_CHNG_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_ST_CHNG_RANGE                      23:23
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_ST_CHNG_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_ST_CHNG_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_ST_CHNG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_ST_CHNG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_ST_CHNG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_ST_CHNG_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_ST_CHNG_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_ST_CHNG_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_ST_CHNG_YES                        _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_CHNG_INTR_EN_SHIFT                 _MK_SHIFT_CONST(24)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_CHNG_INTR_EN_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_CHNG_INTR_EN_RANGE                 24:24
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_CHNG_INTR_EN_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_CHNG_INTR_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_CHNG_INTR_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_CHNG_INTR_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_CHNG_INTR_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_CHNG_INTR_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_CHNG_INTR_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_CHNG_INTR_EN_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_VBUS_WAKEUP_CHNG_INTR_EN_YES                   _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_USB2_VBUS_ID_1
#define XUSB_PADCTL_USB2_VBUS_ID_1                      _MK_ADDR_CONST(0x364)
#define XUSB_PADCTL_USB2_VBUS_ID_1_SECURE                       0x0
#define XUSB_PADCTL_USB2_VBUS_ID_1_DUAL                         0x0
#define XUSB_PADCTL_USB2_VBUS_ID_1_SCR                  0
#define XUSB_PADCTL_USB2_VBUS_ID_1_WORD_COUNT                   0x1
#define XUSB_PADCTL_USB2_VBUS_ID_1_RESET_VAL                    _MK_MASK_CONST(0x211000)
#define XUSB_PADCTL_USB2_VBUS_ID_1_RESET_MASK                   _MK_MASK_CONST(0x1ffffff)
#define XUSB_PADCTL_USB2_VBUS_ID_1_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_READ_MASK                    _MK_MASK_CONST(0x1ffffff)
#define XUSB_PADCTL_USB2_VBUS_ID_1_WRITE_MASK                   _MK_MASK_CONST(0x1bffc36)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_SHIFT                      _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_RANGE                      0:0
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_YES                        _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_ST_CHNG_SHIFT                      _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_ST_CHNG_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_ST_CHNG_RANGE                      1:1
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_ST_CHNG_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_ST_CHNG_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_ST_CHNG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_ST_CHNG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_ST_CHNG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_ST_CHNG_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_ST_CHNG_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_ST_CHNG_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_ST_CHNG_YES                        _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_SHIFT                 _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_RANGE                 2:2
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_SHIFT                     _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_RANGE                     3:3
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_ST_CHNG_SHIFT                     _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_ST_CHNG_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_ST_CHNG_RANGE                     4:4
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_ST_CHNG_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_ST_CHNG_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_ST_CHNG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_ST_CHNG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_ST_CHNG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_ST_CHNG_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_ST_CHNG_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_ST_CHNG_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_ST_CHNG_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_CHNG_INTR_EN_SHIFT                        _MK_SHIFT_CONST(5)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_CHNG_INTR_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_CHNG_INTR_EN_RANGE                        5:5
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_CHNG_INTR_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_CHNG_INTR_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_CHNG_INTR_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_CHNG_INTR_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_CHNG_INTR_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_CHNG_INTR_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_CHNG_INTR_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_CHNG_INTR_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_VALID_CHNG_INTR_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_SHIFT                  _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_RANGE                  6:6
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_A_SHIFT                        _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_A_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_A_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_A_RANGE                        7:7
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_A_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_A_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_A_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_A_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_A_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_A_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_A_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_A_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_A_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_B_SHIFT                        _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_B_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_B_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_B_RANGE                        8:8
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_B_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_B_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_B_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_B_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_B_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_B_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_C_SHIFT                        _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_C_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_C_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_C_RANGE                        9:9
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_C_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_C_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_C_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_C_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_C_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_C_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_C_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_C_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_C_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_ST_CHNG_SHIFT                  _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_ST_CHNG_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_ST_CHNG_RANGE                  10:10
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_ST_CHNG_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_ST_CHNG_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_ST_CHNG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_ST_CHNG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_ST_CHNG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_ST_CHNG_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_ST_CHNG_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_ST_CHNG_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_ST_CHNG_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_CHNG_INTR_EN_SHIFT                     _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_CHNG_INTR_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_CHNG_INTR_EN_RANGE                     11:11
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_CHNG_INTR_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_CHNG_INTR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_CHNG_INTR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_CHNG_INTR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_CHNG_INTR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_CHNG_INTR_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_CHNG_INTR_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_CHNG_INTR_EN_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_IDDIG_CHNG_INTR_EN_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_SOURCE_SELECT_SHIFT                     _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_SOURCE_SELECT_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_SOURCE_SELECT_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_SOURCE_SELECT_RANGE                     13:12
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_SOURCE_SELECT_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_SOURCE_SELECT_DEFAULT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_SOURCE_SELECT_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_SOURCE_SELECT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_SOURCE_SELECT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_SOURCE_SELECT_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_SOURCE_SELECT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_SOURCE_SELECT_VGPIO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_SOURCE_SELECT_VBUS_OVERRIDE                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_OVERRIDE_SHIFT                  _MK_SHIFT_CONST(14)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_OVERRIDE_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_OVERRIDE_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_OVERRIDE_RANGE                  14:14
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_OVERRIDE_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_OVERRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_OVERRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_OVERRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_OVERRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_OVERRIDE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_OVERRIDE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_OVERRIDE_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_OVERRIDE_YES                    _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_OVERRIDE_VBUS_ON                        _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_OVERRIDE_VBUS_OFF                       _MK_ENUM_CONST(0)

#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_OVERRIDE_SHIFT                   _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_OVERRIDE_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_OVERRIDE_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_OVERRIDE_RANGE                   15:15
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_OVERRIDE_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_OVERRIDE_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_OVERRIDE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_OVERRIDE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_OVERRIDE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_OVERRIDE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_OVERRIDE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_OVERRIDE_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_OVERRIDE_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_1_ID_SOURCE_SELECT_SHIFT                       _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_VBUS_ID_1_ID_SOURCE_SELECT_FIELD                       _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_VBUS_ID_1_ID_SOURCE_SELECT_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_1_ID_SOURCE_SELECT_RANGE                       17:16
#define XUSB_PADCTL_USB2_VBUS_ID_1_ID_SOURCE_SELECT_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_VBUS_ID_1_ID_SOURCE_SELECT_DEFAULT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_ID_SOURCE_SELECT_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_VBUS_ID_1_ID_SOURCE_SELECT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_ID_SOURCE_SELECT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_ID_SOURCE_SELECT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_ID_SOURCE_SELECT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_ID_SOURCE_SELECT_VGPIO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_ID_SOURCE_SELECT_ID_OVERRIDE                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_1_ID_OVERRIDE_SHIFT                    _MK_SHIFT_CONST(18)
#define XUSB_PADCTL_USB2_VBUS_ID_1_ID_OVERRIDE_FIELD                    _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_VBUS_ID_1_ID_OVERRIDE_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_1_ID_OVERRIDE_RANGE                    21:18
#define XUSB_PADCTL_USB2_VBUS_ID_1_ID_OVERRIDE_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_VBUS_ID_1_ID_OVERRIDE_DEFAULT                  _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_USB2_VBUS_ID_1_ID_OVERRIDE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_VBUS_ID_1_ID_OVERRIDE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_ID_OVERRIDE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_ID_OVERRIDE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_ID_OVERRIDE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_ID_OVERRIDE_ID_GND                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_ID_OVERRIDE_ID_A                     _MK_ENUM_CONST(4)
#define XUSB_PADCTL_USB2_VBUS_ID_1_ID_OVERRIDE_ID_B                     _MK_ENUM_CONST(2)
#define XUSB_PADCTL_USB2_VBUS_ID_1_ID_OVERRIDE_ID_C                     _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_ID_OVERRIDE_ID_FLOAT                 _MK_ENUM_CONST(8)

#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_SHIFT                    _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_RANGE                    22:22
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_ST_CHNG_SHIFT                    _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_ST_CHNG_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_ST_CHNG_RANGE                    23:23
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_ST_CHNG_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_ST_CHNG_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_ST_CHNG_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_ST_CHNG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_ST_CHNG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_ST_CHNG_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_ST_CHNG_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_ST_CHNG_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_ST_CHNG_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_CHNG_INTR_EN_SHIFT                       _MK_SHIFT_CONST(24)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_CHNG_INTR_EN_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_CHNG_INTR_EN_RANGE                       24:24
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_CHNG_INTR_EN_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_CHNG_INTR_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_CHNG_INTR_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_CHNG_INTR_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_CHNG_INTR_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_CHNG_INTR_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_CHNG_INTR_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_CHNG_INTR_EN_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_1_VBUS_WAKEUP_CHNG_INTR_EN_YES                 _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_USB2_VBUS_ID_2
#define XUSB_PADCTL_USB2_VBUS_ID_2                      _MK_ADDR_CONST(0x368)
#define XUSB_PADCTL_USB2_VBUS_ID_2_SECURE                       0x0
#define XUSB_PADCTL_USB2_VBUS_ID_2_DUAL                         0x0
#define XUSB_PADCTL_USB2_VBUS_ID_2_SCR                  0
#define XUSB_PADCTL_USB2_VBUS_ID_2_WORD_COUNT                   0x1
#define XUSB_PADCTL_USB2_VBUS_ID_2_RESET_VAL                    _MK_MASK_CONST(0x211000)
#define XUSB_PADCTL_USB2_VBUS_ID_2_RESET_MASK                   _MK_MASK_CONST(0x1ffffff)
#define XUSB_PADCTL_USB2_VBUS_ID_2_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_READ_MASK                    _MK_MASK_CONST(0x1ffffff)
#define XUSB_PADCTL_USB2_VBUS_ID_2_WRITE_MASK                   _MK_MASK_CONST(0x1bffc36)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_SHIFT                      _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_RANGE                      0:0
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_YES                        _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_ST_CHNG_SHIFT                      _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_ST_CHNG_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_ST_CHNG_RANGE                      1:1
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_ST_CHNG_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_ST_CHNG_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_ST_CHNG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_ST_CHNG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_ST_CHNG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_ST_CHNG_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_ST_CHNG_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_ST_CHNG_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_ST_CHNG_YES                        _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_SHIFT                 _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_RANGE                 2:2
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_SHIFT                     _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_RANGE                     3:3
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_ST_CHNG_SHIFT                     _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_ST_CHNG_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_ST_CHNG_RANGE                     4:4
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_ST_CHNG_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_ST_CHNG_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_ST_CHNG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_ST_CHNG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_ST_CHNG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_ST_CHNG_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_ST_CHNG_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_ST_CHNG_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_ST_CHNG_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_CHNG_INTR_EN_SHIFT                        _MK_SHIFT_CONST(5)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_CHNG_INTR_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_CHNG_INTR_EN_RANGE                        5:5
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_CHNG_INTR_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_CHNG_INTR_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_CHNG_INTR_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_CHNG_INTR_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_CHNG_INTR_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_CHNG_INTR_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_CHNG_INTR_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_CHNG_INTR_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_VALID_CHNG_INTR_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_SHIFT                  _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_RANGE                  6:6
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_A_SHIFT                        _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_A_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_A_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_A_RANGE                        7:7
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_A_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_A_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_A_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_A_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_A_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_A_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_A_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_A_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_A_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_B_SHIFT                        _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_B_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_B_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_B_RANGE                        8:8
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_B_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_B_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_B_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_B_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_B_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_B_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_C_SHIFT                        _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_C_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_C_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_C_RANGE                        9:9
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_C_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_C_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_C_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_C_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_C_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_C_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_C_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_C_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_C_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_ST_CHNG_SHIFT                  _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_ST_CHNG_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_ST_CHNG_RANGE                  10:10
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_ST_CHNG_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_ST_CHNG_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_ST_CHNG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_ST_CHNG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_ST_CHNG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_ST_CHNG_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_ST_CHNG_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_ST_CHNG_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_ST_CHNG_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_CHNG_INTR_EN_SHIFT                     _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_CHNG_INTR_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_CHNG_INTR_EN_RANGE                     11:11
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_CHNG_INTR_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_CHNG_INTR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_CHNG_INTR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_CHNG_INTR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_CHNG_INTR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_CHNG_INTR_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_CHNG_INTR_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_CHNG_INTR_EN_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_IDDIG_CHNG_INTR_EN_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_SOURCE_SELECT_SHIFT                     _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_SOURCE_SELECT_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_SOURCE_SELECT_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_SOURCE_SELECT_RANGE                     13:12
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_SOURCE_SELECT_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_SOURCE_SELECT_DEFAULT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_SOURCE_SELECT_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_SOURCE_SELECT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_SOURCE_SELECT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_SOURCE_SELECT_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_SOURCE_SELECT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_SOURCE_SELECT_VGPIO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_SOURCE_SELECT_VBUS_OVERRIDE                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_OVERRIDE_SHIFT                  _MK_SHIFT_CONST(14)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_OVERRIDE_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_OVERRIDE_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_OVERRIDE_RANGE                  14:14
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_OVERRIDE_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_OVERRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_OVERRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_OVERRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_OVERRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_OVERRIDE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_OVERRIDE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_OVERRIDE_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_OVERRIDE_YES                    _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_OVERRIDE_VBUS_ON                        _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_OVERRIDE_VBUS_OFF                       _MK_ENUM_CONST(0)

#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_OVERRIDE_SHIFT                   _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_OVERRIDE_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_OVERRIDE_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_OVERRIDE_RANGE                   15:15
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_OVERRIDE_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_OVERRIDE_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_OVERRIDE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_OVERRIDE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_OVERRIDE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_OVERRIDE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_OVERRIDE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_OVERRIDE_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_OVERRIDE_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_2_ID_SOURCE_SELECT_SHIFT                       _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_VBUS_ID_2_ID_SOURCE_SELECT_FIELD                       _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_VBUS_ID_2_ID_SOURCE_SELECT_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_2_ID_SOURCE_SELECT_RANGE                       17:16
#define XUSB_PADCTL_USB2_VBUS_ID_2_ID_SOURCE_SELECT_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_VBUS_ID_2_ID_SOURCE_SELECT_DEFAULT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_ID_SOURCE_SELECT_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_VBUS_ID_2_ID_SOURCE_SELECT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_ID_SOURCE_SELECT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_ID_SOURCE_SELECT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_ID_SOURCE_SELECT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_ID_SOURCE_SELECT_VGPIO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_ID_SOURCE_SELECT_ID_OVERRIDE                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_2_ID_OVERRIDE_SHIFT                    _MK_SHIFT_CONST(18)
#define XUSB_PADCTL_USB2_VBUS_ID_2_ID_OVERRIDE_FIELD                    _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_VBUS_ID_2_ID_OVERRIDE_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_2_ID_OVERRIDE_RANGE                    21:18
#define XUSB_PADCTL_USB2_VBUS_ID_2_ID_OVERRIDE_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_VBUS_ID_2_ID_OVERRIDE_DEFAULT                  _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_USB2_VBUS_ID_2_ID_OVERRIDE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_VBUS_ID_2_ID_OVERRIDE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_ID_OVERRIDE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_ID_OVERRIDE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_ID_OVERRIDE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_ID_OVERRIDE_ID_GND                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_ID_OVERRIDE_ID_A                     _MK_ENUM_CONST(4)
#define XUSB_PADCTL_USB2_VBUS_ID_2_ID_OVERRIDE_ID_B                     _MK_ENUM_CONST(2)
#define XUSB_PADCTL_USB2_VBUS_ID_2_ID_OVERRIDE_ID_C                     _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_ID_OVERRIDE_ID_FLOAT                 _MK_ENUM_CONST(8)

#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_SHIFT                    _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_RANGE                    22:22
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_ST_CHNG_SHIFT                    _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_ST_CHNG_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_ST_CHNG_RANGE                    23:23
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_ST_CHNG_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_ST_CHNG_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_ST_CHNG_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_ST_CHNG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_ST_CHNG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_ST_CHNG_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_ST_CHNG_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_ST_CHNG_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_ST_CHNG_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_CHNG_INTR_EN_SHIFT                       _MK_SHIFT_CONST(24)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_CHNG_INTR_EN_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_CHNG_INTR_EN_RANGE                       24:24
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_CHNG_INTR_EN_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_CHNG_INTR_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_CHNG_INTR_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_CHNG_INTR_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_CHNG_INTR_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_CHNG_INTR_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_CHNG_INTR_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_CHNG_INTR_EN_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_2_VBUS_WAKEUP_CHNG_INTR_EN_YES                 _MK_ENUM_CONST(1)


// Register XUSB_PADCTL_USB2_VBUS_ID_3
#define XUSB_PADCTL_USB2_VBUS_ID_3                      _MK_ADDR_CONST(0x36c)
#define XUSB_PADCTL_USB2_VBUS_ID_3_SECURE                       0x0
#define XUSB_PADCTL_USB2_VBUS_ID_3_DUAL                         0x0
#define XUSB_PADCTL_USB2_VBUS_ID_3_SCR                  0
#define XUSB_PADCTL_USB2_VBUS_ID_3_WORD_COUNT                   0x1
#define XUSB_PADCTL_USB2_VBUS_ID_3_RESET_VAL                    _MK_MASK_CONST(0x211000)
#define XUSB_PADCTL_USB2_VBUS_ID_3_RESET_MASK                   _MK_MASK_CONST(0x1ffffff)
#define XUSB_PADCTL_USB2_VBUS_ID_3_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_READ_MASK                    _MK_MASK_CONST(0x1ffffff)
#define XUSB_PADCTL_USB2_VBUS_ID_3_WRITE_MASK                   _MK_MASK_CONST(0x1bffc36)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_SHIFT                      _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_RANGE                      0:0
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_YES                        _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_ST_CHNG_SHIFT                      _MK_SHIFT_CONST(1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_ST_CHNG_FIELD                      _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_ST_CHNG_RANGE                      1:1
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_ST_CHNG_WOFFSET                    0x0
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_ST_CHNG_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_ST_CHNG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_ST_CHNG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_ST_CHNG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_ST_CHNG_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_ST_CHNG_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_ST_CHNG_NO                 _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_ST_CHNG_YES                        _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_SHIFT                 _MK_SHIFT_CONST(2)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_FIELD                 _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_RANGE                 2:2
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_WOFFSET                       0x0
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_NO                    _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_OTG_VBUS_SESS_VLD_CHNG_INTR_EN_YES                   _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_SHIFT                     _MK_SHIFT_CONST(3)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_RANGE                     3:3
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_ST_CHNG_SHIFT                     _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_ST_CHNG_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_ST_CHNG_RANGE                     4:4
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_ST_CHNG_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_ST_CHNG_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_ST_CHNG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_ST_CHNG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_ST_CHNG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_ST_CHNG_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_ST_CHNG_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_ST_CHNG_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_ST_CHNG_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_CHNG_INTR_EN_SHIFT                        _MK_SHIFT_CONST(5)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_CHNG_INTR_EN_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_CHNG_INTR_EN_RANGE                        5:5
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_CHNG_INTR_EN_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_CHNG_INTR_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_CHNG_INTR_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_CHNG_INTR_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_CHNG_INTR_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_CHNG_INTR_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_CHNG_INTR_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_CHNG_INTR_EN_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_VALID_CHNG_INTR_EN_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_SHIFT                  _MK_SHIFT_CONST(6)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_RANGE                  6:6
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_A_SHIFT                        _MK_SHIFT_CONST(7)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_A_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_A_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_A_RANGE                        7:7
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_A_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_A_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_A_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_A_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_A_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_A_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_A_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_A_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_A_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_B_SHIFT                        _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_B_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_B_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_B_RANGE                        8:8
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_B_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_B_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_B_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_B_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_B_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_B_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_C_SHIFT                        _MK_SHIFT_CONST(9)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_C_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_C_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_C_RANGE                        9:9
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_C_WOFFSET                      0x0
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_C_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_C_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_C_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_C_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_C_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_C_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_C_NO                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_C_YES                  _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_ST_CHNG_SHIFT                  _MK_SHIFT_CONST(10)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_ST_CHNG_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_ST_CHNG_RANGE                  10:10
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_ST_CHNG_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_ST_CHNG_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_ST_CHNG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_ST_CHNG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_ST_CHNG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_ST_CHNG_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_ST_CHNG_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_ST_CHNG_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_ST_CHNG_YES                    _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_CHNG_INTR_EN_SHIFT                     _MK_SHIFT_CONST(11)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_CHNG_INTR_EN_FIELD                     _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_CHNG_INTR_EN_RANGE                     11:11
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_CHNG_INTR_EN_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_CHNG_INTR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_CHNG_INTR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_CHNG_INTR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_CHNG_INTR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_CHNG_INTR_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_CHNG_INTR_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_CHNG_INTR_EN_NO                        _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_IDDIG_CHNG_INTR_EN_YES                       _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_SOURCE_SELECT_SHIFT                     _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_SOURCE_SELECT_FIELD                     _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_SOURCE_SELECT_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_SOURCE_SELECT_RANGE                     13:12
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_SOURCE_SELECT_WOFFSET                   0x0
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_SOURCE_SELECT_DEFAULT                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_SOURCE_SELECT_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_SOURCE_SELECT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_SOURCE_SELECT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_SOURCE_SELECT_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_SOURCE_SELECT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_SOURCE_SELECT_VGPIO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_SOURCE_SELECT_VBUS_OVERRIDE                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_OVERRIDE_SHIFT                  _MK_SHIFT_CONST(14)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_OVERRIDE_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_OVERRIDE_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_OVERRIDE_RANGE                  14:14
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_OVERRIDE_WOFFSET                        0x0
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_OVERRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_OVERRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_OVERRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_OVERRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_OVERRIDE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_OVERRIDE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_OVERRIDE_NO                     _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_OVERRIDE_YES                    _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_OVERRIDE_VBUS_ON                        _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_OVERRIDE_VBUS_OFF                       _MK_ENUM_CONST(0)

#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_OVERRIDE_SHIFT                   _MK_SHIFT_CONST(15)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_OVERRIDE_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_OVERRIDE_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_OVERRIDE_RANGE                   15:15
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_OVERRIDE_WOFFSET                 0x0
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_OVERRIDE_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_OVERRIDE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_OVERRIDE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_OVERRIDE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_OVERRIDE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_OVERRIDE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_OVERRIDE_NO                      _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_OVERRIDE_YES                     _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_3_ID_SOURCE_SELECT_SHIFT                       _MK_SHIFT_CONST(16)
#define XUSB_PADCTL_USB2_VBUS_ID_3_ID_SOURCE_SELECT_FIELD                       _MK_FIELD_CONST(0x3, XUSB_PADCTL_USB2_VBUS_ID_3_ID_SOURCE_SELECT_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_3_ID_SOURCE_SELECT_RANGE                       17:16
#define XUSB_PADCTL_USB2_VBUS_ID_3_ID_SOURCE_SELECT_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_VBUS_ID_3_ID_SOURCE_SELECT_DEFAULT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_ID_SOURCE_SELECT_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_USB2_VBUS_ID_3_ID_SOURCE_SELECT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_ID_SOURCE_SELECT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_ID_SOURCE_SELECT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_ID_SOURCE_SELECT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_ID_SOURCE_SELECT_VGPIO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_ID_SOURCE_SELECT_ID_OVERRIDE                 _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_3_ID_OVERRIDE_SHIFT                    _MK_SHIFT_CONST(18)
#define XUSB_PADCTL_USB2_VBUS_ID_3_ID_OVERRIDE_FIELD                    _MK_FIELD_CONST(0xf, XUSB_PADCTL_USB2_VBUS_ID_3_ID_OVERRIDE_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_3_ID_OVERRIDE_RANGE                    21:18
#define XUSB_PADCTL_USB2_VBUS_ID_3_ID_OVERRIDE_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_VBUS_ID_3_ID_OVERRIDE_DEFAULT                  _MK_MASK_CONST(0x8)
#define XUSB_PADCTL_USB2_VBUS_ID_3_ID_OVERRIDE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_USB2_VBUS_ID_3_ID_OVERRIDE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_ID_OVERRIDE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_ID_OVERRIDE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_ID_OVERRIDE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_ID_OVERRIDE_ID_GND                   _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_ID_OVERRIDE_ID_A                     _MK_ENUM_CONST(4)
#define XUSB_PADCTL_USB2_VBUS_ID_3_ID_OVERRIDE_ID_B                     _MK_ENUM_CONST(2)
#define XUSB_PADCTL_USB2_VBUS_ID_3_ID_OVERRIDE_ID_C                     _MK_ENUM_CONST(1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_ID_OVERRIDE_ID_FLOAT                 _MK_ENUM_CONST(8)

#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_SHIFT                    _MK_SHIFT_CONST(22)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_RANGE                    22:22
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_ST_CHNG_SHIFT                    _MK_SHIFT_CONST(23)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_ST_CHNG_FIELD                    _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_ST_CHNG_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_ST_CHNG_RANGE                    23:23
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_ST_CHNG_WOFFSET                  0x0
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_ST_CHNG_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_ST_CHNG_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_ST_CHNG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_ST_CHNG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_ST_CHNG_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_ST_CHNG_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_ST_CHNG_NO                       _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_ST_CHNG_YES                      _MK_ENUM_CONST(1)

#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_CHNG_INTR_EN_SHIFT                       _MK_SHIFT_CONST(24)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_CHNG_INTR_EN_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_CHNG_INTR_EN_SHIFT)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_CHNG_INTR_EN_RANGE                       24:24
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_CHNG_INTR_EN_WOFFSET                     0x0
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_CHNG_INTR_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_CHNG_INTR_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_CHNG_INTR_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_CHNG_INTR_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_CHNG_INTR_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_CHNG_INTR_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_CHNG_INTR_EN_NO                  _MK_ENUM_CONST(0)
#define XUSB_PADCTL_USB2_VBUS_ID_3_VBUS_WAKEUP_CHNG_INTR_EN_YES                 _MK_ENUM_CONST(1)


// Reserved address 0x370

// Reserved address 0x374

// Reserved address 0x378

// Reserved address 0x37c

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// Reserved address 0x384

// Reserved address 0x388

// Reserved address 0x38c

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// Reserved address 0x394

// Reserved address 0x398

// Reserved address 0x39c

// Reserved address 0x3a0

// Reserved address 0x3a4

// Reserved address 0x3a8

// Reserved address 0x3ac

// Reserved address 0x3b0

// Reserved address 0x3b4

// Reserved address 0x3b8

// Reserved address 0x3bc

// Reserved address 0x3c0

// Reserved address 0x3c4

// Reserved address 0x3c8

// Reserved address 0x3cc

// Reserved address 0x3d0

// Reserved address 0x3d4

// Reserved address 0x3d8

// Reserved address 0x3dc

// Reserved address 0x3e0

// Reserved address 0x3e4

// Reserved address 0x3e8

// Reserved address 0x3ec

// Reserved address 0x3f0

// Reserved address 0x3f4

// Reserved address 0x3f8

// Reserved address 0x3fc

// Reserved address 0x400

// Reserved address 0x404

// Reserved address 0x408

// Reserved address 0x40c

// Reserved address 0x410

// Reserved address 0x414

// Reserved address 0x418

// Reserved address 0x41c

// Reserved address 0x420

// Reserved address 0x424

// Reserved address 0x428

// Reserved address 0x42c

// Reserved address 0x430

// Reserved address 0x434

// Reserved address 0x438

// Reserved address 0x43c

// Reserved address 0x440

// Reserved address 0x444

// Reserved address 0x448

// Reserved address 0x44c

// Reserved address 0x450

// Reserved address 0x454

// Reserved address 0x458

// Reserved address 0x45c

// Reserved address 0x460

// Reserved address 0x464

// Reserved address 0x468

// Reserved address 0x46c

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// Reserved address 0x474

// Reserved address 0x478

// Reserved address 0x47c

// Reserved address 0x480

// Reserved address 0x484

// Reserved address 0x488

// Reserved address 0x48c

// Reserved address 0x490

// Reserved address 0x494

// Reserved address 0x498

// Reserved address 0x49c

// Reserved address 0x4a0

// Reserved address 0x4a4

// Reserved address 0x4a8

// Reserved address 0x4ac

// Reserved address 0x4b0

// Reserved address 0x4b4

// Reserved address 0x4b8

// Reserved address 0x4bc

// Reserved address 0x4c0

// Reserved address 0x4c4

// Reserved address 0x4c8

// Reserved address 0x4cc

// Reserved address 0x4d0

// Reserved address 0x4d4

// Reserved address 0x4d8

// Reserved address 0x4dc

// Reserved address 0x4e0

// Reserved address 0x4e4

// Reserved address 0x4e8

// Reserved address 0x4ec

// Reserved address 0x4f0

// Reserved address 0x4f4

// Reserved address 0x4f8

// Reserved address 0x4fc

// Reserved address 0x500

// Reserved address 0x504

// Reserved address 0x508

// Reserved address 0x50c

// Reserved address 0x510

// Reserved address 0x514

// Reserved address 0x518

// Reserved address 0x51c

// Reserved address 0x520

// Reserved address 0x524

// Reserved address 0x528

// Reserved address 0x52c

// Reserved address 0x530

// Reserved address 0x534

// Reserved address 0x538

// Reserved address 0x53c

// Reserved address 0x540

// Reserved address 0x544

// Reserved address 0x548

// Reserved address 0x54c

// Reserved address 0x550

// Reserved address 0x554

// Reserved address 0x558

// Reserved address 0x55c

// Reserved address 0x560

// Reserved address 0x564

// Reserved address 0x568

// Reserved address 0x56c

// Reserved address 0x570

// Reserved address 0x574

// Reserved address 0x578

// Reserved address 0x57c

// Reserved address 0x580

// Reserved address 0x584

// Reserved address 0x588

// Reserved address 0x58c

// Reserved address 0x590

// Reserved address 0x594

// Reserved address 0x598

// Reserved address 0x59c

// Reserved address 0x5a0

// Reserved address 0x5a4

// Reserved address 0x5a8

// Reserved address 0x5ac

// Reserved address 0x5b0

// Reserved address 0x5b4

// Reserved address 0x5b8

// Reserved address 0x5bc

// Reserved address 0x5c0

// Reserved address 0x5c4

// Reserved address 0x5c8

// Reserved address 0x5cc

// Reserved address 0x5d0

// Reserved address 0x5d4

// Reserved address 0x5d8

// Reserved address 0x5dc

// Reserved address 0x5e0

// Reserved address 0x5e4

// Reserved address 0x5e8

// Reserved address 0x5ec

// Reserved address 0x5f0

// Reserved address 0x5f4

// Reserved address 0x5f8

// Reserved address 0x5fc

// Reserved address 0x600

// Reserved address 0x604

// Reserved address 0x608

// Reserved address 0x60c

// Reserved address 0x610

// Reserved address 0x614

// Reserved address 0x618

// Reserved address 0x61c

// Reserved address 0x620

// Reserved address 0x624

// Reserved address 0x628

// Reserved address 0x62c

// Reserved address 0x630

// Reserved address 0x634

// Reserved address 0x638

// Reserved address 0x63c

// Reserved address 0x640

// Reserved address 0x644

// Reserved address 0x648

// Reserved address 0x64c

// Reserved address 0x650

// Reserved address 0x654

// Reserved address 0x658

// Reserved address 0x65c

// Reserved address 0x660

// Reserved address 0x664

// Reserved address 0x668

// Reserved address 0x66c

// Reserved address 0x670

// Reserved address 0x674

// Reserved address 0x678

// Reserved address 0x67c

// Reserved address 0x680

// Reserved address 0x684

// Reserved address 0x688

// Reserved address 0x68c

// Reserved address 0x690

// Reserved address 0x694

// Reserved address 0x698

// Reserved address 0x69c

// Reserved address 0x6a0

// Reserved address 0x6a4

// Reserved address 0x6a8

// Reserved address 0x6ac

// Reserved address 0x6b0

// Reserved address 0x6b4

// Reserved address 0x6b8

// Reserved address 0x6bc

// Reserved address 0x6c0

// Reserved address 0x6c4

// Reserved address 0x6c8

// Reserved address 0x6cc

// Reserved address 0x6d0

// Reserved address 0x6d4

// Reserved address 0x6d8

// Reserved address 0x6dc

// Reserved address 0x6e0

// Reserved address 0x6e4

// Reserved address 0x6e8

// Reserved address 0x6ec

// Reserved address 0x6f0

// Reserved address 0x6f4

// Reserved address 0x6f8

// Reserved address 0x6fc

// Reserved address 0x700

// Reserved address 0x704

// Reserved address 0x708

// Reserved address 0x70c

// Reserved address 0x710

// Reserved address 0x714

// Reserved address 0x718

// Reserved address 0x71c

// Reserved address 0x720

// Reserved address 0x724

// Reserved address 0x728

// Reserved address 0x72c

// Reserved address 0x730

// Reserved address 0x734

// Reserved address 0x738

// Reserved address 0x73c

// Reserved address 0x740

// Reserved address 0x744

// Reserved address 0x748

// Reserved address 0x74c

// Reserved address 0x750

// Reserved address 0x754

// Reserved address 0x758

// Reserved address 0x75c

// Reserved address 0x760

// Reserved address 0x764

// Reserved address 0x768

// Reserved address 0x76c

// Reserved address 0x770

// Reserved address 0x774

// Reserved address 0x778

// Reserved address 0x77c

// Reserved address 0x780

// Reserved address 0x784

// Reserved address 0x788

// Reserved address 0x78c

// Reserved address 0x790

// Reserved address 0x794

// Reserved address 0x798

// Reserved address 0x79c

// Reserved address 0x7a0

// Reserved address 0x7a4

// Reserved address 0x7a8

// Reserved address 0x7ac

// Reserved address 0x7b0

// Reserved address 0x7b4

// Reserved address 0x7b8

// Reserved address 0x7bc

// Reserved address 0x7c0

// Reserved address 0x7c4

// Reserved address 0x7c8

// Reserved address 0x7cc

// Reserved address 0x7d0

// Reserved address 0x7d4

// Reserved address 0x7d8

// Reserved address 0x7dc

// Reserved address 0x7e0

// Reserved address 0x7e4

// Reserved address 0x7e8

// Reserved address 0x7ec

// Reserved address 0x7f0

// Reserved address 0x7f4

// Reserved address 0x7f8

// Reserved address 0x7fc

// Reserved address 0x800

// Reserved address 0x804

// Reserved address 0x808

// Reserved address 0x80c

// Reserved address 0x810

// Reserved address 0x814

// Reserved address 0x818

// Reserved address 0x81c

// Reserved address 0x820

// Reserved address 0x824

// Reserved address 0x828

// Reserved address 0x82c

// Reserved address 0x830

// Reserved address 0x834

// Reserved address 0x838

// Reserved address 0x83c

// Reserved address 0x840

// Reserved address 0x844

// Reserved address 0x848

// Reserved address 0x84c

// Reserved address 0x850

// Reserved address 0x854

// Reserved address 0x858

// Reserved address 0x85c

// Reserved address 0x860

// Reserved address 0x864

// Reserved address 0x868

// Reserved address 0x86c

// Reserved address 0x870

// Reserved address 0x874

// Reserved address 0x878

// Reserved address 0x87c

// Reserved address 0x880

// Reserved address 0x884

// Reserved address 0x888

// Reserved address 0x88c

// Reserved address 0x890

// Reserved address 0x894

// Reserved address 0x898

// Reserved address 0x89c

// Reserved address 0x8a0

// Reserved address 0x8a4

// Reserved address 0x8a8

// Reserved address 0x8ac

// Reserved address 0x8b0

// Reserved address 0x8b4

// Reserved address 0x8b8

// Reserved address 0x8bc

// Reserved address 0x8c0

// Reserved address 0x8c4

// Reserved address 0x8c8

// Reserved address 0x8cc

// Reserved address 0x8d0

// Reserved address 0x8d4

// Reserved address 0x8d8

// Reserved address 0x8dc

// Reserved address 0x8e0

// Reserved address 0x8e4

// Reserved address 0x8e8

// Reserved address 0x8ec

// Reserved address 0x8f0

// Reserved address 0x8f4

// Reserved address 0x8f8

// Reserved address 0x8fc

// Reserved address 0x900

// Reserved address 0x904

// Reserved address 0x908

// Reserved address 0x90c

// Reserved address 0x910

// Reserved address 0x914

// Reserved address 0x918

// Reserved address 0x91c

// Reserved address 0x920

// Reserved address 0x924

// Reserved address 0x928

// Reserved address 0x92c

// Reserved address 0x930

// Reserved address 0x934

// Reserved address 0x938

// Reserved address 0x93c

// Reserved address 0x940

// Reserved address 0x944

// Reserved address 0x948

// Reserved address 0x94c

// Reserved address 0x950

// Reserved address 0x954

// Reserved address 0x958

// Reserved address 0x95c

// Reserved address 0x960

// Reserved address 0x964

// Reserved address 0x968

// Reserved address 0x96c

// Reserved address 0x970

// Reserved address 0x974

// Reserved address 0x978

// Reserved address 0x97c

// Reserved address 0x980

// Reserved address 0x984

// Reserved address 0x988

// Reserved address 0x98c

// Reserved address 0x990

// Reserved address 0x994

// Reserved address 0x998

// Reserved address 0x99c

// Reserved address 0x9a0

// Reserved address 0x9a4

// Reserved address 0x9a8

// Reserved address 0x9ac

// Reserved address 0x9b0

// Reserved address 0x9b4

// Reserved address 0x9b8

// Reserved address 0x9bc

// Reserved address 0x9c0

// Reserved address 0x9c4

// Reserved address 0x9c8

// Reserved address 0x9cc

// Reserved address 0x9d0

// Reserved address 0x9d4

// Reserved address 0x9d8

// Reserved address 0x9dc

// Reserved address 0x9e0

// Reserved address 0x9e4

// Reserved address 0x9e8

// Reserved address 0x9ec

// Reserved address 0x9f0

// Reserved address 0x9f4

// Reserved address 0x9f8

// Reserved address 0x9fc

// Reserved address 0xa00

// Reserved address 0xa04

// Reserved address 0xa08

// Reserved address 0xa0c

// Reserved address 0xa10

// Reserved address 0xa14

// Reserved address 0xa18

// Reserved address 0xa1c

// Reserved address 0xa20

// Reserved address 0xa24

// Reserved address 0xa28

// Reserved address 0xa2c

// Reserved address 0xa30

// Reserved address 0xa34

// Reserved address 0xa38

// Reserved address 0xa3c

// Reserved address 0xa40

// Reserved address 0xa44

// Reserved address 0xa48

// Reserved address 0xa4c

// Reserved address 0xa50

// Reserved address 0xa54

// Reserved address 0xa58

// Reserved address 0xa5c

// Reserved address 0xa60

// Reserved address 0xa64

// Reserved address 0xa68

// Reserved address 0xa6c

// Reserved address 0xa70

// Reserved address 0xa74

// Reserved address 0xa78

// Reserved address 0xa7c

// Reserved address 0xa80

// Reserved address 0xa84

// Reserved address 0xa88

// Reserved address 0xa8c

// Reserved address 0xa90

// Reserved address 0xa94

// Reserved address 0xa98

// Reserved address 0xa9c

// Reserved address 0xaa0

// Reserved address 0xaa4

// Reserved address 0xaa8

// Reserved address 0xaac

// Reserved address 0xab0

// Reserved address 0xab4

// Reserved address 0xab8

// Reserved address 0xabc

// Reserved address 0xac0

// Reserved address 0xac4

// Reserved address 0xac8

// Reserved address 0xacc

// Reserved address 0xad0

// Reserved address 0xad4

// Reserved address 0xad8

// Reserved address 0xadc

// Reserved address 0xae0

// Reserved address 0xae4

// Reserved address 0xae8

// Reserved address 0xaec

// Reserved address 0xaf0

// Reserved address 0xaf4

// Reserved address 0xaf8

// Reserved address 0xafc

// Reserved address 0xb00

// Reserved address 0xb04

// Reserved address 0xb08

// Reserved address 0xb0c

// Reserved address 0xb10

// Reserved address 0xb14

// Reserved address 0xb18

// Reserved address 0xb1c

// Reserved address 0xb20

// Reserved address 0xb24

// Reserved address 0xb28

// Reserved address 0xb2c

// Reserved address 0xb30

// Reserved address 0xb34

// Reserved address 0xb38

// Reserved address 0xb3c

// Reserved address 0xb40

// Reserved address 0xb44

// Reserved address 0xb48

// Reserved address 0xb4c

// Reserved address 0xb50

// Reserved address 0xb54

// Reserved address 0xb58

// Reserved address 0xb5c

// Reserved address 0xb60

// Reserved address 0xb64

// Reserved address 0xb68

// Reserved address 0xb6c

// Reserved address 0xb70

// Reserved address 0xb74

// Reserved address 0xb78

// Reserved address 0xb7c

// Reserved address 0xb80

// Reserved address 0xb84

// Reserved address 0xb88

// Reserved address 0xb8c

// Reserved address 0xb90

// Reserved address 0xb94

// Reserved address 0xb98

// Reserved address 0xb9c

// Reserved address 0xba0

// Reserved address 0xba4

// Reserved address 0xba8

// Reserved address 0xbac

// Reserved address 0xbb0

// Reserved address 0xbb4

// Reserved address 0xbb8

// Reserved address 0xbbc

// Reserved address 0xbc0

// Reserved address 0xbc4

// Reserved address 0xbc8

// Reserved address 0xbcc

// Reserved address 0xbd0

// Reserved address 0xbd4

// Reserved address 0xbd8

// Reserved address 0xbdc

// Reserved address 0xbe0

// Reserved address 0xbe4

// Reserved address 0xbe8

// Reserved address 0xbec

// Reserved address 0xbf0

// Reserved address 0xbf4

// Reserved address 0xbf8

// Reserved address 0xbfc

// Reserved address 0xc00

// Reserved address 0xc04

// Reserved address 0xc08

// Reserved address 0xc0c

// Reserved address 0xc10

// Reserved address 0xc14

// Reserved address 0xc18

// Reserved address 0xc1c

// Reserved address 0xc20

// Reserved address 0xc24

// Reserved address 0xc28

// Reserved address 0xc2c

// Reserved address 0xc30

// Reserved address 0xc34

// Reserved address 0xc38

// Reserved address 0xc3c

// Reserved address 0xc40

// Reserved address 0xc44

// Reserved address 0xc48

// Reserved address 0xc4c

// Reserved address 0xc50

// Reserved address 0xc54

// Reserved address 0xc58

// Reserved address 0xc5c

// Reserved address 0xc60

// Reserved address 0xc64

// Reserved address 0xc68

// Reserved address 0xc6c

// Reserved address 0xc70

// Reserved address 0xc74

// Reserved address 0xc78

// Reserved address 0xc7c

// Reserved address 0xc80

// Reserved address 0xc84

// Reserved address 0xc88

// Reserved address 0xc8c

// Reserved address 0xc90

// Reserved address 0xc94

// Reserved address 0xc98

// Reserved address 0xc9c

// Reserved address 0xca0

// Reserved address 0xca4

// Reserved address 0xca8

// Reserved address 0xcac

// Reserved address 0xcb0

// Reserved address 0xcb4

// Reserved address 0xcb8

// Reserved address 0xcbc

// Reserved address 0xcc0

// Reserved address 0xcc4

// Reserved address 0xcc8

// Reserved address 0xccc

// Reserved address 0xcd0

// Reserved address 0xcd4

// Reserved address 0xcd8

// Reserved address 0xcdc

// Reserved address 0xce0

// Reserved address 0xce4

// Reserved address 0xce8

// Reserved address 0xcec

// Reserved address 0xcf0

// Reserved address 0xcf4

// Reserved address 0xcf8

// Reserved address 0xcfc

// Reserved address 0xd00

// Reserved address 0xd04

// Reserved address 0xd08

// Reserved address 0xd0c

// Reserved address 0xd10

// Reserved address 0xd14

// Reserved address 0xd18

// Reserved address 0xd1c

// Reserved address 0xd20

// Reserved address 0xd24

// Reserved address 0xd28

// Reserved address 0xd2c

// Reserved address 0xd30

// Reserved address 0xd34

// Reserved address 0xd38

// Reserved address 0xd3c

// Reserved address 0xd40

// Reserved address 0xd44

// Reserved address 0xd48

// Reserved address 0xd4c

// Reserved address 0xd50

// Reserved address 0xd54

// Reserved address 0xd58

// Reserved address 0xd5c

// Reserved address 0xd60

// Reserved address 0xd64

// Reserved address 0xd68

// Reserved address 0xd6c

// Reserved address 0xd70

// Reserved address 0xd74

// Reserved address 0xd78

// Reserved address 0xd7c

// Reserved address 0xd80

// Reserved address 0xd84

// Reserved address 0xd88

// Reserved address 0xd8c

// Reserved address 0xd90

// Reserved address 0xd94

// Reserved address 0xd98

// Reserved address 0xd9c

// Reserved address 0xda0

// Reserved address 0xda4

// Reserved address 0xda8

// Reserved address 0xdac

// Reserved address 0xdb0

// Reserved address 0xdb4

// Reserved address 0xdb8

// Reserved address 0xdbc

// Reserved address 0xdc0

// Reserved address 0xdc4

// Reserved address 0xdc8

// Reserved address 0xdcc

// Reserved address 0xdd0

// Reserved address 0xdd4

// Reserved address 0xdd8

// Reserved address 0xddc

// Reserved address 0xde0

// Reserved address 0xde4

// Reserved address 0xde8

// Reserved address 0xdec

// Reserved address 0xdf0

// Reserved address 0xdf4

// Reserved address 0xdf8

// Reserved address 0xdfc

// Reserved address 0xe00

// Reserved address 0xe04

// Reserved address 0xe08

// Reserved address 0xe0c

// Reserved address 0xe10

// Reserved address 0xe14

// Reserved address 0xe18

// Reserved address 0xe1c

// Reserved address 0xe20

// Reserved address 0xe24

// Reserved address 0xe28

// Reserved address 0xe2c

// Reserved address 0xe30

// Reserved address 0xe34

// Reserved address 0xe38

// Reserved address 0xe3c

// Reserved address 0xe40

// Reserved address 0xe44

// Reserved address 0xe48

// Reserved address 0xe4c

// Reserved address 0xe50

// Reserved address 0xe54

// Reserved address 0xe58

// Reserved address 0xe5c

// Reserved address 0xe60

// Reserved address 0xe64

// Reserved address 0xe68

// Reserved address 0xe6c

// Reserved address 0xe70

// Reserved address 0xe74

// Reserved address 0xe78

// Reserved address 0xe7c

// Reserved address 0xe80

// Reserved address 0xe84

// Reserved address 0xe88

// Reserved address 0xe8c

// Reserved address 0xe90

// Reserved address 0xe94

// Reserved address 0xe98

// Reserved address 0xe9c

// Reserved address 0xea0

// Reserved address 0xea4

// Reserved address 0xea8

// Reserved address 0xeac

// Reserved address 0xeb0

// Reserved address 0xeb4

// Reserved address 0xeb8

// Reserved address 0xebc

// Reserved address 0xec0

// Reserved address 0xec4

// Reserved address 0xec8

// Reserved address 0xecc

// Reserved address 0xed0

// Reserved address 0xed4

// Reserved address 0xed8

// Reserved address 0xedc

// Reserved address 0xee0

// Reserved address 0xee4

// Reserved address 0xee8

// Reserved address 0xeec

// Reserved address 0xef0

// Reserved address 0xef4

// Reserved address 0xef8

// Reserved address 0xefc

// Reserved address 0xf00

// Reserved address 0xf04

// Reserved address 0xf08

// Reserved address 0xf0c

// Reserved address 0xf10

// Reserved address 0xf14

// Reserved address 0xf18

// Reserved address 0xf1c

// Reserved address 0xf20

// Reserved address 0xf24

// Reserved address 0xf28

// Reserved address 0xf2c

// Reserved address 0xf30

// Reserved address 0xf34

// Reserved address 0xf38

// Reserved address 0xf3c

// Reserved address 0xf40

// Reserved address 0xf44

// Reserved address 0xf48

// Reserved address 0xf4c

// Reserved address 0xf50

// Reserved address 0xf54

// Reserved address 0xf58

// Reserved address 0xf5c

// Reserved address 0xf60

// Reserved address 0xf64

// Reserved address 0xf68

// Reserved address 0xf6c

// Reserved address 0xf70

// Reserved address 0xf74

// Reserved address 0xf78

// Reserved address 0xf7c

// Reserved address 0xf80

// Reserved address 0xf84

// Reserved address 0xf88

// Reserved address 0xf8c

// Reserved address 0xf90

// Reserved address 0xf94

// Reserved address 0xf98

// Reserved address 0xf9c

// Reserved address 0xfa0

// Reserved address 0xfa4

// Reserved address 0xfa8

// Reserved address 0xfac

// Reserved address 0xfb0

// Reserved address 0xfb4

// Reserved address 0xfb8

// Reserved address 0xfbc

// Reserved address 0xfc0

// Reserved address 0xfc4

// Reserved address 0xfc8

// Reserved address 0xfcc

// Reserved address 0xfd0

// Reserved address 0xfd4

// Reserved address 0xfd8

// Reserved address 0xfdc

// Reserved address 0xfe0

// Reserved address 0xfe4

// Reserved address 0xfe8

// Reserved address 0xfec

// Reserved address 0xff0

// Reserved address 0xff4

// Reserved address 0xff8

// Reserved address 0xffc

// Reserved address 0x1000

// Reserved address 0x1004

// Reserved address 0x1008

// Reserved address 0x100c

// Reserved address 0x1010

// Reserved address 0x1014

// Reserved address 0x1018

// Reserved address 0x101c

// Reserved address 0x1020

// Reserved address 0x1024

// Reserved address 0x1028

// Reserved address 0x102c

// Reserved address 0x1030

// Reserved address 0x1034

// Reserved address 0x1038

// Reserved address 0x103c

// Reserved address 0x1040

// Reserved address 0x1044

// Reserved address 0x1048

// Reserved address 0x104c

// Reserved address 0x1050

// Reserved address 0x1054

// Reserved address 0x1058

// Reserved address 0x105c

// Reserved address 0x1060

// Reserved address 0x1064

// Reserved address 0x1068

// Reserved address 0x106c

// Reserved address 0x1070

// Reserved address 0x1074

// Reserved address 0x1078

// Reserved address 0x107c

// Reserved address 0x1080

// Reserved address 0x1084

// Reserved address 0x1088

// Reserved address 0x108c

// Reserved address 0x1090

// Reserved address 0x1094

// Reserved address 0x1098

// Reserved address 0x109c

// Reserved address 0x10a0

// Reserved address 0x10a4

// Reserved address 0x10a8

// Reserved address 0x10ac

// Reserved address 0x10b0

// Reserved address 0x10b4

// Reserved address 0x10b8

// Reserved address 0x10bc

// Reserved address 0x10c0

// Reserved address 0x10c4

// Reserved address 0x10c8

// Reserved address 0x10cc

// Reserved address 0x10d0

// Reserved address 0x10d4

// Reserved address 0x10d8

// Reserved address 0x10dc

// Reserved address 0x10e0

// Reserved address 0x10e4

// Reserved address 0x10e8

// Reserved address 0x10ec

// Reserved address 0x10f0

// Reserved address 0x10f4

// Reserved address 0x10f8

// Reserved address 0x10fc

// Reserved address 0x1100

// Reserved address 0x1104

// Reserved address 0x1108

// Reserved address 0x110c

// Reserved address 0x1110

// Reserved address 0x1114

// Reserved address 0x1118

// Reserved address 0x111c

// Reserved address 0x1120

// Reserved address 0x1124

// Reserved address 0x1128

// Reserved address 0x112c

// Reserved address 0x1130

// Reserved address 0x1134

// Reserved address 0x1138

// Reserved address 0x113c

// Reserved address 0x1140

// Reserved address 0x1144

// Reserved address 0x1148

// Reserved address 0x114c

// Reserved address 0x1150

// Reserved address 0x1154

// Reserved address 0x1158

// Reserved address 0x115c

// Reserved address 0x1160

// Reserved address 0x1164

// Reserved address 0x1168

// Reserved address 0x116c

// Reserved address 0x1170

// Reserved address 0x1174

// Reserved address 0x1178

// Reserved address 0x117c

// Reserved address 0x1180

// Reserved address 0x1184

// Reserved address 0x1188

// Reserved address 0x118c

// Reserved address 0x1190

// Reserved address 0x1194

// Reserved address 0x1198

// Reserved address 0x119c

// Reserved address 0x11a0

// Reserved address 0x11a4

// Reserved address 0x11a8

// Reserved address 0x11ac

// Reserved address 0x11b0

// Reserved address 0x11b4

// Reserved address 0x11b8

// Reserved address 0x11bc

// Reserved address 0x11c0

// Reserved address 0x11c4

// Reserved address 0x11c8

// Reserved address 0x11cc

// Reserved address 0x11d0

// Reserved address 0x11d4

// Reserved address 0x11d8

// Reserved address 0x11dc

// Reserved address 0x11e0

// Reserved address 0x11e4

// Reserved address 0x11e8

// Reserved address 0x11ec

// Reserved address 0x11f0

// Reserved address 0x11f4

// Reserved address 0x11f8

// Reserved address 0x11fc

// Reserved address 0x1200

// Reserved address 0x1204

// Reserved address 0x1208

// Reserved address 0x120c

// Reserved address 0x1210

// Reserved address 0x1214

// Reserved address 0x1218

// Reserved address 0x121c

// Reserved address 0x1220

// Reserved address 0x1224

// Reserved address 0x1228

// Reserved address 0x122c

// Reserved address 0x1230

// Reserved address 0x1234

// Reserved address 0x1238

// Reserved address 0x123c

// Reserved address 0x1240

// Reserved address 0x1244

// Reserved address 0x1248

// Reserved address 0x124c

// Reserved address 0x1250

// Reserved address 0x1254

// Reserved address 0x1258

// Reserved address 0x125c

// Reserved address 0x1260

// Reserved address 0x1264

// Reserved address 0x1268

// Reserved address 0x126c

// Reserved address 0x1270

// Reserved address 0x1274

// Reserved address 0x1278

// Reserved address 0x127c

// Reserved address 0x1280

// Reserved address 0x1284

// Reserved address 0x1288

// Reserved address 0x128c

// Reserved address 0x1290

// Reserved address 0x1294

// Reserved address 0x1298

// Reserved address 0x129c

// Reserved address 0x12a0

// Reserved address 0x12a4

// Reserved address 0x12a8

// Reserved address 0x12ac

// Reserved address 0x12b0

// Reserved address 0x12b4

// Reserved address 0x12b8

// Reserved address 0x12bc

// Reserved address 0x12c0

// Reserved address 0x12c4

// Reserved address 0x12c8

// Reserved address 0x12cc

// Reserved address 0x12d0

// Reserved address 0x12d4

// Reserved address 0x12d8

// Reserved address 0x12dc

// Reserved address 0x12e0

// Reserved address 0x12e4

// Reserved address 0x12e8

// Reserved address 0x12ec

// Reserved address 0x12f0

// Reserved address 0x12f4

// Reserved address 0x12f8

// Reserved address 0x12fc

// Reserved address 0x1300

// Reserved address 0x1304

// Reserved address 0x1308

// Reserved address 0x130c

// Reserved address 0x1310

// Reserved address 0x1314

// Reserved address 0x1318

// Reserved address 0x131c

// Reserved address 0x1320

// Reserved address 0x1324

// Reserved address 0x1328

// Reserved address 0x132c

// Reserved address 0x1330

// Reserved address 0x1334

// Reserved address 0x1338

// Reserved address 0x133c

// Reserved address 0x1340

// Reserved address 0x1344

// Reserved address 0x1348

// Reserved address 0x134c

// Reserved address 0x1350

// Reserved address 0x1354

// Reserved address 0x1358

// Reserved address 0x135c

// Reserved address 0x1360

// Register XUSB_PADCTL_HOST_AXI_SEC0_0
#define XUSB_PADCTL_HOST_AXI_SEC0_0                     _MK_ADDR_CONST(0x1364)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_SECURE                      0x1
#define XUSB_PADCTL_HOST_AXI_SEC0_0_DUAL                        0x0
#define XUSB_PADCTL_HOST_AXI_SEC0_0_SCR                         0
#define XUSB_PADCTL_HOST_AXI_SEC0_0_WORD_COUNT                  0x1
#define XUSB_PADCTL_HOST_AXI_SEC0_0_RESET_VAL                   _MK_MASK_CONST(0x11)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_RESET_MASK                  _MK_MASK_CONST(0x11)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_READ_MASK                   _MK_MASK_CONST(0x11)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_WRITE_MASK                  _MK_MASK_CONST(0x11)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_ARPROT1_SHIFT                       _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_ARPROT1_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_HOST_AXI_SEC0_0_ARPROT1_SHIFT)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_ARPROT1_RANGE                       0:0
#define XUSB_PADCTL_HOST_AXI_SEC0_0_ARPROT1_WOFFSET                     0x0
#define XUSB_PADCTL_HOST_AXI_SEC0_0_ARPROT1_DEFAULT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_ARPROT1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_ARPROT1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_ARPROT1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_ARPROT1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_ARPROT1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_HOST_AXI_SEC0_0_AWPROT1_SHIFT                       _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_AWPROT1_FIELD                       _MK_FIELD_CONST(0x1, XUSB_PADCTL_HOST_AXI_SEC0_0_AWPROT1_SHIFT)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_AWPROT1_RANGE                       4:4
#define XUSB_PADCTL_HOST_AXI_SEC0_0_AWPROT1_WOFFSET                     0x0
#define XUSB_PADCTL_HOST_AXI_SEC0_0_AWPROT1_DEFAULT                     _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_AWPROT1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_AWPROT1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_AWPROT1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_AWPROT1_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC0_0_AWPROT1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register XUSB_PADCTL_HOST_AXI_SEC2_0
#define XUSB_PADCTL_HOST_AXI_SEC2_0                     _MK_ADDR_CONST(0x1368)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_SECURE                      0x0
#define XUSB_PADCTL_HOST_AXI_SEC2_0_DUAL                        0x0
#define XUSB_PADCTL_HOST_AXI_SEC2_0_SCR                         0
#define XUSB_PADCTL_HOST_AXI_SEC2_0_WORD_COUNT                  0x1
#define XUSB_PADCTL_HOST_AXI_SEC2_0_RESET_VAL                   _MK_MASK_CONST(0x1013)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_RESET_MASK                  _MK_MASK_CONST(0x1f1f)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_READ_MASK                   _MK_MASK_CONST(0x1f1f)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_WRITE_MASK                  _MK_MASK_CONST(0x1f1f)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_SHIFT                       _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_FIELD                       _MK_FIELD_CONST(0xf, XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_SHIFT)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_RANGE                       3:0
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_WOFFSET                     0x0
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_DEFAULT                     _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_OVRD_SHIFT                  _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_OVRD_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_OVRD_SHIFT)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_OVRD_RANGE                  4:4
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_OVRD_WOFFSET                        0x0
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_OVRD_DEFAULT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_OVRD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_OVRD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_OVRD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_OVRD_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_ARCACHE_OVRD_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_SHIFT                       _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_FIELD                       _MK_FIELD_CONST(0xf, XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_SHIFT)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_RANGE                       11:8
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_WOFFSET                     0x0
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_OVRD_SHIFT                  _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_OVRD_FIELD                  _MK_FIELD_CONST(0x1, XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_OVRD_SHIFT)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_OVRD_RANGE                  12:12
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_OVRD_WOFFSET                        0x0
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_OVRD_DEFAULT                        _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_OVRD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_OVRD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_OVRD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_OVRD_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_SEC2_0_AWCACHE_OVRD_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register XUSB_PADCTL_HOST_AXI_STREAMID_PF_0
#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0                      _MK_ADDR_CONST(0x136c)
#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0_SECURE                       0x1
#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0_DUAL                         0x0
#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0_SCR                  0
#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0_WORD_COUNT                   0x1
#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0_RESET_MASK                   _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0_READ_MASK                    _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0_PF_STREAMID_SHIFT                    _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0_PF_STREAMID_FIELD                    _MK_FIELD_CONST(0xff, XUSB_PADCTL_HOST_AXI_STREAMID_PF_0_PF_STREAMID_SHIFT)
#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0_PF_STREAMID_RANGE                    7:0
#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0_PF_STREAMID_WOFFSET                  0x0
#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0_PF_STREAMID_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0_PF_STREAMID_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0_PF_STREAMID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0_PF_STREAMID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0_PF_STREAMID_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0_PF_STREAMID_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register XUSB_PADCTL_HOST_AXI_STREAMID_VF_0
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0                      _MK_ADDR_CONST(0x1370)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0_SECURE                       0x1
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0_DUAL                         0x0
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0_SCR                  0
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0_WORD_COUNT                   0x1
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0_RESET_MASK                   _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0_READ_MASK                    _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0_VF_STREAMID_SHIFT                    _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0_VF_STREAMID_FIELD                    _MK_FIELD_CONST(0xff, XUSB_PADCTL_HOST_AXI_STREAMID_VF_0_VF_STREAMID_SHIFT)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0_VF_STREAMID_RANGE                    7:0
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0_VF_STREAMID_WOFFSET                  0x0
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0_VF_STREAMID_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0_VF_STREAMID_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0_VF_STREAMID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0_VF_STREAMID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0_VF_STREAMID_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0_VF_STREAMID_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register XUSB_PADCTL_HOST_AXI_STREAMID_VF
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF                        _MK_ADDR_CONST(0x1370)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_SECURE                         0x1
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_DUAL                   0x0
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_SCR                    0
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_WORD_COUNT                     0x1
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_RESET_VAL                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_RESET_MASK                     _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_READ_MASK                      _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_WRITE_MASK                     _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_VF_STREAMID_SHIFT                      _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_VF_STREAMID_FIELD                      _MK_FIELD_CONST(0xff, XUSB_PADCTL_HOST_AXI_STREAMID_VF_VF_STREAMID_SHIFT)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_VF_STREAMID_RANGE                      7:0
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_VF_STREAMID_WOFFSET                    0x0
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_VF_STREAMID_DEFAULT                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_VF_STREAMID_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_VF_STREAMID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_VF_STREAMID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_VF_STREAMID_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_VF_STREAMID_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register XUSB_PADCTL_HOST_AXI_STREAMID_VF_1
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1                      _MK_ADDR_CONST(0x1374)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1_SECURE                       0x1
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1_DUAL                         0x0
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1_SCR                  0
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1_WORD_COUNT                   0x1
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1_RESET_VAL                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1_RESET_MASK                   _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1_READ_MASK                    _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1_WRITE_MASK                   _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1_VF_STREAMID_SHIFT                    _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1_VF_STREAMID_FIELD                    _MK_FIELD_CONST(0xff, XUSB_PADCTL_HOST_AXI_STREAMID_VF_1_VF_STREAMID_SHIFT)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1_VF_STREAMID_RANGE                    7:0
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1_VF_STREAMID_WOFFSET                  0x0
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1_VF_STREAMID_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1_VF_STREAMID_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1_VF_STREAMID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1_VF_STREAMID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1_VF_STREAMID_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1_VF_STREAMID_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register XUSB_PADCTL_HOST_AXI_STREAMID_VF_2
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2                      _MK_ADDR_CONST(0x1378)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2_SECURE                       0x1
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2_DUAL                         0x0
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2_SCR                  0
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2_WORD_COUNT                   0x1
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2_RESET_VAL                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2_RESET_MASK                   _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2_READ_MASK                    _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2_WRITE_MASK                   _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2_VF_STREAMID_SHIFT                    _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2_VF_STREAMID_FIELD                    _MK_FIELD_CONST(0xff, XUSB_PADCTL_HOST_AXI_STREAMID_VF_2_VF_STREAMID_SHIFT)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2_VF_STREAMID_RANGE                    7:0
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2_VF_STREAMID_WOFFSET                  0x0
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2_VF_STREAMID_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2_VF_STREAMID_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2_VF_STREAMID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2_VF_STREAMID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2_VF_STREAMID_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2_VF_STREAMID_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register XUSB_PADCTL_HOST_AXI_STREAMID_VF_3
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3                      _MK_ADDR_CONST(0x137c)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3_SECURE                       0x1
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3_DUAL                         0x0
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3_SCR                  0
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3_WORD_COUNT                   0x1
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3_RESET_VAL                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3_RESET_MASK                   _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3_READ_MASK                    _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3_WRITE_MASK                   _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3_VF_STREAMID_SHIFT                    _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3_VF_STREAMID_FIELD                    _MK_FIELD_CONST(0xff, XUSB_PADCTL_HOST_AXI_STREAMID_VF_3_VF_STREAMID_SHIFT)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3_VF_STREAMID_RANGE                    7:0
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3_VF_STREAMID_WOFFSET                  0x0
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3_VF_STREAMID_DEFAULT                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3_VF_STREAMID_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3_VF_STREAMID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3_VF_STREAMID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3_VF_STREAMID_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3_VF_STREAMID_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Reserved address 0x1380

// Reserved address 0x1384

// Reserved address 0x1388

// Reserved address 0x138c

// Reserved address 0x1390

// Register XUSB_PADCTL_DEV_AXI_SEC0_0
#define XUSB_PADCTL_DEV_AXI_SEC0_0                      _MK_ADDR_CONST(0x1394)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_SECURE                       0x1
#define XUSB_PADCTL_DEV_AXI_SEC0_0_DUAL                         0x0
#define XUSB_PADCTL_DEV_AXI_SEC0_0_SCR                  0
#define XUSB_PADCTL_DEV_AXI_SEC0_0_WORD_COUNT                   0x1
#define XUSB_PADCTL_DEV_AXI_SEC0_0_RESET_VAL                    _MK_MASK_CONST(0x11)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_RESET_MASK                   _MK_MASK_CONST(0x11)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_READ_MASK                    _MK_MASK_CONST(0x11)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_WRITE_MASK                   _MK_MASK_CONST(0x11)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_ARPROT1_SHIFT                        _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_ARPROT1_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_DEV_AXI_SEC0_0_ARPROT1_SHIFT)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_ARPROT1_RANGE                        0:0
#define XUSB_PADCTL_DEV_AXI_SEC0_0_ARPROT1_WOFFSET                      0x0
#define XUSB_PADCTL_DEV_AXI_SEC0_0_ARPROT1_DEFAULT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_ARPROT1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_ARPROT1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_ARPROT1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_ARPROT1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_ARPROT1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_DEV_AXI_SEC0_0_AWPROT1_SHIFT                        _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_AWPROT1_FIELD                        _MK_FIELD_CONST(0x1, XUSB_PADCTL_DEV_AXI_SEC0_0_AWPROT1_SHIFT)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_AWPROT1_RANGE                        4:4
#define XUSB_PADCTL_DEV_AXI_SEC0_0_AWPROT1_WOFFSET                      0x0
#define XUSB_PADCTL_DEV_AXI_SEC0_0_AWPROT1_DEFAULT                      _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_AWPROT1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_AWPROT1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_AWPROT1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_AWPROT1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC0_0_AWPROT1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register XUSB_PADCTL_DEV_AXI_SEC2_0
#define XUSB_PADCTL_DEV_AXI_SEC2_0                      _MK_ADDR_CONST(0x1398)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_SECURE                       0x0
#define XUSB_PADCTL_DEV_AXI_SEC2_0_DUAL                         0x0
#define XUSB_PADCTL_DEV_AXI_SEC2_0_SCR                  0
#define XUSB_PADCTL_DEV_AXI_SEC2_0_WORD_COUNT                   0x1
#define XUSB_PADCTL_DEV_AXI_SEC2_0_RESET_VAL                    _MK_MASK_CONST(0x1013)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_RESET_MASK                   _MK_MASK_CONST(0x1f1f)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_READ_MASK                    _MK_MASK_CONST(0x1f1f)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_WRITE_MASK                   _MK_MASK_CONST(0x1f1f)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_SHIFT                        _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_SHIFT)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_RANGE                        3:0
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_WOFFSET                      0x0
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_DEFAULT                      _MK_MASK_CONST(0x3)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_OVRD_SHIFT                   _MK_SHIFT_CONST(4)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_OVRD_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_OVRD_SHIFT)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_OVRD_RANGE                   4:4
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_OVRD_WOFFSET                 0x0
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_OVRD_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_OVRD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_OVRD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_OVRD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_OVRD_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_ARCACHE_OVRD_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_SHIFT                        _MK_SHIFT_CONST(8)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_FIELD                        _MK_FIELD_CONST(0xf, XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_SHIFT)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_RANGE                        11:8
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_WOFFSET                      0x0
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_OVRD_SHIFT                   _MK_SHIFT_CONST(12)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_OVRD_FIELD                   _MK_FIELD_CONST(0x1, XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_OVRD_SHIFT)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_OVRD_RANGE                   12:12
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_OVRD_WOFFSET                 0x0
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_OVRD_DEFAULT                 _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_OVRD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_OVRD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_OVRD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_OVRD_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_SEC2_0_AWCACHE_OVRD_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register XUSB_PADCTL_DEV_AXI_STREAMID_PF_0
#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0                       _MK_ADDR_CONST(0x139c)
#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0_SECURE                        0x1
#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0_DUAL                  0x0
#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0_SCR                   0
#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0_WORD_COUNT                    0x1
#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0_PF_STREAMID_SHIFT                     _MK_SHIFT_CONST(0)
#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0_PF_STREAMID_FIELD                     _MK_FIELD_CONST(0xff, XUSB_PADCTL_DEV_AXI_STREAMID_PF_0_PF_STREAMID_SHIFT)
#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0_PF_STREAMID_RANGE                     7:0
#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0_PF_STREAMID_WOFFSET                   0x0
#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0_PF_STREAMID_DEFAULT                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0_PF_STREAMID_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0_PF_STREAMID_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0_PF_STREAMID_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0_PF_STREAMID_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0_PF_STREAMID_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Reserved address 0x13a0

// Reserved address 0x13a4

// Reserved address 0x13a8

// Reserved address 0x13ac

//
// REGISTER LIST
//
#define LIST_ARXUSB_PADCTL_REGS(_op_) \
_op_(XUSB_PADCTL_BOOT_MEDIA_0) \
_op_(XUSB_PADCTL_USB2_PAD_MUX_0) \
_op_(XUSB_PADCTL_USB2_PORT_CAP_0) \
_op_(XUSB_PADCTL_SS_PORT_CAP_0) \
_op_(XUSB_PADCTL_USB2_OC_MAP_0) \
_op_(XUSB_PADCTL_SS_OC_MAP_0) \
_op_(XUSB_PADCTL_VBUS_OC_MAP_0) \
_op_(XUSB_PADCTL_OC_DET_0) \
_op_(XUSB_PADCTL_ELPG_PROGRAM_0_0) \
_op_(XUSB_PADCTL_ELPG_PROGRAM_1_0) \
_op_(XUSB_PADCTL_PM_SPARE_0) \
_op_(XUSB_PADCTL_SS_PORT_CFG_0) \
_op_(XUSB_PADCTL_USB2_VBUS_ID_MAP_0) \
_op_(XUSB_PADCTL_SS_VBUS_ID_MAP_0) \
_op_(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0) \
_op_(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL1_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD0_CTL_2_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0) \
_op_(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0) \
_op_(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL1_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD1_CTL_2_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0) \
_op_(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0) \
_op_(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL1_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD2_CTL_2_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0) \
_op_(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0) \
_op_(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL1_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD3_CTL_2_0) \
_op_(XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0) \
_op_(XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0) \
_op_(XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0) \
_op_(XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0) \
_op_(XUSB_PADCTL_USB2_VBUS_ID_0) \
_op_(XUSB_PADCTL_USB2_VBUS_ID) \
_op_(XUSB_PADCTL_USB2_VBUS_ID_1) \
_op_(XUSB_PADCTL_USB2_VBUS_ID_2) \
_op_(XUSB_PADCTL_USB2_VBUS_ID_3) \
_op_(XUSB_PADCTL_HOST_AXI_SEC0_0) \
_op_(XUSB_PADCTL_HOST_AXI_SEC2_0) \
_op_(XUSB_PADCTL_HOST_AXI_STREAMID_PF_0) \
_op_(XUSB_PADCTL_HOST_AXI_STREAMID_VF_0) \
_op_(XUSB_PADCTL_HOST_AXI_STREAMID_VF) \
_op_(XUSB_PADCTL_HOST_AXI_STREAMID_VF_1) \
_op_(XUSB_PADCTL_HOST_AXI_STREAMID_VF_2) \
_op_(XUSB_PADCTL_HOST_AXI_STREAMID_VF_3) \
_op_(XUSB_PADCTL_DEV_AXI_SEC0_0) \
_op_(XUSB_PADCTL_DEV_AXI_SEC2_0) \
_op_(XUSB_PADCTL_DEV_AXI_STREAMID_PF_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_XUSB_PADCTL        0x00000000

//
// ARXUSB_PADCTL REGISTER BANKS
//

#define XUSB_PADCTL0_FIRST_REG 0x0000 // XUSB_PADCTL_BOOT_MEDIA_0
#define XUSB_PADCTL0_LAST_REG 0x0034 // XUSB_PADCTL_SS_VBUS_ID_MAP_0
#define XUSB_PADCTL1_FIRST_REG 0x0080 // XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD0_CTL0_0
#define XUSB_PADCTL1_LAST_REG 0x0094 // XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0
#define XUSB_PADCTL2_FIRST_REG 0x00c0 // XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD1_CTL0_0
#define XUSB_PADCTL2_LAST_REG 0x00d4 // XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0
#define XUSB_PADCTL3_FIRST_REG 0x0100 // XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD2_CTL0_0
#define XUSB_PADCTL3_LAST_REG 0x0114 // XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0
#define XUSB_PADCTL4_FIRST_REG 0x0140 // XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD3_CTL0_0
#define XUSB_PADCTL4_LAST_REG 0x0154 // XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0
#define XUSB_PADCTL5_FIRST_REG 0x0280 // XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0
#define XUSB_PADCTL5_LAST_REG 0x0288 // XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
#define XUSB_PADCTL6_FIRST_REG 0x0360 // XUSB_PADCTL_USB2_VBUS_ID_0
#define XUSB_PADCTL6_LAST_REG 0x036c // XUSB_PADCTL_USB2_VBUS_ID_3
#define XUSB_PADCTL7_FIRST_REG 0x1364 // XUSB_PADCTL_HOST_AXI_SEC0_0
#define XUSB_PADCTL7_LAST_REG 0x137c // XUSB_PADCTL_HOST_AXI_STREAMID_VF_3
#define XUSB_PADCTL8_FIRST_REG 0x1394 // XUSB_PADCTL_DEV_AXI_SEC0_0
#define XUSB_PADCTL8_LAST_REG 0x139c // XUSB_PADCTL_DEV_AXI_STREAMID_PF_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif
#ifndef _MK_FIELD_CONST
  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
#endif

#endif // ifndef ___ARXUSB_PADCTL_H_INC_
