//
// Copyright (c) 2018 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ___ARUPHY_LANE_H_INC_
#define ___ARUPHY_LANE_H_INC_
#define NV_MOBILE_ARUPHY_LANE_H_UNIT_OF_OFFSET 1B

// Register UPHY_LANE_MISC_CTL_1_0
#define UPHY_LANE_MISC_CTL_1_0                  _MK_ADDR_CONST(0x4)
#define UPHY_LANE_MISC_CTL_1_0_SECURE                   0x0
#define UPHY_LANE_MISC_CTL_1_0_DUAL                     0x0
#define UPHY_LANE_MISC_CTL_1_0_SCR                      0
#define UPHY_LANE_MISC_CTL_1_0_WORD_COUNT                       0x1
#define UPHY_LANE_MISC_CTL_1_0_RESET_VAL                        _MK_MASK_CONST(0x11003131)
#define UPHY_LANE_MISC_CTL_1_0_RESET_MASK                       _MK_MASK_CONST(0xff3fb3f3)
#define UPHY_LANE_MISC_CTL_1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_READ_MASK                        _MK_MASK_CONST(0xff3fb3f3)
#define UPHY_LANE_MISC_CTL_1_0_WRITE_MASK                       _MK_MASK_CONST(0xff3fb3f3)
#define UPHY_LANE_MISC_CTL_1_0_TX_IDDQ_SHIFT                    _MK_SHIFT_CONST(0)
#define UPHY_LANE_MISC_CTL_1_0_TX_IDDQ_FIELD                    _MK_FIELD_CONST(0x1, UPHY_LANE_MISC_CTL_1_0_TX_IDDQ_SHIFT)
#define UPHY_LANE_MISC_CTL_1_0_TX_IDDQ_RANGE                    0:0
#define UPHY_LANE_MISC_CTL_1_0_TX_IDDQ_WOFFSET                  0x0
#define UPHY_LANE_MISC_CTL_1_0_TX_IDDQ_DEFAULT                  _MK_MASK_CONST(0x1)
#define UPHY_LANE_MISC_CTL_1_0_TX_IDDQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define UPHY_LANE_MISC_CTL_1_0_TX_IDDQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_IDDQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_IDDQ_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_IDDQ_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define UPHY_LANE_MISC_CTL_1_0_TX_IDDQ_OVRD_SHIFT                       _MK_SHIFT_CONST(1)
#define UPHY_LANE_MISC_CTL_1_0_TX_IDDQ_OVRD_FIELD                       _MK_FIELD_CONST(0x1, UPHY_LANE_MISC_CTL_1_0_TX_IDDQ_OVRD_SHIFT)
#define UPHY_LANE_MISC_CTL_1_0_TX_IDDQ_OVRD_RANGE                       1:1
#define UPHY_LANE_MISC_CTL_1_0_TX_IDDQ_OVRD_WOFFSET                     0x0
#define UPHY_LANE_MISC_CTL_1_0_TX_IDDQ_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_IDDQ_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define UPHY_LANE_MISC_CTL_1_0_TX_IDDQ_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_IDDQ_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_IDDQ_OVRD_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_IDDQ_OVRD_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define UPHY_LANE_MISC_CTL_1_0_TX_SLEEP_SHIFT                   _MK_SHIFT_CONST(4)
#define UPHY_LANE_MISC_CTL_1_0_TX_SLEEP_FIELD                   _MK_FIELD_CONST(0x3, UPHY_LANE_MISC_CTL_1_0_TX_SLEEP_SHIFT)
#define UPHY_LANE_MISC_CTL_1_0_TX_SLEEP_RANGE                   5:4
#define UPHY_LANE_MISC_CTL_1_0_TX_SLEEP_WOFFSET                 0x0
#define UPHY_LANE_MISC_CTL_1_0_TX_SLEEP_DEFAULT                 _MK_MASK_CONST(0x3)
#define UPHY_LANE_MISC_CTL_1_0_TX_SLEEP_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define UPHY_LANE_MISC_CTL_1_0_TX_SLEEP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_SLEEP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_SLEEP_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_SLEEP_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define UPHY_LANE_MISC_CTL_1_0_TX_DATA_READY_SHIFT                      _MK_SHIFT_CONST(6)
#define UPHY_LANE_MISC_CTL_1_0_TX_DATA_READY_FIELD                      _MK_FIELD_CONST(0x1, UPHY_LANE_MISC_CTL_1_0_TX_DATA_READY_SHIFT)
#define UPHY_LANE_MISC_CTL_1_0_TX_DATA_READY_RANGE                      6:6
#define UPHY_LANE_MISC_CTL_1_0_TX_DATA_READY_WOFFSET                    0x0
#define UPHY_LANE_MISC_CTL_1_0_TX_DATA_READY_DEFAULT                    _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_DATA_READY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define UPHY_LANE_MISC_CTL_1_0_TX_DATA_READY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_DATA_READY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_DATA_READY_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_DATA_READY_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define UPHY_LANE_MISC_CTL_1_0_TX_DATA_EN_SHIFT                 _MK_SHIFT_CONST(7)
#define UPHY_LANE_MISC_CTL_1_0_TX_DATA_EN_FIELD                 _MK_FIELD_CONST(0x1, UPHY_LANE_MISC_CTL_1_0_TX_DATA_EN_SHIFT)
#define UPHY_LANE_MISC_CTL_1_0_TX_DATA_EN_RANGE                 7:7
#define UPHY_LANE_MISC_CTL_1_0_TX_DATA_EN_WOFFSET                       0x0
#define UPHY_LANE_MISC_CTL_1_0_TX_DATA_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_DATA_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define UPHY_LANE_MISC_CTL_1_0_TX_DATA_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_DATA_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_DATA_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_DATA_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define UPHY_LANE_MISC_CTL_1_0_RX_IDDQ_SHIFT                    _MK_SHIFT_CONST(8)
#define UPHY_LANE_MISC_CTL_1_0_RX_IDDQ_FIELD                    _MK_FIELD_CONST(0x1, UPHY_LANE_MISC_CTL_1_0_RX_IDDQ_SHIFT)
#define UPHY_LANE_MISC_CTL_1_0_RX_IDDQ_RANGE                    8:8
#define UPHY_LANE_MISC_CTL_1_0_RX_IDDQ_WOFFSET                  0x0
#define UPHY_LANE_MISC_CTL_1_0_RX_IDDQ_DEFAULT                  _MK_MASK_CONST(0x1)
#define UPHY_LANE_MISC_CTL_1_0_RX_IDDQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define UPHY_LANE_MISC_CTL_1_0_RX_IDDQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_IDDQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_IDDQ_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_IDDQ_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define UPHY_LANE_MISC_CTL_1_0_RX_IDDQ_OVRD_SHIFT                       _MK_SHIFT_CONST(9)
#define UPHY_LANE_MISC_CTL_1_0_RX_IDDQ_OVRD_FIELD                       _MK_FIELD_CONST(0x1, UPHY_LANE_MISC_CTL_1_0_RX_IDDQ_OVRD_SHIFT)
#define UPHY_LANE_MISC_CTL_1_0_RX_IDDQ_OVRD_RANGE                       9:9
#define UPHY_LANE_MISC_CTL_1_0_RX_IDDQ_OVRD_WOFFSET                     0x0
#define UPHY_LANE_MISC_CTL_1_0_RX_IDDQ_OVRD_DEFAULT                     _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_IDDQ_OVRD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define UPHY_LANE_MISC_CTL_1_0_RX_IDDQ_OVRD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_IDDQ_OVRD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_IDDQ_OVRD_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_IDDQ_OVRD_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define UPHY_LANE_MISC_CTL_1_0_RX_SLEEP_SHIFT                   _MK_SHIFT_CONST(12)
#define UPHY_LANE_MISC_CTL_1_0_RX_SLEEP_FIELD                   _MK_FIELD_CONST(0x3, UPHY_LANE_MISC_CTL_1_0_RX_SLEEP_SHIFT)
#define UPHY_LANE_MISC_CTL_1_0_RX_SLEEP_RANGE                   13:12
#define UPHY_LANE_MISC_CTL_1_0_RX_SLEEP_WOFFSET                 0x0
#define UPHY_LANE_MISC_CTL_1_0_RX_SLEEP_DEFAULT                 _MK_MASK_CONST(0x3)
#define UPHY_LANE_MISC_CTL_1_0_RX_SLEEP_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define UPHY_LANE_MISC_CTL_1_0_RX_SLEEP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_SLEEP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_SLEEP_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_SLEEP_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define UPHY_LANE_MISC_CTL_1_0_RX_DATA_EN_SHIFT                 _MK_SHIFT_CONST(15)
#define UPHY_LANE_MISC_CTL_1_0_RX_DATA_EN_FIELD                 _MK_FIELD_CONST(0x1, UPHY_LANE_MISC_CTL_1_0_RX_DATA_EN_SHIFT)
#define UPHY_LANE_MISC_CTL_1_0_RX_DATA_EN_RANGE                 15:15
#define UPHY_LANE_MISC_CTL_1_0_RX_DATA_EN_WOFFSET                       0x0
#define UPHY_LANE_MISC_CTL_1_0_RX_DATA_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_DATA_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define UPHY_LANE_MISC_CTL_1_0_RX_DATA_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_DATA_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_DATA_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_DATA_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_PDIV_SHIFT                       _MK_SHIFT_CONST(16)
#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_PDIV_FIELD                       _MK_FIELD_CONST(0x3, UPHY_LANE_MISC_CTL_1_0_TX_RATE_PDIV_SHIFT)
#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_PDIV_RANGE                       17:16
#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_PDIV_WOFFSET                     0x0
#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_PDIV_DEFAULT                     _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_PDIV_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_PDIV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_PDIV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_PDIV_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_PDIV_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_PDIV_SHIFT                       _MK_SHIFT_CONST(18)
#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_PDIV_FIELD                       _MK_FIELD_CONST(0x3, UPHY_LANE_MISC_CTL_1_0_RX_RATE_PDIV_SHIFT)
#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_PDIV_RANGE                       19:18
#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_PDIV_WOFFSET                     0x0
#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_PDIV_DEFAULT                     _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_PDIV_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_PDIV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_PDIV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_PDIV_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_PDIV_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define UPHY_LANE_MISC_CTL_1_0_TX_PWR_OVRD_SHIFT                        _MK_SHIFT_CONST(20)
#define UPHY_LANE_MISC_CTL_1_0_TX_PWR_OVRD_FIELD                        _MK_FIELD_CONST(0x1, UPHY_LANE_MISC_CTL_1_0_TX_PWR_OVRD_SHIFT)
#define UPHY_LANE_MISC_CTL_1_0_TX_PWR_OVRD_RANGE                        20:20
#define UPHY_LANE_MISC_CTL_1_0_TX_PWR_OVRD_WOFFSET                      0x0
#define UPHY_LANE_MISC_CTL_1_0_TX_PWR_OVRD_DEFAULT                      _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_PWR_OVRD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define UPHY_LANE_MISC_CTL_1_0_TX_PWR_OVRD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_PWR_OVRD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_PWR_OVRD_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_PWR_OVRD_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define UPHY_LANE_MISC_CTL_1_0_RX_PWR_OVRD_SHIFT                        _MK_SHIFT_CONST(21)
#define UPHY_LANE_MISC_CTL_1_0_RX_PWR_OVRD_FIELD                        _MK_FIELD_CONST(0x1, UPHY_LANE_MISC_CTL_1_0_RX_PWR_OVRD_SHIFT)
#define UPHY_LANE_MISC_CTL_1_0_RX_PWR_OVRD_RANGE                        21:21
#define UPHY_LANE_MISC_CTL_1_0_RX_PWR_OVRD_WOFFSET                      0x0
#define UPHY_LANE_MISC_CTL_1_0_RX_PWR_OVRD_DEFAULT                      _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_PWR_OVRD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define UPHY_LANE_MISC_CTL_1_0_RX_PWR_OVRD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_PWR_OVRD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_PWR_OVRD_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_PWR_OVRD_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_ID_SHIFT                 _MK_SHIFT_CONST(24)
#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_ID_FIELD                 _MK_FIELD_CONST(0x7, UPHY_LANE_MISC_CTL_1_0_TX_RATE_ID_SHIFT)
#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_ID_RANGE                 26:24
#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_ID_WOFFSET                       0x0
#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_ID_DEFAULT                       _MK_MASK_CONST(0x1)
#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_ID_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_ID_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_ID_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_ID_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_ID_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_ID_OVRD_SHIFT                    _MK_SHIFT_CONST(27)
#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_ID_OVRD_FIELD                    _MK_FIELD_CONST(0x1, UPHY_LANE_MISC_CTL_1_0_TX_RATE_ID_OVRD_SHIFT)
#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_ID_OVRD_RANGE                    27:27
#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_ID_OVRD_WOFFSET                  0x0
#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_ID_OVRD_DEFAULT                  _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_ID_OVRD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_ID_OVRD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_ID_OVRD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_ID_OVRD_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_TX_RATE_ID_OVRD_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_ID_SHIFT                 _MK_SHIFT_CONST(28)
#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_ID_FIELD                 _MK_FIELD_CONST(0x7, UPHY_LANE_MISC_CTL_1_0_RX_RATE_ID_SHIFT)
#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_ID_RANGE                 30:28
#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_ID_WOFFSET                       0x0
#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_ID_DEFAULT                       _MK_MASK_CONST(0x1)
#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_ID_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_ID_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_ID_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_ID_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_ID_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_ID_OVRD_SHIFT                    _MK_SHIFT_CONST(31)
#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_ID_OVRD_FIELD                    _MK_FIELD_CONST(0x1, UPHY_LANE_MISC_CTL_1_0_RX_RATE_ID_OVRD_SHIFT)
#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_ID_OVRD_RANGE                    31:31
#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_ID_OVRD_WOFFSET                  0x0
#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_ID_OVRD_DEFAULT                  _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_ID_OVRD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_ID_OVRD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_ID_OVRD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_ID_OVRD_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define UPHY_LANE_MISC_CTL_1_0_RX_RATE_ID_OVRD_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Reserved address 0x1c

// Reserved address 0x20

// Reserved address 0x24

// Reserved address 0x28

// Reserved address 0x2c

// Reserved address 0x30

// Reserved address 0x34

// Reserved address 0x38

// Reserved address 0x3c

// Reserved address 0x40

// Reserved address 0x44

// Reserved address 0x48

// Reserved address 0x4c

// Reserved address 0x50

// Reserved address 0x54

// Reserved address 0x58

// Reserved address 0x5c

// Reserved address 0x60

// Reserved address 0x64

// Reserved address 0x68

// Reserved address 0x6c

// Reserved address 0x70

// Reserved address 0x74

// Reserved address 0x78

// Reserved address 0x7c

// Reserved address 0xac

// Reserved address 0xb0

// Reserved address 0xb4

// Reserved address 0xb8

// Reserved address 0xbc

// Reserved address 0xc0

// Reserved address 0xc4

// Reserved address 0xc8

// Reserved address 0xcc

// Reserved address 0xd0

// Reserved address 0xd4

// Reserved address 0xd8

// Reserved address 0xdc

// Reserved address 0xe0

// Reserved address 0xe4

// Reserved address 0xe8

// Reserved address 0xec

// Reserved address 0xf0

// Reserved address 0xf4

// Reserved address 0xf8

// Reserved address 0xfc

// Reserved address 0x100

// Reserved address 0x104

// Reserved address 0x108

// Reserved address 0x10c

// Reserved address 0x110

// Reserved address 0x114

// Reserved address 0x118

// Reserved address 0x11c

// Reserved address 0x120

// Reserved address 0x124

// Reserved address 0x128

// Reserved address 0x12c

// Reserved address 0x130

// Reserved address 0x134

// Reserved address 0x138

// Reserved address 0x13c

// Reserved address 0x140

// Reserved address 0x144

// Reserved address 0x148

// Reserved address 0x14c

// Reserved address 0x150

// Reserved address 0x154

// Reserved address 0x158

// Reserved address 0x15c

// Reserved address 0x160

// Reserved address 0x164

// Reserved address 0x168

// Reserved address 0x16c

// Reserved address 0x170

// Reserved address 0x174

// Reserved address 0x178

// Reserved address 0x17c

// Reserved address 0x18c

// Reserved address 0x190

// Reserved address 0x194

// Reserved address 0x198

// Reserved address 0x19c

// Reserved address 0x1a0

// Reserved address 0x1a4

// Reserved address 0x1a8

// Reserved address 0x1ac

// Reserved address 0x1b0

// Reserved address 0x1b4

// Reserved address 0x1b8

// Reserved address 0x1bc

// Reserved address 0x1c8

// Reserved address 0x1cc

// Reserved address 0x1d0

// Reserved address 0x1d4

// Reserved address 0x1d8

// Reserved address 0x1dc

// Reserved address 0x1e0

// Reserved address 0x1e4

// Reserved address 0x1e8

// Reserved address 0x1ec

// Reserved address 0x1f0

// Reserved address 0x1f4

// Reserved address 0x1f8

// Reserved address 0x1fc

// Reserved address 0x204

// Reserved address 0x208

// Reserved address 0x20c

// Reserved address 0x210

// Reserved address 0x214

// Reserved address 0x218

// Reserved address 0x21c

// Reserved address 0x220

// Reserved address 0x224

// Reserved address 0x228

// Reserved address 0x22c

// Reserved address 0x230

// Reserved address 0x234

// Reserved address 0x238

// Reserved address 0x23c

// Reserved address 0x248

// Reserved address 0x24c

// Reserved address 0x250

// Reserved address 0x254

// Reserved address 0x258

// Reserved address 0x25c

// Reserved address 0x260

// Reserved address 0x264

// Reserved address 0x268

// Reserved address 0x26c

// Reserved address 0x270

// Reserved address 0x274

// Reserved address 0x278

// Reserved address 0x27c

// Reserved address 0x280

// Reserved address 0x284

// Reserved address 0x288

// Reserved address 0x28c

// Reserved address 0x290

// Reserved address 0x294

// Reserved address 0x298

// Reserved address 0x29c

// Reserved address 0x2a0

// Reserved address 0x2a4

// Reserved address 0x2a8

// Reserved address 0x2ac

// Reserved address 0x2b0

// Reserved address 0x2b4

// Reserved address 0x2b8

// Reserved address 0x2bc

// Reserved address 0x2c8

// Reserved address 0x2cc

// Reserved address 0x2d0

// Reserved address 0x2d4

// Reserved address 0x2d8

// Reserved address 0x2dc

// Reserved address 0x2e0

// Reserved address 0x2e4

// Reserved address 0x2e8

// Reserved address 0x2ec

// Reserved address 0x2f0

// Reserved address 0x2f4

// Reserved address 0x2f8

// Reserved address 0x2fc

// Reserved address 0x314

// Reserved address 0x318

// Reserved address 0x31c

// Reserved address 0x320

// Reserved address 0x324

// Reserved address 0x328

// Reserved address 0x32c

// Reserved address 0x330

// Reserved address 0x334

// Reserved address 0x338

// Reserved address 0x33c

// Reserved address 0x340

// Reserved address 0x344

// Reserved address 0x348

// Reserved address 0x34c

// Reserved address 0x350

// Reserved address 0x354

// Reserved address 0x358

// Reserved address 0x35c

// Reserved address 0x360

// Reserved address 0x364

// Reserved address 0x368

// Reserved address 0x36c

// Reserved address 0x370

// Reserved address 0x374

// Reserved address 0x378

// Reserved address 0x37c

// Reserved address 0x380

// Reserved address 0x390

// Reserved address 0x394

// Reserved address 0x398

// Reserved address 0x39c

// Reserved address 0x3a0

// Reserved address 0x3a4

// Reserved address 0x3a8

// Reserved address 0x3ac

// Reserved address 0x3b0

// Reserved address 0x3b4

// Reserved address 0x3b8

// Reserved address 0x3bc

// Reserved address 0x3c0

//
// REGISTER LIST
//
#define LIST_ARUPHY_LANE_REGS(_op_) \
_op_(UPHY_LANE_MISC_CTL_1_0) \

//
// ADDRESS SPACES
//

#define BASE_ADDRESS_UPHY_LANE  0x00000000

//
// ARUPHY_LANE REGISTER BANKS
//

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif
#ifndef _MK_FIELD_CONST
  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
#endif

#endif // ifndef ___ARUPHY_LANE_H_INC_
