//
// Copyright (c) 2018 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ___ARQUALENG_H_INC_
#define ___ARQUALENG_H_INC_
#define NV_MOBILE_ARQUALENG_H_UNIT_OF_OFFSET 1B

// Register QUALENG_TRAFFIC_CTRL_0
#define QUALENG_TRAFFIC_CTRL_0                  _MK_ADDR_CONST(0x0)
#define QUALENG_TRAFFIC_CTRL_0_SECURE                   0x0
#define QUALENG_TRAFFIC_CTRL_0_DUAL                     0x0
#define QUALENG_TRAFFIC_CTRL_0_SCR                      0
#define QUALENG_TRAFFIC_CTRL_0_WORD_COUNT                       0x1
#define QUALENG_TRAFFIC_CTRL_0_RESET_VAL                        _MK_MASK_CONST(0x400000)
#define QUALENG_TRAFFIC_CTRL_0_RESET_MASK                       _MK_MASK_CONST(0xff3ff7)
#define QUALENG_TRAFFIC_CTRL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define QUALENG_TRAFFIC_CTRL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QUALENG_TRAFFIC_CTRL_0_READ_MASK                        _MK_MASK_CONST(0xff3ff7)
#define QUALENG_TRAFFIC_CTRL_0_WRITE_MASK                       _MK_MASK_CONST(0xff3ff7)
#define QUALENG_TRAFFIC_CTRL_0_START_TEST_SHIFT                 _MK_SHIFT_CONST(0)
#define QUALENG_TRAFFIC_CTRL_0_START_TEST_FIELD                 _MK_FIELD_CONST(0x1, QUALENG_TRAFFIC_CTRL_0_START_TEST_SHIFT)
#define QUALENG_TRAFFIC_CTRL_0_START_TEST_RANGE                 0:0
#define QUALENG_TRAFFIC_CTRL_0_START_TEST_WOFFSET                       0x0
#define QUALENG_TRAFFIC_CTRL_0_START_TEST_DEFAULT                       _MK_MASK_CONST(0x0)
#define QUALENG_TRAFFIC_CTRL_0_START_TEST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define QUALENG_TRAFFIC_CTRL_0_START_TEST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define QUALENG_TRAFFIC_CTRL_0_START_TEST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define QUALENG_TRAFFIC_CTRL_0_START_TEST_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define QUALENG_TRAFFIC_CTRL_0_START_TEST_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define QUALENG_TRAFFIC_CTRL_0_START_TEST_INIT_ENUM                     DISABLE
#define QUALENG_TRAFFIC_CTRL_0_START_TEST_DISABLE                       _MK_ENUM_CONST(0)
#define QUALENG_TRAFFIC_CTRL_0_START_TEST_ENABLE                        _MK_ENUM_CONST(1)

#define QUALENG_TRAFFIC_CTRL_0_RESET_LOGIC_SHIFT                        _MK_SHIFT_CONST(1)
#define QUALENG_TRAFFIC_CTRL_0_RESET_LOGIC_FIELD                        _MK_FIELD_CONST(0x1, QUALENG_TRAFFIC_CTRL_0_RESET_LOGIC_SHIFT)
#define QUALENG_TRAFFIC_CTRL_0_RESET_LOGIC_RANGE                        1:1
#define QUALENG_TRAFFIC_CTRL_0_RESET_LOGIC_WOFFSET                      0x0
#define QUALENG_TRAFFIC_CTRL_0_RESET_LOGIC_DEFAULT                      _MK_MASK_CONST(0x0)
#define QUALENG_TRAFFIC_CTRL_0_RESET_LOGIC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define QUALENG_TRAFFIC_CTRL_0_RESET_LOGIC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_TRAFFIC_CTRL_0_RESET_LOGIC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_TRAFFIC_CTRL_0_RESET_LOGIC_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define QUALENG_TRAFFIC_CTRL_0_RESET_LOGIC_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QUALENG_TRAFFIC_CTRL_0_RESET_LOGIC_INIT_ENUM                    DISABLE
#define QUALENG_TRAFFIC_CTRL_0_RESET_LOGIC_DISABLE                      _MK_ENUM_CONST(0)
#define QUALENG_TRAFFIC_CTRL_0_RESET_LOGIC_ENABLE                       _MK_ENUM_CONST(1)

#define QUALENG_TRAFFIC_CTRL_0_RESET_STATUS_SHIFT                       _MK_SHIFT_CONST(2)
#define QUALENG_TRAFFIC_CTRL_0_RESET_STATUS_FIELD                       _MK_FIELD_CONST(0x1, QUALENG_TRAFFIC_CTRL_0_RESET_STATUS_SHIFT)
#define QUALENG_TRAFFIC_CTRL_0_RESET_STATUS_RANGE                       2:2
#define QUALENG_TRAFFIC_CTRL_0_RESET_STATUS_WOFFSET                     0x0
#define QUALENG_TRAFFIC_CTRL_0_RESET_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_TRAFFIC_CTRL_0_RESET_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define QUALENG_TRAFFIC_CTRL_0_RESET_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define QUALENG_TRAFFIC_CTRL_0_RESET_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define QUALENG_TRAFFIC_CTRL_0_RESET_STATUS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define QUALENG_TRAFFIC_CTRL_0_RESET_STATUS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define QUALENG_TRAFFIC_CTRL_0_RESET_STATUS_INIT_ENUM                   DISABLE
#define QUALENG_TRAFFIC_CTRL_0_RESET_STATUS_DISABLE                     _MK_ENUM_CONST(0)
#define QUALENG_TRAFFIC_CTRL_0_RESET_STATUS_ENABLE                      _MK_ENUM_CONST(1)

#define QUALENG_TRAFFIC_CTRL_0_STOP_ON_ERR_COUNT_SHIFT                  _MK_SHIFT_CONST(4)
#define QUALENG_TRAFFIC_CTRL_0_STOP_ON_ERR_COUNT_FIELD                  _MK_FIELD_CONST(0x3ff, QUALENG_TRAFFIC_CTRL_0_STOP_ON_ERR_COUNT_SHIFT)
#define QUALENG_TRAFFIC_CTRL_0_STOP_ON_ERR_COUNT_RANGE                  13:4
#define QUALENG_TRAFFIC_CTRL_0_STOP_ON_ERR_COUNT_WOFFSET                        0x0
#define QUALENG_TRAFFIC_CTRL_0_STOP_ON_ERR_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_TRAFFIC_CTRL_0_STOP_ON_ERR_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
#define QUALENG_TRAFFIC_CTRL_0_STOP_ON_ERR_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_TRAFFIC_CTRL_0_STOP_ON_ERR_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_TRAFFIC_CTRL_0_STOP_ON_ERR_COUNT_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_TRAFFIC_CTRL_0_STOP_ON_ERR_COUNT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QUALENG_TRAFFIC_CTRL_0_STOP_ON_ERR_COUNT_INIT_ENUM                      DISABLE
#define QUALENG_TRAFFIC_CTRL_0_STOP_ON_ERR_COUNT_DISABLE                        _MK_ENUM_CONST(0)

#define QUALENG_TRAFFIC_CTRL_0_INTERLOCK_COUNT_SHIFT                    _MK_SHIFT_CONST(16)
#define QUALENG_TRAFFIC_CTRL_0_INTERLOCK_COUNT_FIELD                    _MK_FIELD_CONST(0xff, QUALENG_TRAFFIC_CTRL_0_INTERLOCK_COUNT_SHIFT)
#define QUALENG_TRAFFIC_CTRL_0_INTERLOCK_COUNT_RANGE                    23:16
#define QUALENG_TRAFFIC_CTRL_0_INTERLOCK_COUNT_WOFFSET                  0x0
#define QUALENG_TRAFFIC_CTRL_0_INTERLOCK_COUNT_DEFAULT                  _MK_MASK_CONST(0x40)
#define QUALENG_TRAFFIC_CTRL_0_INTERLOCK_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define QUALENG_TRAFFIC_CTRL_0_INTERLOCK_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QUALENG_TRAFFIC_CTRL_0_INTERLOCK_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QUALENG_TRAFFIC_CTRL_0_INTERLOCK_COUNT_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define QUALENG_TRAFFIC_CTRL_0_INTERLOCK_COUNT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define QUALENG_TRAFFIC_CTRL_0_INTERLOCK_COUNT_DISABLE                  _MK_ENUM_CONST(0)

// Register QUALENG_PATTERN_0
#define QUALENG_PATTERN_0                       _MK_ADDR_CONST(0x4)
#define QUALENG_PATTERN_0_SECURE                        0x0
#define QUALENG_PATTERN_0_DUAL                  0x0
#define QUALENG_PATTERN_0_SCR                   0
#define QUALENG_PATTERN_0_WORD_COUNT                    0x1
#define QUALENG_PATTERN_0_RESET_VAL                     _MK_MASK_CONST(0x12000)
#define QUALENG_PATTERN_0_RESET_MASK                    _MK_MASK_CONST(0x731f3)
#define QUALENG_PATTERN_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define QUALENG_PATTERN_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define QUALENG_PATTERN_0_READ_MASK                     _MK_MASK_CONST(0x731f3)
#define QUALENG_PATTERN_0_WRITE_MASK                    _MK_MASK_CONST(0x731f3)
#define QUALENG_PATTERN_0_PATTERN_REPEAT_TYPE_SHIFT                     _MK_SHIFT_CONST(0)
#define QUALENG_PATTERN_0_PATTERN_REPEAT_TYPE_FIELD                     _MK_FIELD_CONST(0x3, QUALENG_PATTERN_0_PATTERN_REPEAT_TYPE_SHIFT)
#define QUALENG_PATTERN_0_PATTERN_REPEAT_TYPE_RANGE                     1:0
#define QUALENG_PATTERN_0_PATTERN_REPEAT_TYPE_WOFFSET                   0x0
#define QUALENG_PATTERN_0_PATTERN_REPEAT_TYPE_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_PATTERN_0_PATTERN_REPEAT_TYPE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define QUALENG_PATTERN_0_PATTERN_REPEAT_TYPE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_PATTERN_0_PATTERN_REPEAT_TYPE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_PATTERN_0_PATTERN_REPEAT_TYPE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define QUALENG_PATTERN_0_PATTERN_REPEAT_TYPE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define QUALENG_PATTERN_0_PATTERN_REPEAT_TYPE_INIT_ENUM                 SIMPLE
#define QUALENG_PATTERN_0_PATTERN_REPEAT_TYPE_SIMPLE                    _MK_ENUM_CONST(0)
#define QUALENG_PATTERN_0_PATTERN_REPEAT_TYPE_INVERT_DATA                       _MK_ENUM_CONST(1)
#define QUALENG_PATTERN_0_PATTERN_REPEAT_TYPE_INVERT_DATA_BE                    _MK_ENUM_CONST(2)

#define QUALENG_PATTERN_0_PATTERN_REPEAT_COUNT_SHIFT                    _MK_SHIFT_CONST(4)
#define QUALENG_PATTERN_0_PATTERN_REPEAT_COUNT_FIELD                    _MK_FIELD_CONST(0x1f, QUALENG_PATTERN_0_PATTERN_REPEAT_COUNT_SHIFT)
#define QUALENG_PATTERN_0_PATTERN_REPEAT_COUNT_RANGE                    8:4
#define QUALENG_PATTERN_0_PATTERN_REPEAT_COUNT_WOFFSET                  0x0
#define QUALENG_PATTERN_0_PATTERN_REPEAT_COUNT_DEFAULT                  _MK_MASK_CONST(0x0)
#define QUALENG_PATTERN_0_PATTERN_REPEAT_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define QUALENG_PATTERN_0_PATTERN_REPEAT_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QUALENG_PATTERN_0_PATTERN_REPEAT_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QUALENG_PATTERN_0_PATTERN_REPEAT_COUNT_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define QUALENG_PATTERN_0_PATTERN_REPEAT_COUNT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define QUALENG_PATTERN_0_PATTERN_REPEAT_COUNT_INIT_ENUM                        NO_REPEAT
#define QUALENG_PATTERN_0_PATTERN_REPEAT_COUNT_NO_REPEAT                        _MK_ENUM_CONST(0)

#define QUALENG_PATTERN_0_PATTERN_SOURCE_SHIFT                  _MK_SHIFT_CONST(12)
#define QUALENG_PATTERN_0_PATTERN_SOURCE_FIELD                  _MK_FIELD_CONST(0x3, QUALENG_PATTERN_0_PATTERN_SOURCE_SHIFT)
#define QUALENG_PATTERN_0_PATTERN_SOURCE_RANGE                  13:12
#define QUALENG_PATTERN_0_PATTERN_SOURCE_WOFFSET                        0x0
#define QUALENG_PATTERN_0_PATTERN_SOURCE_DEFAULT                        _MK_MASK_CONST(0x2)
#define QUALENG_PATTERN_0_PATTERN_SOURCE_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define QUALENG_PATTERN_0_PATTERN_SOURCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_PATTERN_0_PATTERN_SOURCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_PATTERN_0_PATTERN_SOURCE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_PATTERN_0_PATTERN_SOURCE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QUALENG_PATTERN_0_PATTERN_SOURCE_INIT_ENUM                      ADDRESS
#define QUALENG_PATTERN_0_PATTERN_SOURCE_PATRAM                 _MK_ENUM_CONST(0)
#define QUALENG_PATTERN_0_PATTERN_SOURCE_PRBS                   _MK_ENUM_CONST(1)
#define QUALENG_PATTERN_0_PATTERN_SOURCE_ADDRESS                        _MK_ENUM_CONST(2)

#define QUALENG_PATTERN_0_PATTERN_BE_SOURCE_SHIFT                       _MK_SHIFT_CONST(16)
#define QUALENG_PATTERN_0_PATTERN_BE_SOURCE_FIELD                       _MK_FIELD_CONST(0x7, QUALENG_PATTERN_0_PATTERN_BE_SOURCE_SHIFT)
#define QUALENG_PATTERN_0_PATTERN_BE_SOURCE_RANGE                       18:16
#define QUALENG_PATTERN_0_PATTERN_BE_SOURCE_WOFFSET                     0x0
#define QUALENG_PATTERN_0_PATTERN_BE_SOURCE_DEFAULT                     _MK_MASK_CONST(0x1)
#define QUALENG_PATTERN_0_PATTERN_BE_SOURCE_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define QUALENG_PATTERN_0_PATTERN_BE_SOURCE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define QUALENG_PATTERN_0_PATTERN_BE_SOURCE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define QUALENG_PATTERN_0_PATTERN_BE_SOURCE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define QUALENG_PATTERN_0_PATTERN_BE_SOURCE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define QUALENG_PATTERN_0_PATTERN_BE_SOURCE_INIT_ENUM                   FULL
#define QUALENG_PATTERN_0_PATTERN_BE_SOURCE_PATRAM                      _MK_ENUM_CONST(0)
#define QUALENG_PATTERN_0_PATTERN_BE_SOURCE_FULL                        _MK_ENUM_CONST(1)
#define QUALENG_PATTERN_0_PATTERN_BE_SOURCE_RANDOM_12P5                 _MK_ENUM_CONST(2)
#define QUALENG_PATTERN_0_PATTERN_BE_SOURCE_RANDOM_25                   _MK_ENUM_CONST(3)
#define QUALENG_PATTERN_0_PATTERN_BE_SOURCE_RANDOM_50                   _MK_ENUM_CONST(4)

// Register QUALENG_MIU_TRAFFIC_CTRL_0
#define QUALENG_MIU_TRAFFIC_CTRL_0                      _MK_ADDR_CONST(0x20)
#define QUALENG_MIU_TRAFFIC_CTRL_0_SECURE                       0x0
#define QUALENG_MIU_TRAFFIC_CTRL_0_DUAL                         0x0
#define QUALENG_MIU_TRAFFIC_CTRL_0_SCR                  0
#define QUALENG_MIU_TRAFFIC_CTRL_0_WORD_COUNT                   0x1
#define QUALENG_MIU_TRAFFIC_CTRL_0_RESET_VAL                    _MK_MASK_CONST(0x2)
#define QUALENG_MIU_TRAFFIC_CTRL_0_RESET_MASK                   _MK_MASK_CONST(0x1ff3)
#define QUALENG_MIU_TRAFFIC_CTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_0_READ_MASK                    _MK_MASK_CONST(0x1ff3)
#define QUALENG_MIU_TRAFFIC_CTRL_0_WRITE_MASK                   _MK_MASK_CONST(0x1ff3)
#define QUALENG_MIU_TRAFFIC_CTRL_0_READ_SHIFT                   _MK_SHIFT_CONST(0)
#define QUALENG_MIU_TRAFFIC_CTRL_0_READ_FIELD                   _MK_FIELD_CONST(0x1, QUALENG_MIU_TRAFFIC_CTRL_0_READ_SHIFT)
#define QUALENG_MIU_TRAFFIC_CTRL_0_READ_RANGE                   0:0
#define QUALENG_MIU_TRAFFIC_CTRL_0_READ_WOFFSET                 0x0
#define QUALENG_MIU_TRAFFIC_CTRL_0_READ_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_0_READ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_0_READ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_0_READ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_0_READ_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_0_READ_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_0_READ_INIT_ENUM                       DISABLE
#define QUALENG_MIU_TRAFFIC_CTRL_0_READ_DISABLE                 _MK_ENUM_CONST(0)
#define QUALENG_MIU_TRAFFIC_CTRL_0_READ_ENABLE                  _MK_ENUM_CONST(1)

#define QUALENG_MIU_TRAFFIC_CTRL_0_WRITE_SHIFT                  _MK_SHIFT_CONST(1)
#define QUALENG_MIU_TRAFFIC_CTRL_0_WRITE_FIELD                  _MK_FIELD_CONST(0x1, QUALENG_MIU_TRAFFIC_CTRL_0_WRITE_SHIFT)
#define QUALENG_MIU_TRAFFIC_CTRL_0_WRITE_RANGE                  1:1
#define QUALENG_MIU_TRAFFIC_CTRL_0_WRITE_WOFFSET                        0x0
#define QUALENG_MIU_TRAFFIC_CTRL_0_WRITE_DEFAULT                        _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_0_WRITE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_0_WRITE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_0_WRITE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_0_WRITE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_0_WRITE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_0_WRITE_INIT_ENUM                      ENABLE
#define QUALENG_MIU_TRAFFIC_CTRL_0_WRITE_DISABLE                        _MK_ENUM_CONST(0)
#define QUALENG_MIU_TRAFFIC_CTRL_0_WRITE_ENABLE                 _MK_ENUM_CONST(1)

#define QUALENG_MIU_TRAFFIC_CTRL_0_OUTSTANDING_REQ_LIMIT_SHIFT                  _MK_SHIFT_CONST(4)
#define QUALENG_MIU_TRAFFIC_CTRL_0_OUTSTANDING_REQ_LIMIT_FIELD                  _MK_FIELD_CONST(0x1ff, QUALENG_MIU_TRAFFIC_CTRL_0_OUTSTANDING_REQ_LIMIT_SHIFT)
#define QUALENG_MIU_TRAFFIC_CTRL_0_OUTSTANDING_REQ_LIMIT_RANGE                  12:4
#define QUALENG_MIU_TRAFFIC_CTRL_0_OUTSTANDING_REQ_LIMIT_WOFFSET                        0x0
#define QUALENG_MIU_TRAFFIC_CTRL_0_OUTSTANDING_REQ_LIMIT_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_0_OUTSTANDING_REQ_LIMIT_DEFAULT_MASK                   _MK_MASK_CONST(0x1ff)
#define QUALENG_MIU_TRAFFIC_CTRL_0_OUTSTANDING_REQ_LIMIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_0_OUTSTANDING_REQ_LIMIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_0_OUTSTANDING_REQ_LIMIT_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_0_OUTSTANDING_REQ_LIMIT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_0_OUTSTANDING_REQ_LIMIT_INIT_ENUM                      DISABLE
#define QUALENG_MIU_TRAFFIC_CTRL_0_OUTSTANDING_REQ_LIMIT_DISABLE                        _MK_ENUM_CONST(0)

// Register QUALENG_MIU_TRAFFIC_CTRL
#define QUALENG_MIU_TRAFFIC_CTRL                        _MK_ADDR_CONST(0x20)
#define QUALENG_MIU_TRAFFIC_CTRL_SECURE                         0x0
#define QUALENG_MIU_TRAFFIC_CTRL_DUAL                   0x0
#define QUALENG_MIU_TRAFFIC_CTRL_SCR                    0
#define QUALENG_MIU_TRAFFIC_CTRL_WORD_COUNT                     0x1
#define QUALENG_MIU_TRAFFIC_CTRL_RESET_VAL                      _MK_MASK_CONST(0x2)
#define QUALENG_MIU_TRAFFIC_CTRL_RESET_MASK                     _MK_MASK_CONST(0x1ff3)
#define QUALENG_MIU_TRAFFIC_CTRL_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_READ_MASK                      _MK_MASK_CONST(0x1ff3)
#define QUALENG_MIU_TRAFFIC_CTRL_WRITE_MASK                     _MK_MASK_CONST(0x1ff3)
#define QUALENG_MIU_TRAFFIC_CTRL_READ_SHIFT                     _MK_SHIFT_CONST(0)
#define QUALENG_MIU_TRAFFIC_CTRL_READ_FIELD                     _MK_FIELD_CONST(0x1, QUALENG_MIU_TRAFFIC_CTRL_READ_SHIFT)
#define QUALENG_MIU_TRAFFIC_CTRL_READ_RANGE                     0:0
#define QUALENG_MIU_TRAFFIC_CTRL_READ_WOFFSET                   0x0
#define QUALENG_MIU_TRAFFIC_CTRL_READ_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_READ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_READ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_READ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_READ_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_READ_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_READ_INIT_ENUM                 DISABLE
#define QUALENG_MIU_TRAFFIC_CTRL_READ_DISABLE                   _MK_ENUM_CONST(0)
#define QUALENG_MIU_TRAFFIC_CTRL_READ_ENABLE                    _MK_ENUM_CONST(1)

#define QUALENG_MIU_TRAFFIC_CTRL_WRITE_SHIFT                    _MK_SHIFT_CONST(1)
#define QUALENG_MIU_TRAFFIC_CTRL_WRITE_FIELD                    _MK_FIELD_CONST(0x1, QUALENG_MIU_TRAFFIC_CTRL_WRITE_SHIFT)
#define QUALENG_MIU_TRAFFIC_CTRL_WRITE_RANGE                    1:1
#define QUALENG_MIU_TRAFFIC_CTRL_WRITE_WOFFSET                  0x0
#define QUALENG_MIU_TRAFFIC_CTRL_WRITE_DEFAULT                  _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_WRITE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_WRITE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_WRITE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_WRITE_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_WRITE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_WRITE_INIT_ENUM                        ENABLE
#define QUALENG_MIU_TRAFFIC_CTRL_WRITE_DISABLE                  _MK_ENUM_CONST(0)
#define QUALENG_MIU_TRAFFIC_CTRL_WRITE_ENABLE                   _MK_ENUM_CONST(1)

#define QUALENG_MIU_TRAFFIC_CTRL_OUTSTANDING_REQ_LIMIT_SHIFT                    _MK_SHIFT_CONST(4)
#define QUALENG_MIU_TRAFFIC_CTRL_OUTSTANDING_REQ_LIMIT_FIELD                    _MK_FIELD_CONST(0x1ff, QUALENG_MIU_TRAFFIC_CTRL_OUTSTANDING_REQ_LIMIT_SHIFT)
#define QUALENG_MIU_TRAFFIC_CTRL_OUTSTANDING_REQ_LIMIT_RANGE                    12:4
#define QUALENG_MIU_TRAFFIC_CTRL_OUTSTANDING_REQ_LIMIT_WOFFSET                  0x0
#define QUALENG_MIU_TRAFFIC_CTRL_OUTSTANDING_REQ_LIMIT_DEFAULT                  _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_OUTSTANDING_REQ_LIMIT_DEFAULT_MASK                     _MK_MASK_CONST(0x1ff)
#define QUALENG_MIU_TRAFFIC_CTRL_OUTSTANDING_REQ_LIMIT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_OUTSTANDING_REQ_LIMIT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_OUTSTANDING_REQ_LIMIT_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_OUTSTANDING_REQ_LIMIT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_OUTSTANDING_REQ_LIMIT_INIT_ENUM                        DISABLE
#define QUALENG_MIU_TRAFFIC_CTRL_OUTSTANDING_REQ_LIMIT_DISABLE                  _MK_ENUM_CONST(0)

// Register QUALENG_MIU_TRAFFIC_CTRL_1
#define QUALENG_MIU_TRAFFIC_CTRL_1                      _MK_ADDR_CONST(0x24)
#define QUALENG_MIU_TRAFFIC_CTRL_1_SECURE                       0x0
#define QUALENG_MIU_TRAFFIC_CTRL_1_DUAL                         0x0
#define QUALENG_MIU_TRAFFIC_CTRL_1_SCR                  0
#define QUALENG_MIU_TRAFFIC_CTRL_1_WORD_COUNT                   0x1
#define QUALENG_MIU_TRAFFIC_CTRL_1_RESET_VAL                    _MK_MASK_CONST(0x2)
#define QUALENG_MIU_TRAFFIC_CTRL_1_RESET_MASK                   _MK_MASK_CONST(0x1ff3)
#define QUALENG_MIU_TRAFFIC_CTRL_1_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_1_READ_MASK                    _MK_MASK_CONST(0x1ff3)
#define QUALENG_MIU_TRAFFIC_CTRL_1_WRITE_MASK                   _MK_MASK_CONST(0x1ff3)
#define QUALENG_MIU_TRAFFIC_CTRL_1_READ_SHIFT                   _MK_SHIFT_CONST(0)
#define QUALENG_MIU_TRAFFIC_CTRL_1_READ_FIELD                   _MK_FIELD_CONST(0x1, QUALENG_MIU_TRAFFIC_CTRL_1_READ_SHIFT)
#define QUALENG_MIU_TRAFFIC_CTRL_1_READ_RANGE                   0:0
#define QUALENG_MIU_TRAFFIC_CTRL_1_READ_WOFFSET                 0x0
#define QUALENG_MIU_TRAFFIC_CTRL_1_READ_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_1_READ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_1_READ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_1_READ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_1_READ_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_1_READ_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_1_READ_INIT_ENUM                       DISABLE
#define QUALENG_MIU_TRAFFIC_CTRL_1_READ_DISABLE                 _MK_ENUM_CONST(0)
#define QUALENG_MIU_TRAFFIC_CTRL_1_READ_ENABLE                  _MK_ENUM_CONST(1)

#define QUALENG_MIU_TRAFFIC_CTRL_1_WRITE_SHIFT                  _MK_SHIFT_CONST(1)
#define QUALENG_MIU_TRAFFIC_CTRL_1_WRITE_FIELD                  _MK_FIELD_CONST(0x1, QUALENG_MIU_TRAFFIC_CTRL_1_WRITE_SHIFT)
#define QUALENG_MIU_TRAFFIC_CTRL_1_WRITE_RANGE                  1:1
#define QUALENG_MIU_TRAFFIC_CTRL_1_WRITE_WOFFSET                        0x0
#define QUALENG_MIU_TRAFFIC_CTRL_1_WRITE_DEFAULT                        _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_1_WRITE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_1_WRITE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_1_WRITE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_1_WRITE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_1_WRITE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_1_WRITE_INIT_ENUM                      ENABLE
#define QUALENG_MIU_TRAFFIC_CTRL_1_WRITE_DISABLE                        _MK_ENUM_CONST(0)
#define QUALENG_MIU_TRAFFIC_CTRL_1_WRITE_ENABLE                 _MK_ENUM_CONST(1)

#define QUALENG_MIU_TRAFFIC_CTRL_1_OUTSTANDING_REQ_LIMIT_SHIFT                  _MK_SHIFT_CONST(4)
#define QUALENG_MIU_TRAFFIC_CTRL_1_OUTSTANDING_REQ_LIMIT_FIELD                  _MK_FIELD_CONST(0x1ff, QUALENG_MIU_TRAFFIC_CTRL_1_OUTSTANDING_REQ_LIMIT_SHIFT)
#define QUALENG_MIU_TRAFFIC_CTRL_1_OUTSTANDING_REQ_LIMIT_RANGE                  12:4
#define QUALENG_MIU_TRAFFIC_CTRL_1_OUTSTANDING_REQ_LIMIT_WOFFSET                        0x0
#define QUALENG_MIU_TRAFFIC_CTRL_1_OUTSTANDING_REQ_LIMIT_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_1_OUTSTANDING_REQ_LIMIT_DEFAULT_MASK                   _MK_MASK_CONST(0x1ff)
#define QUALENG_MIU_TRAFFIC_CTRL_1_OUTSTANDING_REQ_LIMIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_1_OUTSTANDING_REQ_LIMIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_1_OUTSTANDING_REQ_LIMIT_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_1_OUTSTANDING_REQ_LIMIT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_1_OUTSTANDING_REQ_LIMIT_INIT_ENUM                      DISABLE
#define QUALENG_MIU_TRAFFIC_CTRL_1_OUTSTANDING_REQ_LIMIT_DISABLE                        _MK_ENUM_CONST(0)

// Register QUALENG_MIU_TRAFFIC_CTRL_2
#define QUALENG_MIU_TRAFFIC_CTRL_2                      _MK_ADDR_CONST(0x28)
#define QUALENG_MIU_TRAFFIC_CTRL_2_SECURE                       0x0
#define QUALENG_MIU_TRAFFIC_CTRL_2_DUAL                         0x0
#define QUALENG_MIU_TRAFFIC_CTRL_2_SCR                  0
#define QUALENG_MIU_TRAFFIC_CTRL_2_WORD_COUNT                   0x1
#define QUALENG_MIU_TRAFFIC_CTRL_2_RESET_VAL                    _MK_MASK_CONST(0x2)
#define QUALENG_MIU_TRAFFIC_CTRL_2_RESET_MASK                   _MK_MASK_CONST(0x1ff3)
#define QUALENG_MIU_TRAFFIC_CTRL_2_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_2_READ_MASK                    _MK_MASK_CONST(0x1ff3)
#define QUALENG_MIU_TRAFFIC_CTRL_2_WRITE_MASK                   _MK_MASK_CONST(0x1ff3)
#define QUALENG_MIU_TRAFFIC_CTRL_2_READ_SHIFT                   _MK_SHIFT_CONST(0)
#define QUALENG_MIU_TRAFFIC_CTRL_2_READ_FIELD                   _MK_FIELD_CONST(0x1, QUALENG_MIU_TRAFFIC_CTRL_2_READ_SHIFT)
#define QUALENG_MIU_TRAFFIC_CTRL_2_READ_RANGE                   0:0
#define QUALENG_MIU_TRAFFIC_CTRL_2_READ_WOFFSET                 0x0
#define QUALENG_MIU_TRAFFIC_CTRL_2_READ_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_2_READ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_2_READ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_2_READ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_2_READ_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_2_READ_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_2_READ_INIT_ENUM                       DISABLE
#define QUALENG_MIU_TRAFFIC_CTRL_2_READ_DISABLE                 _MK_ENUM_CONST(0)
#define QUALENG_MIU_TRAFFIC_CTRL_2_READ_ENABLE                  _MK_ENUM_CONST(1)

#define QUALENG_MIU_TRAFFIC_CTRL_2_WRITE_SHIFT                  _MK_SHIFT_CONST(1)
#define QUALENG_MIU_TRAFFIC_CTRL_2_WRITE_FIELD                  _MK_FIELD_CONST(0x1, QUALENG_MIU_TRAFFIC_CTRL_2_WRITE_SHIFT)
#define QUALENG_MIU_TRAFFIC_CTRL_2_WRITE_RANGE                  1:1
#define QUALENG_MIU_TRAFFIC_CTRL_2_WRITE_WOFFSET                        0x0
#define QUALENG_MIU_TRAFFIC_CTRL_2_WRITE_DEFAULT                        _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_2_WRITE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_2_WRITE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_2_WRITE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_2_WRITE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_2_WRITE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_2_WRITE_INIT_ENUM                      ENABLE
#define QUALENG_MIU_TRAFFIC_CTRL_2_WRITE_DISABLE                        _MK_ENUM_CONST(0)
#define QUALENG_MIU_TRAFFIC_CTRL_2_WRITE_ENABLE                 _MK_ENUM_CONST(1)

#define QUALENG_MIU_TRAFFIC_CTRL_2_OUTSTANDING_REQ_LIMIT_SHIFT                  _MK_SHIFT_CONST(4)
#define QUALENG_MIU_TRAFFIC_CTRL_2_OUTSTANDING_REQ_LIMIT_FIELD                  _MK_FIELD_CONST(0x1ff, QUALENG_MIU_TRAFFIC_CTRL_2_OUTSTANDING_REQ_LIMIT_SHIFT)
#define QUALENG_MIU_TRAFFIC_CTRL_2_OUTSTANDING_REQ_LIMIT_RANGE                  12:4
#define QUALENG_MIU_TRAFFIC_CTRL_2_OUTSTANDING_REQ_LIMIT_WOFFSET                        0x0
#define QUALENG_MIU_TRAFFIC_CTRL_2_OUTSTANDING_REQ_LIMIT_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_2_OUTSTANDING_REQ_LIMIT_DEFAULT_MASK                   _MK_MASK_CONST(0x1ff)
#define QUALENG_MIU_TRAFFIC_CTRL_2_OUTSTANDING_REQ_LIMIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_2_OUTSTANDING_REQ_LIMIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_2_OUTSTANDING_REQ_LIMIT_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_2_OUTSTANDING_REQ_LIMIT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_2_OUTSTANDING_REQ_LIMIT_INIT_ENUM                      DISABLE
#define QUALENG_MIU_TRAFFIC_CTRL_2_OUTSTANDING_REQ_LIMIT_DISABLE                        _MK_ENUM_CONST(0)

// Register QUALENG_MIU_TRAFFIC_CTRL_3
#define QUALENG_MIU_TRAFFIC_CTRL_3                      _MK_ADDR_CONST(0x2c)
#define QUALENG_MIU_TRAFFIC_CTRL_3_SECURE                       0x0
#define QUALENG_MIU_TRAFFIC_CTRL_3_DUAL                         0x0
#define QUALENG_MIU_TRAFFIC_CTRL_3_SCR                  0
#define QUALENG_MIU_TRAFFIC_CTRL_3_WORD_COUNT                   0x1
#define QUALENG_MIU_TRAFFIC_CTRL_3_RESET_VAL                    _MK_MASK_CONST(0x2)
#define QUALENG_MIU_TRAFFIC_CTRL_3_RESET_MASK                   _MK_MASK_CONST(0x1ff3)
#define QUALENG_MIU_TRAFFIC_CTRL_3_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_3_READ_MASK                    _MK_MASK_CONST(0x1ff3)
#define QUALENG_MIU_TRAFFIC_CTRL_3_WRITE_MASK                   _MK_MASK_CONST(0x1ff3)
#define QUALENG_MIU_TRAFFIC_CTRL_3_READ_SHIFT                   _MK_SHIFT_CONST(0)
#define QUALENG_MIU_TRAFFIC_CTRL_3_READ_FIELD                   _MK_FIELD_CONST(0x1, QUALENG_MIU_TRAFFIC_CTRL_3_READ_SHIFT)
#define QUALENG_MIU_TRAFFIC_CTRL_3_READ_RANGE                   0:0
#define QUALENG_MIU_TRAFFIC_CTRL_3_READ_WOFFSET                 0x0
#define QUALENG_MIU_TRAFFIC_CTRL_3_READ_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_3_READ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_3_READ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_3_READ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_3_READ_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_3_READ_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_3_READ_INIT_ENUM                       DISABLE
#define QUALENG_MIU_TRAFFIC_CTRL_3_READ_DISABLE                 _MK_ENUM_CONST(0)
#define QUALENG_MIU_TRAFFIC_CTRL_3_READ_ENABLE                  _MK_ENUM_CONST(1)

#define QUALENG_MIU_TRAFFIC_CTRL_3_WRITE_SHIFT                  _MK_SHIFT_CONST(1)
#define QUALENG_MIU_TRAFFIC_CTRL_3_WRITE_FIELD                  _MK_FIELD_CONST(0x1, QUALENG_MIU_TRAFFIC_CTRL_3_WRITE_SHIFT)
#define QUALENG_MIU_TRAFFIC_CTRL_3_WRITE_RANGE                  1:1
#define QUALENG_MIU_TRAFFIC_CTRL_3_WRITE_WOFFSET                        0x0
#define QUALENG_MIU_TRAFFIC_CTRL_3_WRITE_DEFAULT                        _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_3_WRITE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_3_WRITE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_3_WRITE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_3_WRITE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_3_WRITE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_3_WRITE_INIT_ENUM                      ENABLE
#define QUALENG_MIU_TRAFFIC_CTRL_3_WRITE_DISABLE                        _MK_ENUM_CONST(0)
#define QUALENG_MIU_TRAFFIC_CTRL_3_WRITE_ENABLE                 _MK_ENUM_CONST(1)

#define QUALENG_MIU_TRAFFIC_CTRL_3_OUTSTANDING_REQ_LIMIT_SHIFT                  _MK_SHIFT_CONST(4)
#define QUALENG_MIU_TRAFFIC_CTRL_3_OUTSTANDING_REQ_LIMIT_FIELD                  _MK_FIELD_CONST(0x1ff, QUALENG_MIU_TRAFFIC_CTRL_3_OUTSTANDING_REQ_LIMIT_SHIFT)
#define QUALENG_MIU_TRAFFIC_CTRL_3_OUTSTANDING_REQ_LIMIT_RANGE                  12:4
#define QUALENG_MIU_TRAFFIC_CTRL_3_OUTSTANDING_REQ_LIMIT_WOFFSET                        0x0
#define QUALENG_MIU_TRAFFIC_CTRL_3_OUTSTANDING_REQ_LIMIT_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_3_OUTSTANDING_REQ_LIMIT_DEFAULT_MASK                   _MK_MASK_CONST(0x1ff)
#define QUALENG_MIU_TRAFFIC_CTRL_3_OUTSTANDING_REQ_LIMIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_3_OUTSTANDING_REQ_LIMIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_3_OUTSTANDING_REQ_LIMIT_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_3_OUTSTANDING_REQ_LIMIT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_3_OUTSTANDING_REQ_LIMIT_INIT_ENUM                      DISABLE
#define QUALENG_MIU_TRAFFIC_CTRL_3_OUTSTANDING_REQ_LIMIT_DISABLE                        _MK_ENUM_CONST(0)

// Register QUALENG_MIU_TRAFFIC_CTRL_4
#define QUALENG_MIU_TRAFFIC_CTRL_4                      _MK_ADDR_CONST(0x30)
#define QUALENG_MIU_TRAFFIC_CTRL_4_SECURE                       0x0
#define QUALENG_MIU_TRAFFIC_CTRL_4_DUAL                         0x0
#define QUALENG_MIU_TRAFFIC_CTRL_4_SCR                  0
#define QUALENG_MIU_TRAFFIC_CTRL_4_WORD_COUNT                   0x1
#define QUALENG_MIU_TRAFFIC_CTRL_4_RESET_VAL                    _MK_MASK_CONST(0x2)
#define QUALENG_MIU_TRAFFIC_CTRL_4_RESET_MASK                   _MK_MASK_CONST(0x1ff3)
#define QUALENG_MIU_TRAFFIC_CTRL_4_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_4_READ_MASK                    _MK_MASK_CONST(0x1ff3)
#define QUALENG_MIU_TRAFFIC_CTRL_4_WRITE_MASK                   _MK_MASK_CONST(0x1ff3)
#define QUALENG_MIU_TRAFFIC_CTRL_4_READ_SHIFT                   _MK_SHIFT_CONST(0)
#define QUALENG_MIU_TRAFFIC_CTRL_4_READ_FIELD                   _MK_FIELD_CONST(0x1, QUALENG_MIU_TRAFFIC_CTRL_4_READ_SHIFT)
#define QUALENG_MIU_TRAFFIC_CTRL_4_READ_RANGE                   0:0
#define QUALENG_MIU_TRAFFIC_CTRL_4_READ_WOFFSET                 0x0
#define QUALENG_MIU_TRAFFIC_CTRL_4_READ_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_4_READ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_4_READ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_4_READ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_4_READ_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_4_READ_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_4_READ_INIT_ENUM                       DISABLE
#define QUALENG_MIU_TRAFFIC_CTRL_4_READ_DISABLE                 _MK_ENUM_CONST(0)
#define QUALENG_MIU_TRAFFIC_CTRL_4_READ_ENABLE                  _MK_ENUM_CONST(1)

#define QUALENG_MIU_TRAFFIC_CTRL_4_WRITE_SHIFT                  _MK_SHIFT_CONST(1)
#define QUALENG_MIU_TRAFFIC_CTRL_4_WRITE_FIELD                  _MK_FIELD_CONST(0x1, QUALENG_MIU_TRAFFIC_CTRL_4_WRITE_SHIFT)
#define QUALENG_MIU_TRAFFIC_CTRL_4_WRITE_RANGE                  1:1
#define QUALENG_MIU_TRAFFIC_CTRL_4_WRITE_WOFFSET                        0x0
#define QUALENG_MIU_TRAFFIC_CTRL_4_WRITE_DEFAULT                        _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_4_WRITE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_4_WRITE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_4_WRITE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_4_WRITE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_4_WRITE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_4_WRITE_INIT_ENUM                      ENABLE
#define QUALENG_MIU_TRAFFIC_CTRL_4_WRITE_DISABLE                        _MK_ENUM_CONST(0)
#define QUALENG_MIU_TRAFFIC_CTRL_4_WRITE_ENABLE                 _MK_ENUM_CONST(1)

#define QUALENG_MIU_TRAFFIC_CTRL_4_OUTSTANDING_REQ_LIMIT_SHIFT                  _MK_SHIFT_CONST(4)
#define QUALENG_MIU_TRAFFIC_CTRL_4_OUTSTANDING_REQ_LIMIT_FIELD                  _MK_FIELD_CONST(0x1ff, QUALENG_MIU_TRAFFIC_CTRL_4_OUTSTANDING_REQ_LIMIT_SHIFT)
#define QUALENG_MIU_TRAFFIC_CTRL_4_OUTSTANDING_REQ_LIMIT_RANGE                  12:4
#define QUALENG_MIU_TRAFFIC_CTRL_4_OUTSTANDING_REQ_LIMIT_WOFFSET                        0x0
#define QUALENG_MIU_TRAFFIC_CTRL_4_OUTSTANDING_REQ_LIMIT_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_4_OUTSTANDING_REQ_LIMIT_DEFAULT_MASK                   _MK_MASK_CONST(0x1ff)
#define QUALENG_MIU_TRAFFIC_CTRL_4_OUTSTANDING_REQ_LIMIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_4_OUTSTANDING_REQ_LIMIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_4_OUTSTANDING_REQ_LIMIT_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_4_OUTSTANDING_REQ_LIMIT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_4_OUTSTANDING_REQ_LIMIT_INIT_ENUM                      DISABLE
#define QUALENG_MIU_TRAFFIC_CTRL_4_OUTSTANDING_REQ_LIMIT_DISABLE                        _MK_ENUM_CONST(0)

// Register QUALENG_MIU_TRAFFIC_CTRL_5
#define QUALENG_MIU_TRAFFIC_CTRL_5                      _MK_ADDR_CONST(0x34)
#define QUALENG_MIU_TRAFFIC_CTRL_5_SECURE                       0x0
#define QUALENG_MIU_TRAFFIC_CTRL_5_DUAL                         0x0
#define QUALENG_MIU_TRAFFIC_CTRL_5_SCR                  0
#define QUALENG_MIU_TRAFFIC_CTRL_5_WORD_COUNT                   0x1
#define QUALENG_MIU_TRAFFIC_CTRL_5_RESET_VAL                    _MK_MASK_CONST(0x2)
#define QUALENG_MIU_TRAFFIC_CTRL_5_RESET_MASK                   _MK_MASK_CONST(0x1ff3)
#define QUALENG_MIU_TRAFFIC_CTRL_5_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_5_READ_MASK                    _MK_MASK_CONST(0x1ff3)
#define QUALENG_MIU_TRAFFIC_CTRL_5_WRITE_MASK                   _MK_MASK_CONST(0x1ff3)
#define QUALENG_MIU_TRAFFIC_CTRL_5_READ_SHIFT                   _MK_SHIFT_CONST(0)
#define QUALENG_MIU_TRAFFIC_CTRL_5_READ_FIELD                   _MK_FIELD_CONST(0x1, QUALENG_MIU_TRAFFIC_CTRL_5_READ_SHIFT)
#define QUALENG_MIU_TRAFFIC_CTRL_5_READ_RANGE                   0:0
#define QUALENG_MIU_TRAFFIC_CTRL_5_READ_WOFFSET                 0x0
#define QUALENG_MIU_TRAFFIC_CTRL_5_READ_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_5_READ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_5_READ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_5_READ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_5_READ_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_5_READ_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_5_READ_INIT_ENUM                       DISABLE
#define QUALENG_MIU_TRAFFIC_CTRL_5_READ_DISABLE                 _MK_ENUM_CONST(0)
#define QUALENG_MIU_TRAFFIC_CTRL_5_READ_ENABLE                  _MK_ENUM_CONST(1)

#define QUALENG_MIU_TRAFFIC_CTRL_5_WRITE_SHIFT                  _MK_SHIFT_CONST(1)
#define QUALENG_MIU_TRAFFIC_CTRL_5_WRITE_FIELD                  _MK_FIELD_CONST(0x1, QUALENG_MIU_TRAFFIC_CTRL_5_WRITE_SHIFT)
#define QUALENG_MIU_TRAFFIC_CTRL_5_WRITE_RANGE                  1:1
#define QUALENG_MIU_TRAFFIC_CTRL_5_WRITE_WOFFSET                        0x0
#define QUALENG_MIU_TRAFFIC_CTRL_5_WRITE_DEFAULT                        _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_5_WRITE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_5_WRITE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_5_WRITE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_5_WRITE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_5_WRITE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_5_WRITE_INIT_ENUM                      ENABLE
#define QUALENG_MIU_TRAFFIC_CTRL_5_WRITE_DISABLE                        _MK_ENUM_CONST(0)
#define QUALENG_MIU_TRAFFIC_CTRL_5_WRITE_ENABLE                 _MK_ENUM_CONST(1)

#define QUALENG_MIU_TRAFFIC_CTRL_5_OUTSTANDING_REQ_LIMIT_SHIFT                  _MK_SHIFT_CONST(4)
#define QUALENG_MIU_TRAFFIC_CTRL_5_OUTSTANDING_REQ_LIMIT_FIELD                  _MK_FIELD_CONST(0x1ff, QUALENG_MIU_TRAFFIC_CTRL_5_OUTSTANDING_REQ_LIMIT_SHIFT)
#define QUALENG_MIU_TRAFFIC_CTRL_5_OUTSTANDING_REQ_LIMIT_RANGE                  12:4
#define QUALENG_MIU_TRAFFIC_CTRL_5_OUTSTANDING_REQ_LIMIT_WOFFSET                        0x0
#define QUALENG_MIU_TRAFFIC_CTRL_5_OUTSTANDING_REQ_LIMIT_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_5_OUTSTANDING_REQ_LIMIT_DEFAULT_MASK                   _MK_MASK_CONST(0x1ff)
#define QUALENG_MIU_TRAFFIC_CTRL_5_OUTSTANDING_REQ_LIMIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_5_OUTSTANDING_REQ_LIMIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_5_OUTSTANDING_REQ_LIMIT_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_5_OUTSTANDING_REQ_LIMIT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_5_OUTSTANDING_REQ_LIMIT_INIT_ENUM                      DISABLE
#define QUALENG_MIU_TRAFFIC_CTRL_5_OUTSTANDING_REQ_LIMIT_DISABLE                        _MK_ENUM_CONST(0)

// Register QUALENG_MIU_TRAFFIC_CTRL_6
#define QUALENG_MIU_TRAFFIC_CTRL_6                      _MK_ADDR_CONST(0x38)
#define QUALENG_MIU_TRAFFIC_CTRL_6_SECURE                       0x0
#define QUALENG_MIU_TRAFFIC_CTRL_6_DUAL                         0x0
#define QUALENG_MIU_TRAFFIC_CTRL_6_SCR                  0
#define QUALENG_MIU_TRAFFIC_CTRL_6_WORD_COUNT                   0x1
#define QUALENG_MIU_TRAFFIC_CTRL_6_RESET_VAL                    _MK_MASK_CONST(0x2)
#define QUALENG_MIU_TRAFFIC_CTRL_6_RESET_MASK                   _MK_MASK_CONST(0x1ff3)
#define QUALENG_MIU_TRAFFIC_CTRL_6_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_6_READ_MASK                    _MK_MASK_CONST(0x1ff3)
#define QUALENG_MIU_TRAFFIC_CTRL_6_WRITE_MASK                   _MK_MASK_CONST(0x1ff3)
#define QUALENG_MIU_TRAFFIC_CTRL_6_READ_SHIFT                   _MK_SHIFT_CONST(0)
#define QUALENG_MIU_TRAFFIC_CTRL_6_READ_FIELD                   _MK_FIELD_CONST(0x1, QUALENG_MIU_TRAFFIC_CTRL_6_READ_SHIFT)
#define QUALENG_MIU_TRAFFIC_CTRL_6_READ_RANGE                   0:0
#define QUALENG_MIU_TRAFFIC_CTRL_6_READ_WOFFSET                 0x0
#define QUALENG_MIU_TRAFFIC_CTRL_6_READ_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_6_READ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_6_READ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_6_READ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_6_READ_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_6_READ_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_6_READ_INIT_ENUM                       DISABLE
#define QUALENG_MIU_TRAFFIC_CTRL_6_READ_DISABLE                 _MK_ENUM_CONST(0)
#define QUALENG_MIU_TRAFFIC_CTRL_6_READ_ENABLE                  _MK_ENUM_CONST(1)

#define QUALENG_MIU_TRAFFIC_CTRL_6_WRITE_SHIFT                  _MK_SHIFT_CONST(1)
#define QUALENG_MIU_TRAFFIC_CTRL_6_WRITE_FIELD                  _MK_FIELD_CONST(0x1, QUALENG_MIU_TRAFFIC_CTRL_6_WRITE_SHIFT)
#define QUALENG_MIU_TRAFFIC_CTRL_6_WRITE_RANGE                  1:1
#define QUALENG_MIU_TRAFFIC_CTRL_6_WRITE_WOFFSET                        0x0
#define QUALENG_MIU_TRAFFIC_CTRL_6_WRITE_DEFAULT                        _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_6_WRITE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_6_WRITE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_6_WRITE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_6_WRITE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_6_WRITE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_6_WRITE_INIT_ENUM                      ENABLE
#define QUALENG_MIU_TRAFFIC_CTRL_6_WRITE_DISABLE                        _MK_ENUM_CONST(0)
#define QUALENG_MIU_TRAFFIC_CTRL_6_WRITE_ENABLE                 _MK_ENUM_CONST(1)

#define QUALENG_MIU_TRAFFIC_CTRL_6_OUTSTANDING_REQ_LIMIT_SHIFT                  _MK_SHIFT_CONST(4)
#define QUALENG_MIU_TRAFFIC_CTRL_6_OUTSTANDING_REQ_LIMIT_FIELD                  _MK_FIELD_CONST(0x1ff, QUALENG_MIU_TRAFFIC_CTRL_6_OUTSTANDING_REQ_LIMIT_SHIFT)
#define QUALENG_MIU_TRAFFIC_CTRL_6_OUTSTANDING_REQ_LIMIT_RANGE                  12:4
#define QUALENG_MIU_TRAFFIC_CTRL_6_OUTSTANDING_REQ_LIMIT_WOFFSET                        0x0
#define QUALENG_MIU_TRAFFIC_CTRL_6_OUTSTANDING_REQ_LIMIT_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_6_OUTSTANDING_REQ_LIMIT_DEFAULT_MASK                   _MK_MASK_CONST(0x1ff)
#define QUALENG_MIU_TRAFFIC_CTRL_6_OUTSTANDING_REQ_LIMIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_6_OUTSTANDING_REQ_LIMIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_6_OUTSTANDING_REQ_LIMIT_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_6_OUTSTANDING_REQ_LIMIT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_6_OUTSTANDING_REQ_LIMIT_INIT_ENUM                      DISABLE
#define QUALENG_MIU_TRAFFIC_CTRL_6_OUTSTANDING_REQ_LIMIT_DISABLE                        _MK_ENUM_CONST(0)

// Register QUALENG_MIU_TRAFFIC_CTRL_7
#define QUALENG_MIU_TRAFFIC_CTRL_7                      _MK_ADDR_CONST(0x3c)
#define QUALENG_MIU_TRAFFIC_CTRL_7_SECURE                       0x0
#define QUALENG_MIU_TRAFFIC_CTRL_7_DUAL                         0x0
#define QUALENG_MIU_TRAFFIC_CTRL_7_SCR                  0
#define QUALENG_MIU_TRAFFIC_CTRL_7_WORD_COUNT                   0x1
#define QUALENG_MIU_TRAFFIC_CTRL_7_RESET_VAL                    _MK_MASK_CONST(0x2)
#define QUALENG_MIU_TRAFFIC_CTRL_7_RESET_MASK                   _MK_MASK_CONST(0x1ff3)
#define QUALENG_MIU_TRAFFIC_CTRL_7_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_7_READ_MASK                    _MK_MASK_CONST(0x1ff3)
#define QUALENG_MIU_TRAFFIC_CTRL_7_WRITE_MASK                   _MK_MASK_CONST(0x1ff3)
#define QUALENG_MIU_TRAFFIC_CTRL_7_READ_SHIFT                   _MK_SHIFT_CONST(0)
#define QUALENG_MIU_TRAFFIC_CTRL_7_READ_FIELD                   _MK_FIELD_CONST(0x1, QUALENG_MIU_TRAFFIC_CTRL_7_READ_SHIFT)
#define QUALENG_MIU_TRAFFIC_CTRL_7_READ_RANGE                   0:0
#define QUALENG_MIU_TRAFFIC_CTRL_7_READ_WOFFSET                 0x0
#define QUALENG_MIU_TRAFFIC_CTRL_7_READ_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_7_READ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_7_READ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_7_READ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_7_READ_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_7_READ_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_7_READ_INIT_ENUM                       DISABLE
#define QUALENG_MIU_TRAFFIC_CTRL_7_READ_DISABLE                 _MK_ENUM_CONST(0)
#define QUALENG_MIU_TRAFFIC_CTRL_7_READ_ENABLE                  _MK_ENUM_CONST(1)

#define QUALENG_MIU_TRAFFIC_CTRL_7_WRITE_SHIFT                  _MK_SHIFT_CONST(1)
#define QUALENG_MIU_TRAFFIC_CTRL_7_WRITE_FIELD                  _MK_FIELD_CONST(0x1, QUALENG_MIU_TRAFFIC_CTRL_7_WRITE_SHIFT)
#define QUALENG_MIU_TRAFFIC_CTRL_7_WRITE_RANGE                  1:1
#define QUALENG_MIU_TRAFFIC_CTRL_7_WRITE_WOFFSET                        0x0
#define QUALENG_MIU_TRAFFIC_CTRL_7_WRITE_DEFAULT                        _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_7_WRITE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_7_WRITE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_7_WRITE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_7_WRITE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_7_WRITE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_7_WRITE_INIT_ENUM                      ENABLE
#define QUALENG_MIU_TRAFFIC_CTRL_7_WRITE_DISABLE                        _MK_ENUM_CONST(0)
#define QUALENG_MIU_TRAFFIC_CTRL_7_WRITE_ENABLE                 _MK_ENUM_CONST(1)

#define QUALENG_MIU_TRAFFIC_CTRL_7_OUTSTANDING_REQ_LIMIT_SHIFT                  _MK_SHIFT_CONST(4)
#define QUALENG_MIU_TRAFFIC_CTRL_7_OUTSTANDING_REQ_LIMIT_FIELD                  _MK_FIELD_CONST(0x1ff, QUALENG_MIU_TRAFFIC_CTRL_7_OUTSTANDING_REQ_LIMIT_SHIFT)
#define QUALENG_MIU_TRAFFIC_CTRL_7_OUTSTANDING_REQ_LIMIT_RANGE                  12:4
#define QUALENG_MIU_TRAFFIC_CTRL_7_OUTSTANDING_REQ_LIMIT_WOFFSET                        0x0
#define QUALENG_MIU_TRAFFIC_CTRL_7_OUTSTANDING_REQ_LIMIT_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_7_OUTSTANDING_REQ_LIMIT_DEFAULT_MASK                   _MK_MASK_CONST(0x1ff)
#define QUALENG_MIU_TRAFFIC_CTRL_7_OUTSTANDING_REQ_LIMIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_7_OUTSTANDING_REQ_LIMIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_CTRL_7_OUTSTANDING_REQ_LIMIT_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_7_OUTSTANDING_REQ_LIMIT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_CTRL_7_OUTSTANDING_REQ_LIMIT_INIT_ENUM                      DISABLE
#define QUALENG_MIU_TRAFFIC_CTRL_7_OUTSTANDING_REQ_LIMIT_DISABLE                        _MK_ENUM_CONST(0)

// Register QUALENG_MIU_TRAFFIC_INTERLEAVE_0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_0                        _MK_ADDR_CONST(0x40)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_0_SECURE                         0x0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_0_DUAL                   0x0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_0_SCR                    0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_0_WORD_COUNT                     0x1
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_0_RESET_VAL                      _MK_MASK_CONST(0x20)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_0_RESET_MASK                     _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_0_READ_MASK                      _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_0_WRITE_MASK                     _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_0_ACCESS_PER_TURN_SHIFT                  _MK_SHIFT_CONST(0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_0_ACCESS_PER_TURN_FIELD                  _MK_FIELD_CONST(0xfffff, QUALENG_MIU_TRAFFIC_INTERLEAVE_0_ACCESS_PER_TURN_SHIFT)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_0_ACCESS_PER_TURN_RANGE                  19:0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_0_ACCESS_PER_TURN_WOFFSET                        0x0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_0_ACCESS_PER_TURN_DEFAULT                        _MK_MASK_CONST(0x20)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_0_ACCESS_PER_TURN_DEFAULT_MASK                   _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_0_ACCESS_PER_TURN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_0_ACCESS_PER_TURN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_0_ACCESS_PER_TURN_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_0_ACCESS_PER_TURN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_TRAFFIC_INTERLEAVE
#define QUALENG_MIU_TRAFFIC_INTERLEAVE                  _MK_ADDR_CONST(0x40)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_SECURE                   0x0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_DUAL                     0x0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_SCR                      0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_WORD_COUNT                       0x1
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_RESET_VAL                        _MK_MASK_CONST(0x20)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_RESET_MASK                       _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_READ_MASK                        _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_WRITE_MASK                       _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_ACCESS_PER_TURN_SHIFT                    _MK_SHIFT_CONST(0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_ACCESS_PER_TURN_FIELD                    _MK_FIELD_CONST(0xfffff, QUALENG_MIU_TRAFFIC_INTERLEAVE_ACCESS_PER_TURN_SHIFT)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_ACCESS_PER_TURN_RANGE                    19:0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_ACCESS_PER_TURN_WOFFSET                  0x0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_ACCESS_PER_TURN_DEFAULT                  _MK_MASK_CONST(0x20)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_ACCESS_PER_TURN_DEFAULT_MASK                     _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_ACCESS_PER_TURN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_ACCESS_PER_TURN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_ACCESS_PER_TURN_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_ACCESS_PER_TURN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_TRAFFIC_INTERLEAVE_1
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_1                        _MK_ADDR_CONST(0x44)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_1_SECURE                         0x0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_1_DUAL                   0x0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_1_SCR                    0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_1_WORD_COUNT                     0x1
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_1_RESET_VAL                      _MK_MASK_CONST(0x20)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_1_RESET_MASK                     _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_1_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_1_READ_MASK                      _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_1_WRITE_MASK                     _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_1_ACCESS_PER_TURN_SHIFT                  _MK_SHIFT_CONST(0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_1_ACCESS_PER_TURN_FIELD                  _MK_FIELD_CONST(0xfffff, QUALENG_MIU_TRAFFIC_INTERLEAVE_1_ACCESS_PER_TURN_SHIFT)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_1_ACCESS_PER_TURN_RANGE                  19:0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_1_ACCESS_PER_TURN_WOFFSET                        0x0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_1_ACCESS_PER_TURN_DEFAULT                        _MK_MASK_CONST(0x20)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_1_ACCESS_PER_TURN_DEFAULT_MASK                   _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_1_ACCESS_PER_TURN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_1_ACCESS_PER_TURN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_1_ACCESS_PER_TURN_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_1_ACCESS_PER_TURN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_TRAFFIC_INTERLEAVE_2
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_2                        _MK_ADDR_CONST(0x48)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_2_SECURE                         0x0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_2_DUAL                   0x0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_2_SCR                    0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_2_WORD_COUNT                     0x1
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_2_RESET_VAL                      _MK_MASK_CONST(0x20)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_2_RESET_MASK                     _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_2_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_2_READ_MASK                      _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_2_WRITE_MASK                     _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_2_ACCESS_PER_TURN_SHIFT                  _MK_SHIFT_CONST(0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_2_ACCESS_PER_TURN_FIELD                  _MK_FIELD_CONST(0xfffff, QUALENG_MIU_TRAFFIC_INTERLEAVE_2_ACCESS_PER_TURN_SHIFT)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_2_ACCESS_PER_TURN_RANGE                  19:0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_2_ACCESS_PER_TURN_WOFFSET                        0x0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_2_ACCESS_PER_TURN_DEFAULT                        _MK_MASK_CONST(0x20)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_2_ACCESS_PER_TURN_DEFAULT_MASK                   _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_2_ACCESS_PER_TURN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_2_ACCESS_PER_TURN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_2_ACCESS_PER_TURN_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_2_ACCESS_PER_TURN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_TRAFFIC_INTERLEAVE_3
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_3                        _MK_ADDR_CONST(0x4c)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_3_SECURE                         0x0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_3_DUAL                   0x0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_3_SCR                    0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_3_WORD_COUNT                     0x1
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_3_RESET_VAL                      _MK_MASK_CONST(0x20)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_3_RESET_MASK                     _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_3_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_3_READ_MASK                      _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_3_WRITE_MASK                     _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_3_ACCESS_PER_TURN_SHIFT                  _MK_SHIFT_CONST(0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_3_ACCESS_PER_TURN_FIELD                  _MK_FIELD_CONST(0xfffff, QUALENG_MIU_TRAFFIC_INTERLEAVE_3_ACCESS_PER_TURN_SHIFT)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_3_ACCESS_PER_TURN_RANGE                  19:0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_3_ACCESS_PER_TURN_WOFFSET                        0x0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_3_ACCESS_PER_TURN_DEFAULT                        _MK_MASK_CONST(0x20)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_3_ACCESS_PER_TURN_DEFAULT_MASK                   _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_3_ACCESS_PER_TURN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_3_ACCESS_PER_TURN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_3_ACCESS_PER_TURN_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_3_ACCESS_PER_TURN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_TRAFFIC_INTERLEAVE_4
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_4                        _MK_ADDR_CONST(0x50)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_4_SECURE                         0x0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_4_DUAL                   0x0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_4_SCR                    0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_4_WORD_COUNT                     0x1
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_4_RESET_VAL                      _MK_MASK_CONST(0x20)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_4_RESET_MASK                     _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_4_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_4_READ_MASK                      _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_4_WRITE_MASK                     _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_4_ACCESS_PER_TURN_SHIFT                  _MK_SHIFT_CONST(0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_4_ACCESS_PER_TURN_FIELD                  _MK_FIELD_CONST(0xfffff, QUALENG_MIU_TRAFFIC_INTERLEAVE_4_ACCESS_PER_TURN_SHIFT)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_4_ACCESS_PER_TURN_RANGE                  19:0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_4_ACCESS_PER_TURN_WOFFSET                        0x0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_4_ACCESS_PER_TURN_DEFAULT                        _MK_MASK_CONST(0x20)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_4_ACCESS_PER_TURN_DEFAULT_MASK                   _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_4_ACCESS_PER_TURN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_4_ACCESS_PER_TURN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_4_ACCESS_PER_TURN_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_4_ACCESS_PER_TURN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_TRAFFIC_INTERLEAVE_5
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_5                        _MK_ADDR_CONST(0x54)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_5_SECURE                         0x0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_5_DUAL                   0x0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_5_SCR                    0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_5_WORD_COUNT                     0x1
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_5_RESET_VAL                      _MK_MASK_CONST(0x20)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_5_RESET_MASK                     _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_5_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_5_READ_MASK                      _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_5_WRITE_MASK                     _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_5_ACCESS_PER_TURN_SHIFT                  _MK_SHIFT_CONST(0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_5_ACCESS_PER_TURN_FIELD                  _MK_FIELD_CONST(0xfffff, QUALENG_MIU_TRAFFIC_INTERLEAVE_5_ACCESS_PER_TURN_SHIFT)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_5_ACCESS_PER_TURN_RANGE                  19:0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_5_ACCESS_PER_TURN_WOFFSET                        0x0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_5_ACCESS_PER_TURN_DEFAULT                        _MK_MASK_CONST(0x20)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_5_ACCESS_PER_TURN_DEFAULT_MASK                   _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_5_ACCESS_PER_TURN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_5_ACCESS_PER_TURN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_5_ACCESS_PER_TURN_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_5_ACCESS_PER_TURN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_TRAFFIC_INTERLEAVE_6
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_6                        _MK_ADDR_CONST(0x58)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_6_SECURE                         0x0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_6_DUAL                   0x0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_6_SCR                    0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_6_WORD_COUNT                     0x1
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_6_RESET_VAL                      _MK_MASK_CONST(0x20)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_6_RESET_MASK                     _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_6_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_6_READ_MASK                      _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_6_WRITE_MASK                     _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_6_ACCESS_PER_TURN_SHIFT                  _MK_SHIFT_CONST(0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_6_ACCESS_PER_TURN_FIELD                  _MK_FIELD_CONST(0xfffff, QUALENG_MIU_TRAFFIC_INTERLEAVE_6_ACCESS_PER_TURN_SHIFT)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_6_ACCESS_PER_TURN_RANGE                  19:0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_6_ACCESS_PER_TURN_WOFFSET                        0x0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_6_ACCESS_PER_TURN_DEFAULT                        _MK_MASK_CONST(0x20)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_6_ACCESS_PER_TURN_DEFAULT_MASK                   _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_6_ACCESS_PER_TURN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_6_ACCESS_PER_TURN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_6_ACCESS_PER_TURN_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_6_ACCESS_PER_TURN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_TRAFFIC_INTERLEAVE_7
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_7                        _MK_ADDR_CONST(0x5c)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_7_SECURE                         0x0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_7_DUAL                   0x0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_7_SCR                    0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_7_WORD_COUNT                     0x1
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_7_RESET_VAL                      _MK_MASK_CONST(0x20)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_7_RESET_MASK                     _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_7_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_7_READ_MASK                      _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_7_WRITE_MASK                     _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_7_ACCESS_PER_TURN_SHIFT                  _MK_SHIFT_CONST(0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_7_ACCESS_PER_TURN_FIELD                  _MK_FIELD_CONST(0xfffff, QUALENG_MIU_TRAFFIC_INTERLEAVE_7_ACCESS_PER_TURN_SHIFT)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_7_ACCESS_PER_TURN_RANGE                  19:0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_7_ACCESS_PER_TURN_WOFFSET                        0x0
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_7_ACCESS_PER_TURN_DEFAULT                        _MK_MASK_CONST(0x20)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_7_ACCESS_PER_TURN_DEFAULT_MASK                   _MK_MASK_CONST(0xfffff)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_7_ACCESS_PER_TURN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_7_ACCESS_PER_TURN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_7_ACCESS_PER_TURN_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_INTERLEAVE_7_ACCESS_PER_TURN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_TRAFFIC_TURNS_LOW_0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_0                 _MK_ADDR_CONST(0x60)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_0_SECURE                  0x0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_0_DUAL                    0x0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_0_SCR                     0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_0_WORD_COUNT                      0x1
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_0_NUM_TURNS_LOW_SHIFT                     _MK_SHIFT_CONST(0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_0_NUM_TURNS_LOW_FIELD                     _MK_FIELD_CONST(0xffffffff, QUALENG_MIU_TRAFFIC_TURNS_LOW_0_NUM_TURNS_LOW_SHIFT)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_0_NUM_TURNS_LOW_RANGE                     31:0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_0_NUM_TURNS_LOW_WOFFSET                   0x0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_0_NUM_TURNS_LOW_DEFAULT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_0_NUM_TURNS_LOW_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_0_NUM_TURNS_LOW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_0_NUM_TURNS_LOW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_0_NUM_TURNS_LOW_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_0_NUM_TURNS_LOW_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_TRAFFIC_TURNS_LOW
#define QUALENG_MIU_TRAFFIC_TURNS_LOW                   _MK_ADDR_CONST(0x60)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_SECURE                    0x0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_DUAL                      0x0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_SCR                       0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_WORD_COUNT                        0x1
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_RESET_VAL                         _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_NUM_TURNS_LOW_SHIFT                       _MK_SHIFT_CONST(0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_NUM_TURNS_LOW_FIELD                       _MK_FIELD_CONST(0xffffffff, QUALENG_MIU_TRAFFIC_TURNS_LOW_NUM_TURNS_LOW_SHIFT)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_NUM_TURNS_LOW_RANGE                       31:0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_NUM_TURNS_LOW_WOFFSET                     0x0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_NUM_TURNS_LOW_DEFAULT                     _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_NUM_TURNS_LOW_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_NUM_TURNS_LOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_NUM_TURNS_LOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_NUM_TURNS_LOW_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_NUM_TURNS_LOW_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_TRAFFIC_TURNS_LOW_1
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_1                 _MK_ADDR_CONST(0x64)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_1_SECURE                  0x0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_1_DUAL                    0x0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_1_SCR                     0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_1_WORD_COUNT                      0x1
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_1_RESET_VAL                       _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_1_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_1_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_1_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_1_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_1_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_1_NUM_TURNS_LOW_SHIFT                     _MK_SHIFT_CONST(0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_1_NUM_TURNS_LOW_FIELD                     _MK_FIELD_CONST(0xffffffff, QUALENG_MIU_TRAFFIC_TURNS_LOW_1_NUM_TURNS_LOW_SHIFT)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_1_NUM_TURNS_LOW_RANGE                     31:0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_1_NUM_TURNS_LOW_WOFFSET                   0x0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_1_NUM_TURNS_LOW_DEFAULT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_1_NUM_TURNS_LOW_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_1_NUM_TURNS_LOW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_1_NUM_TURNS_LOW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_1_NUM_TURNS_LOW_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_1_NUM_TURNS_LOW_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_TRAFFIC_TURNS_LOW_2
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_2                 _MK_ADDR_CONST(0x68)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_2_SECURE                  0x0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_2_DUAL                    0x0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_2_SCR                     0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_2_WORD_COUNT                      0x1
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_2_RESET_VAL                       _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_2_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_2_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_2_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_2_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_2_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_2_NUM_TURNS_LOW_SHIFT                     _MK_SHIFT_CONST(0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_2_NUM_TURNS_LOW_FIELD                     _MK_FIELD_CONST(0xffffffff, QUALENG_MIU_TRAFFIC_TURNS_LOW_2_NUM_TURNS_LOW_SHIFT)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_2_NUM_TURNS_LOW_RANGE                     31:0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_2_NUM_TURNS_LOW_WOFFSET                   0x0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_2_NUM_TURNS_LOW_DEFAULT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_2_NUM_TURNS_LOW_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_2_NUM_TURNS_LOW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_2_NUM_TURNS_LOW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_2_NUM_TURNS_LOW_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_2_NUM_TURNS_LOW_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_TRAFFIC_TURNS_LOW_3
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_3                 _MK_ADDR_CONST(0x6c)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_3_SECURE                  0x0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_3_DUAL                    0x0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_3_SCR                     0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_3_WORD_COUNT                      0x1
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_3_RESET_VAL                       _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_3_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_3_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_3_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_3_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_3_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_3_NUM_TURNS_LOW_SHIFT                     _MK_SHIFT_CONST(0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_3_NUM_TURNS_LOW_FIELD                     _MK_FIELD_CONST(0xffffffff, QUALENG_MIU_TRAFFIC_TURNS_LOW_3_NUM_TURNS_LOW_SHIFT)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_3_NUM_TURNS_LOW_RANGE                     31:0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_3_NUM_TURNS_LOW_WOFFSET                   0x0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_3_NUM_TURNS_LOW_DEFAULT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_3_NUM_TURNS_LOW_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_3_NUM_TURNS_LOW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_3_NUM_TURNS_LOW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_3_NUM_TURNS_LOW_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_3_NUM_TURNS_LOW_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_TRAFFIC_TURNS_LOW_4
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_4                 _MK_ADDR_CONST(0x70)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_4_SECURE                  0x0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_4_DUAL                    0x0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_4_SCR                     0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_4_WORD_COUNT                      0x1
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_4_RESET_VAL                       _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_4_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_4_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_4_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_4_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_4_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_4_NUM_TURNS_LOW_SHIFT                     _MK_SHIFT_CONST(0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_4_NUM_TURNS_LOW_FIELD                     _MK_FIELD_CONST(0xffffffff, QUALENG_MIU_TRAFFIC_TURNS_LOW_4_NUM_TURNS_LOW_SHIFT)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_4_NUM_TURNS_LOW_RANGE                     31:0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_4_NUM_TURNS_LOW_WOFFSET                   0x0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_4_NUM_TURNS_LOW_DEFAULT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_4_NUM_TURNS_LOW_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_4_NUM_TURNS_LOW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_4_NUM_TURNS_LOW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_4_NUM_TURNS_LOW_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_4_NUM_TURNS_LOW_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_TRAFFIC_TURNS_LOW_5
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_5                 _MK_ADDR_CONST(0x74)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_5_SECURE                  0x0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_5_DUAL                    0x0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_5_SCR                     0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_5_WORD_COUNT                      0x1
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_5_RESET_VAL                       _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_5_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_5_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_5_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_5_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_5_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_5_NUM_TURNS_LOW_SHIFT                     _MK_SHIFT_CONST(0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_5_NUM_TURNS_LOW_FIELD                     _MK_FIELD_CONST(0xffffffff, QUALENG_MIU_TRAFFIC_TURNS_LOW_5_NUM_TURNS_LOW_SHIFT)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_5_NUM_TURNS_LOW_RANGE                     31:0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_5_NUM_TURNS_LOW_WOFFSET                   0x0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_5_NUM_TURNS_LOW_DEFAULT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_5_NUM_TURNS_LOW_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_5_NUM_TURNS_LOW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_5_NUM_TURNS_LOW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_5_NUM_TURNS_LOW_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_5_NUM_TURNS_LOW_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_TRAFFIC_TURNS_LOW_6
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_6                 _MK_ADDR_CONST(0x78)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_6_SECURE                  0x0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_6_DUAL                    0x0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_6_SCR                     0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_6_WORD_COUNT                      0x1
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_6_RESET_VAL                       _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_6_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_6_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_6_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_6_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_6_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_6_NUM_TURNS_LOW_SHIFT                     _MK_SHIFT_CONST(0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_6_NUM_TURNS_LOW_FIELD                     _MK_FIELD_CONST(0xffffffff, QUALENG_MIU_TRAFFIC_TURNS_LOW_6_NUM_TURNS_LOW_SHIFT)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_6_NUM_TURNS_LOW_RANGE                     31:0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_6_NUM_TURNS_LOW_WOFFSET                   0x0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_6_NUM_TURNS_LOW_DEFAULT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_6_NUM_TURNS_LOW_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_6_NUM_TURNS_LOW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_6_NUM_TURNS_LOW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_6_NUM_TURNS_LOW_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_6_NUM_TURNS_LOW_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_TRAFFIC_TURNS_LOW_7
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_7                 _MK_ADDR_CONST(0x7c)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_7_SECURE                  0x0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_7_DUAL                    0x0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_7_SCR                     0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_7_WORD_COUNT                      0x1
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_7_RESET_VAL                       _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_7_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_7_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_7_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_7_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_7_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_7_NUM_TURNS_LOW_SHIFT                     _MK_SHIFT_CONST(0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_7_NUM_TURNS_LOW_FIELD                     _MK_FIELD_CONST(0xffffffff, QUALENG_MIU_TRAFFIC_TURNS_LOW_7_NUM_TURNS_LOW_SHIFT)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_7_NUM_TURNS_LOW_RANGE                     31:0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_7_NUM_TURNS_LOW_WOFFSET                   0x0
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_7_NUM_TURNS_LOW_DEFAULT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_7_NUM_TURNS_LOW_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_7_NUM_TURNS_LOW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_7_NUM_TURNS_LOW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_7_NUM_TURNS_LOW_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_TRAFFIC_TURNS_LOW_7_NUM_TURNS_LOW_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_ADDR_CFG_0
#define QUALENG_MIU_ADDR_CFG_0                  _MK_ADDR_CONST(0x120)
#define QUALENG_MIU_ADDR_CFG_0_SECURE                   0x0
#define QUALENG_MIU_ADDR_CFG_0_DUAL                     0x0
#define QUALENG_MIU_ADDR_CFG_0_SCR                      0
#define QUALENG_MIU_ADDR_CFG_0_WORD_COUNT                       0x1
#define QUALENG_MIU_ADDR_CFG_0_RESET_VAL                        _MK_MASK_CONST(0xffff0020)
#define QUALENG_MIU_ADDR_CFG_0_RESET_MASK                       _MK_MASK_CONST(0xffff3fff)
#define QUALENG_MIU_ADDR_CFG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_0_READ_MASK                        _MK_MASK_CONST(0xffff3fff)
#define QUALENG_MIU_ADDR_CFG_0_WRITE_MASK                       _MK_MASK_CONST(0xffff3fff)
#define QUALENG_MIU_ADDR_CFG_0_SO_DEV_SHIFT                     _MK_SHIFT_CONST(0)
#define QUALENG_MIU_ADDR_CFG_0_SO_DEV_FIELD                     _MK_FIELD_CONST(0x1, QUALENG_MIU_ADDR_CFG_0_SO_DEV_SHIFT)
#define QUALENG_MIU_ADDR_CFG_0_SO_DEV_RANGE                     0:0
#define QUALENG_MIU_ADDR_CFG_0_SO_DEV_WOFFSET                   0x0
#define QUALENG_MIU_ADDR_CFG_0_SO_DEV_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_0_SO_DEV_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_0_SO_DEV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_0_SO_DEV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_0_SO_DEV_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_0_SO_DEV_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_0_SO_DEV_INIT_ENUM                 NORMAL
#define QUALENG_MIU_ADDR_CFG_0_SO_DEV_NORMAL                    _MK_ENUM_CONST(0)
#define QUALENG_MIU_ADDR_CFG_0_SO_DEV_SO_DEV                    _MK_ENUM_CONST(1)

#define QUALENG_MIU_ADDR_CFG_0_RANDOM_ACCESS_SHIFT                      _MK_SHIFT_CONST(1)
#define QUALENG_MIU_ADDR_CFG_0_RANDOM_ACCESS_FIELD                      _MK_FIELD_CONST(0x1, QUALENG_MIU_ADDR_CFG_0_RANDOM_ACCESS_SHIFT)
#define QUALENG_MIU_ADDR_CFG_0_RANDOM_ACCESS_RANGE                      1:1
#define QUALENG_MIU_ADDR_CFG_0_RANDOM_ACCESS_WOFFSET                    0x0
#define QUALENG_MIU_ADDR_CFG_0_RANDOM_ACCESS_DEFAULT                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_0_RANDOM_ACCESS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_0_RANDOM_ACCESS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_0_RANDOM_ACCESS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_0_RANDOM_ACCESS_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_0_RANDOM_ACCESS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_0_RANDOM_ACCESS_INIT_ENUM                  DISABLE
#define QUALENG_MIU_ADDR_CFG_0_RANDOM_ACCESS_DISABLE                    _MK_ENUM_CONST(0)
#define QUALENG_MIU_ADDR_CFG_0_RANDOM_ACCESS_ENABLE                     _MK_ENUM_CONST(1)

#define QUALENG_MIU_ADDR_CFG_0_ACCESS_PER_ACTIVATE_SHIFT                        _MK_SHIFT_CONST(2)
#define QUALENG_MIU_ADDR_CFG_0_ACCESS_PER_ACTIVATE_FIELD                        _MK_FIELD_CONST(0x1f, QUALENG_MIU_ADDR_CFG_0_ACCESS_PER_ACTIVATE_SHIFT)
#define QUALENG_MIU_ADDR_CFG_0_ACCESS_PER_ACTIVATE_RANGE                        6:2
#define QUALENG_MIU_ADDR_CFG_0_ACCESS_PER_ACTIVATE_WOFFSET                      0x0
#define QUALENG_MIU_ADDR_CFG_0_ACCESS_PER_ACTIVATE_DEFAULT                      _MK_MASK_CONST(0x8)
#define QUALENG_MIU_ADDR_CFG_0_ACCESS_PER_ACTIVATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define QUALENG_MIU_ADDR_CFG_0_ACCESS_PER_ACTIVATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_0_ACCESS_PER_ACTIVATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_0_ACCESS_PER_ACTIVATE_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_0_ACCESS_PER_ACTIVATE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_0_ACCESS_PER_ACTIVATE_INT_512B                     _MK_ENUM_CONST(8)
#define QUALENG_MIU_ADDR_CFG_0_ACCESS_PER_ACTIVATE_INT_1KB                      _MK_ENUM_CONST(16)

#define QUALENG_MIU_ADDR_CFG_0_SWIZZLE_INDEX_LOWER_SHIFT                        _MK_SHIFT_CONST(7)
#define QUALENG_MIU_ADDR_CFG_0_SWIZZLE_INDEX_LOWER_FIELD                        _MK_FIELD_CONST(0x3, QUALENG_MIU_ADDR_CFG_0_SWIZZLE_INDEX_LOWER_SHIFT)
#define QUALENG_MIU_ADDR_CFG_0_SWIZZLE_INDEX_LOWER_RANGE                        8:7
#define QUALENG_MIU_ADDR_CFG_0_SWIZZLE_INDEX_LOWER_WOFFSET                      0x0
#define QUALENG_MIU_ADDR_CFG_0_SWIZZLE_INDEX_LOWER_DEFAULT                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_0_SWIZZLE_INDEX_LOWER_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define QUALENG_MIU_ADDR_CFG_0_SWIZZLE_INDEX_LOWER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_0_SWIZZLE_INDEX_LOWER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_0_SWIZZLE_INDEX_LOWER_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_0_SWIZZLE_INDEX_LOWER_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_0_SWIZZLE_INDEX_LOWER_INIT_ENUM                    DISABLE
#define QUALENG_MIU_ADDR_CFG_0_SWIZZLE_INDEX_LOWER_DISABLE                      _MK_ENUM_CONST(0)

#define QUALENG_MIU_ADDR_CFG_0_SWIZZLE_INDEX_UPPER_SHIFT                        _MK_SHIFT_CONST(9)
#define QUALENG_MIU_ADDR_CFG_0_SWIZZLE_INDEX_UPPER_FIELD                        _MK_FIELD_CONST(0x1f, QUALENG_MIU_ADDR_CFG_0_SWIZZLE_INDEX_UPPER_SHIFT)
#define QUALENG_MIU_ADDR_CFG_0_SWIZZLE_INDEX_UPPER_RANGE                        13:9
#define QUALENG_MIU_ADDR_CFG_0_SWIZZLE_INDEX_UPPER_WOFFSET                      0x0
#define QUALENG_MIU_ADDR_CFG_0_SWIZZLE_INDEX_UPPER_DEFAULT                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_0_SWIZZLE_INDEX_UPPER_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define QUALENG_MIU_ADDR_CFG_0_SWIZZLE_INDEX_UPPER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_0_SWIZZLE_INDEX_UPPER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_0_SWIZZLE_INDEX_UPPER_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_0_SWIZZLE_INDEX_UPPER_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_0_SWIZZLE_INDEX_UPPER_INIT_ENUM                    DISABLE
#define QUALENG_MIU_ADDR_CFG_0_SWIZZLE_INDEX_UPPER_DISABLE                      _MK_ENUM_CONST(0)

#define QUALENG_MIU_ADDR_CFG_0_LOGICAL_CHANNEL_ENABLE_SHIFT                     _MK_SHIFT_CONST(16)
#define QUALENG_MIU_ADDR_CFG_0_LOGICAL_CHANNEL_ENABLE_FIELD                     _MK_FIELD_CONST(0xffff, QUALENG_MIU_ADDR_CFG_0_LOGICAL_CHANNEL_ENABLE_SHIFT)
#define QUALENG_MIU_ADDR_CFG_0_LOGICAL_CHANNEL_ENABLE_RANGE                     31:16
#define QUALENG_MIU_ADDR_CFG_0_LOGICAL_CHANNEL_ENABLE_WOFFSET                   0x0
#define QUALENG_MIU_ADDR_CFG_0_LOGICAL_CHANNEL_ENABLE_DEFAULT                   _MK_MASK_CONST(0xffff)
#define QUALENG_MIU_ADDR_CFG_0_LOGICAL_CHANNEL_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define QUALENG_MIU_ADDR_CFG_0_LOGICAL_CHANNEL_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_0_LOGICAL_CHANNEL_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_0_LOGICAL_CHANNEL_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_0_LOGICAL_CHANNEL_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_ADDR_CFG
#define QUALENG_MIU_ADDR_CFG                    _MK_ADDR_CONST(0x120)
#define QUALENG_MIU_ADDR_CFG_SECURE                     0x0
#define QUALENG_MIU_ADDR_CFG_DUAL                       0x0
#define QUALENG_MIU_ADDR_CFG_SCR                        0
#define QUALENG_MIU_ADDR_CFG_WORD_COUNT                         0x1
#define QUALENG_MIU_ADDR_CFG_RESET_VAL                  _MK_MASK_CONST(0xffff0020)
#define QUALENG_MIU_ADDR_CFG_RESET_MASK                         _MK_MASK_CONST(0xffff3fff)
#define QUALENG_MIU_ADDR_CFG_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_READ_MASK                  _MK_MASK_CONST(0xffff3fff)
#define QUALENG_MIU_ADDR_CFG_WRITE_MASK                         _MK_MASK_CONST(0xffff3fff)
#define QUALENG_MIU_ADDR_CFG_SO_DEV_SHIFT                       _MK_SHIFT_CONST(0)
#define QUALENG_MIU_ADDR_CFG_SO_DEV_FIELD                       _MK_FIELD_CONST(0x1, QUALENG_MIU_ADDR_CFG_SO_DEV_SHIFT)
#define QUALENG_MIU_ADDR_CFG_SO_DEV_RANGE                       0:0
#define QUALENG_MIU_ADDR_CFG_SO_DEV_WOFFSET                     0x0
#define QUALENG_MIU_ADDR_CFG_SO_DEV_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_SO_DEV_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_SO_DEV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_SO_DEV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_SO_DEV_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_SO_DEV_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_SO_DEV_INIT_ENUM                   NORMAL
#define QUALENG_MIU_ADDR_CFG_SO_DEV_NORMAL                      _MK_ENUM_CONST(0)
#define QUALENG_MIU_ADDR_CFG_SO_DEV_SO_DEV                      _MK_ENUM_CONST(1)

#define QUALENG_MIU_ADDR_CFG_RANDOM_ACCESS_SHIFT                        _MK_SHIFT_CONST(1)
#define QUALENG_MIU_ADDR_CFG_RANDOM_ACCESS_FIELD                        _MK_FIELD_CONST(0x1, QUALENG_MIU_ADDR_CFG_RANDOM_ACCESS_SHIFT)
#define QUALENG_MIU_ADDR_CFG_RANDOM_ACCESS_RANGE                        1:1
#define QUALENG_MIU_ADDR_CFG_RANDOM_ACCESS_WOFFSET                      0x0
#define QUALENG_MIU_ADDR_CFG_RANDOM_ACCESS_DEFAULT                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_RANDOM_ACCESS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_RANDOM_ACCESS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_RANDOM_ACCESS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_RANDOM_ACCESS_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_RANDOM_ACCESS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_RANDOM_ACCESS_INIT_ENUM                    DISABLE
#define QUALENG_MIU_ADDR_CFG_RANDOM_ACCESS_DISABLE                      _MK_ENUM_CONST(0)
#define QUALENG_MIU_ADDR_CFG_RANDOM_ACCESS_ENABLE                       _MK_ENUM_CONST(1)

#define QUALENG_MIU_ADDR_CFG_ACCESS_PER_ACTIVATE_SHIFT                  _MK_SHIFT_CONST(2)
#define QUALENG_MIU_ADDR_CFG_ACCESS_PER_ACTIVATE_FIELD                  _MK_FIELD_CONST(0x1f, QUALENG_MIU_ADDR_CFG_ACCESS_PER_ACTIVATE_SHIFT)
#define QUALENG_MIU_ADDR_CFG_ACCESS_PER_ACTIVATE_RANGE                  6:2
#define QUALENG_MIU_ADDR_CFG_ACCESS_PER_ACTIVATE_WOFFSET                        0x0
#define QUALENG_MIU_ADDR_CFG_ACCESS_PER_ACTIVATE_DEFAULT                        _MK_MASK_CONST(0x8)
#define QUALENG_MIU_ADDR_CFG_ACCESS_PER_ACTIVATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define QUALENG_MIU_ADDR_CFG_ACCESS_PER_ACTIVATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_ACCESS_PER_ACTIVATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_ACCESS_PER_ACTIVATE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_ACCESS_PER_ACTIVATE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_ACCESS_PER_ACTIVATE_INT_512B                       _MK_ENUM_CONST(8)
#define QUALENG_MIU_ADDR_CFG_ACCESS_PER_ACTIVATE_INT_1KB                        _MK_ENUM_CONST(16)

#define QUALENG_MIU_ADDR_CFG_SWIZZLE_INDEX_LOWER_SHIFT                  _MK_SHIFT_CONST(7)
#define QUALENG_MIU_ADDR_CFG_SWIZZLE_INDEX_LOWER_FIELD                  _MK_FIELD_CONST(0x3, QUALENG_MIU_ADDR_CFG_SWIZZLE_INDEX_LOWER_SHIFT)
#define QUALENG_MIU_ADDR_CFG_SWIZZLE_INDEX_LOWER_RANGE                  8:7
#define QUALENG_MIU_ADDR_CFG_SWIZZLE_INDEX_LOWER_WOFFSET                        0x0
#define QUALENG_MIU_ADDR_CFG_SWIZZLE_INDEX_LOWER_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_SWIZZLE_INDEX_LOWER_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define QUALENG_MIU_ADDR_CFG_SWIZZLE_INDEX_LOWER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_SWIZZLE_INDEX_LOWER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_SWIZZLE_INDEX_LOWER_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_SWIZZLE_INDEX_LOWER_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_SWIZZLE_INDEX_LOWER_INIT_ENUM                      DISABLE
#define QUALENG_MIU_ADDR_CFG_SWIZZLE_INDEX_LOWER_DISABLE                        _MK_ENUM_CONST(0)

#define QUALENG_MIU_ADDR_CFG_SWIZZLE_INDEX_UPPER_SHIFT                  _MK_SHIFT_CONST(9)
#define QUALENG_MIU_ADDR_CFG_SWIZZLE_INDEX_UPPER_FIELD                  _MK_FIELD_CONST(0x1f, QUALENG_MIU_ADDR_CFG_SWIZZLE_INDEX_UPPER_SHIFT)
#define QUALENG_MIU_ADDR_CFG_SWIZZLE_INDEX_UPPER_RANGE                  13:9
#define QUALENG_MIU_ADDR_CFG_SWIZZLE_INDEX_UPPER_WOFFSET                        0x0
#define QUALENG_MIU_ADDR_CFG_SWIZZLE_INDEX_UPPER_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_SWIZZLE_INDEX_UPPER_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define QUALENG_MIU_ADDR_CFG_SWIZZLE_INDEX_UPPER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_SWIZZLE_INDEX_UPPER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_SWIZZLE_INDEX_UPPER_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_SWIZZLE_INDEX_UPPER_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_SWIZZLE_INDEX_UPPER_INIT_ENUM                      DISABLE
#define QUALENG_MIU_ADDR_CFG_SWIZZLE_INDEX_UPPER_DISABLE                        _MK_ENUM_CONST(0)

#define QUALENG_MIU_ADDR_CFG_LOGICAL_CHANNEL_ENABLE_SHIFT                       _MK_SHIFT_CONST(16)
#define QUALENG_MIU_ADDR_CFG_LOGICAL_CHANNEL_ENABLE_FIELD                       _MK_FIELD_CONST(0xffff, QUALENG_MIU_ADDR_CFG_LOGICAL_CHANNEL_ENABLE_SHIFT)
#define QUALENG_MIU_ADDR_CFG_LOGICAL_CHANNEL_ENABLE_RANGE                       31:16
#define QUALENG_MIU_ADDR_CFG_LOGICAL_CHANNEL_ENABLE_WOFFSET                     0x0
#define QUALENG_MIU_ADDR_CFG_LOGICAL_CHANNEL_ENABLE_DEFAULT                     _MK_MASK_CONST(0xffff)
#define QUALENG_MIU_ADDR_CFG_LOGICAL_CHANNEL_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
#define QUALENG_MIU_ADDR_CFG_LOGICAL_CHANNEL_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_LOGICAL_CHANNEL_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_LOGICAL_CHANNEL_ENABLE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_LOGICAL_CHANNEL_ENABLE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_ADDR_CFG_1
#define QUALENG_MIU_ADDR_CFG_1                  _MK_ADDR_CONST(0x124)
#define QUALENG_MIU_ADDR_CFG_1_SECURE                   0x0
#define QUALENG_MIU_ADDR_CFG_1_DUAL                     0x0
#define QUALENG_MIU_ADDR_CFG_1_SCR                      0
#define QUALENG_MIU_ADDR_CFG_1_WORD_COUNT                       0x1
#define QUALENG_MIU_ADDR_CFG_1_RESET_VAL                        _MK_MASK_CONST(0xffff0020)
#define QUALENG_MIU_ADDR_CFG_1_RESET_MASK                       _MK_MASK_CONST(0xffff3fff)
#define QUALENG_MIU_ADDR_CFG_1_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_1_READ_MASK                        _MK_MASK_CONST(0xffff3fff)
#define QUALENG_MIU_ADDR_CFG_1_WRITE_MASK                       _MK_MASK_CONST(0xffff3fff)
#define QUALENG_MIU_ADDR_CFG_1_SO_DEV_SHIFT                     _MK_SHIFT_CONST(0)
#define QUALENG_MIU_ADDR_CFG_1_SO_DEV_FIELD                     _MK_FIELD_CONST(0x1, QUALENG_MIU_ADDR_CFG_1_SO_DEV_SHIFT)
#define QUALENG_MIU_ADDR_CFG_1_SO_DEV_RANGE                     0:0
#define QUALENG_MIU_ADDR_CFG_1_SO_DEV_WOFFSET                   0x0
#define QUALENG_MIU_ADDR_CFG_1_SO_DEV_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_1_SO_DEV_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_1_SO_DEV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_1_SO_DEV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_1_SO_DEV_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_1_SO_DEV_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_1_SO_DEV_INIT_ENUM                 NORMAL
#define QUALENG_MIU_ADDR_CFG_1_SO_DEV_NORMAL                    _MK_ENUM_CONST(0)
#define QUALENG_MIU_ADDR_CFG_1_SO_DEV_SO_DEV                    _MK_ENUM_CONST(1)

#define QUALENG_MIU_ADDR_CFG_1_RANDOM_ACCESS_SHIFT                      _MK_SHIFT_CONST(1)
#define QUALENG_MIU_ADDR_CFG_1_RANDOM_ACCESS_FIELD                      _MK_FIELD_CONST(0x1, QUALENG_MIU_ADDR_CFG_1_RANDOM_ACCESS_SHIFT)
#define QUALENG_MIU_ADDR_CFG_1_RANDOM_ACCESS_RANGE                      1:1
#define QUALENG_MIU_ADDR_CFG_1_RANDOM_ACCESS_WOFFSET                    0x0
#define QUALENG_MIU_ADDR_CFG_1_RANDOM_ACCESS_DEFAULT                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_1_RANDOM_ACCESS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_1_RANDOM_ACCESS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_1_RANDOM_ACCESS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_1_RANDOM_ACCESS_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_1_RANDOM_ACCESS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_1_RANDOM_ACCESS_INIT_ENUM                  DISABLE
#define QUALENG_MIU_ADDR_CFG_1_RANDOM_ACCESS_DISABLE                    _MK_ENUM_CONST(0)
#define QUALENG_MIU_ADDR_CFG_1_RANDOM_ACCESS_ENABLE                     _MK_ENUM_CONST(1)

#define QUALENG_MIU_ADDR_CFG_1_ACCESS_PER_ACTIVATE_SHIFT                        _MK_SHIFT_CONST(2)
#define QUALENG_MIU_ADDR_CFG_1_ACCESS_PER_ACTIVATE_FIELD                        _MK_FIELD_CONST(0x1f, QUALENG_MIU_ADDR_CFG_1_ACCESS_PER_ACTIVATE_SHIFT)
#define QUALENG_MIU_ADDR_CFG_1_ACCESS_PER_ACTIVATE_RANGE                        6:2
#define QUALENG_MIU_ADDR_CFG_1_ACCESS_PER_ACTIVATE_WOFFSET                      0x0
#define QUALENG_MIU_ADDR_CFG_1_ACCESS_PER_ACTIVATE_DEFAULT                      _MK_MASK_CONST(0x8)
#define QUALENG_MIU_ADDR_CFG_1_ACCESS_PER_ACTIVATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define QUALENG_MIU_ADDR_CFG_1_ACCESS_PER_ACTIVATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_1_ACCESS_PER_ACTIVATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_1_ACCESS_PER_ACTIVATE_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_1_ACCESS_PER_ACTIVATE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_1_ACCESS_PER_ACTIVATE_INT_512B                     _MK_ENUM_CONST(8)
#define QUALENG_MIU_ADDR_CFG_1_ACCESS_PER_ACTIVATE_INT_1KB                      _MK_ENUM_CONST(16)

#define QUALENG_MIU_ADDR_CFG_1_SWIZZLE_INDEX_LOWER_SHIFT                        _MK_SHIFT_CONST(7)
#define QUALENG_MIU_ADDR_CFG_1_SWIZZLE_INDEX_LOWER_FIELD                        _MK_FIELD_CONST(0x3, QUALENG_MIU_ADDR_CFG_1_SWIZZLE_INDEX_LOWER_SHIFT)
#define QUALENG_MIU_ADDR_CFG_1_SWIZZLE_INDEX_LOWER_RANGE                        8:7
#define QUALENG_MIU_ADDR_CFG_1_SWIZZLE_INDEX_LOWER_WOFFSET                      0x0
#define QUALENG_MIU_ADDR_CFG_1_SWIZZLE_INDEX_LOWER_DEFAULT                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_1_SWIZZLE_INDEX_LOWER_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define QUALENG_MIU_ADDR_CFG_1_SWIZZLE_INDEX_LOWER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_1_SWIZZLE_INDEX_LOWER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_1_SWIZZLE_INDEX_LOWER_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_1_SWIZZLE_INDEX_LOWER_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_1_SWIZZLE_INDEX_LOWER_INIT_ENUM                    DISABLE
#define QUALENG_MIU_ADDR_CFG_1_SWIZZLE_INDEX_LOWER_DISABLE                      _MK_ENUM_CONST(0)

#define QUALENG_MIU_ADDR_CFG_1_SWIZZLE_INDEX_UPPER_SHIFT                        _MK_SHIFT_CONST(9)
#define QUALENG_MIU_ADDR_CFG_1_SWIZZLE_INDEX_UPPER_FIELD                        _MK_FIELD_CONST(0x1f, QUALENG_MIU_ADDR_CFG_1_SWIZZLE_INDEX_UPPER_SHIFT)
#define QUALENG_MIU_ADDR_CFG_1_SWIZZLE_INDEX_UPPER_RANGE                        13:9
#define QUALENG_MIU_ADDR_CFG_1_SWIZZLE_INDEX_UPPER_WOFFSET                      0x0
#define QUALENG_MIU_ADDR_CFG_1_SWIZZLE_INDEX_UPPER_DEFAULT                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_1_SWIZZLE_INDEX_UPPER_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define QUALENG_MIU_ADDR_CFG_1_SWIZZLE_INDEX_UPPER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_1_SWIZZLE_INDEX_UPPER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_1_SWIZZLE_INDEX_UPPER_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_1_SWIZZLE_INDEX_UPPER_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_1_SWIZZLE_INDEX_UPPER_INIT_ENUM                    DISABLE
#define QUALENG_MIU_ADDR_CFG_1_SWIZZLE_INDEX_UPPER_DISABLE                      _MK_ENUM_CONST(0)

#define QUALENG_MIU_ADDR_CFG_1_LOGICAL_CHANNEL_ENABLE_SHIFT                     _MK_SHIFT_CONST(16)
#define QUALENG_MIU_ADDR_CFG_1_LOGICAL_CHANNEL_ENABLE_FIELD                     _MK_FIELD_CONST(0xffff, QUALENG_MIU_ADDR_CFG_1_LOGICAL_CHANNEL_ENABLE_SHIFT)
#define QUALENG_MIU_ADDR_CFG_1_LOGICAL_CHANNEL_ENABLE_RANGE                     31:16
#define QUALENG_MIU_ADDR_CFG_1_LOGICAL_CHANNEL_ENABLE_WOFFSET                   0x0
#define QUALENG_MIU_ADDR_CFG_1_LOGICAL_CHANNEL_ENABLE_DEFAULT                   _MK_MASK_CONST(0xffff)
#define QUALENG_MIU_ADDR_CFG_1_LOGICAL_CHANNEL_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define QUALENG_MIU_ADDR_CFG_1_LOGICAL_CHANNEL_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_1_LOGICAL_CHANNEL_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_1_LOGICAL_CHANNEL_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_1_LOGICAL_CHANNEL_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_ADDR_CFG_2
#define QUALENG_MIU_ADDR_CFG_2                  _MK_ADDR_CONST(0x128)
#define QUALENG_MIU_ADDR_CFG_2_SECURE                   0x0
#define QUALENG_MIU_ADDR_CFG_2_DUAL                     0x0
#define QUALENG_MIU_ADDR_CFG_2_SCR                      0
#define QUALENG_MIU_ADDR_CFG_2_WORD_COUNT                       0x1
#define QUALENG_MIU_ADDR_CFG_2_RESET_VAL                        _MK_MASK_CONST(0xffff0020)
#define QUALENG_MIU_ADDR_CFG_2_RESET_MASK                       _MK_MASK_CONST(0xffff3fff)
#define QUALENG_MIU_ADDR_CFG_2_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_2_READ_MASK                        _MK_MASK_CONST(0xffff3fff)
#define QUALENG_MIU_ADDR_CFG_2_WRITE_MASK                       _MK_MASK_CONST(0xffff3fff)
#define QUALENG_MIU_ADDR_CFG_2_SO_DEV_SHIFT                     _MK_SHIFT_CONST(0)
#define QUALENG_MIU_ADDR_CFG_2_SO_DEV_FIELD                     _MK_FIELD_CONST(0x1, QUALENG_MIU_ADDR_CFG_2_SO_DEV_SHIFT)
#define QUALENG_MIU_ADDR_CFG_2_SO_DEV_RANGE                     0:0
#define QUALENG_MIU_ADDR_CFG_2_SO_DEV_WOFFSET                   0x0
#define QUALENG_MIU_ADDR_CFG_2_SO_DEV_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_2_SO_DEV_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_2_SO_DEV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_2_SO_DEV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_2_SO_DEV_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_2_SO_DEV_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_2_SO_DEV_INIT_ENUM                 NORMAL
#define QUALENG_MIU_ADDR_CFG_2_SO_DEV_NORMAL                    _MK_ENUM_CONST(0)
#define QUALENG_MIU_ADDR_CFG_2_SO_DEV_SO_DEV                    _MK_ENUM_CONST(1)

#define QUALENG_MIU_ADDR_CFG_2_RANDOM_ACCESS_SHIFT                      _MK_SHIFT_CONST(1)
#define QUALENG_MIU_ADDR_CFG_2_RANDOM_ACCESS_FIELD                      _MK_FIELD_CONST(0x1, QUALENG_MIU_ADDR_CFG_2_RANDOM_ACCESS_SHIFT)
#define QUALENG_MIU_ADDR_CFG_2_RANDOM_ACCESS_RANGE                      1:1
#define QUALENG_MIU_ADDR_CFG_2_RANDOM_ACCESS_WOFFSET                    0x0
#define QUALENG_MIU_ADDR_CFG_2_RANDOM_ACCESS_DEFAULT                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_2_RANDOM_ACCESS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_2_RANDOM_ACCESS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_2_RANDOM_ACCESS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_2_RANDOM_ACCESS_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_2_RANDOM_ACCESS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_2_RANDOM_ACCESS_INIT_ENUM                  DISABLE
#define QUALENG_MIU_ADDR_CFG_2_RANDOM_ACCESS_DISABLE                    _MK_ENUM_CONST(0)
#define QUALENG_MIU_ADDR_CFG_2_RANDOM_ACCESS_ENABLE                     _MK_ENUM_CONST(1)

#define QUALENG_MIU_ADDR_CFG_2_ACCESS_PER_ACTIVATE_SHIFT                        _MK_SHIFT_CONST(2)
#define QUALENG_MIU_ADDR_CFG_2_ACCESS_PER_ACTIVATE_FIELD                        _MK_FIELD_CONST(0x1f, QUALENG_MIU_ADDR_CFG_2_ACCESS_PER_ACTIVATE_SHIFT)
#define QUALENG_MIU_ADDR_CFG_2_ACCESS_PER_ACTIVATE_RANGE                        6:2
#define QUALENG_MIU_ADDR_CFG_2_ACCESS_PER_ACTIVATE_WOFFSET                      0x0
#define QUALENG_MIU_ADDR_CFG_2_ACCESS_PER_ACTIVATE_DEFAULT                      _MK_MASK_CONST(0x8)
#define QUALENG_MIU_ADDR_CFG_2_ACCESS_PER_ACTIVATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define QUALENG_MIU_ADDR_CFG_2_ACCESS_PER_ACTIVATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_2_ACCESS_PER_ACTIVATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_2_ACCESS_PER_ACTIVATE_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_2_ACCESS_PER_ACTIVATE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_2_ACCESS_PER_ACTIVATE_INT_512B                     _MK_ENUM_CONST(8)
#define QUALENG_MIU_ADDR_CFG_2_ACCESS_PER_ACTIVATE_INT_1KB                      _MK_ENUM_CONST(16)

#define QUALENG_MIU_ADDR_CFG_2_SWIZZLE_INDEX_LOWER_SHIFT                        _MK_SHIFT_CONST(7)
#define QUALENG_MIU_ADDR_CFG_2_SWIZZLE_INDEX_LOWER_FIELD                        _MK_FIELD_CONST(0x3, QUALENG_MIU_ADDR_CFG_2_SWIZZLE_INDEX_LOWER_SHIFT)
#define QUALENG_MIU_ADDR_CFG_2_SWIZZLE_INDEX_LOWER_RANGE                        8:7
#define QUALENG_MIU_ADDR_CFG_2_SWIZZLE_INDEX_LOWER_WOFFSET                      0x0
#define QUALENG_MIU_ADDR_CFG_2_SWIZZLE_INDEX_LOWER_DEFAULT                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_2_SWIZZLE_INDEX_LOWER_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define QUALENG_MIU_ADDR_CFG_2_SWIZZLE_INDEX_LOWER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_2_SWIZZLE_INDEX_LOWER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_2_SWIZZLE_INDEX_LOWER_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_2_SWIZZLE_INDEX_LOWER_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_2_SWIZZLE_INDEX_LOWER_INIT_ENUM                    DISABLE
#define QUALENG_MIU_ADDR_CFG_2_SWIZZLE_INDEX_LOWER_DISABLE                      _MK_ENUM_CONST(0)

#define QUALENG_MIU_ADDR_CFG_2_SWIZZLE_INDEX_UPPER_SHIFT                        _MK_SHIFT_CONST(9)
#define QUALENG_MIU_ADDR_CFG_2_SWIZZLE_INDEX_UPPER_FIELD                        _MK_FIELD_CONST(0x1f, QUALENG_MIU_ADDR_CFG_2_SWIZZLE_INDEX_UPPER_SHIFT)
#define QUALENG_MIU_ADDR_CFG_2_SWIZZLE_INDEX_UPPER_RANGE                        13:9
#define QUALENG_MIU_ADDR_CFG_2_SWIZZLE_INDEX_UPPER_WOFFSET                      0x0
#define QUALENG_MIU_ADDR_CFG_2_SWIZZLE_INDEX_UPPER_DEFAULT                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_2_SWIZZLE_INDEX_UPPER_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define QUALENG_MIU_ADDR_CFG_2_SWIZZLE_INDEX_UPPER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_2_SWIZZLE_INDEX_UPPER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_2_SWIZZLE_INDEX_UPPER_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_2_SWIZZLE_INDEX_UPPER_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_2_SWIZZLE_INDEX_UPPER_INIT_ENUM                    DISABLE
#define QUALENG_MIU_ADDR_CFG_2_SWIZZLE_INDEX_UPPER_DISABLE                      _MK_ENUM_CONST(0)

#define QUALENG_MIU_ADDR_CFG_2_LOGICAL_CHANNEL_ENABLE_SHIFT                     _MK_SHIFT_CONST(16)
#define QUALENG_MIU_ADDR_CFG_2_LOGICAL_CHANNEL_ENABLE_FIELD                     _MK_FIELD_CONST(0xffff, QUALENG_MIU_ADDR_CFG_2_LOGICAL_CHANNEL_ENABLE_SHIFT)
#define QUALENG_MIU_ADDR_CFG_2_LOGICAL_CHANNEL_ENABLE_RANGE                     31:16
#define QUALENG_MIU_ADDR_CFG_2_LOGICAL_CHANNEL_ENABLE_WOFFSET                   0x0
#define QUALENG_MIU_ADDR_CFG_2_LOGICAL_CHANNEL_ENABLE_DEFAULT                   _MK_MASK_CONST(0xffff)
#define QUALENG_MIU_ADDR_CFG_2_LOGICAL_CHANNEL_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define QUALENG_MIU_ADDR_CFG_2_LOGICAL_CHANNEL_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_2_LOGICAL_CHANNEL_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_2_LOGICAL_CHANNEL_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_2_LOGICAL_CHANNEL_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_ADDR_CFG_3
#define QUALENG_MIU_ADDR_CFG_3                  _MK_ADDR_CONST(0x12c)
#define QUALENG_MIU_ADDR_CFG_3_SECURE                   0x0
#define QUALENG_MIU_ADDR_CFG_3_DUAL                     0x0
#define QUALENG_MIU_ADDR_CFG_3_SCR                      0
#define QUALENG_MIU_ADDR_CFG_3_WORD_COUNT                       0x1
#define QUALENG_MIU_ADDR_CFG_3_RESET_VAL                        _MK_MASK_CONST(0xffff0020)
#define QUALENG_MIU_ADDR_CFG_3_RESET_MASK                       _MK_MASK_CONST(0xffff3fff)
#define QUALENG_MIU_ADDR_CFG_3_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_3_READ_MASK                        _MK_MASK_CONST(0xffff3fff)
#define QUALENG_MIU_ADDR_CFG_3_WRITE_MASK                       _MK_MASK_CONST(0xffff3fff)
#define QUALENG_MIU_ADDR_CFG_3_SO_DEV_SHIFT                     _MK_SHIFT_CONST(0)
#define QUALENG_MIU_ADDR_CFG_3_SO_DEV_FIELD                     _MK_FIELD_CONST(0x1, QUALENG_MIU_ADDR_CFG_3_SO_DEV_SHIFT)
#define QUALENG_MIU_ADDR_CFG_3_SO_DEV_RANGE                     0:0
#define QUALENG_MIU_ADDR_CFG_3_SO_DEV_WOFFSET                   0x0
#define QUALENG_MIU_ADDR_CFG_3_SO_DEV_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_3_SO_DEV_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_3_SO_DEV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_3_SO_DEV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_3_SO_DEV_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_3_SO_DEV_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_3_SO_DEV_INIT_ENUM                 NORMAL
#define QUALENG_MIU_ADDR_CFG_3_SO_DEV_NORMAL                    _MK_ENUM_CONST(0)
#define QUALENG_MIU_ADDR_CFG_3_SO_DEV_SO_DEV                    _MK_ENUM_CONST(1)

#define QUALENG_MIU_ADDR_CFG_3_RANDOM_ACCESS_SHIFT                      _MK_SHIFT_CONST(1)
#define QUALENG_MIU_ADDR_CFG_3_RANDOM_ACCESS_FIELD                      _MK_FIELD_CONST(0x1, QUALENG_MIU_ADDR_CFG_3_RANDOM_ACCESS_SHIFT)
#define QUALENG_MIU_ADDR_CFG_3_RANDOM_ACCESS_RANGE                      1:1
#define QUALENG_MIU_ADDR_CFG_3_RANDOM_ACCESS_WOFFSET                    0x0
#define QUALENG_MIU_ADDR_CFG_3_RANDOM_ACCESS_DEFAULT                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_3_RANDOM_ACCESS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_3_RANDOM_ACCESS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_3_RANDOM_ACCESS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_3_RANDOM_ACCESS_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_3_RANDOM_ACCESS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_3_RANDOM_ACCESS_INIT_ENUM                  DISABLE
#define QUALENG_MIU_ADDR_CFG_3_RANDOM_ACCESS_DISABLE                    _MK_ENUM_CONST(0)
#define QUALENG_MIU_ADDR_CFG_3_RANDOM_ACCESS_ENABLE                     _MK_ENUM_CONST(1)

#define QUALENG_MIU_ADDR_CFG_3_ACCESS_PER_ACTIVATE_SHIFT                        _MK_SHIFT_CONST(2)
#define QUALENG_MIU_ADDR_CFG_3_ACCESS_PER_ACTIVATE_FIELD                        _MK_FIELD_CONST(0x1f, QUALENG_MIU_ADDR_CFG_3_ACCESS_PER_ACTIVATE_SHIFT)
#define QUALENG_MIU_ADDR_CFG_3_ACCESS_PER_ACTIVATE_RANGE                        6:2
#define QUALENG_MIU_ADDR_CFG_3_ACCESS_PER_ACTIVATE_WOFFSET                      0x0
#define QUALENG_MIU_ADDR_CFG_3_ACCESS_PER_ACTIVATE_DEFAULT                      _MK_MASK_CONST(0x8)
#define QUALENG_MIU_ADDR_CFG_3_ACCESS_PER_ACTIVATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define QUALENG_MIU_ADDR_CFG_3_ACCESS_PER_ACTIVATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_3_ACCESS_PER_ACTIVATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_3_ACCESS_PER_ACTIVATE_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_3_ACCESS_PER_ACTIVATE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_3_ACCESS_PER_ACTIVATE_INT_512B                     _MK_ENUM_CONST(8)
#define QUALENG_MIU_ADDR_CFG_3_ACCESS_PER_ACTIVATE_INT_1KB                      _MK_ENUM_CONST(16)

#define QUALENG_MIU_ADDR_CFG_3_SWIZZLE_INDEX_LOWER_SHIFT                        _MK_SHIFT_CONST(7)
#define QUALENG_MIU_ADDR_CFG_3_SWIZZLE_INDEX_LOWER_FIELD                        _MK_FIELD_CONST(0x3, QUALENG_MIU_ADDR_CFG_3_SWIZZLE_INDEX_LOWER_SHIFT)
#define QUALENG_MIU_ADDR_CFG_3_SWIZZLE_INDEX_LOWER_RANGE                        8:7
#define QUALENG_MIU_ADDR_CFG_3_SWIZZLE_INDEX_LOWER_WOFFSET                      0x0
#define QUALENG_MIU_ADDR_CFG_3_SWIZZLE_INDEX_LOWER_DEFAULT                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_3_SWIZZLE_INDEX_LOWER_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define QUALENG_MIU_ADDR_CFG_3_SWIZZLE_INDEX_LOWER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_3_SWIZZLE_INDEX_LOWER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_3_SWIZZLE_INDEX_LOWER_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_3_SWIZZLE_INDEX_LOWER_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_3_SWIZZLE_INDEX_LOWER_INIT_ENUM                    DISABLE
#define QUALENG_MIU_ADDR_CFG_3_SWIZZLE_INDEX_LOWER_DISABLE                      _MK_ENUM_CONST(0)

#define QUALENG_MIU_ADDR_CFG_3_SWIZZLE_INDEX_UPPER_SHIFT                        _MK_SHIFT_CONST(9)
#define QUALENG_MIU_ADDR_CFG_3_SWIZZLE_INDEX_UPPER_FIELD                        _MK_FIELD_CONST(0x1f, QUALENG_MIU_ADDR_CFG_3_SWIZZLE_INDEX_UPPER_SHIFT)
#define QUALENG_MIU_ADDR_CFG_3_SWIZZLE_INDEX_UPPER_RANGE                        13:9
#define QUALENG_MIU_ADDR_CFG_3_SWIZZLE_INDEX_UPPER_WOFFSET                      0x0
#define QUALENG_MIU_ADDR_CFG_3_SWIZZLE_INDEX_UPPER_DEFAULT                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_3_SWIZZLE_INDEX_UPPER_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define QUALENG_MIU_ADDR_CFG_3_SWIZZLE_INDEX_UPPER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_3_SWIZZLE_INDEX_UPPER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_3_SWIZZLE_INDEX_UPPER_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_3_SWIZZLE_INDEX_UPPER_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_3_SWIZZLE_INDEX_UPPER_INIT_ENUM                    DISABLE
#define QUALENG_MIU_ADDR_CFG_3_SWIZZLE_INDEX_UPPER_DISABLE                      _MK_ENUM_CONST(0)

#define QUALENG_MIU_ADDR_CFG_3_LOGICAL_CHANNEL_ENABLE_SHIFT                     _MK_SHIFT_CONST(16)
#define QUALENG_MIU_ADDR_CFG_3_LOGICAL_CHANNEL_ENABLE_FIELD                     _MK_FIELD_CONST(0xffff, QUALENG_MIU_ADDR_CFG_3_LOGICAL_CHANNEL_ENABLE_SHIFT)
#define QUALENG_MIU_ADDR_CFG_3_LOGICAL_CHANNEL_ENABLE_RANGE                     31:16
#define QUALENG_MIU_ADDR_CFG_3_LOGICAL_CHANNEL_ENABLE_WOFFSET                   0x0
#define QUALENG_MIU_ADDR_CFG_3_LOGICAL_CHANNEL_ENABLE_DEFAULT                   _MK_MASK_CONST(0xffff)
#define QUALENG_MIU_ADDR_CFG_3_LOGICAL_CHANNEL_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define QUALENG_MIU_ADDR_CFG_3_LOGICAL_CHANNEL_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_3_LOGICAL_CHANNEL_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_3_LOGICAL_CHANNEL_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_3_LOGICAL_CHANNEL_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_ADDR_CFG_4
#define QUALENG_MIU_ADDR_CFG_4                  _MK_ADDR_CONST(0x130)
#define QUALENG_MIU_ADDR_CFG_4_SECURE                   0x0
#define QUALENG_MIU_ADDR_CFG_4_DUAL                     0x0
#define QUALENG_MIU_ADDR_CFG_4_SCR                      0
#define QUALENG_MIU_ADDR_CFG_4_WORD_COUNT                       0x1
#define QUALENG_MIU_ADDR_CFG_4_RESET_VAL                        _MK_MASK_CONST(0xffff0020)
#define QUALENG_MIU_ADDR_CFG_4_RESET_MASK                       _MK_MASK_CONST(0xffff3fff)
#define QUALENG_MIU_ADDR_CFG_4_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_4_READ_MASK                        _MK_MASK_CONST(0xffff3fff)
#define QUALENG_MIU_ADDR_CFG_4_WRITE_MASK                       _MK_MASK_CONST(0xffff3fff)
#define QUALENG_MIU_ADDR_CFG_4_SO_DEV_SHIFT                     _MK_SHIFT_CONST(0)
#define QUALENG_MIU_ADDR_CFG_4_SO_DEV_FIELD                     _MK_FIELD_CONST(0x1, QUALENG_MIU_ADDR_CFG_4_SO_DEV_SHIFT)
#define QUALENG_MIU_ADDR_CFG_4_SO_DEV_RANGE                     0:0
#define QUALENG_MIU_ADDR_CFG_4_SO_DEV_WOFFSET                   0x0
#define QUALENG_MIU_ADDR_CFG_4_SO_DEV_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_4_SO_DEV_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_4_SO_DEV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_4_SO_DEV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_4_SO_DEV_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_4_SO_DEV_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_4_SO_DEV_INIT_ENUM                 NORMAL
#define QUALENG_MIU_ADDR_CFG_4_SO_DEV_NORMAL                    _MK_ENUM_CONST(0)
#define QUALENG_MIU_ADDR_CFG_4_SO_DEV_SO_DEV                    _MK_ENUM_CONST(1)

#define QUALENG_MIU_ADDR_CFG_4_RANDOM_ACCESS_SHIFT                      _MK_SHIFT_CONST(1)
#define QUALENG_MIU_ADDR_CFG_4_RANDOM_ACCESS_FIELD                      _MK_FIELD_CONST(0x1, QUALENG_MIU_ADDR_CFG_4_RANDOM_ACCESS_SHIFT)
#define QUALENG_MIU_ADDR_CFG_4_RANDOM_ACCESS_RANGE                      1:1
#define QUALENG_MIU_ADDR_CFG_4_RANDOM_ACCESS_WOFFSET                    0x0
#define QUALENG_MIU_ADDR_CFG_4_RANDOM_ACCESS_DEFAULT                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_4_RANDOM_ACCESS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_4_RANDOM_ACCESS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_4_RANDOM_ACCESS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_4_RANDOM_ACCESS_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_4_RANDOM_ACCESS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_4_RANDOM_ACCESS_INIT_ENUM                  DISABLE
#define QUALENG_MIU_ADDR_CFG_4_RANDOM_ACCESS_DISABLE                    _MK_ENUM_CONST(0)
#define QUALENG_MIU_ADDR_CFG_4_RANDOM_ACCESS_ENABLE                     _MK_ENUM_CONST(1)

#define QUALENG_MIU_ADDR_CFG_4_ACCESS_PER_ACTIVATE_SHIFT                        _MK_SHIFT_CONST(2)
#define QUALENG_MIU_ADDR_CFG_4_ACCESS_PER_ACTIVATE_FIELD                        _MK_FIELD_CONST(0x1f, QUALENG_MIU_ADDR_CFG_4_ACCESS_PER_ACTIVATE_SHIFT)
#define QUALENG_MIU_ADDR_CFG_4_ACCESS_PER_ACTIVATE_RANGE                        6:2
#define QUALENG_MIU_ADDR_CFG_4_ACCESS_PER_ACTIVATE_WOFFSET                      0x0
#define QUALENG_MIU_ADDR_CFG_4_ACCESS_PER_ACTIVATE_DEFAULT                      _MK_MASK_CONST(0x8)
#define QUALENG_MIU_ADDR_CFG_4_ACCESS_PER_ACTIVATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define QUALENG_MIU_ADDR_CFG_4_ACCESS_PER_ACTIVATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_4_ACCESS_PER_ACTIVATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_4_ACCESS_PER_ACTIVATE_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_4_ACCESS_PER_ACTIVATE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_4_ACCESS_PER_ACTIVATE_INT_512B                     _MK_ENUM_CONST(8)
#define QUALENG_MIU_ADDR_CFG_4_ACCESS_PER_ACTIVATE_INT_1KB                      _MK_ENUM_CONST(16)

#define QUALENG_MIU_ADDR_CFG_4_SWIZZLE_INDEX_LOWER_SHIFT                        _MK_SHIFT_CONST(7)
#define QUALENG_MIU_ADDR_CFG_4_SWIZZLE_INDEX_LOWER_FIELD                        _MK_FIELD_CONST(0x3, QUALENG_MIU_ADDR_CFG_4_SWIZZLE_INDEX_LOWER_SHIFT)
#define QUALENG_MIU_ADDR_CFG_4_SWIZZLE_INDEX_LOWER_RANGE                        8:7
#define QUALENG_MIU_ADDR_CFG_4_SWIZZLE_INDEX_LOWER_WOFFSET                      0x0
#define QUALENG_MIU_ADDR_CFG_4_SWIZZLE_INDEX_LOWER_DEFAULT                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_4_SWIZZLE_INDEX_LOWER_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define QUALENG_MIU_ADDR_CFG_4_SWIZZLE_INDEX_LOWER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_4_SWIZZLE_INDEX_LOWER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_4_SWIZZLE_INDEX_LOWER_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_4_SWIZZLE_INDEX_LOWER_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_4_SWIZZLE_INDEX_LOWER_INIT_ENUM                    DISABLE
#define QUALENG_MIU_ADDR_CFG_4_SWIZZLE_INDEX_LOWER_DISABLE                      _MK_ENUM_CONST(0)

#define QUALENG_MIU_ADDR_CFG_4_SWIZZLE_INDEX_UPPER_SHIFT                        _MK_SHIFT_CONST(9)
#define QUALENG_MIU_ADDR_CFG_4_SWIZZLE_INDEX_UPPER_FIELD                        _MK_FIELD_CONST(0x1f, QUALENG_MIU_ADDR_CFG_4_SWIZZLE_INDEX_UPPER_SHIFT)
#define QUALENG_MIU_ADDR_CFG_4_SWIZZLE_INDEX_UPPER_RANGE                        13:9
#define QUALENG_MIU_ADDR_CFG_4_SWIZZLE_INDEX_UPPER_WOFFSET                      0x0
#define QUALENG_MIU_ADDR_CFG_4_SWIZZLE_INDEX_UPPER_DEFAULT                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_4_SWIZZLE_INDEX_UPPER_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define QUALENG_MIU_ADDR_CFG_4_SWIZZLE_INDEX_UPPER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_4_SWIZZLE_INDEX_UPPER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_4_SWIZZLE_INDEX_UPPER_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_4_SWIZZLE_INDEX_UPPER_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_4_SWIZZLE_INDEX_UPPER_INIT_ENUM                    DISABLE
#define QUALENG_MIU_ADDR_CFG_4_SWIZZLE_INDEX_UPPER_DISABLE                      _MK_ENUM_CONST(0)

#define QUALENG_MIU_ADDR_CFG_4_LOGICAL_CHANNEL_ENABLE_SHIFT                     _MK_SHIFT_CONST(16)
#define QUALENG_MIU_ADDR_CFG_4_LOGICAL_CHANNEL_ENABLE_FIELD                     _MK_FIELD_CONST(0xffff, QUALENG_MIU_ADDR_CFG_4_LOGICAL_CHANNEL_ENABLE_SHIFT)
#define QUALENG_MIU_ADDR_CFG_4_LOGICAL_CHANNEL_ENABLE_RANGE                     31:16
#define QUALENG_MIU_ADDR_CFG_4_LOGICAL_CHANNEL_ENABLE_WOFFSET                   0x0
#define QUALENG_MIU_ADDR_CFG_4_LOGICAL_CHANNEL_ENABLE_DEFAULT                   _MK_MASK_CONST(0xffff)
#define QUALENG_MIU_ADDR_CFG_4_LOGICAL_CHANNEL_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define QUALENG_MIU_ADDR_CFG_4_LOGICAL_CHANNEL_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_4_LOGICAL_CHANNEL_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_4_LOGICAL_CHANNEL_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_4_LOGICAL_CHANNEL_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_ADDR_CFG_5
#define QUALENG_MIU_ADDR_CFG_5                  _MK_ADDR_CONST(0x134)
#define QUALENG_MIU_ADDR_CFG_5_SECURE                   0x0
#define QUALENG_MIU_ADDR_CFG_5_DUAL                     0x0
#define QUALENG_MIU_ADDR_CFG_5_SCR                      0
#define QUALENG_MIU_ADDR_CFG_5_WORD_COUNT                       0x1
#define QUALENG_MIU_ADDR_CFG_5_RESET_VAL                        _MK_MASK_CONST(0xffff0020)
#define QUALENG_MIU_ADDR_CFG_5_RESET_MASK                       _MK_MASK_CONST(0xffff3fff)
#define QUALENG_MIU_ADDR_CFG_5_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_5_READ_MASK                        _MK_MASK_CONST(0xffff3fff)
#define QUALENG_MIU_ADDR_CFG_5_WRITE_MASK                       _MK_MASK_CONST(0xffff3fff)
#define QUALENG_MIU_ADDR_CFG_5_SO_DEV_SHIFT                     _MK_SHIFT_CONST(0)
#define QUALENG_MIU_ADDR_CFG_5_SO_DEV_FIELD                     _MK_FIELD_CONST(0x1, QUALENG_MIU_ADDR_CFG_5_SO_DEV_SHIFT)
#define QUALENG_MIU_ADDR_CFG_5_SO_DEV_RANGE                     0:0
#define QUALENG_MIU_ADDR_CFG_5_SO_DEV_WOFFSET                   0x0
#define QUALENG_MIU_ADDR_CFG_5_SO_DEV_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_5_SO_DEV_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_5_SO_DEV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_5_SO_DEV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_5_SO_DEV_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_5_SO_DEV_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_5_SO_DEV_INIT_ENUM                 NORMAL
#define QUALENG_MIU_ADDR_CFG_5_SO_DEV_NORMAL                    _MK_ENUM_CONST(0)
#define QUALENG_MIU_ADDR_CFG_5_SO_DEV_SO_DEV                    _MK_ENUM_CONST(1)

#define QUALENG_MIU_ADDR_CFG_5_RANDOM_ACCESS_SHIFT                      _MK_SHIFT_CONST(1)
#define QUALENG_MIU_ADDR_CFG_5_RANDOM_ACCESS_FIELD                      _MK_FIELD_CONST(0x1, QUALENG_MIU_ADDR_CFG_5_RANDOM_ACCESS_SHIFT)
#define QUALENG_MIU_ADDR_CFG_5_RANDOM_ACCESS_RANGE                      1:1
#define QUALENG_MIU_ADDR_CFG_5_RANDOM_ACCESS_WOFFSET                    0x0
#define QUALENG_MIU_ADDR_CFG_5_RANDOM_ACCESS_DEFAULT                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_5_RANDOM_ACCESS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_5_RANDOM_ACCESS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_5_RANDOM_ACCESS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_5_RANDOM_ACCESS_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_5_RANDOM_ACCESS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_5_RANDOM_ACCESS_INIT_ENUM                  DISABLE
#define QUALENG_MIU_ADDR_CFG_5_RANDOM_ACCESS_DISABLE                    _MK_ENUM_CONST(0)
#define QUALENG_MIU_ADDR_CFG_5_RANDOM_ACCESS_ENABLE                     _MK_ENUM_CONST(1)

#define QUALENG_MIU_ADDR_CFG_5_ACCESS_PER_ACTIVATE_SHIFT                        _MK_SHIFT_CONST(2)
#define QUALENG_MIU_ADDR_CFG_5_ACCESS_PER_ACTIVATE_FIELD                        _MK_FIELD_CONST(0x1f, QUALENG_MIU_ADDR_CFG_5_ACCESS_PER_ACTIVATE_SHIFT)
#define QUALENG_MIU_ADDR_CFG_5_ACCESS_PER_ACTIVATE_RANGE                        6:2
#define QUALENG_MIU_ADDR_CFG_5_ACCESS_PER_ACTIVATE_WOFFSET                      0x0
#define QUALENG_MIU_ADDR_CFG_5_ACCESS_PER_ACTIVATE_DEFAULT                      _MK_MASK_CONST(0x8)
#define QUALENG_MIU_ADDR_CFG_5_ACCESS_PER_ACTIVATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define QUALENG_MIU_ADDR_CFG_5_ACCESS_PER_ACTIVATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_5_ACCESS_PER_ACTIVATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_5_ACCESS_PER_ACTIVATE_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_5_ACCESS_PER_ACTIVATE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_5_ACCESS_PER_ACTIVATE_INT_512B                     _MK_ENUM_CONST(8)
#define QUALENG_MIU_ADDR_CFG_5_ACCESS_PER_ACTIVATE_INT_1KB                      _MK_ENUM_CONST(16)

#define QUALENG_MIU_ADDR_CFG_5_SWIZZLE_INDEX_LOWER_SHIFT                        _MK_SHIFT_CONST(7)
#define QUALENG_MIU_ADDR_CFG_5_SWIZZLE_INDEX_LOWER_FIELD                        _MK_FIELD_CONST(0x3, QUALENG_MIU_ADDR_CFG_5_SWIZZLE_INDEX_LOWER_SHIFT)
#define QUALENG_MIU_ADDR_CFG_5_SWIZZLE_INDEX_LOWER_RANGE                        8:7
#define QUALENG_MIU_ADDR_CFG_5_SWIZZLE_INDEX_LOWER_WOFFSET                      0x0
#define QUALENG_MIU_ADDR_CFG_5_SWIZZLE_INDEX_LOWER_DEFAULT                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_5_SWIZZLE_INDEX_LOWER_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define QUALENG_MIU_ADDR_CFG_5_SWIZZLE_INDEX_LOWER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_5_SWIZZLE_INDEX_LOWER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_5_SWIZZLE_INDEX_LOWER_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_5_SWIZZLE_INDEX_LOWER_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_5_SWIZZLE_INDEX_LOWER_INIT_ENUM                    DISABLE
#define QUALENG_MIU_ADDR_CFG_5_SWIZZLE_INDEX_LOWER_DISABLE                      _MK_ENUM_CONST(0)

#define QUALENG_MIU_ADDR_CFG_5_SWIZZLE_INDEX_UPPER_SHIFT                        _MK_SHIFT_CONST(9)
#define QUALENG_MIU_ADDR_CFG_5_SWIZZLE_INDEX_UPPER_FIELD                        _MK_FIELD_CONST(0x1f, QUALENG_MIU_ADDR_CFG_5_SWIZZLE_INDEX_UPPER_SHIFT)
#define QUALENG_MIU_ADDR_CFG_5_SWIZZLE_INDEX_UPPER_RANGE                        13:9
#define QUALENG_MIU_ADDR_CFG_5_SWIZZLE_INDEX_UPPER_WOFFSET                      0x0
#define QUALENG_MIU_ADDR_CFG_5_SWIZZLE_INDEX_UPPER_DEFAULT                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_5_SWIZZLE_INDEX_UPPER_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define QUALENG_MIU_ADDR_CFG_5_SWIZZLE_INDEX_UPPER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_5_SWIZZLE_INDEX_UPPER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_5_SWIZZLE_INDEX_UPPER_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_5_SWIZZLE_INDEX_UPPER_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_5_SWIZZLE_INDEX_UPPER_INIT_ENUM                    DISABLE
#define QUALENG_MIU_ADDR_CFG_5_SWIZZLE_INDEX_UPPER_DISABLE                      _MK_ENUM_CONST(0)

#define QUALENG_MIU_ADDR_CFG_5_LOGICAL_CHANNEL_ENABLE_SHIFT                     _MK_SHIFT_CONST(16)
#define QUALENG_MIU_ADDR_CFG_5_LOGICAL_CHANNEL_ENABLE_FIELD                     _MK_FIELD_CONST(0xffff, QUALENG_MIU_ADDR_CFG_5_LOGICAL_CHANNEL_ENABLE_SHIFT)
#define QUALENG_MIU_ADDR_CFG_5_LOGICAL_CHANNEL_ENABLE_RANGE                     31:16
#define QUALENG_MIU_ADDR_CFG_5_LOGICAL_CHANNEL_ENABLE_WOFFSET                   0x0
#define QUALENG_MIU_ADDR_CFG_5_LOGICAL_CHANNEL_ENABLE_DEFAULT                   _MK_MASK_CONST(0xffff)
#define QUALENG_MIU_ADDR_CFG_5_LOGICAL_CHANNEL_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define QUALENG_MIU_ADDR_CFG_5_LOGICAL_CHANNEL_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_5_LOGICAL_CHANNEL_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_5_LOGICAL_CHANNEL_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_5_LOGICAL_CHANNEL_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_ADDR_CFG_6
#define QUALENG_MIU_ADDR_CFG_6                  _MK_ADDR_CONST(0x138)
#define QUALENG_MIU_ADDR_CFG_6_SECURE                   0x0
#define QUALENG_MIU_ADDR_CFG_6_DUAL                     0x0
#define QUALENG_MIU_ADDR_CFG_6_SCR                      0
#define QUALENG_MIU_ADDR_CFG_6_WORD_COUNT                       0x1
#define QUALENG_MIU_ADDR_CFG_6_RESET_VAL                        _MK_MASK_CONST(0xffff0020)
#define QUALENG_MIU_ADDR_CFG_6_RESET_MASK                       _MK_MASK_CONST(0xffff3fff)
#define QUALENG_MIU_ADDR_CFG_6_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_6_READ_MASK                        _MK_MASK_CONST(0xffff3fff)
#define QUALENG_MIU_ADDR_CFG_6_WRITE_MASK                       _MK_MASK_CONST(0xffff3fff)
#define QUALENG_MIU_ADDR_CFG_6_SO_DEV_SHIFT                     _MK_SHIFT_CONST(0)
#define QUALENG_MIU_ADDR_CFG_6_SO_DEV_FIELD                     _MK_FIELD_CONST(0x1, QUALENG_MIU_ADDR_CFG_6_SO_DEV_SHIFT)
#define QUALENG_MIU_ADDR_CFG_6_SO_DEV_RANGE                     0:0
#define QUALENG_MIU_ADDR_CFG_6_SO_DEV_WOFFSET                   0x0
#define QUALENG_MIU_ADDR_CFG_6_SO_DEV_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_6_SO_DEV_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_6_SO_DEV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_6_SO_DEV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_6_SO_DEV_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_6_SO_DEV_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_6_SO_DEV_INIT_ENUM                 NORMAL
#define QUALENG_MIU_ADDR_CFG_6_SO_DEV_NORMAL                    _MK_ENUM_CONST(0)
#define QUALENG_MIU_ADDR_CFG_6_SO_DEV_SO_DEV                    _MK_ENUM_CONST(1)

#define QUALENG_MIU_ADDR_CFG_6_RANDOM_ACCESS_SHIFT                      _MK_SHIFT_CONST(1)
#define QUALENG_MIU_ADDR_CFG_6_RANDOM_ACCESS_FIELD                      _MK_FIELD_CONST(0x1, QUALENG_MIU_ADDR_CFG_6_RANDOM_ACCESS_SHIFT)
#define QUALENG_MIU_ADDR_CFG_6_RANDOM_ACCESS_RANGE                      1:1
#define QUALENG_MIU_ADDR_CFG_6_RANDOM_ACCESS_WOFFSET                    0x0
#define QUALENG_MIU_ADDR_CFG_6_RANDOM_ACCESS_DEFAULT                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_6_RANDOM_ACCESS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_6_RANDOM_ACCESS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_6_RANDOM_ACCESS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_6_RANDOM_ACCESS_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_6_RANDOM_ACCESS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_6_RANDOM_ACCESS_INIT_ENUM                  DISABLE
#define QUALENG_MIU_ADDR_CFG_6_RANDOM_ACCESS_DISABLE                    _MK_ENUM_CONST(0)
#define QUALENG_MIU_ADDR_CFG_6_RANDOM_ACCESS_ENABLE                     _MK_ENUM_CONST(1)

#define QUALENG_MIU_ADDR_CFG_6_ACCESS_PER_ACTIVATE_SHIFT                        _MK_SHIFT_CONST(2)
#define QUALENG_MIU_ADDR_CFG_6_ACCESS_PER_ACTIVATE_FIELD                        _MK_FIELD_CONST(0x1f, QUALENG_MIU_ADDR_CFG_6_ACCESS_PER_ACTIVATE_SHIFT)
#define QUALENG_MIU_ADDR_CFG_6_ACCESS_PER_ACTIVATE_RANGE                        6:2
#define QUALENG_MIU_ADDR_CFG_6_ACCESS_PER_ACTIVATE_WOFFSET                      0x0
#define QUALENG_MIU_ADDR_CFG_6_ACCESS_PER_ACTIVATE_DEFAULT                      _MK_MASK_CONST(0x8)
#define QUALENG_MIU_ADDR_CFG_6_ACCESS_PER_ACTIVATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define QUALENG_MIU_ADDR_CFG_6_ACCESS_PER_ACTIVATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_6_ACCESS_PER_ACTIVATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_6_ACCESS_PER_ACTIVATE_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_6_ACCESS_PER_ACTIVATE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_6_ACCESS_PER_ACTIVATE_INT_512B                     _MK_ENUM_CONST(8)
#define QUALENG_MIU_ADDR_CFG_6_ACCESS_PER_ACTIVATE_INT_1KB                      _MK_ENUM_CONST(16)

#define QUALENG_MIU_ADDR_CFG_6_SWIZZLE_INDEX_LOWER_SHIFT                        _MK_SHIFT_CONST(7)
#define QUALENG_MIU_ADDR_CFG_6_SWIZZLE_INDEX_LOWER_FIELD                        _MK_FIELD_CONST(0x3, QUALENG_MIU_ADDR_CFG_6_SWIZZLE_INDEX_LOWER_SHIFT)
#define QUALENG_MIU_ADDR_CFG_6_SWIZZLE_INDEX_LOWER_RANGE                        8:7
#define QUALENG_MIU_ADDR_CFG_6_SWIZZLE_INDEX_LOWER_WOFFSET                      0x0
#define QUALENG_MIU_ADDR_CFG_6_SWIZZLE_INDEX_LOWER_DEFAULT                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_6_SWIZZLE_INDEX_LOWER_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define QUALENG_MIU_ADDR_CFG_6_SWIZZLE_INDEX_LOWER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_6_SWIZZLE_INDEX_LOWER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_6_SWIZZLE_INDEX_LOWER_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_6_SWIZZLE_INDEX_LOWER_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_6_SWIZZLE_INDEX_LOWER_INIT_ENUM                    DISABLE
#define QUALENG_MIU_ADDR_CFG_6_SWIZZLE_INDEX_LOWER_DISABLE                      _MK_ENUM_CONST(0)

#define QUALENG_MIU_ADDR_CFG_6_SWIZZLE_INDEX_UPPER_SHIFT                        _MK_SHIFT_CONST(9)
#define QUALENG_MIU_ADDR_CFG_6_SWIZZLE_INDEX_UPPER_FIELD                        _MK_FIELD_CONST(0x1f, QUALENG_MIU_ADDR_CFG_6_SWIZZLE_INDEX_UPPER_SHIFT)
#define QUALENG_MIU_ADDR_CFG_6_SWIZZLE_INDEX_UPPER_RANGE                        13:9
#define QUALENG_MIU_ADDR_CFG_6_SWIZZLE_INDEX_UPPER_WOFFSET                      0x0
#define QUALENG_MIU_ADDR_CFG_6_SWIZZLE_INDEX_UPPER_DEFAULT                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_6_SWIZZLE_INDEX_UPPER_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define QUALENG_MIU_ADDR_CFG_6_SWIZZLE_INDEX_UPPER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_6_SWIZZLE_INDEX_UPPER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_6_SWIZZLE_INDEX_UPPER_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_6_SWIZZLE_INDEX_UPPER_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_6_SWIZZLE_INDEX_UPPER_INIT_ENUM                    DISABLE
#define QUALENG_MIU_ADDR_CFG_6_SWIZZLE_INDEX_UPPER_DISABLE                      _MK_ENUM_CONST(0)

#define QUALENG_MIU_ADDR_CFG_6_LOGICAL_CHANNEL_ENABLE_SHIFT                     _MK_SHIFT_CONST(16)
#define QUALENG_MIU_ADDR_CFG_6_LOGICAL_CHANNEL_ENABLE_FIELD                     _MK_FIELD_CONST(0xffff, QUALENG_MIU_ADDR_CFG_6_LOGICAL_CHANNEL_ENABLE_SHIFT)
#define QUALENG_MIU_ADDR_CFG_6_LOGICAL_CHANNEL_ENABLE_RANGE                     31:16
#define QUALENG_MIU_ADDR_CFG_6_LOGICAL_CHANNEL_ENABLE_WOFFSET                   0x0
#define QUALENG_MIU_ADDR_CFG_6_LOGICAL_CHANNEL_ENABLE_DEFAULT                   _MK_MASK_CONST(0xffff)
#define QUALENG_MIU_ADDR_CFG_6_LOGICAL_CHANNEL_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define QUALENG_MIU_ADDR_CFG_6_LOGICAL_CHANNEL_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_6_LOGICAL_CHANNEL_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_6_LOGICAL_CHANNEL_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_6_LOGICAL_CHANNEL_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_ADDR_CFG_7
#define QUALENG_MIU_ADDR_CFG_7                  _MK_ADDR_CONST(0x13c)
#define QUALENG_MIU_ADDR_CFG_7_SECURE                   0x0
#define QUALENG_MIU_ADDR_CFG_7_DUAL                     0x0
#define QUALENG_MIU_ADDR_CFG_7_SCR                      0
#define QUALENG_MIU_ADDR_CFG_7_WORD_COUNT                       0x1
#define QUALENG_MIU_ADDR_CFG_7_RESET_VAL                        _MK_MASK_CONST(0xffff0020)
#define QUALENG_MIU_ADDR_CFG_7_RESET_MASK                       _MK_MASK_CONST(0xffff3fff)
#define QUALENG_MIU_ADDR_CFG_7_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_7_READ_MASK                        _MK_MASK_CONST(0xffff3fff)
#define QUALENG_MIU_ADDR_CFG_7_WRITE_MASK                       _MK_MASK_CONST(0xffff3fff)
#define QUALENG_MIU_ADDR_CFG_7_SO_DEV_SHIFT                     _MK_SHIFT_CONST(0)
#define QUALENG_MIU_ADDR_CFG_7_SO_DEV_FIELD                     _MK_FIELD_CONST(0x1, QUALENG_MIU_ADDR_CFG_7_SO_DEV_SHIFT)
#define QUALENG_MIU_ADDR_CFG_7_SO_DEV_RANGE                     0:0
#define QUALENG_MIU_ADDR_CFG_7_SO_DEV_WOFFSET                   0x0
#define QUALENG_MIU_ADDR_CFG_7_SO_DEV_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_7_SO_DEV_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_7_SO_DEV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_7_SO_DEV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_7_SO_DEV_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_7_SO_DEV_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_7_SO_DEV_INIT_ENUM                 NORMAL
#define QUALENG_MIU_ADDR_CFG_7_SO_DEV_NORMAL                    _MK_ENUM_CONST(0)
#define QUALENG_MIU_ADDR_CFG_7_SO_DEV_SO_DEV                    _MK_ENUM_CONST(1)

#define QUALENG_MIU_ADDR_CFG_7_RANDOM_ACCESS_SHIFT                      _MK_SHIFT_CONST(1)
#define QUALENG_MIU_ADDR_CFG_7_RANDOM_ACCESS_FIELD                      _MK_FIELD_CONST(0x1, QUALENG_MIU_ADDR_CFG_7_RANDOM_ACCESS_SHIFT)
#define QUALENG_MIU_ADDR_CFG_7_RANDOM_ACCESS_RANGE                      1:1
#define QUALENG_MIU_ADDR_CFG_7_RANDOM_ACCESS_WOFFSET                    0x0
#define QUALENG_MIU_ADDR_CFG_7_RANDOM_ACCESS_DEFAULT                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_7_RANDOM_ACCESS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_7_RANDOM_ACCESS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_7_RANDOM_ACCESS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_7_RANDOM_ACCESS_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_7_RANDOM_ACCESS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_7_RANDOM_ACCESS_INIT_ENUM                  DISABLE
#define QUALENG_MIU_ADDR_CFG_7_RANDOM_ACCESS_DISABLE                    _MK_ENUM_CONST(0)
#define QUALENG_MIU_ADDR_CFG_7_RANDOM_ACCESS_ENABLE                     _MK_ENUM_CONST(1)

#define QUALENG_MIU_ADDR_CFG_7_ACCESS_PER_ACTIVATE_SHIFT                        _MK_SHIFT_CONST(2)
#define QUALENG_MIU_ADDR_CFG_7_ACCESS_PER_ACTIVATE_FIELD                        _MK_FIELD_CONST(0x1f, QUALENG_MIU_ADDR_CFG_7_ACCESS_PER_ACTIVATE_SHIFT)
#define QUALENG_MIU_ADDR_CFG_7_ACCESS_PER_ACTIVATE_RANGE                        6:2
#define QUALENG_MIU_ADDR_CFG_7_ACCESS_PER_ACTIVATE_WOFFSET                      0x0
#define QUALENG_MIU_ADDR_CFG_7_ACCESS_PER_ACTIVATE_DEFAULT                      _MK_MASK_CONST(0x8)
#define QUALENG_MIU_ADDR_CFG_7_ACCESS_PER_ACTIVATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define QUALENG_MIU_ADDR_CFG_7_ACCESS_PER_ACTIVATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_7_ACCESS_PER_ACTIVATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_7_ACCESS_PER_ACTIVATE_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_7_ACCESS_PER_ACTIVATE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_7_ACCESS_PER_ACTIVATE_INT_512B                     _MK_ENUM_CONST(8)
#define QUALENG_MIU_ADDR_CFG_7_ACCESS_PER_ACTIVATE_INT_1KB                      _MK_ENUM_CONST(16)

#define QUALENG_MIU_ADDR_CFG_7_SWIZZLE_INDEX_LOWER_SHIFT                        _MK_SHIFT_CONST(7)
#define QUALENG_MIU_ADDR_CFG_7_SWIZZLE_INDEX_LOWER_FIELD                        _MK_FIELD_CONST(0x3, QUALENG_MIU_ADDR_CFG_7_SWIZZLE_INDEX_LOWER_SHIFT)
#define QUALENG_MIU_ADDR_CFG_7_SWIZZLE_INDEX_LOWER_RANGE                        8:7
#define QUALENG_MIU_ADDR_CFG_7_SWIZZLE_INDEX_LOWER_WOFFSET                      0x0
#define QUALENG_MIU_ADDR_CFG_7_SWIZZLE_INDEX_LOWER_DEFAULT                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_7_SWIZZLE_INDEX_LOWER_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define QUALENG_MIU_ADDR_CFG_7_SWIZZLE_INDEX_LOWER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_7_SWIZZLE_INDEX_LOWER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_7_SWIZZLE_INDEX_LOWER_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_7_SWIZZLE_INDEX_LOWER_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_7_SWIZZLE_INDEX_LOWER_INIT_ENUM                    DISABLE
#define QUALENG_MIU_ADDR_CFG_7_SWIZZLE_INDEX_LOWER_DISABLE                      _MK_ENUM_CONST(0)

#define QUALENG_MIU_ADDR_CFG_7_SWIZZLE_INDEX_UPPER_SHIFT                        _MK_SHIFT_CONST(9)
#define QUALENG_MIU_ADDR_CFG_7_SWIZZLE_INDEX_UPPER_FIELD                        _MK_FIELD_CONST(0x1f, QUALENG_MIU_ADDR_CFG_7_SWIZZLE_INDEX_UPPER_SHIFT)
#define QUALENG_MIU_ADDR_CFG_7_SWIZZLE_INDEX_UPPER_RANGE                        13:9
#define QUALENG_MIU_ADDR_CFG_7_SWIZZLE_INDEX_UPPER_WOFFSET                      0x0
#define QUALENG_MIU_ADDR_CFG_7_SWIZZLE_INDEX_UPPER_DEFAULT                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_7_SWIZZLE_INDEX_UPPER_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define QUALENG_MIU_ADDR_CFG_7_SWIZZLE_INDEX_UPPER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_7_SWIZZLE_INDEX_UPPER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_7_SWIZZLE_INDEX_UPPER_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_7_SWIZZLE_INDEX_UPPER_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_7_SWIZZLE_INDEX_UPPER_INIT_ENUM                    DISABLE
#define QUALENG_MIU_ADDR_CFG_7_SWIZZLE_INDEX_UPPER_DISABLE                      _MK_ENUM_CONST(0)

#define QUALENG_MIU_ADDR_CFG_7_LOGICAL_CHANNEL_ENABLE_SHIFT                     _MK_SHIFT_CONST(16)
#define QUALENG_MIU_ADDR_CFG_7_LOGICAL_CHANNEL_ENABLE_FIELD                     _MK_FIELD_CONST(0xffff, QUALENG_MIU_ADDR_CFG_7_LOGICAL_CHANNEL_ENABLE_SHIFT)
#define QUALENG_MIU_ADDR_CFG_7_LOGICAL_CHANNEL_ENABLE_RANGE                     31:16
#define QUALENG_MIU_ADDR_CFG_7_LOGICAL_CHANNEL_ENABLE_WOFFSET                   0x0
#define QUALENG_MIU_ADDR_CFG_7_LOGICAL_CHANNEL_ENABLE_DEFAULT                   _MK_MASK_CONST(0xffff)
#define QUALENG_MIU_ADDR_CFG_7_LOGICAL_CHANNEL_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define QUALENG_MIU_ADDR_CFG_7_LOGICAL_CHANNEL_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_7_LOGICAL_CHANNEL_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_CFG_7_LOGICAL_CHANNEL_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_CFG_7_LOGICAL_CHANNEL_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_ADDR_PAGE_START_0
#define QUALENG_MIU_ADDR_PAGE_START_0                   _MK_ADDR_CONST(0x140)
#define QUALENG_MIU_ADDR_PAGE_START_0_SECURE                    0x0
#define QUALENG_MIU_ADDR_PAGE_START_0_DUAL                      0x0
#define QUALENG_MIU_ADDR_PAGE_START_0_SCR                       0
#define QUALENG_MIU_ADDR_PAGE_START_0_WORD_COUNT                        0x1
#define QUALENG_MIU_ADDR_PAGE_START_0_RESET_VAL                         _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_START_0_RESET_MASK                        _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_0_READ_MASK                         _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_0_WRITE_MASK                        _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_0_PAGE_START_SHIFT                  _MK_SHIFT_CONST(0)
#define QUALENG_MIU_ADDR_PAGE_START_0_PAGE_START_FIELD                  _MK_FIELD_CONST(0x3ffffff, QUALENG_MIU_ADDR_PAGE_START_0_PAGE_START_SHIFT)
#define QUALENG_MIU_ADDR_PAGE_START_0_PAGE_START_RANGE                  25:0
#define QUALENG_MIU_ADDR_PAGE_START_0_PAGE_START_WOFFSET                        0x0
#define QUALENG_MIU_ADDR_PAGE_START_0_PAGE_START_DEFAULT                        _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_START_0_PAGE_START_DEFAULT_MASK                   _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_0_PAGE_START_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_0_PAGE_START_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_0_PAGE_START_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_PAGE_START_0_PAGE_START_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_ADDR_PAGE_START
#define QUALENG_MIU_ADDR_PAGE_START                     _MK_ADDR_CONST(0x140)
#define QUALENG_MIU_ADDR_PAGE_START_SECURE                      0x0
#define QUALENG_MIU_ADDR_PAGE_START_DUAL                        0x0
#define QUALENG_MIU_ADDR_PAGE_START_SCR                         0
#define QUALENG_MIU_ADDR_PAGE_START_WORD_COUNT                  0x1
#define QUALENG_MIU_ADDR_PAGE_START_RESET_VAL                   _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_START_RESET_MASK                  _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_READ_MASK                   _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_WRITE_MASK                  _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_PAGE_START_SHIFT                    _MK_SHIFT_CONST(0)
#define QUALENG_MIU_ADDR_PAGE_START_PAGE_START_FIELD                    _MK_FIELD_CONST(0x3ffffff, QUALENG_MIU_ADDR_PAGE_START_PAGE_START_SHIFT)
#define QUALENG_MIU_ADDR_PAGE_START_PAGE_START_RANGE                    25:0
#define QUALENG_MIU_ADDR_PAGE_START_PAGE_START_WOFFSET                  0x0
#define QUALENG_MIU_ADDR_PAGE_START_PAGE_START_DEFAULT                  _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_START_PAGE_START_DEFAULT_MASK                     _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_PAGE_START_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_PAGE_START_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_PAGE_START_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_PAGE_START_PAGE_START_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_ADDR_PAGE_START_1
#define QUALENG_MIU_ADDR_PAGE_START_1                   _MK_ADDR_CONST(0x144)
#define QUALENG_MIU_ADDR_PAGE_START_1_SECURE                    0x0
#define QUALENG_MIU_ADDR_PAGE_START_1_DUAL                      0x0
#define QUALENG_MIU_ADDR_PAGE_START_1_SCR                       0
#define QUALENG_MIU_ADDR_PAGE_START_1_WORD_COUNT                        0x1
#define QUALENG_MIU_ADDR_PAGE_START_1_RESET_VAL                         _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_START_1_RESET_MASK                        _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_1_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_1_READ_MASK                         _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_1_WRITE_MASK                        _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_1_PAGE_START_SHIFT                  _MK_SHIFT_CONST(0)
#define QUALENG_MIU_ADDR_PAGE_START_1_PAGE_START_FIELD                  _MK_FIELD_CONST(0x3ffffff, QUALENG_MIU_ADDR_PAGE_START_1_PAGE_START_SHIFT)
#define QUALENG_MIU_ADDR_PAGE_START_1_PAGE_START_RANGE                  25:0
#define QUALENG_MIU_ADDR_PAGE_START_1_PAGE_START_WOFFSET                        0x0
#define QUALENG_MIU_ADDR_PAGE_START_1_PAGE_START_DEFAULT                        _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_START_1_PAGE_START_DEFAULT_MASK                   _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_1_PAGE_START_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_1_PAGE_START_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_1_PAGE_START_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_PAGE_START_1_PAGE_START_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_ADDR_PAGE_START_2
#define QUALENG_MIU_ADDR_PAGE_START_2                   _MK_ADDR_CONST(0x148)
#define QUALENG_MIU_ADDR_PAGE_START_2_SECURE                    0x0
#define QUALENG_MIU_ADDR_PAGE_START_2_DUAL                      0x0
#define QUALENG_MIU_ADDR_PAGE_START_2_SCR                       0
#define QUALENG_MIU_ADDR_PAGE_START_2_WORD_COUNT                        0x1
#define QUALENG_MIU_ADDR_PAGE_START_2_RESET_VAL                         _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_START_2_RESET_MASK                        _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_2_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_2_READ_MASK                         _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_2_WRITE_MASK                        _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_2_PAGE_START_SHIFT                  _MK_SHIFT_CONST(0)
#define QUALENG_MIU_ADDR_PAGE_START_2_PAGE_START_FIELD                  _MK_FIELD_CONST(0x3ffffff, QUALENG_MIU_ADDR_PAGE_START_2_PAGE_START_SHIFT)
#define QUALENG_MIU_ADDR_PAGE_START_2_PAGE_START_RANGE                  25:0
#define QUALENG_MIU_ADDR_PAGE_START_2_PAGE_START_WOFFSET                        0x0
#define QUALENG_MIU_ADDR_PAGE_START_2_PAGE_START_DEFAULT                        _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_START_2_PAGE_START_DEFAULT_MASK                   _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_2_PAGE_START_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_2_PAGE_START_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_2_PAGE_START_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_PAGE_START_2_PAGE_START_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_ADDR_PAGE_START_3
#define QUALENG_MIU_ADDR_PAGE_START_3                   _MK_ADDR_CONST(0x14c)
#define QUALENG_MIU_ADDR_PAGE_START_3_SECURE                    0x0
#define QUALENG_MIU_ADDR_PAGE_START_3_DUAL                      0x0
#define QUALENG_MIU_ADDR_PAGE_START_3_SCR                       0
#define QUALENG_MIU_ADDR_PAGE_START_3_WORD_COUNT                        0x1
#define QUALENG_MIU_ADDR_PAGE_START_3_RESET_VAL                         _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_START_3_RESET_MASK                        _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_3_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_3_READ_MASK                         _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_3_WRITE_MASK                        _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_3_PAGE_START_SHIFT                  _MK_SHIFT_CONST(0)
#define QUALENG_MIU_ADDR_PAGE_START_3_PAGE_START_FIELD                  _MK_FIELD_CONST(0x3ffffff, QUALENG_MIU_ADDR_PAGE_START_3_PAGE_START_SHIFT)
#define QUALENG_MIU_ADDR_PAGE_START_3_PAGE_START_RANGE                  25:0
#define QUALENG_MIU_ADDR_PAGE_START_3_PAGE_START_WOFFSET                        0x0
#define QUALENG_MIU_ADDR_PAGE_START_3_PAGE_START_DEFAULT                        _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_START_3_PAGE_START_DEFAULT_MASK                   _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_3_PAGE_START_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_3_PAGE_START_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_3_PAGE_START_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_PAGE_START_3_PAGE_START_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_ADDR_PAGE_START_4
#define QUALENG_MIU_ADDR_PAGE_START_4                   _MK_ADDR_CONST(0x150)
#define QUALENG_MIU_ADDR_PAGE_START_4_SECURE                    0x0
#define QUALENG_MIU_ADDR_PAGE_START_4_DUAL                      0x0
#define QUALENG_MIU_ADDR_PAGE_START_4_SCR                       0
#define QUALENG_MIU_ADDR_PAGE_START_4_WORD_COUNT                        0x1
#define QUALENG_MIU_ADDR_PAGE_START_4_RESET_VAL                         _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_START_4_RESET_MASK                        _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_4_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_4_READ_MASK                         _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_4_WRITE_MASK                        _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_4_PAGE_START_SHIFT                  _MK_SHIFT_CONST(0)
#define QUALENG_MIU_ADDR_PAGE_START_4_PAGE_START_FIELD                  _MK_FIELD_CONST(0x3ffffff, QUALENG_MIU_ADDR_PAGE_START_4_PAGE_START_SHIFT)
#define QUALENG_MIU_ADDR_PAGE_START_4_PAGE_START_RANGE                  25:0
#define QUALENG_MIU_ADDR_PAGE_START_4_PAGE_START_WOFFSET                        0x0
#define QUALENG_MIU_ADDR_PAGE_START_4_PAGE_START_DEFAULT                        _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_START_4_PAGE_START_DEFAULT_MASK                   _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_4_PAGE_START_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_4_PAGE_START_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_4_PAGE_START_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_PAGE_START_4_PAGE_START_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_ADDR_PAGE_START_5
#define QUALENG_MIU_ADDR_PAGE_START_5                   _MK_ADDR_CONST(0x154)
#define QUALENG_MIU_ADDR_PAGE_START_5_SECURE                    0x0
#define QUALENG_MIU_ADDR_PAGE_START_5_DUAL                      0x0
#define QUALENG_MIU_ADDR_PAGE_START_5_SCR                       0
#define QUALENG_MIU_ADDR_PAGE_START_5_WORD_COUNT                        0x1
#define QUALENG_MIU_ADDR_PAGE_START_5_RESET_VAL                         _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_START_5_RESET_MASK                        _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_5_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_5_READ_MASK                         _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_5_WRITE_MASK                        _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_5_PAGE_START_SHIFT                  _MK_SHIFT_CONST(0)
#define QUALENG_MIU_ADDR_PAGE_START_5_PAGE_START_FIELD                  _MK_FIELD_CONST(0x3ffffff, QUALENG_MIU_ADDR_PAGE_START_5_PAGE_START_SHIFT)
#define QUALENG_MIU_ADDR_PAGE_START_5_PAGE_START_RANGE                  25:0
#define QUALENG_MIU_ADDR_PAGE_START_5_PAGE_START_WOFFSET                        0x0
#define QUALENG_MIU_ADDR_PAGE_START_5_PAGE_START_DEFAULT                        _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_START_5_PAGE_START_DEFAULT_MASK                   _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_5_PAGE_START_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_5_PAGE_START_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_5_PAGE_START_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_PAGE_START_5_PAGE_START_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_ADDR_PAGE_START_6
#define QUALENG_MIU_ADDR_PAGE_START_6                   _MK_ADDR_CONST(0x158)
#define QUALENG_MIU_ADDR_PAGE_START_6_SECURE                    0x0
#define QUALENG_MIU_ADDR_PAGE_START_6_DUAL                      0x0
#define QUALENG_MIU_ADDR_PAGE_START_6_SCR                       0
#define QUALENG_MIU_ADDR_PAGE_START_6_WORD_COUNT                        0x1
#define QUALENG_MIU_ADDR_PAGE_START_6_RESET_VAL                         _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_START_6_RESET_MASK                        _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_6_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_6_READ_MASK                         _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_6_WRITE_MASK                        _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_6_PAGE_START_SHIFT                  _MK_SHIFT_CONST(0)
#define QUALENG_MIU_ADDR_PAGE_START_6_PAGE_START_FIELD                  _MK_FIELD_CONST(0x3ffffff, QUALENG_MIU_ADDR_PAGE_START_6_PAGE_START_SHIFT)
#define QUALENG_MIU_ADDR_PAGE_START_6_PAGE_START_RANGE                  25:0
#define QUALENG_MIU_ADDR_PAGE_START_6_PAGE_START_WOFFSET                        0x0
#define QUALENG_MIU_ADDR_PAGE_START_6_PAGE_START_DEFAULT                        _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_START_6_PAGE_START_DEFAULT_MASK                   _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_6_PAGE_START_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_6_PAGE_START_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_6_PAGE_START_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_PAGE_START_6_PAGE_START_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_ADDR_PAGE_START_7
#define QUALENG_MIU_ADDR_PAGE_START_7                   _MK_ADDR_CONST(0x15c)
#define QUALENG_MIU_ADDR_PAGE_START_7_SECURE                    0x0
#define QUALENG_MIU_ADDR_PAGE_START_7_DUAL                      0x0
#define QUALENG_MIU_ADDR_PAGE_START_7_SCR                       0
#define QUALENG_MIU_ADDR_PAGE_START_7_WORD_COUNT                        0x1
#define QUALENG_MIU_ADDR_PAGE_START_7_RESET_VAL                         _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_START_7_RESET_MASK                        _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_7_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_7_READ_MASK                         _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_7_WRITE_MASK                        _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_7_PAGE_START_SHIFT                  _MK_SHIFT_CONST(0)
#define QUALENG_MIU_ADDR_PAGE_START_7_PAGE_START_FIELD                  _MK_FIELD_CONST(0x3ffffff, QUALENG_MIU_ADDR_PAGE_START_7_PAGE_START_SHIFT)
#define QUALENG_MIU_ADDR_PAGE_START_7_PAGE_START_RANGE                  25:0
#define QUALENG_MIU_ADDR_PAGE_START_7_PAGE_START_WOFFSET                        0x0
#define QUALENG_MIU_ADDR_PAGE_START_7_PAGE_START_DEFAULT                        _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_START_7_PAGE_START_DEFAULT_MASK                   _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_START_7_PAGE_START_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_7_PAGE_START_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_START_7_PAGE_START_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_PAGE_START_7_PAGE_START_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_ADDR_PAGE_END_0
#define QUALENG_MIU_ADDR_PAGE_END_0                     _MK_ADDR_CONST(0x160)
#define QUALENG_MIU_ADDR_PAGE_END_0_SECURE                      0x0
#define QUALENG_MIU_ADDR_PAGE_END_0_DUAL                        0x0
#define QUALENG_MIU_ADDR_PAGE_END_0_SCR                         0
#define QUALENG_MIU_ADDR_PAGE_END_0_WORD_COUNT                  0x1
#define QUALENG_MIU_ADDR_PAGE_END_0_RESET_VAL                   _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_END_0_RESET_MASK                  _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_0_READ_MASK                   _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_0_WRITE_MASK                  _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_0_PAGE_END_SHIFT                      _MK_SHIFT_CONST(0)
#define QUALENG_MIU_ADDR_PAGE_END_0_PAGE_END_FIELD                      _MK_FIELD_CONST(0x3ffffff, QUALENG_MIU_ADDR_PAGE_END_0_PAGE_END_SHIFT)
#define QUALENG_MIU_ADDR_PAGE_END_0_PAGE_END_RANGE                      25:0
#define QUALENG_MIU_ADDR_PAGE_END_0_PAGE_END_WOFFSET                    0x0
#define QUALENG_MIU_ADDR_PAGE_END_0_PAGE_END_DEFAULT                    _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_END_0_PAGE_END_DEFAULT_MASK                       _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_0_PAGE_END_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_0_PAGE_END_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_0_PAGE_END_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_PAGE_END_0_PAGE_END_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_ADDR_PAGE_END
#define QUALENG_MIU_ADDR_PAGE_END                       _MK_ADDR_CONST(0x160)
#define QUALENG_MIU_ADDR_PAGE_END_SECURE                        0x0
#define QUALENG_MIU_ADDR_PAGE_END_DUAL                  0x0
#define QUALENG_MIU_ADDR_PAGE_END_SCR                   0
#define QUALENG_MIU_ADDR_PAGE_END_WORD_COUNT                    0x1
#define QUALENG_MIU_ADDR_PAGE_END_RESET_VAL                     _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_END_RESET_MASK                    _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_READ_MASK                     _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_WRITE_MASK                    _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_PAGE_END_SHIFT                        _MK_SHIFT_CONST(0)
#define QUALENG_MIU_ADDR_PAGE_END_PAGE_END_FIELD                        _MK_FIELD_CONST(0x3ffffff, QUALENG_MIU_ADDR_PAGE_END_PAGE_END_SHIFT)
#define QUALENG_MIU_ADDR_PAGE_END_PAGE_END_RANGE                        25:0
#define QUALENG_MIU_ADDR_PAGE_END_PAGE_END_WOFFSET                      0x0
#define QUALENG_MIU_ADDR_PAGE_END_PAGE_END_DEFAULT                      _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_END_PAGE_END_DEFAULT_MASK                 _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_PAGE_END_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_PAGE_END_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_PAGE_END_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_PAGE_END_PAGE_END_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_ADDR_PAGE_END_1
#define QUALENG_MIU_ADDR_PAGE_END_1                     _MK_ADDR_CONST(0x164)
#define QUALENG_MIU_ADDR_PAGE_END_1_SECURE                      0x0
#define QUALENG_MIU_ADDR_PAGE_END_1_DUAL                        0x0
#define QUALENG_MIU_ADDR_PAGE_END_1_SCR                         0
#define QUALENG_MIU_ADDR_PAGE_END_1_WORD_COUNT                  0x1
#define QUALENG_MIU_ADDR_PAGE_END_1_RESET_VAL                   _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_END_1_RESET_MASK                  _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_1_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_1_READ_MASK                   _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_1_WRITE_MASK                  _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_1_PAGE_END_SHIFT                      _MK_SHIFT_CONST(0)
#define QUALENG_MIU_ADDR_PAGE_END_1_PAGE_END_FIELD                      _MK_FIELD_CONST(0x3ffffff, QUALENG_MIU_ADDR_PAGE_END_1_PAGE_END_SHIFT)
#define QUALENG_MIU_ADDR_PAGE_END_1_PAGE_END_RANGE                      25:0
#define QUALENG_MIU_ADDR_PAGE_END_1_PAGE_END_WOFFSET                    0x0
#define QUALENG_MIU_ADDR_PAGE_END_1_PAGE_END_DEFAULT                    _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_END_1_PAGE_END_DEFAULT_MASK                       _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_1_PAGE_END_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_1_PAGE_END_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_1_PAGE_END_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_PAGE_END_1_PAGE_END_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_ADDR_PAGE_END_2
#define QUALENG_MIU_ADDR_PAGE_END_2                     _MK_ADDR_CONST(0x168)
#define QUALENG_MIU_ADDR_PAGE_END_2_SECURE                      0x0
#define QUALENG_MIU_ADDR_PAGE_END_2_DUAL                        0x0
#define QUALENG_MIU_ADDR_PAGE_END_2_SCR                         0
#define QUALENG_MIU_ADDR_PAGE_END_2_WORD_COUNT                  0x1
#define QUALENG_MIU_ADDR_PAGE_END_2_RESET_VAL                   _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_END_2_RESET_MASK                  _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_2_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_2_READ_MASK                   _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_2_WRITE_MASK                  _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_2_PAGE_END_SHIFT                      _MK_SHIFT_CONST(0)
#define QUALENG_MIU_ADDR_PAGE_END_2_PAGE_END_FIELD                      _MK_FIELD_CONST(0x3ffffff, QUALENG_MIU_ADDR_PAGE_END_2_PAGE_END_SHIFT)
#define QUALENG_MIU_ADDR_PAGE_END_2_PAGE_END_RANGE                      25:0
#define QUALENG_MIU_ADDR_PAGE_END_2_PAGE_END_WOFFSET                    0x0
#define QUALENG_MIU_ADDR_PAGE_END_2_PAGE_END_DEFAULT                    _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_END_2_PAGE_END_DEFAULT_MASK                       _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_2_PAGE_END_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_2_PAGE_END_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_2_PAGE_END_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_PAGE_END_2_PAGE_END_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_ADDR_PAGE_END_3
#define QUALENG_MIU_ADDR_PAGE_END_3                     _MK_ADDR_CONST(0x16c)
#define QUALENG_MIU_ADDR_PAGE_END_3_SECURE                      0x0
#define QUALENG_MIU_ADDR_PAGE_END_3_DUAL                        0x0
#define QUALENG_MIU_ADDR_PAGE_END_3_SCR                         0
#define QUALENG_MIU_ADDR_PAGE_END_3_WORD_COUNT                  0x1
#define QUALENG_MIU_ADDR_PAGE_END_3_RESET_VAL                   _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_END_3_RESET_MASK                  _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_3_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_3_READ_MASK                   _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_3_WRITE_MASK                  _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_3_PAGE_END_SHIFT                      _MK_SHIFT_CONST(0)
#define QUALENG_MIU_ADDR_PAGE_END_3_PAGE_END_FIELD                      _MK_FIELD_CONST(0x3ffffff, QUALENG_MIU_ADDR_PAGE_END_3_PAGE_END_SHIFT)
#define QUALENG_MIU_ADDR_PAGE_END_3_PAGE_END_RANGE                      25:0
#define QUALENG_MIU_ADDR_PAGE_END_3_PAGE_END_WOFFSET                    0x0
#define QUALENG_MIU_ADDR_PAGE_END_3_PAGE_END_DEFAULT                    _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_END_3_PAGE_END_DEFAULT_MASK                       _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_3_PAGE_END_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_3_PAGE_END_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_3_PAGE_END_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_PAGE_END_3_PAGE_END_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_ADDR_PAGE_END_4
#define QUALENG_MIU_ADDR_PAGE_END_4                     _MK_ADDR_CONST(0x170)
#define QUALENG_MIU_ADDR_PAGE_END_4_SECURE                      0x0
#define QUALENG_MIU_ADDR_PAGE_END_4_DUAL                        0x0
#define QUALENG_MIU_ADDR_PAGE_END_4_SCR                         0
#define QUALENG_MIU_ADDR_PAGE_END_4_WORD_COUNT                  0x1
#define QUALENG_MIU_ADDR_PAGE_END_4_RESET_VAL                   _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_END_4_RESET_MASK                  _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_4_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_4_READ_MASK                   _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_4_WRITE_MASK                  _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_4_PAGE_END_SHIFT                      _MK_SHIFT_CONST(0)
#define QUALENG_MIU_ADDR_PAGE_END_4_PAGE_END_FIELD                      _MK_FIELD_CONST(0x3ffffff, QUALENG_MIU_ADDR_PAGE_END_4_PAGE_END_SHIFT)
#define QUALENG_MIU_ADDR_PAGE_END_4_PAGE_END_RANGE                      25:0
#define QUALENG_MIU_ADDR_PAGE_END_4_PAGE_END_WOFFSET                    0x0
#define QUALENG_MIU_ADDR_PAGE_END_4_PAGE_END_DEFAULT                    _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_END_4_PAGE_END_DEFAULT_MASK                       _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_4_PAGE_END_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_4_PAGE_END_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_4_PAGE_END_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_PAGE_END_4_PAGE_END_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_ADDR_PAGE_END_5
#define QUALENG_MIU_ADDR_PAGE_END_5                     _MK_ADDR_CONST(0x174)
#define QUALENG_MIU_ADDR_PAGE_END_5_SECURE                      0x0
#define QUALENG_MIU_ADDR_PAGE_END_5_DUAL                        0x0
#define QUALENG_MIU_ADDR_PAGE_END_5_SCR                         0
#define QUALENG_MIU_ADDR_PAGE_END_5_WORD_COUNT                  0x1
#define QUALENG_MIU_ADDR_PAGE_END_5_RESET_VAL                   _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_END_5_RESET_MASK                  _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_5_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_5_READ_MASK                   _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_5_WRITE_MASK                  _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_5_PAGE_END_SHIFT                      _MK_SHIFT_CONST(0)
#define QUALENG_MIU_ADDR_PAGE_END_5_PAGE_END_FIELD                      _MK_FIELD_CONST(0x3ffffff, QUALENG_MIU_ADDR_PAGE_END_5_PAGE_END_SHIFT)
#define QUALENG_MIU_ADDR_PAGE_END_5_PAGE_END_RANGE                      25:0
#define QUALENG_MIU_ADDR_PAGE_END_5_PAGE_END_WOFFSET                    0x0
#define QUALENG_MIU_ADDR_PAGE_END_5_PAGE_END_DEFAULT                    _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_END_5_PAGE_END_DEFAULT_MASK                       _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_5_PAGE_END_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_5_PAGE_END_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_5_PAGE_END_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_PAGE_END_5_PAGE_END_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_ADDR_PAGE_END_6
#define QUALENG_MIU_ADDR_PAGE_END_6                     _MK_ADDR_CONST(0x178)
#define QUALENG_MIU_ADDR_PAGE_END_6_SECURE                      0x0
#define QUALENG_MIU_ADDR_PAGE_END_6_DUAL                        0x0
#define QUALENG_MIU_ADDR_PAGE_END_6_SCR                         0
#define QUALENG_MIU_ADDR_PAGE_END_6_WORD_COUNT                  0x1
#define QUALENG_MIU_ADDR_PAGE_END_6_RESET_VAL                   _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_END_6_RESET_MASK                  _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_6_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_6_READ_MASK                   _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_6_WRITE_MASK                  _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_6_PAGE_END_SHIFT                      _MK_SHIFT_CONST(0)
#define QUALENG_MIU_ADDR_PAGE_END_6_PAGE_END_FIELD                      _MK_FIELD_CONST(0x3ffffff, QUALENG_MIU_ADDR_PAGE_END_6_PAGE_END_SHIFT)
#define QUALENG_MIU_ADDR_PAGE_END_6_PAGE_END_RANGE                      25:0
#define QUALENG_MIU_ADDR_PAGE_END_6_PAGE_END_WOFFSET                    0x0
#define QUALENG_MIU_ADDR_PAGE_END_6_PAGE_END_DEFAULT                    _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_END_6_PAGE_END_DEFAULT_MASK                       _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_6_PAGE_END_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_6_PAGE_END_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_6_PAGE_END_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_PAGE_END_6_PAGE_END_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register QUALENG_MIU_ADDR_PAGE_END_7
#define QUALENG_MIU_ADDR_PAGE_END_7                     _MK_ADDR_CONST(0x17c)
#define QUALENG_MIU_ADDR_PAGE_END_7_SECURE                      0x0
#define QUALENG_MIU_ADDR_PAGE_END_7_DUAL                        0x0
#define QUALENG_MIU_ADDR_PAGE_END_7_SCR                         0
#define QUALENG_MIU_ADDR_PAGE_END_7_WORD_COUNT                  0x1
#define QUALENG_MIU_ADDR_PAGE_END_7_RESET_VAL                   _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_END_7_RESET_MASK                  _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_7_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_7_READ_MASK                   _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_7_WRITE_MASK                  _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_7_PAGE_END_SHIFT                      _MK_SHIFT_CONST(0)
#define QUALENG_MIU_ADDR_PAGE_END_7_PAGE_END_FIELD                      _MK_FIELD_CONST(0x3ffffff, QUALENG_MIU_ADDR_PAGE_END_7_PAGE_END_SHIFT)
#define QUALENG_MIU_ADDR_PAGE_END_7_PAGE_END_RANGE                      25:0
#define QUALENG_MIU_ADDR_PAGE_END_7_PAGE_END_WOFFSET                    0x0
#define QUALENG_MIU_ADDR_PAGE_END_7_PAGE_END_DEFAULT                    _MK_MASK_CONST(0x20000)
#define QUALENG_MIU_ADDR_PAGE_END_7_PAGE_END_DEFAULT_MASK                       _MK_MASK_CONST(0x3ffffff)
#define QUALENG_MIU_ADDR_PAGE_END_7_PAGE_END_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_7_PAGE_END_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QUALENG_MIU_ADDR_PAGE_END_7_PAGE_END_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define QUALENG_MIU_ADDR_PAGE_END_7_PAGE_END_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register QUALENG_STATUS_0
#define QUALENG_STATUS_0                        _MK_ADDR_CONST(0x230)
#define QUALENG_STATUS_0_SECURE                         0x0
#define QUALENG_STATUS_0_DUAL                   0x0
#define QUALENG_STATUS_0_SCR                    0
#define QUALENG_STATUS_0_WORD_COUNT                     0x1
#define QUALENG_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define QUALENG_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define QUALENG_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define QUALENG_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_STATUS_0_READ_MASK                      _MK_MASK_CONST(0x3)
#define QUALENG_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define QUALENG_STATUS_0_STATUS_SHIFT                   _MK_SHIFT_CONST(0)
#define QUALENG_STATUS_0_STATUS_FIELD                   _MK_FIELD_CONST(0x3, QUALENG_STATUS_0_STATUS_SHIFT)
#define QUALENG_STATUS_0_STATUS_RANGE                   1:0
#define QUALENG_STATUS_0_STATUS_WOFFSET                 0x0
#define QUALENG_STATUS_0_STATUS_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_STATUS_0_STATUS_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QUALENG_STATUS_0_STATUS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define QUALENG_STATUS_0_STATUS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define QUALENG_STATUS_0_STATUS_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define QUALENG_STATUS_0_STATUS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define QUALENG_STATUS_0_STATUS_IDLE                    _MK_ENUM_CONST(0)
#define QUALENG_STATUS_0_STATUS_BUSY                    _MK_ENUM_CONST(1)
#define QUALENG_STATUS_0_STATUS_STOP_ON_ERROR                   _MK_ENUM_CONST(2)
#define QUALENG_STATUS_0_STATUS_STOP_ON_ERROR_IDLE                      _MK_ENUM_CONST(3)

// Register QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_0
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_0                  _MK_ADDR_CONST(0x800)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_0_SECURE                   0x0
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_0_DUAL                     0x0
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_0_SCR                      0
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_0_WORD_COUNT                       0x1
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_0_RESET_MASK                       _MK_MASK_CONST(0xfffffe00)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_0_READ_MASK                        _MK_MASK_CONST(0xfffffe00)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffe00)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_0_EMEM_CHANNEL_MASK_SHIFT                  _MK_SHIFT_CONST(9)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_0_EMEM_CHANNEL_MASK_FIELD                  _MK_FIELD_CONST(0x7fffff, QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_0_EMEM_CHANNEL_MASK_SHIFT)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_0_EMEM_CHANNEL_MASK_RANGE                  31:9
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_0_EMEM_CHANNEL_MASK_WOFFSET                        0x0
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_0_EMEM_CHANNEL_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_0_EMEM_CHANNEL_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x7fffff)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_0_EMEM_CHANNEL_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_0_EMEM_CHANNEL_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_0_EMEM_CHANNEL_MASK_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_0_EMEM_CHANNEL_MASK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_1_0
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_1_0                        _MK_ADDR_CONST(0x804)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_1_0_SECURE                         0x0
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_1_0_DUAL                   0x0
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_1_0_SCR                    0
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_1_0_WORD_COUNT                     0x1
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_1_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_1_0_RESET_MASK                     _MK_MASK_CONST(0xfffffe00)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_1_0_READ_MASK                      _MK_MASK_CONST(0xfffffe00)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_1_0_WRITE_MASK                     _MK_MASK_CONST(0xfffffe00)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_1_0_EMEM_CHANNEL_MASK_1_SHIFT                      _MK_SHIFT_CONST(9)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_1_0_EMEM_CHANNEL_MASK_1_FIELD                      _MK_FIELD_CONST(0x7fffff, QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_1_0_EMEM_CHANNEL_MASK_1_SHIFT)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_1_0_EMEM_CHANNEL_MASK_1_RANGE                      31:9
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_1_0_EMEM_CHANNEL_MASK_1_WOFFSET                    0x0
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_1_0_EMEM_CHANNEL_MASK_1_DEFAULT                    _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_1_0_EMEM_CHANNEL_MASK_1_DEFAULT_MASK                       _MK_MASK_CONST(0x7fffff)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_1_0_EMEM_CHANNEL_MASK_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_1_0_EMEM_CHANNEL_MASK_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_1_0_EMEM_CHANNEL_MASK_1_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_1_0_EMEM_CHANNEL_MASK_1_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_2_0
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_2_0                        _MK_ADDR_CONST(0x808)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_2_0_SECURE                         0x0
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_2_0_DUAL                   0x0
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_2_0_SCR                    0
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_2_0_WORD_COUNT                     0x1
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_2_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_2_0_RESET_MASK                     _MK_MASK_CONST(0xfffffe00)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_2_0_READ_MASK                      _MK_MASK_CONST(0xfffffe00)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_2_0_WRITE_MASK                     _MK_MASK_CONST(0xfffffe00)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_2_0_EMEM_CHANNEL_MASK_2_SHIFT                      _MK_SHIFT_CONST(9)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_2_0_EMEM_CHANNEL_MASK_2_FIELD                      _MK_FIELD_CONST(0x7fffff, QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_2_0_EMEM_CHANNEL_MASK_2_SHIFT)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_2_0_EMEM_CHANNEL_MASK_2_RANGE                      31:9
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_2_0_EMEM_CHANNEL_MASK_2_WOFFSET                    0x0
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_2_0_EMEM_CHANNEL_MASK_2_DEFAULT                    _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_2_0_EMEM_CHANNEL_MASK_2_DEFAULT_MASK                       _MK_MASK_CONST(0x7fffff)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_2_0_EMEM_CHANNEL_MASK_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_2_0_EMEM_CHANNEL_MASK_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_2_0_EMEM_CHANNEL_MASK_2_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_2_0_EMEM_CHANNEL_MASK_2_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_3_0
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_3_0                        _MK_ADDR_CONST(0x80c)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_3_0_SECURE                         0x0
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_3_0_DUAL                   0x0
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_3_0_SCR                    0
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_3_0_WORD_COUNT                     0x1
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_3_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_3_0_RESET_MASK                     _MK_MASK_CONST(0xfffffe00)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_3_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_3_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_3_0_READ_MASK                      _MK_MASK_CONST(0xfffffe00)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_3_0_WRITE_MASK                     _MK_MASK_CONST(0xfffffe00)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_3_0_EMEM_CHANNEL_MASK_3_SHIFT                      _MK_SHIFT_CONST(9)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_3_0_EMEM_CHANNEL_MASK_3_FIELD                      _MK_FIELD_CONST(0x7fffff, QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_3_0_EMEM_CHANNEL_MASK_3_SHIFT)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_3_0_EMEM_CHANNEL_MASK_3_RANGE                      31:9
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_3_0_EMEM_CHANNEL_MASK_3_WOFFSET                    0x0
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_3_0_EMEM_CHANNEL_MASK_3_DEFAULT                    _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_3_0_EMEM_CHANNEL_MASK_3_DEFAULT_MASK                       _MK_MASK_CONST(0x7fffff)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_3_0_EMEM_CHANNEL_MASK_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_3_0_EMEM_CHANNEL_MASK_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_3_0_EMEM_CHANNEL_MASK_3_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_3_0_EMEM_CHANNEL_MASK_3_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register QUALENG_MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0                        _MK_ADDR_CONST(0x810)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0_SECURE                         0x0
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0_DUAL                   0x0
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0_SCR                    0
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0_WORD_COUNT                     0x1
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0_RESET_VAL                      _MK_MASK_CONST(0xf)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0_RESET_MASK                     _MK_MASK_CONST(0xffff)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0_READ_MASK                      _MK_MASK_CONST(0xffff)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0_WRITE_MASK                     _MK_MASK_CONST(0xffff)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0_EMEM_CHANNEL_ENABLE_SHIFT                      _MK_SHIFT_CONST(0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0_EMEM_CHANNEL_ENABLE_FIELD                      _MK_FIELD_CONST(0xffff, QUALENG_MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0_EMEM_CHANNEL_ENABLE_SHIFT)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0_EMEM_CHANNEL_ENABLE_RANGE                      15:0
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0_EMEM_CHANNEL_ENABLE_WOFFSET                    0x0
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0_EMEM_CHANNEL_ENABLE_DEFAULT                    _MK_MASK_CONST(0xf)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0_EMEM_CHANNEL_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0_EMEM_CHANNEL_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0_EMEM_CHANNEL_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0_EMEM_CHANNEL_ENABLE_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define QUALENG_MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0_EMEM_CHANNEL_ENABLE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Reserved address 0x1020

// Reserved address 0x1024

// Reserved address 0x1028

// Reserved address 0x102c

// Reserved address 0x104c

// Reserved address 0x1054

// Reserved address 0x1058

// Reserved address 0x105c

// Reserved address 0x107c

// Reserved address 0x1084

// Reserved address 0x1088

// Reserved address 0x108c

// Reserved address 0x10ac

// Reserved address 0x10b4

// Reserved address 0x10b8

// Reserved address 0x10bc

//
// REGISTER LIST
//
#define LIST_ARQUALENG_REGS(_op_) \
_op_(QUALENG_TRAFFIC_CTRL_0) \
_op_(QUALENG_PATTERN_0) \
_op_(QUALENG_MIU_TRAFFIC_CTRL_0) \
_op_(QUALENG_MIU_TRAFFIC_CTRL) \
_op_(QUALENG_MIU_TRAFFIC_CTRL_1) \
_op_(QUALENG_MIU_TRAFFIC_CTRL_2) \
_op_(QUALENG_MIU_TRAFFIC_CTRL_3) \
_op_(QUALENG_MIU_TRAFFIC_CTRL_4) \
_op_(QUALENG_MIU_TRAFFIC_CTRL_5) \
_op_(QUALENG_MIU_TRAFFIC_CTRL_6) \
_op_(QUALENG_MIU_TRAFFIC_CTRL_7) \
_op_(QUALENG_MIU_TRAFFIC_INTERLEAVE_0) \
_op_(QUALENG_MIU_TRAFFIC_INTERLEAVE) \
_op_(QUALENG_MIU_TRAFFIC_INTERLEAVE_1) \
_op_(QUALENG_MIU_TRAFFIC_INTERLEAVE_2) \
_op_(QUALENG_MIU_TRAFFIC_INTERLEAVE_3) \
_op_(QUALENG_MIU_TRAFFIC_INTERLEAVE_4) \
_op_(QUALENG_MIU_TRAFFIC_INTERLEAVE_5) \
_op_(QUALENG_MIU_TRAFFIC_INTERLEAVE_6) \
_op_(QUALENG_MIU_TRAFFIC_INTERLEAVE_7) \
_op_(QUALENG_MIU_TRAFFIC_TURNS_LOW_0) \
_op_(QUALENG_MIU_TRAFFIC_TURNS_LOW) \
_op_(QUALENG_MIU_TRAFFIC_TURNS_LOW_1) \
_op_(QUALENG_MIU_TRAFFIC_TURNS_LOW_2) \
_op_(QUALENG_MIU_TRAFFIC_TURNS_LOW_3) \
_op_(QUALENG_MIU_TRAFFIC_TURNS_LOW_4) \
_op_(QUALENG_MIU_TRAFFIC_TURNS_LOW_5) \
_op_(QUALENG_MIU_TRAFFIC_TURNS_LOW_6) \
_op_(QUALENG_MIU_TRAFFIC_TURNS_LOW_7) \
_op_(QUALENG_MIU_ADDR_CFG_0) \
_op_(QUALENG_MIU_ADDR_CFG) \
_op_(QUALENG_MIU_ADDR_CFG_1) \
_op_(QUALENG_MIU_ADDR_CFG_2) \
_op_(QUALENG_MIU_ADDR_CFG_3) \
_op_(QUALENG_MIU_ADDR_CFG_4) \
_op_(QUALENG_MIU_ADDR_CFG_5) \
_op_(QUALENG_MIU_ADDR_CFG_6) \
_op_(QUALENG_MIU_ADDR_CFG_7) \
_op_(QUALENG_MIU_ADDR_PAGE_START_0) \
_op_(QUALENG_MIU_ADDR_PAGE_START) \
_op_(QUALENG_MIU_ADDR_PAGE_START_1) \
_op_(QUALENG_MIU_ADDR_PAGE_START_2) \
_op_(QUALENG_MIU_ADDR_PAGE_START_3) \
_op_(QUALENG_MIU_ADDR_PAGE_START_4) \
_op_(QUALENG_MIU_ADDR_PAGE_START_5) \
_op_(QUALENG_MIU_ADDR_PAGE_START_6) \
_op_(QUALENG_MIU_ADDR_PAGE_START_7) \
_op_(QUALENG_MIU_ADDR_PAGE_END_0) \
_op_(QUALENG_MIU_ADDR_PAGE_END) \
_op_(QUALENG_MIU_ADDR_PAGE_END_1) \
_op_(QUALENG_MIU_ADDR_PAGE_END_2) \
_op_(QUALENG_MIU_ADDR_PAGE_END_3) \
_op_(QUALENG_MIU_ADDR_PAGE_END_4) \
_op_(QUALENG_MIU_ADDR_PAGE_END_5) \
_op_(QUALENG_MIU_ADDR_PAGE_END_6) \
_op_(QUALENG_MIU_ADDR_PAGE_END_7) \
_op_(QUALENG_STATUS_0) \
_op_(QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_0) \
_op_(QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_1_0) \
_op_(QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_2_0) \
_op_(QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_3_0) \
_op_(QUALENG_MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0) \

//
// ADDRESS SPACES
//

#define BASE_ADDRESS_QUALENG    0x00000000
#define BASE_ADDRESS_QUALENG_EC 0x00001000
#define BASE_ADDRESS_QUALENG_DEBUG      0x00001200

//
// ARQUALENG REGISTER BANKS
//

#define QUALENG0_FIRST_REG 0x0000 // QUALENG_TRAFFIC_CTRL_0
#define QUALENG1_FIRST_REG 0x0020 // QUALENG_MIU_TRAFFIC_CTRL_0
#define QUALENG3_LAST_REG 0x0230 // QUALENG_STATUS_0
#define QUALENG7_FIRST_REG 0x0800 // QUALENG_MC_EMEM_ADR_CFG_CHANNEL_MASK_0
#define QUALENG7_LAST_REG 0x0810 // QUALENG_MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif
#ifndef _MK_FIELD_CONST
  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
#endif

#endif // ifndef ___ARQUALENG_H_INC_
