//
// Copyright (c) 2018 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ___ARQSPI_H_INC_
#define ___ARQSPI_H_INC_
#define NV_MOBILE_ARQSPI_H_UNIT_OF_OFFSET 1B


// Register QSPI_COMMAND_0
#define QSPI_COMMAND_0                  _MK_ADDR_CONST(0x0)
#define QSPI_COMMAND_0_SECURE                   0x0
#define QSPI_COMMAND_0_DUAL                     0x0
#define QSPI_COMMAND_0_SCR                      0
#define QSPI_COMMAND_0_WORD_COUNT                       0x1
#define QSPI_COMMAND_0_RESET_VAL                        _MK_MASK_CONST(0x4050001f)
#define QSPI_COMMAND_0_RESET_MASK                       _MK_MASK_CONST(0xfc7f9bbf)
#define QSPI_COMMAND_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_READ_MASK                        _MK_MASK_CONST(0xfc7f9bbf)
#define QSPI_COMMAND_0_WRITE_MASK                       _MK_MASK_CONST(0xfc7f9bbf)
#define QSPI_COMMAND_0_PIO_SHIFT                        _MK_SHIFT_CONST(31)
#define QSPI_COMMAND_0_PIO_FIELD                        _MK_FIELD_CONST(0x1, QSPI_COMMAND_0_PIO_SHIFT)
#define QSPI_COMMAND_0_PIO_RANGE                        31:31
#define QSPI_COMMAND_0_PIO_WOFFSET                      0x0
#define QSPI_COMMAND_0_PIO_DEFAULT                      _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_PIO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_PIO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_PIO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_PIO_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_PIO_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_PIO_STOP                 _MK_ENUM_CONST(0)
#define QSPI_COMMAND_0_PIO_PIO                  _MK_ENUM_CONST(1)

#define QSPI_COMMAND_0_M_S_SHIFT                        _MK_SHIFT_CONST(30)
#define QSPI_COMMAND_0_M_S_FIELD                        _MK_FIELD_CONST(0x1, QSPI_COMMAND_0_M_S_SHIFT)
#define QSPI_COMMAND_0_M_S_RANGE                        30:30
#define QSPI_COMMAND_0_M_S_WOFFSET                      0x0
#define QSPI_COMMAND_0_M_S_DEFAULT                      _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_M_S_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_M_S_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_M_S_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_M_S_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_M_S_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_M_S_RSVD                 _MK_ENUM_CONST(0)
#define QSPI_COMMAND_0_M_S_MASTER                       _MK_ENUM_CONST(1)

#define QSPI_COMMAND_0_MODE_SHIFT                       _MK_SHIFT_CONST(28)
#define QSPI_COMMAND_0_MODE_FIELD                       _MK_FIELD_CONST(0x3, QSPI_COMMAND_0_MODE_SHIFT)
#define QSPI_COMMAND_0_MODE_RANGE                       29:28
#define QSPI_COMMAND_0_MODE_WOFFSET                     0x0
#define QSPI_COMMAND_0_MODE_DEFAULT                     _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_MODE_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define QSPI_COMMAND_0_MODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_MODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_MODE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_MODE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_MODE_Mode0                       _MK_ENUM_CONST(0)
#define QSPI_COMMAND_0_MODE_RSVD1                       _MK_ENUM_CONST(1)
#define QSPI_COMMAND_0_MODE_RSVD2                       _MK_ENUM_CONST(2)
#define QSPI_COMMAND_0_MODE_Mode3                       _MK_ENUM_CONST(3)

#define QSPI_COMMAND_0_CS_SEL_SHIFT                     _MK_SHIFT_CONST(26)
#define QSPI_COMMAND_0_CS_SEL_FIELD                     _MK_FIELD_CONST(0x3, QSPI_COMMAND_0_CS_SEL_SHIFT)
#define QSPI_COMMAND_0_CS_SEL_RANGE                     27:26
#define QSPI_COMMAND_0_CS_SEL_WOFFSET                   0x0
#define QSPI_COMMAND_0_CS_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_CS_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define QSPI_COMMAND_0_CS_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_CS_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_CS_SEL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_CS_SEL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_CS_SEL_CS0                       _MK_ENUM_CONST(0)
#define QSPI_COMMAND_0_CS_SEL_RSVD1                     _MK_ENUM_CONST(1)
#define QSPI_COMMAND_0_CS_SEL_RSVD2                     _MK_ENUM_CONST(2)
#define QSPI_COMMAND_0_CS_SEL_RSVD3                     _MK_ENUM_CONST(3)

#define QSPI_COMMAND_0_CS_POL_INACTIVE0_SHIFT                   _MK_SHIFT_CONST(22)
#define QSPI_COMMAND_0_CS_POL_INACTIVE0_FIELD                   _MK_FIELD_CONST(0x1, QSPI_COMMAND_0_CS_POL_INACTIVE0_SHIFT)
#define QSPI_COMMAND_0_CS_POL_INACTIVE0_RANGE                   22:22
#define QSPI_COMMAND_0_CS_POL_INACTIVE0_WOFFSET                 0x0
#define QSPI_COMMAND_0_CS_POL_INACTIVE0_DEFAULT                 _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_CS_POL_INACTIVE0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_CS_POL_INACTIVE0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_CS_POL_INACTIVE0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_CS_POL_INACTIVE0_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_CS_POL_INACTIVE0_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_CS_POL_INACTIVE0_LOW                     _MK_ENUM_CONST(0)
#define QSPI_COMMAND_0_CS_POL_INACTIVE0_HIGH                    _MK_ENUM_CONST(1)

#define QSPI_COMMAND_0_CS_SW_HW_SHIFT                   _MK_SHIFT_CONST(21)
#define QSPI_COMMAND_0_CS_SW_HW_FIELD                   _MK_FIELD_CONST(0x1, QSPI_COMMAND_0_CS_SW_HW_SHIFT)
#define QSPI_COMMAND_0_CS_SW_HW_RANGE                   21:21
#define QSPI_COMMAND_0_CS_SW_HW_WOFFSET                 0x0
#define QSPI_COMMAND_0_CS_SW_HW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_CS_SW_HW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_CS_SW_HW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_CS_SW_HW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_CS_SW_HW_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_CS_SW_HW_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_CS_SW_HW_HARDWARE                        _MK_ENUM_CONST(0)
#define QSPI_COMMAND_0_CS_SW_HW_SOFTWARE                        _MK_ENUM_CONST(1)

#define QSPI_COMMAND_0_CS_SW_VAL_SHIFT                  _MK_SHIFT_CONST(20)
#define QSPI_COMMAND_0_CS_SW_VAL_FIELD                  _MK_FIELD_CONST(0x1, QSPI_COMMAND_0_CS_SW_VAL_SHIFT)
#define QSPI_COMMAND_0_CS_SW_VAL_RANGE                  20:20
#define QSPI_COMMAND_0_CS_SW_VAL_WOFFSET                        0x0
#define QSPI_COMMAND_0_CS_SW_VAL_DEFAULT                        _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_CS_SW_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_CS_SW_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_CS_SW_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_CS_SW_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_CS_SW_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_CS_SW_VAL_LOW                    _MK_ENUM_CONST(0)
#define QSPI_COMMAND_0_CS_SW_VAL_HIGH                   _MK_ENUM_CONST(1)

#define QSPI_COMMAND_0_IDLE_SDA_SHIFT                   _MK_SHIFT_CONST(18)
#define QSPI_COMMAND_0_IDLE_SDA_FIELD                   _MK_FIELD_CONST(0x3, QSPI_COMMAND_0_IDLE_SDA_SHIFT)
#define QSPI_COMMAND_0_IDLE_SDA_RANGE                   19:18
#define QSPI_COMMAND_0_IDLE_SDA_WOFFSET                 0x0
#define QSPI_COMMAND_0_IDLE_SDA_DEFAULT                 _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_IDLE_SDA_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define QSPI_COMMAND_0_IDLE_SDA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_IDLE_SDA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_IDLE_SDA_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_IDLE_SDA_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_IDLE_SDA_DRIVE_LOW                       _MK_ENUM_CONST(0)
#define QSPI_COMMAND_0_IDLE_SDA_DRIVE_HIGH                      _MK_ENUM_CONST(1)
#define QSPI_COMMAND_0_IDLE_SDA_PULL_LOW                        _MK_ENUM_CONST(2)
#define QSPI_COMMAND_0_IDLE_SDA_PULL_HIGH                       _MK_ENUM_CONST(3)

#define QSPI_COMMAND_0_BIDIR_SHIFT                      _MK_SHIFT_CONST(17)
#define QSPI_COMMAND_0_BIDIR_FIELD                      _MK_FIELD_CONST(0x1, QSPI_COMMAND_0_BIDIR_SHIFT)
#define QSPI_COMMAND_0_BIDIR_RANGE                      17:17
#define QSPI_COMMAND_0_BIDIR_WOFFSET                    0x0
#define QSPI_COMMAND_0_BIDIR_DEFAULT                    _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_BIDIR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_BIDIR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_BIDIR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_BIDIR_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_BIDIR_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_BIDIR_NORMAL                     _MK_ENUM_CONST(0)
#define QSPI_COMMAND_0_BIDIR_BIDIR                      _MK_ENUM_CONST(1)

#define QSPI_COMMAND_0_En_LE_Bit_SHIFT                  _MK_SHIFT_CONST(16)
#define QSPI_COMMAND_0_En_LE_Bit_FIELD                  _MK_FIELD_CONST(0x1, QSPI_COMMAND_0_En_LE_Bit_SHIFT)
#define QSPI_COMMAND_0_En_LE_Bit_RANGE                  16:16
#define QSPI_COMMAND_0_En_LE_Bit_WOFFSET                        0x0
#define QSPI_COMMAND_0_En_LE_Bit_DEFAULT                        _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_En_LE_Bit_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_En_LE_Bit_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_En_LE_Bit_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_En_LE_Bit_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_En_LE_Bit_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_En_LE_Bit_LAST                   _MK_ENUM_CONST(0)
#define QSPI_COMMAND_0_En_LE_Bit_FIRST                  _MK_ENUM_CONST(1)

#define QSPI_COMMAND_0_En_LE_Byte_SHIFT                 _MK_SHIFT_CONST(15)
#define QSPI_COMMAND_0_En_LE_Byte_FIELD                 _MK_FIELD_CONST(0x1, QSPI_COMMAND_0_En_LE_Byte_SHIFT)
#define QSPI_COMMAND_0_En_LE_Byte_RANGE                 15:15
#define QSPI_COMMAND_0_En_LE_Byte_WOFFSET                       0x0
#define QSPI_COMMAND_0_En_LE_Byte_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_En_LE_Byte_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_En_LE_Byte_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_En_LE_Byte_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_En_LE_Byte_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_En_LE_Byte_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_En_LE_Byte_LAST                  _MK_ENUM_CONST(0)
#define QSPI_COMMAND_0_En_LE_Byte_FIRST                 _MK_ENUM_CONST(1)

#define QSPI_COMMAND_0_Rx_EN_SHIFT                      _MK_SHIFT_CONST(12)
#define QSPI_COMMAND_0_Rx_EN_FIELD                      _MK_FIELD_CONST(0x1, QSPI_COMMAND_0_Rx_EN_SHIFT)
#define QSPI_COMMAND_0_Rx_EN_RANGE                      12:12
#define QSPI_COMMAND_0_Rx_EN_WOFFSET                    0x0
#define QSPI_COMMAND_0_Rx_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_Rx_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_Rx_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_Rx_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_Rx_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_Rx_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_Rx_EN_DISABLE                    _MK_ENUM_CONST(0)
#define QSPI_COMMAND_0_Rx_EN_ENABLE                     _MK_ENUM_CONST(1)

#define QSPI_COMMAND_0_Tx_EN_SHIFT                      _MK_SHIFT_CONST(11)
#define QSPI_COMMAND_0_Tx_EN_FIELD                      _MK_FIELD_CONST(0x1, QSPI_COMMAND_0_Tx_EN_SHIFT)
#define QSPI_COMMAND_0_Tx_EN_RANGE                      11:11
#define QSPI_COMMAND_0_Tx_EN_WOFFSET                    0x0
#define QSPI_COMMAND_0_Tx_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_Tx_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_Tx_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_Tx_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_Tx_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_Tx_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_Tx_EN_DISABLE                    _MK_ENUM_CONST(0)
#define QSPI_COMMAND_0_Tx_EN_ENABLE                     _MK_ENUM_CONST(1)

#define QSPI_COMMAND_0_SDR_DDR_SEL_SHIFT                        _MK_SHIFT_CONST(9)
#define QSPI_COMMAND_0_SDR_DDR_SEL_FIELD                        _MK_FIELD_CONST(0x1, QSPI_COMMAND_0_SDR_DDR_SEL_SHIFT)
#define QSPI_COMMAND_0_SDR_DDR_SEL_RANGE                        9:9
#define QSPI_COMMAND_0_SDR_DDR_SEL_WOFFSET                      0x0
#define QSPI_COMMAND_0_SDR_DDR_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_SDR_DDR_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_SDR_DDR_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_SDR_DDR_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_SDR_DDR_SEL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_SDR_DDR_SEL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_SDR_DDR_SEL_SDR                  _MK_ENUM_CONST(0)
#define QSPI_COMMAND_0_SDR_DDR_SEL_DDR                  _MK_ENUM_CONST(1)

#define QSPI_COMMAND_0_INTERFACE_WIDTH_SHIFT                    _MK_SHIFT_CONST(7)
#define QSPI_COMMAND_0_INTERFACE_WIDTH_FIELD                    _MK_FIELD_CONST(0x3, QSPI_COMMAND_0_INTERFACE_WIDTH_SHIFT)
#define QSPI_COMMAND_0_INTERFACE_WIDTH_RANGE                    8:7
#define QSPI_COMMAND_0_INTERFACE_WIDTH_WOFFSET                  0x0
#define QSPI_COMMAND_0_INTERFACE_WIDTH_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_INTERFACE_WIDTH_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define QSPI_COMMAND_0_INTERFACE_WIDTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_INTERFACE_WIDTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_INTERFACE_WIDTH_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_INTERFACE_WIDTH_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_INTERFACE_WIDTH_SINGLE                   _MK_ENUM_CONST(0)
#define QSPI_COMMAND_0_INTERFACE_WIDTH_DUAL                     _MK_ENUM_CONST(1)
#define QSPI_COMMAND_0_INTERFACE_WIDTH_QUAD                     _MK_ENUM_CONST(2)

#define QSPI_COMMAND_0_PACKED_SHIFT                     _MK_SHIFT_CONST(5)
#define QSPI_COMMAND_0_PACKED_FIELD                     _MK_FIELD_CONST(0x1, QSPI_COMMAND_0_PACKED_SHIFT)
#define QSPI_COMMAND_0_PACKED_RANGE                     5:5
#define QSPI_COMMAND_0_PACKED_WOFFSET                   0x0
#define QSPI_COMMAND_0_PACKED_DEFAULT                   _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_PACKED_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_PACKED_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_PACKED_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_PACKED_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_PACKED_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define QSPI_COMMAND_0_PACKED_DISABLE                   _MK_ENUM_CONST(0)
#define QSPI_COMMAND_0_PACKED_ENABLE                    _MK_ENUM_CONST(1)

#define QSPI_COMMAND_0_BIT_LENGTH_SHIFT                 _MK_SHIFT_CONST(0)
#define QSPI_COMMAND_0_BIT_LENGTH_FIELD                 _MK_FIELD_CONST(0x1f, QSPI_COMMAND_0_BIT_LENGTH_SHIFT)
#define QSPI_COMMAND_0_BIT_LENGTH_RANGE                 4:0
#define QSPI_COMMAND_0_BIT_LENGTH_WOFFSET                       0x0
#define QSPI_COMMAND_0_BIT_LENGTH_DEFAULT                       _MK_MASK_CONST(0x1f)
#define QSPI_COMMAND_0_BIT_LENGTH_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
#define QSPI_COMMAND_0_BIT_LENGTH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_BIT_LENGTH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_BIT_LENGTH_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define QSPI_COMMAND_0_BIT_LENGTH_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register QSPI_COMMAND2_0
#define QSPI_COMMAND2_0                 _MK_ADDR_CONST(0x4)
#define QSPI_COMMAND2_0_SECURE                  0x0
#define QSPI_COMMAND2_0_DUAL                    0x0
#define QSPI_COMMAND2_0_SCR                     0
#define QSPI_COMMAND2_0_WORD_COUNT                      0x1
#define QSPI_COMMAND2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define QSPI_COMMAND2_0_RESET_MASK                      _MK_MASK_CONST(0x7cff)
#define QSPI_COMMAND2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define QSPI_COMMAND2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define QSPI_COMMAND2_0_READ_MASK                       _MK_MASK_CONST(0x7cff)
#define QSPI_COMMAND2_0_WRITE_MASK                      _MK_MASK_CONST(0x7cff)
#define QSPI_COMMAND2_0_Tx_Clk_TAP_DELAY_SHIFT                  _MK_SHIFT_CONST(10)
#define QSPI_COMMAND2_0_Tx_Clk_TAP_DELAY_FIELD                  _MK_FIELD_CONST(0x1f, QSPI_COMMAND2_0_Tx_Clk_TAP_DELAY_SHIFT)
#define QSPI_COMMAND2_0_Tx_Clk_TAP_DELAY_RANGE                  14:10
#define QSPI_COMMAND2_0_Tx_Clk_TAP_DELAY_WOFFSET                        0x0
#define QSPI_COMMAND2_0_Tx_Clk_TAP_DELAY_DEFAULT                        _MK_MASK_CONST(0x0)
#define QSPI_COMMAND2_0_Tx_Clk_TAP_DELAY_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define QSPI_COMMAND2_0_Tx_Clk_TAP_DELAY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QSPI_COMMAND2_0_Tx_Clk_TAP_DELAY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QSPI_COMMAND2_0_Tx_Clk_TAP_DELAY_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define QSPI_COMMAND2_0_Tx_Clk_TAP_DELAY_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define QSPI_COMMAND2_0_Rx_Clk_TAP_DELAY_SHIFT                  _MK_SHIFT_CONST(0)
#define QSPI_COMMAND2_0_Rx_Clk_TAP_DELAY_FIELD                  _MK_FIELD_CONST(0xff, QSPI_COMMAND2_0_Rx_Clk_TAP_DELAY_SHIFT)
#define QSPI_COMMAND2_0_Rx_Clk_TAP_DELAY_RANGE                  7:0
#define QSPI_COMMAND2_0_Rx_Clk_TAP_DELAY_WOFFSET                        0x0
#define QSPI_COMMAND2_0_Rx_Clk_TAP_DELAY_DEFAULT                        _MK_MASK_CONST(0x0)
#define QSPI_COMMAND2_0_Rx_Clk_TAP_DELAY_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define QSPI_COMMAND2_0_Rx_Clk_TAP_DELAY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QSPI_COMMAND2_0_Rx_Clk_TAP_DELAY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QSPI_COMMAND2_0_Rx_Clk_TAP_DELAY_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define QSPI_COMMAND2_0_Rx_Clk_TAP_DELAY_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register QSPI_TIMING_REG1_0
#define QSPI_TIMING_REG1_0                      _MK_ADDR_CONST(0x8)
#define QSPI_TIMING_REG1_0_SECURE                       0x0
#define QSPI_TIMING_REG1_0_DUAL                         0x0
#define QSPI_TIMING_REG1_0_SCR                  0
#define QSPI_TIMING_REG1_0_WORD_COUNT                   0x1
#define QSPI_TIMING_REG1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define QSPI_TIMING_REG1_0_RESET_MASK                   _MK_MASK_CONST(0xff)
#define QSPI_TIMING_REG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define QSPI_TIMING_REG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QSPI_TIMING_REG1_0_READ_MASK                    _MK_MASK_CONST(0xff)
#define QSPI_TIMING_REG1_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
#define QSPI_TIMING_REG1_0_CS_SETUP_0_SHIFT                     _MK_SHIFT_CONST(4)
#define QSPI_TIMING_REG1_0_CS_SETUP_0_FIELD                     _MK_FIELD_CONST(0xf, QSPI_TIMING_REG1_0_CS_SETUP_0_SHIFT)
#define QSPI_TIMING_REG1_0_CS_SETUP_0_RANGE                     7:4
#define QSPI_TIMING_REG1_0_CS_SETUP_0_WOFFSET                   0x0
#define QSPI_TIMING_REG1_0_CS_SETUP_0_DEFAULT                   _MK_MASK_CONST(0x0)
#define QSPI_TIMING_REG1_0_CS_SETUP_0_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define QSPI_TIMING_REG1_0_CS_SETUP_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QSPI_TIMING_REG1_0_CS_SETUP_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QSPI_TIMING_REG1_0_CS_SETUP_0_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define QSPI_TIMING_REG1_0_CS_SETUP_0_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define QSPI_TIMING_REG1_0_CS_HOLD_0_SHIFT                      _MK_SHIFT_CONST(0)
#define QSPI_TIMING_REG1_0_CS_HOLD_0_FIELD                      _MK_FIELD_CONST(0xf, QSPI_TIMING_REG1_0_CS_HOLD_0_SHIFT)
#define QSPI_TIMING_REG1_0_CS_HOLD_0_RANGE                      3:0
#define QSPI_TIMING_REG1_0_CS_HOLD_0_WOFFSET                    0x0
#define QSPI_TIMING_REG1_0_CS_HOLD_0_DEFAULT                    _MK_MASK_CONST(0x0)
#define QSPI_TIMING_REG1_0_CS_HOLD_0_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define QSPI_TIMING_REG1_0_CS_HOLD_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QSPI_TIMING_REG1_0_CS_HOLD_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QSPI_TIMING_REG1_0_CS_HOLD_0_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define QSPI_TIMING_REG1_0_CS_HOLD_0_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register QSPI_TIMING_REG2_0
#define QSPI_TIMING_REG2_0                      _MK_ADDR_CONST(0xc)
#define QSPI_TIMING_REG2_0_SECURE                       0x0
#define QSPI_TIMING_REG2_0_DUAL                         0x0
#define QSPI_TIMING_REG2_0_SCR                  0
#define QSPI_TIMING_REG2_0_WORD_COUNT                   0x1
#define QSPI_TIMING_REG2_0_RESET_VAL                    _MK_MASK_CONST(0x20)
#define QSPI_TIMING_REG2_0_RESET_MASK                   _MK_MASK_CONST(0x3f)
#define QSPI_TIMING_REG2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define QSPI_TIMING_REG2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QSPI_TIMING_REG2_0_READ_MASK                    _MK_MASK_CONST(0x3f)
#define QSPI_TIMING_REG2_0_WRITE_MASK                   _MK_MASK_CONST(0x3f)
#define QSPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_SHIFT                    _MK_SHIFT_CONST(5)
#define QSPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_FIELD                    _MK_FIELD_CONST(0x1, QSPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_SHIFT)
#define QSPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_RANGE                    5:5
#define QSPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_WOFFSET                  0x0
#define QSPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_DEFAULT                  _MK_MASK_CONST(0x1)
#define QSPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define QSPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define QSPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define QSPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_SHIFT                       _MK_SHIFT_CONST(0)
#define QSPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_FIELD                       _MK_FIELD_CONST(0x1f, QSPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_SHIFT)
#define QSPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_RANGE                       4:0
#define QSPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_WOFFSET                     0x0
#define QSPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_DEFAULT                     _MK_MASK_CONST(0x0)
#define QSPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
#define QSPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define QSPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define QSPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register QSPI_TRANSFER_STATUS_0
#define QSPI_TRANSFER_STATUS_0                  _MK_ADDR_CONST(0x10)
#define QSPI_TRANSFER_STATUS_0_SECURE                   0x0
#define QSPI_TRANSFER_STATUS_0_DUAL                     0x0
#define QSPI_TRANSFER_STATUS_0_SCR                      0
#define QSPI_TRANSFER_STATUS_0_WORD_COUNT                       0x1
#define QSPI_TRANSFER_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define QSPI_TRANSFER_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0x4fffffff)
#define QSPI_TRANSFER_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define QSPI_TRANSFER_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_TRANSFER_STATUS_0_READ_MASK                        _MK_MASK_CONST(0x4fffffff)
#define QSPI_TRANSFER_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x40000000)
#define QSPI_TRANSFER_STATUS_0_RDY_SHIFT                        _MK_SHIFT_CONST(30)
#define QSPI_TRANSFER_STATUS_0_RDY_FIELD                        _MK_FIELD_CONST(0x1, QSPI_TRANSFER_STATUS_0_RDY_SHIFT)
#define QSPI_TRANSFER_STATUS_0_RDY_RANGE                        30:30
#define QSPI_TRANSFER_STATUS_0_RDY_WOFFSET                      0x0
#define QSPI_TRANSFER_STATUS_0_RDY_DEFAULT                      _MK_MASK_CONST(0x0)
#define QSPI_TRANSFER_STATUS_0_RDY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define QSPI_TRANSFER_STATUS_0_RDY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QSPI_TRANSFER_STATUS_0_RDY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QSPI_TRANSFER_STATUS_0_RDY_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define QSPI_TRANSFER_STATUS_0_RDY_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define QSPI_TRANSFER_STATUS_0_RDY_NOT_READY                    _MK_ENUM_CONST(0)
#define QSPI_TRANSFER_STATUS_0_RDY_READY                        _MK_ENUM_CONST(1)

#define QSPI_TRANSFER_STATUS_0_BLK_CNT_SHIFT                    _MK_SHIFT_CONST(0)
#define QSPI_TRANSFER_STATUS_0_BLK_CNT_FIELD                    _MK_FIELD_CONST(0xfffffff, QSPI_TRANSFER_STATUS_0_BLK_CNT_SHIFT)
#define QSPI_TRANSFER_STATUS_0_BLK_CNT_RANGE                    27:0
#define QSPI_TRANSFER_STATUS_0_BLK_CNT_WOFFSET                  0x0
#define QSPI_TRANSFER_STATUS_0_BLK_CNT_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_TRANSFER_STATUS_0_BLK_CNT_DEFAULT_MASK                     _MK_MASK_CONST(0xfffffff)
#define QSPI_TRANSFER_STATUS_0_BLK_CNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_TRANSFER_STATUS_0_BLK_CNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_TRANSFER_STATUS_0_BLK_CNT_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define QSPI_TRANSFER_STATUS_0_BLK_CNT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register QSPI_FIFO_STATUS_0
#define QSPI_FIFO_STATUS_0                      _MK_ADDR_CONST(0x14)
#define QSPI_FIFO_STATUS_0_SECURE                       0x0
#define QSPI_FIFO_STATUS_0_DUAL                         0x0
#define QSPI_FIFO_STATUS_0_SCR                  0
#define QSPI_FIFO_STATUS_0_WORD_COUNT                   0x1
#define QSPI_FIFO_STATUS_0_RESET_VAL                    _MK_MASK_CONST(0x400005)
#define QSPI_FIFO_STATUS_0_RESET_MASK                   _MK_MASK_CONST(0x3fffc1ff)
#define QSPI_FIFO_STATUS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_READ_MASK                    _MK_MASK_CONST(0x3fffc1ff)
#define QSPI_FIFO_STATUS_0_WRITE_MASK                   _MK_MASK_CONST(0xc1f0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_SHIFT                     _MK_SHIFT_CONST(23)
#define QSPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_FIELD                     _MK_FIELD_CONST(0x7f, QSPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_SHIFT)
#define QSPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_RANGE                     29:23
#define QSPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_WOFFSET                   0x0
#define QSPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_DEFAULT                   _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
#define QSPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define QSPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_SHIFT                    _MK_SHIFT_CONST(16)
#define QSPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_FIELD                    _MK_FIELD_CONST(0x7f, QSPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_SHIFT)
#define QSPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_RANGE                    22:16
#define QSPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_WOFFSET                  0x0
#define QSPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_DEFAULT                  _MK_MASK_CONST(0x40)
#define QSPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
#define QSPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define QSPI_FIFO_STATUS_0_RX_FIFO_FLUSH_SHIFT                  _MK_SHIFT_CONST(15)
#define QSPI_FIFO_STATUS_0_RX_FIFO_FLUSH_FIELD                  _MK_FIELD_CONST(0x1, QSPI_FIFO_STATUS_0_RX_FIFO_FLUSH_SHIFT)
#define QSPI_FIFO_STATUS_0_RX_FIFO_FLUSH_RANGE                  15:15
#define QSPI_FIFO_STATUS_0_RX_FIFO_FLUSH_WOFFSET                        0x0
#define QSPI_FIFO_STATUS_0_RX_FIFO_FLUSH_DEFAULT                        _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_FLUSH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define QSPI_FIFO_STATUS_0_RX_FIFO_FLUSH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_FLUSH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_FLUSH_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_FLUSH_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QSPI_FIFO_STATUS_0_RX_FIFO_FLUSH_NOP                    _MK_ENUM_CONST(0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_FLUSH_FLUSH                  _MK_ENUM_CONST(1)

#define QSPI_FIFO_STATUS_0_TX_FIFO_FLUSH_SHIFT                  _MK_SHIFT_CONST(14)
#define QSPI_FIFO_STATUS_0_TX_FIFO_FLUSH_FIELD                  _MK_FIELD_CONST(0x1, QSPI_FIFO_STATUS_0_TX_FIFO_FLUSH_SHIFT)
#define QSPI_FIFO_STATUS_0_TX_FIFO_FLUSH_RANGE                  14:14
#define QSPI_FIFO_STATUS_0_TX_FIFO_FLUSH_WOFFSET                        0x0
#define QSPI_FIFO_STATUS_0_TX_FIFO_FLUSH_DEFAULT                        _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_TX_FIFO_FLUSH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define QSPI_FIFO_STATUS_0_TX_FIFO_FLUSH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_TX_FIFO_FLUSH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_TX_FIFO_FLUSH_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_TX_FIFO_FLUSH_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QSPI_FIFO_STATUS_0_TX_FIFO_FLUSH_NOP                    _MK_ENUM_CONST(0)
#define QSPI_FIFO_STATUS_0_TX_FIFO_FLUSH_FLUSH                  _MK_ENUM_CONST(1)

#define QSPI_FIFO_STATUS_0_ERR_SHIFT                    _MK_SHIFT_CONST(8)
#define QSPI_FIFO_STATUS_0_ERR_FIELD                    _MK_FIELD_CONST(0x1, QSPI_FIFO_STATUS_0_ERR_SHIFT)
#define QSPI_FIFO_STATUS_0_ERR_RANGE                    8:8
#define QSPI_FIFO_STATUS_0_ERR_WOFFSET                  0x0
#define QSPI_FIFO_STATUS_0_ERR_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define QSPI_FIFO_STATUS_0_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_ERR_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_ERR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define QSPI_FIFO_STATUS_0_ERR_OK                       _MK_ENUM_CONST(0)
#define QSPI_FIFO_STATUS_0_ERR_ERROR                    _MK_ENUM_CONST(1)

#define QSPI_FIFO_STATUS_0_TX_FIFO_OVF_SHIFT                    _MK_SHIFT_CONST(7)
#define QSPI_FIFO_STATUS_0_TX_FIFO_OVF_FIELD                    _MK_FIELD_CONST(0x1, QSPI_FIFO_STATUS_0_TX_FIFO_OVF_SHIFT)
#define QSPI_FIFO_STATUS_0_TX_FIFO_OVF_RANGE                    7:7
#define QSPI_FIFO_STATUS_0_TX_FIFO_OVF_WOFFSET                  0x0
#define QSPI_FIFO_STATUS_0_TX_FIFO_OVF_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_TX_FIFO_OVF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define QSPI_FIFO_STATUS_0_TX_FIFO_OVF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_TX_FIFO_OVF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_TX_FIFO_OVF_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_TX_FIFO_OVF_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define QSPI_FIFO_STATUS_0_TX_FIFO_OVF_OK                       _MK_ENUM_CONST(0)
#define QSPI_FIFO_STATUS_0_TX_FIFO_OVF_ERROR                    _MK_ENUM_CONST(1)

#define QSPI_FIFO_STATUS_0_TX_FIFO_UNF_SHIFT                    _MK_SHIFT_CONST(6)
#define QSPI_FIFO_STATUS_0_TX_FIFO_UNF_FIELD                    _MK_FIELD_CONST(0x1, QSPI_FIFO_STATUS_0_TX_FIFO_UNF_SHIFT)
#define QSPI_FIFO_STATUS_0_TX_FIFO_UNF_RANGE                    6:6
#define QSPI_FIFO_STATUS_0_TX_FIFO_UNF_WOFFSET                  0x0
#define QSPI_FIFO_STATUS_0_TX_FIFO_UNF_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_TX_FIFO_UNF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define QSPI_FIFO_STATUS_0_TX_FIFO_UNF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_TX_FIFO_UNF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_TX_FIFO_UNF_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_TX_FIFO_UNF_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define QSPI_FIFO_STATUS_0_TX_FIFO_UNF_OK                       _MK_ENUM_CONST(0)
#define QSPI_FIFO_STATUS_0_TX_FIFO_UNF_ERROR                    _MK_ENUM_CONST(1)

#define QSPI_FIFO_STATUS_0_RX_FIFO_OVF_SHIFT                    _MK_SHIFT_CONST(5)
#define QSPI_FIFO_STATUS_0_RX_FIFO_OVF_FIELD                    _MK_FIELD_CONST(0x1, QSPI_FIFO_STATUS_0_RX_FIFO_OVF_SHIFT)
#define QSPI_FIFO_STATUS_0_RX_FIFO_OVF_RANGE                    5:5
#define QSPI_FIFO_STATUS_0_RX_FIFO_OVF_WOFFSET                  0x0
#define QSPI_FIFO_STATUS_0_RX_FIFO_OVF_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_OVF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define QSPI_FIFO_STATUS_0_RX_FIFO_OVF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_OVF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_OVF_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_OVF_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define QSPI_FIFO_STATUS_0_RX_FIFO_OVF_OK                       _MK_ENUM_CONST(0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_OVF_ERROR                    _MK_ENUM_CONST(1)

#define QSPI_FIFO_STATUS_0_RX_FIFO_UNF_SHIFT                    _MK_SHIFT_CONST(4)
#define QSPI_FIFO_STATUS_0_RX_FIFO_UNF_FIELD                    _MK_FIELD_CONST(0x1, QSPI_FIFO_STATUS_0_RX_FIFO_UNF_SHIFT)
#define QSPI_FIFO_STATUS_0_RX_FIFO_UNF_RANGE                    4:4
#define QSPI_FIFO_STATUS_0_RX_FIFO_UNF_WOFFSET                  0x0
#define QSPI_FIFO_STATUS_0_RX_FIFO_UNF_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_UNF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define QSPI_FIFO_STATUS_0_RX_FIFO_UNF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_UNF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_UNF_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_UNF_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define QSPI_FIFO_STATUS_0_RX_FIFO_UNF_OK                       _MK_ENUM_CONST(0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_UNF_ERROR                    _MK_ENUM_CONST(1)

#define QSPI_FIFO_STATUS_0_TX_FIFO_FULL_SHIFT                   _MK_SHIFT_CONST(3)
#define QSPI_FIFO_STATUS_0_TX_FIFO_FULL_FIELD                   _MK_FIELD_CONST(0x1, QSPI_FIFO_STATUS_0_TX_FIFO_FULL_SHIFT)
#define QSPI_FIFO_STATUS_0_TX_FIFO_FULL_RANGE                   3:3
#define QSPI_FIFO_STATUS_0_TX_FIFO_FULL_WOFFSET                 0x0
#define QSPI_FIFO_STATUS_0_TX_FIFO_FULL_DEFAULT                 _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_TX_FIFO_FULL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define QSPI_FIFO_STATUS_0_TX_FIFO_FULL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_TX_FIFO_FULL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_TX_FIFO_FULL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_TX_FIFO_FULL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define QSPI_FIFO_STATUS_0_TX_FIFO_FULL_NOT_FULL                        _MK_ENUM_CONST(0)
#define QSPI_FIFO_STATUS_0_TX_FIFO_FULL_FULL                    _MK_ENUM_CONST(1)

#define QSPI_FIFO_STATUS_0_TX_FIFO_EMPTY_SHIFT                  _MK_SHIFT_CONST(2)
#define QSPI_FIFO_STATUS_0_TX_FIFO_EMPTY_FIELD                  _MK_FIELD_CONST(0x1, QSPI_FIFO_STATUS_0_TX_FIFO_EMPTY_SHIFT)
#define QSPI_FIFO_STATUS_0_TX_FIFO_EMPTY_RANGE                  2:2
#define QSPI_FIFO_STATUS_0_TX_FIFO_EMPTY_WOFFSET                        0x0
#define QSPI_FIFO_STATUS_0_TX_FIFO_EMPTY_DEFAULT                        _MK_MASK_CONST(0x1)
#define QSPI_FIFO_STATUS_0_TX_FIFO_EMPTY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define QSPI_FIFO_STATUS_0_TX_FIFO_EMPTY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_TX_FIFO_EMPTY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_TX_FIFO_EMPTY_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_TX_FIFO_EMPTY_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QSPI_FIFO_STATUS_0_TX_FIFO_EMPTY_NOT_EMPTY                      _MK_ENUM_CONST(0)
#define QSPI_FIFO_STATUS_0_TX_FIFO_EMPTY_EMPTY                  _MK_ENUM_CONST(1)

#define QSPI_FIFO_STATUS_0_RX_FIFO_FULL_SHIFT                   _MK_SHIFT_CONST(1)
#define QSPI_FIFO_STATUS_0_RX_FIFO_FULL_FIELD                   _MK_FIELD_CONST(0x1, QSPI_FIFO_STATUS_0_RX_FIFO_FULL_SHIFT)
#define QSPI_FIFO_STATUS_0_RX_FIFO_FULL_RANGE                   1:1
#define QSPI_FIFO_STATUS_0_RX_FIFO_FULL_WOFFSET                 0x0
#define QSPI_FIFO_STATUS_0_RX_FIFO_FULL_DEFAULT                 _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_FULL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define QSPI_FIFO_STATUS_0_RX_FIFO_FULL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_FULL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_FULL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_FULL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define QSPI_FIFO_STATUS_0_RX_FIFO_FULL_NOT_FULL                        _MK_ENUM_CONST(0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_FULL_FULL                    _MK_ENUM_CONST(1)

#define QSPI_FIFO_STATUS_0_RX_FIFO_EMPTY_SHIFT                  _MK_SHIFT_CONST(0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_EMPTY_FIELD                  _MK_FIELD_CONST(0x1, QSPI_FIFO_STATUS_0_RX_FIFO_EMPTY_SHIFT)
#define QSPI_FIFO_STATUS_0_RX_FIFO_EMPTY_RANGE                  0:0
#define QSPI_FIFO_STATUS_0_RX_FIFO_EMPTY_WOFFSET                        0x0
#define QSPI_FIFO_STATUS_0_RX_FIFO_EMPTY_DEFAULT                        _MK_MASK_CONST(0x1)
#define QSPI_FIFO_STATUS_0_RX_FIFO_EMPTY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define QSPI_FIFO_STATUS_0_RX_FIFO_EMPTY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_EMPTY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_EMPTY_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_EMPTY_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QSPI_FIFO_STATUS_0_RX_FIFO_EMPTY_NOT_EMPTY                      _MK_ENUM_CONST(0)
#define QSPI_FIFO_STATUS_0_RX_FIFO_EMPTY_EMPTY                  _MK_ENUM_CONST(1)


// Register QSPI_TX_DATA_0
#define QSPI_TX_DATA_0                  _MK_ADDR_CONST(0x18)
#define QSPI_TX_DATA_0_SECURE                   0x0
#define QSPI_TX_DATA_0_DUAL                     0x0
#define QSPI_TX_DATA_0_SCR                      0
#define QSPI_TX_DATA_0_WORD_COUNT                       0x1
#define QSPI_TX_DATA_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define QSPI_TX_DATA_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define QSPI_TX_DATA_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define QSPI_TX_DATA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_TX_DATA_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define QSPI_TX_DATA_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define QSPI_TX_DATA_0_Tx_BUFFER_SHIFT                  _MK_SHIFT_CONST(0)
#define QSPI_TX_DATA_0_Tx_BUFFER_FIELD                  _MK_FIELD_CONST(0xffffffff, QSPI_TX_DATA_0_Tx_BUFFER_SHIFT)
#define QSPI_TX_DATA_0_Tx_BUFFER_RANGE                  31:0
#define QSPI_TX_DATA_0_Tx_BUFFER_WOFFSET                        0x0
#define QSPI_TX_DATA_0_Tx_BUFFER_DEFAULT                        _MK_MASK_CONST(0x0)
#define QSPI_TX_DATA_0_Tx_BUFFER_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define QSPI_TX_DATA_0_Tx_BUFFER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QSPI_TX_DATA_0_Tx_BUFFER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QSPI_TX_DATA_0_Tx_BUFFER_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define QSPI_TX_DATA_0_Tx_BUFFER_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register QSPI_RX_DATA_0
#define QSPI_RX_DATA_0                  _MK_ADDR_CONST(0x1c)
#define QSPI_RX_DATA_0_SECURE                   0x0
#define QSPI_RX_DATA_0_DUAL                     0x0
#define QSPI_RX_DATA_0_SCR                      0
#define QSPI_RX_DATA_0_WORD_COUNT                       0x1
#define QSPI_RX_DATA_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define QSPI_RX_DATA_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define QSPI_RX_DATA_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define QSPI_RX_DATA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_RX_DATA_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define QSPI_RX_DATA_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define QSPI_RX_DATA_0_Rx_BUFFER_SHIFT                  _MK_SHIFT_CONST(0)
#define QSPI_RX_DATA_0_Rx_BUFFER_FIELD                  _MK_FIELD_CONST(0xffffffff, QSPI_RX_DATA_0_Rx_BUFFER_SHIFT)
#define QSPI_RX_DATA_0_Rx_BUFFER_RANGE                  31:0
#define QSPI_RX_DATA_0_Rx_BUFFER_WOFFSET                        0x0
#define QSPI_RX_DATA_0_Rx_BUFFER_DEFAULT                        _MK_MASK_CONST(0x0)
#define QSPI_RX_DATA_0_Rx_BUFFER_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define QSPI_RX_DATA_0_Rx_BUFFER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QSPI_RX_DATA_0_Rx_BUFFER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QSPI_RX_DATA_0_Rx_BUFFER_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define QSPI_RX_DATA_0_Rx_BUFFER_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register QSPI_DMA_CTL_0
#define QSPI_DMA_CTL_0                  _MK_ADDR_CONST(0x20)
#define QSPI_DMA_CTL_0_SECURE                   0x0
#define QSPI_DMA_CTL_0_DUAL                     0x0
#define QSPI_DMA_CTL_0_SCR                      0
#define QSPI_DMA_CTL_0_WORD_COUNT                       0x1
#define QSPI_DMA_CTL_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define QSPI_DMA_CTL_0_RESET_MASK                       _MK_MASK_CONST(0x80198000)
#define QSPI_DMA_CTL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define QSPI_DMA_CTL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_DMA_CTL_0_READ_MASK                        _MK_MASK_CONST(0x80198000)
#define QSPI_DMA_CTL_0_WRITE_MASK                       _MK_MASK_CONST(0x80198000)
#define QSPI_DMA_CTL_0_DMA_EN_SHIFT                     _MK_SHIFT_CONST(31)
#define QSPI_DMA_CTL_0_DMA_EN_FIELD                     _MK_FIELD_CONST(0x1, QSPI_DMA_CTL_0_DMA_EN_SHIFT)
#define QSPI_DMA_CTL_0_DMA_EN_RANGE                     31:31
#define QSPI_DMA_CTL_0_DMA_EN_WOFFSET                   0x0
#define QSPI_DMA_CTL_0_DMA_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define QSPI_DMA_CTL_0_DMA_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define QSPI_DMA_CTL_0_DMA_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QSPI_DMA_CTL_0_DMA_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QSPI_DMA_CTL_0_DMA_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define QSPI_DMA_CTL_0_DMA_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define QSPI_DMA_CTL_0_DMA_EN_DISABLE                   _MK_ENUM_CONST(0)
#define QSPI_DMA_CTL_0_DMA_EN_ENABLE                    _MK_ENUM_CONST(1)

#define QSPI_DMA_CTL_0_RX_TRIG_SHIFT                    _MK_SHIFT_CONST(19)
#define QSPI_DMA_CTL_0_RX_TRIG_FIELD                    _MK_FIELD_CONST(0x3, QSPI_DMA_CTL_0_RX_TRIG_SHIFT)
#define QSPI_DMA_CTL_0_RX_TRIG_RANGE                    20:19
#define QSPI_DMA_CTL_0_RX_TRIG_WOFFSET                  0x0
#define QSPI_DMA_CTL_0_RX_TRIG_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_DMA_CTL_0_RX_TRIG_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define QSPI_DMA_CTL_0_RX_TRIG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_DMA_CTL_0_RX_TRIG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_DMA_CTL_0_RX_TRIG_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define QSPI_DMA_CTL_0_RX_TRIG_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define QSPI_DMA_CTL_0_RX_TRIG_TRIG1                    _MK_ENUM_CONST(0)
#define QSPI_DMA_CTL_0_RX_TRIG_TRIG4                    _MK_ENUM_CONST(1)
#define QSPI_DMA_CTL_0_RX_TRIG_TRIG8                    _MK_ENUM_CONST(2)
#define QSPI_DMA_CTL_0_RX_TRIG_TRIG16                   _MK_ENUM_CONST(3)

#define QSPI_DMA_CTL_0_TX_TRIG_SHIFT                    _MK_SHIFT_CONST(15)
#define QSPI_DMA_CTL_0_TX_TRIG_FIELD                    _MK_FIELD_CONST(0x3, QSPI_DMA_CTL_0_TX_TRIG_SHIFT)
#define QSPI_DMA_CTL_0_TX_TRIG_RANGE                    16:15
#define QSPI_DMA_CTL_0_TX_TRIG_WOFFSET                  0x0
#define QSPI_DMA_CTL_0_TX_TRIG_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_DMA_CTL_0_TX_TRIG_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define QSPI_DMA_CTL_0_TX_TRIG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_DMA_CTL_0_TX_TRIG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_DMA_CTL_0_TX_TRIG_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define QSPI_DMA_CTL_0_TX_TRIG_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define QSPI_DMA_CTL_0_TX_TRIG_TRIG1                    _MK_ENUM_CONST(0)
#define QSPI_DMA_CTL_0_TX_TRIG_TRIG4                    _MK_ENUM_CONST(1)
#define QSPI_DMA_CTL_0_TX_TRIG_TRIG8                    _MK_ENUM_CONST(2)
#define QSPI_DMA_CTL_0_TX_TRIG_TRIG16                   _MK_ENUM_CONST(3)


// Register QSPI_DMA_BLK_SIZE_0
#define QSPI_DMA_BLK_SIZE_0                     _MK_ADDR_CONST(0x24)
#define QSPI_DMA_BLK_SIZE_0_SECURE                      0x0
#define QSPI_DMA_BLK_SIZE_0_DUAL                        0x0
#define QSPI_DMA_BLK_SIZE_0_SCR                         0
#define QSPI_DMA_BLK_SIZE_0_WORD_COUNT                  0x1
#define QSPI_DMA_BLK_SIZE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define QSPI_DMA_BLK_SIZE_0_RESET_MASK                  _MK_MASK_CONST(0xfffffff)
#define QSPI_DMA_BLK_SIZE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define QSPI_DMA_BLK_SIZE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define QSPI_DMA_BLK_SIZE_0_READ_MASK                   _MK_MASK_CONST(0xfffffff)
#define QSPI_DMA_BLK_SIZE_0_WRITE_MASK                  _MK_MASK_CONST(0xfffffff)
#define QSPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_SHIFT                        _MK_SHIFT_CONST(0)
#define QSPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_FIELD                        _MK_FIELD_CONST(0xfffffff, QSPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_SHIFT)
#define QSPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_RANGE                        27:0
#define QSPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_WOFFSET                      0x0
#define QSPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_DEFAULT                      _MK_MASK_CONST(0x0)
#define QSPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_DEFAULT_MASK                 _MK_MASK_CONST(0xfffffff)
#define QSPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QSPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QSPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define QSPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Reserved address 0x28

// Reserved address 0x2c

// Reserved address 0x30

// Reserved address 0x34

// Reserved address 0x38

// Reserved address 0x3c

// Reserved address 0x40

// Reserved address 0x44

// Reserved address 0x48

// Reserved address 0x4c

// Reserved address 0x50

// Reserved address 0x54

// Reserved address 0x58

// Reserved address 0x5c

// Reserved address 0x60

// Reserved address 0x64

// Reserved address 0x68

// Reserved address 0x6c

// Reserved address 0x70

// Reserved address 0x74

// Reserved address 0x78

// Reserved address 0x7c

// Reserved address 0x80

// Reserved address 0x84

// Reserved address 0x88

// Reserved address 0x8c

// Reserved address 0x90

// Reserved address 0x94

// Reserved address 0x98

// Reserved address 0x9c

// Reserved address 0xa0

// Reserved address 0xa4

// Reserved address 0xa8

// Reserved address 0xac

// Reserved address 0xb0

// Reserved address 0xb4

// Reserved address 0xb8

// Reserved address 0xbc

// Reserved address 0xc0

// Reserved address 0xc4

// Reserved address 0xc8

// Reserved address 0xcc

// Reserved address 0xd0

// Reserved address 0xd4

// Reserved address 0xd8

// Reserved address 0xdc

// Reserved address 0xe0

// Reserved address 0xe4

// Reserved address 0xe8

// Reserved address 0xec

// Reserved address 0xf0

// Reserved address 0xf4

// Reserved address 0xf8

// Reserved address 0xfc

// Reserved address 0x100

// Reserved address 0x104

// Register QSPI_TX_FIFO_0
#define QSPI_TX_FIFO_0                  _MK_ADDR_CONST(0x108)
#define QSPI_TX_FIFO_0_SECURE                   0x0
#define QSPI_TX_FIFO_0_DUAL                     0x0
#define QSPI_TX_FIFO_0_SCR                      0
#define QSPI_TX_FIFO_0_WORD_COUNT                       0x1
#define QSPI_TX_FIFO_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define QSPI_TX_FIFO_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define QSPI_TX_FIFO_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define QSPI_TX_FIFO_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_TX_FIFO_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define QSPI_TX_FIFO_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define QSPI_TX_FIFO_0_TX_FIFO_REGISTER_SHIFT                   _MK_SHIFT_CONST(0)
#define QSPI_TX_FIFO_0_TX_FIFO_REGISTER_FIELD                   _MK_FIELD_CONST(0xffffffff, QSPI_TX_FIFO_0_TX_FIFO_REGISTER_SHIFT)
#define QSPI_TX_FIFO_0_TX_FIFO_REGISTER_RANGE                   31:0
#define QSPI_TX_FIFO_0_TX_FIFO_REGISTER_WOFFSET                 0x0
#define QSPI_TX_FIFO_0_TX_FIFO_REGISTER_DEFAULT                 _MK_MASK_CONST(0x0)
#define QSPI_TX_FIFO_0_TX_FIFO_REGISTER_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define QSPI_TX_FIFO_0_TX_FIFO_REGISTER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define QSPI_TX_FIFO_0_TX_FIFO_REGISTER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define QSPI_TX_FIFO_0_TX_FIFO_REGISTER_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define QSPI_TX_FIFO_0_TX_FIFO_REGISTER_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Reserved address 0x10c

// Reserved address 0x110

// Reserved address 0x114

// Reserved address 0x118

// Reserved address 0x11c

// Reserved address 0x120

// Reserved address 0x124

// Reserved address 0x128

// Reserved address 0x12c

// Reserved address 0x130

// Reserved address 0x134

// Reserved address 0x138

// Reserved address 0x13c

// Reserved address 0x140

// Reserved address 0x144

// Reserved address 0x148

// Reserved address 0x14c

// Reserved address 0x150

// Reserved address 0x154

// Reserved address 0x158

// Reserved address 0x15c

// Reserved address 0x160

// Reserved address 0x164

// Reserved address 0x168

// Reserved address 0x16c

// Reserved address 0x170

// Reserved address 0x174

// Reserved address 0x178

// Reserved address 0x17c

// Reserved address 0x180

// Reserved address 0x184

// Register QSPI_RX_FIFO_0
#define QSPI_RX_FIFO_0                  _MK_ADDR_CONST(0x188)
#define QSPI_RX_FIFO_0_SECURE                   0x0
#define QSPI_RX_FIFO_0_DUAL                     0x0
#define QSPI_RX_FIFO_0_SCR                      0
#define QSPI_RX_FIFO_0_WORD_COUNT                       0x1
#define QSPI_RX_FIFO_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define QSPI_RX_FIFO_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define QSPI_RX_FIFO_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define QSPI_RX_FIFO_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_RX_FIFO_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define QSPI_RX_FIFO_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define QSPI_RX_FIFO_0_RX_FIFO_REGISTER_SHIFT                   _MK_SHIFT_CONST(0)
#define QSPI_RX_FIFO_0_RX_FIFO_REGISTER_FIELD                   _MK_FIELD_CONST(0xffffffff, QSPI_RX_FIFO_0_RX_FIFO_REGISTER_SHIFT)
#define QSPI_RX_FIFO_0_RX_FIFO_REGISTER_RANGE                   31:0
#define QSPI_RX_FIFO_0_RX_FIFO_REGISTER_WOFFSET                 0x0
#define QSPI_RX_FIFO_0_RX_FIFO_REGISTER_DEFAULT                 _MK_MASK_CONST(0x0)
#define QSPI_RX_FIFO_0_RX_FIFO_REGISTER_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define QSPI_RX_FIFO_0_RX_FIFO_REGISTER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define QSPI_RX_FIFO_0_RX_FIFO_REGISTER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define QSPI_RX_FIFO_0_RX_FIFO_REGISTER_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define QSPI_RX_FIFO_0_RX_FIFO_REGISTER_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register QSPI_INTR_MASK_0
#define QSPI_INTR_MASK_0                        _MK_ADDR_CONST(0x18c)
#define QSPI_INTR_MASK_0_SECURE                         0x0
#define QSPI_INTR_MASK_0_DUAL                   0x0
#define QSPI_INTR_MASK_0_SCR                    0
#define QSPI_INTR_MASK_0_WORD_COUNT                     0x1
#define QSPI_INTR_MASK_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define QSPI_INTR_MASK_0_RESET_MASK                     _MK_MASK_CONST(0x3e000000)
#define QSPI_INTR_MASK_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define QSPI_INTR_MASK_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QSPI_INTR_MASK_0_READ_MASK                      _MK_MASK_CONST(0x3e000000)
#define QSPI_INTR_MASK_0_WRITE_MASK                     _MK_MASK_CONST(0x3e000000)
#define QSPI_INTR_MASK_0_RDY_INTR_MASK_SHIFT                    _MK_SHIFT_CONST(29)
#define QSPI_INTR_MASK_0_RDY_INTR_MASK_FIELD                    _MK_FIELD_CONST(0x1, QSPI_INTR_MASK_0_RDY_INTR_MASK_SHIFT)
#define QSPI_INTR_MASK_0_RDY_INTR_MASK_RANGE                    29:29
#define QSPI_INTR_MASK_0_RDY_INTR_MASK_WOFFSET                  0x0
#define QSPI_INTR_MASK_0_RDY_INTR_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_INTR_MASK_0_RDY_INTR_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define QSPI_INTR_MASK_0_RDY_INTR_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_INTR_MASK_0_RDY_INTR_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_INTR_MASK_0_RDY_INTR_MASK_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define QSPI_INTR_MASK_0_RDY_INTR_MASK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define QSPI_INTR_MASK_0_RDY_INTR_MASK_DISABLE                  _MK_ENUM_CONST(0)
#define QSPI_INTR_MASK_0_RDY_INTR_MASK_ENABLE                   _MK_ENUM_CONST(1)

#define QSPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_SHIFT                    _MK_SHIFT_CONST(28)
#define QSPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_FIELD                    _MK_FIELD_CONST(0x1, QSPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_SHIFT)
#define QSPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_RANGE                    28:28
#define QSPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_WOFFSET                  0x0
#define QSPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define QSPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define QSPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define QSPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_DISABLE                  _MK_ENUM_CONST(0)
#define QSPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_ENABLE                   _MK_ENUM_CONST(1)

#define QSPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_SHIFT                    _MK_SHIFT_CONST(27)
#define QSPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_FIELD                    _MK_FIELD_CONST(0x1, QSPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_SHIFT)
#define QSPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_RANGE                    27:27
#define QSPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_WOFFSET                  0x0
#define QSPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define QSPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define QSPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define QSPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_DISABLE                  _MK_ENUM_CONST(0)
#define QSPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_ENABLE                   _MK_ENUM_CONST(1)

#define QSPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_SHIFT                    _MK_SHIFT_CONST(26)
#define QSPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_FIELD                    _MK_FIELD_CONST(0x1, QSPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_SHIFT)
#define QSPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_RANGE                    26:26
#define QSPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_WOFFSET                  0x0
#define QSPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define QSPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define QSPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define QSPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_DISABLE                  _MK_ENUM_CONST(0)
#define QSPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_ENABLE                   _MK_ENUM_CONST(1)

#define QSPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_SHIFT                    _MK_SHIFT_CONST(25)
#define QSPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_FIELD                    _MK_FIELD_CONST(0x1, QSPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_SHIFT)
#define QSPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_RANGE                    25:25
#define QSPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_WOFFSET                  0x0
#define QSPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define QSPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define QSPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define QSPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_DISABLE                  _MK_ENUM_CONST(0)
#define QSPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_ENABLE                   _MK_ENUM_CONST(1)


// Register QSPI_SPARE_CTLR_0
#define QSPI_SPARE_CTLR_0                       _MK_ADDR_CONST(0x190)
#define QSPI_SPARE_CTLR_0_SECURE                        0x0
#define QSPI_SPARE_CTLR_0_DUAL                  0x0
#define QSPI_SPARE_CTLR_0_SCR                   0
#define QSPI_SPARE_CTLR_0_WORD_COUNT                    0x1
#define QSPI_SPARE_CTLR_0_RESET_VAL                     _MK_MASK_CONST(0xfff0000)
#define QSPI_SPARE_CTLR_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define QSPI_SPARE_CTLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define QSPI_SPARE_CTLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define QSPI_SPARE_CTLR_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define QSPI_SPARE_CTLR_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_SHIFT                    _MK_SHIFT_CONST(24)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_FIELD                    _MK_FIELD_CONST(0xff, QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_SHIFT)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_RANGE                    31:24
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_WOFFSET                  0x0
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_DEFAULT                  _MK_MASK_CONST(0xf)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_SHIFT                    _MK_SHIFT_CONST(16)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_FIELD                    _MK_FIELD_CONST(0xff, QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_SHIFT)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_RANGE                    23:16
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_WOFFSET                  0x0
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_DEFAULT                  _MK_MASK_CONST(0xff)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_SHIFT                    _MK_SHIFT_CONST(8)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_FIELD                    _MK_FIELD_CONST(0xff, QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_SHIFT)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_RANGE                    15:8
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_WOFFSET                  0x0
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_SHIFT                    _MK_SHIFT_CONST(0)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_FIELD                    _MK_FIELD_CONST(0xff, QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_SHIFT)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_RANGE                    7:0
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_WOFFSET                  0x0
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define QSPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register QSPI_MISC_0
#define QSPI_MISC_0                     _MK_ADDR_CONST(0x194)
#define QSPI_MISC_0_SECURE                      0x0
#define QSPI_MISC_0_DUAL                        0x0
#define QSPI_MISC_0_SCR                         0
#define QSPI_MISC_0_WORD_COUNT                  0x1
#define QSPI_MISC_0_RESET_VAL                   _MK_MASK_CONST(0x80000000)
#define QSPI_MISC_0_RESET_MASK                  _MK_MASK_CONST(0x800000ff)
#define QSPI_MISC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define QSPI_MISC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define QSPI_MISC_0_READ_MASK                   _MK_MASK_CONST(0x800000ff)
#define QSPI_MISC_0_WRITE_MASK                  _MK_MASK_CONST(0x800000ff)
#define QSPI_MISC_0_CLKEN_OVERRIDE_SHIFT                        _MK_SHIFT_CONST(31)
#define QSPI_MISC_0_CLKEN_OVERRIDE_FIELD                        _MK_FIELD_CONST(0x1, QSPI_MISC_0_CLKEN_OVERRIDE_SHIFT)
#define QSPI_MISC_0_CLKEN_OVERRIDE_RANGE                        31:31
#define QSPI_MISC_0_CLKEN_OVERRIDE_WOFFSET                      0x0
#define QSPI_MISC_0_CLKEN_OVERRIDE_DEFAULT                      _MK_MASK_CONST(0x1)
#define QSPI_MISC_0_CLKEN_OVERRIDE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define QSPI_MISC_0_CLKEN_OVERRIDE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QSPI_MISC_0_CLKEN_OVERRIDE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QSPI_MISC_0_CLKEN_OVERRIDE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define QSPI_MISC_0_CLKEN_OVERRIDE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define QSPI_MISC_0_NUM_OF_DUMMY_CLK_CYCLES_SHIFT                       _MK_SHIFT_CONST(0)
#define QSPI_MISC_0_NUM_OF_DUMMY_CLK_CYCLES_FIELD                       _MK_FIELD_CONST(0xff, QSPI_MISC_0_NUM_OF_DUMMY_CLK_CYCLES_SHIFT)
#define QSPI_MISC_0_NUM_OF_DUMMY_CLK_CYCLES_RANGE                       7:0
#define QSPI_MISC_0_NUM_OF_DUMMY_CLK_CYCLES_WOFFSET                     0x0
#define QSPI_MISC_0_NUM_OF_DUMMY_CLK_CYCLES_DEFAULT                     _MK_MASK_CONST(0x0)
#define QSPI_MISC_0_NUM_OF_DUMMY_CLK_CYCLES_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define QSPI_MISC_0_NUM_OF_DUMMY_CLK_CYCLES_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_MISC_0_NUM_OF_DUMMY_CLK_CYCLES_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define QSPI_MISC_0_NUM_OF_DUMMY_CLK_CYCLES_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define QSPI_MISC_0_NUM_OF_DUMMY_CLK_CYCLES_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register QSPI_TIMING3_0
#define QSPI_TIMING3_0                  _MK_ADDR_CONST(0x198)
#define QSPI_TIMING3_0_SECURE                   0x0
#define QSPI_TIMING3_0_DUAL                     0x0
#define QSPI_TIMING3_0_SCR                      0
#define QSPI_TIMING3_0_WORD_COUNT                       0x1
#define QSPI_TIMING3_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define QSPI_TIMING3_0_RESET_MASK                       _MK_MASK_CONST(0x1f1f1f1f)
#define QSPI_TIMING3_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define QSPI_TIMING3_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_TIMING3_0_READ_MASK                        _MK_MASK_CONST(0x1f1f1f1f)
#define QSPI_TIMING3_0_WRITE_MASK                       _MK_MASK_CONST(0x1f1f1f1f)
#define QSPI_TIMING3_0_DATA3_LINE_TAP_DELAY_SHIFT                       _MK_SHIFT_CONST(24)
#define QSPI_TIMING3_0_DATA3_LINE_TAP_DELAY_FIELD                       _MK_FIELD_CONST(0x1f, QSPI_TIMING3_0_DATA3_LINE_TAP_DELAY_SHIFT)
#define QSPI_TIMING3_0_DATA3_LINE_TAP_DELAY_RANGE                       28:24
#define QSPI_TIMING3_0_DATA3_LINE_TAP_DELAY_WOFFSET                     0x0
#define QSPI_TIMING3_0_DATA3_LINE_TAP_DELAY_DEFAULT                     _MK_MASK_CONST(0x0)
#define QSPI_TIMING3_0_DATA3_LINE_TAP_DELAY_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
#define QSPI_TIMING3_0_DATA3_LINE_TAP_DELAY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_TIMING3_0_DATA3_LINE_TAP_DELAY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define QSPI_TIMING3_0_DATA3_LINE_TAP_DELAY_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define QSPI_TIMING3_0_DATA3_LINE_TAP_DELAY_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define QSPI_TIMING3_0_DATA2_LINE_TAP_DELAY_SHIFT                       _MK_SHIFT_CONST(16)
#define QSPI_TIMING3_0_DATA2_LINE_TAP_DELAY_FIELD                       _MK_FIELD_CONST(0x1f, QSPI_TIMING3_0_DATA2_LINE_TAP_DELAY_SHIFT)
#define QSPI_TIMING3_0_DATA2_LINE_TAP_DELAY_RANGE                       20:16
#define QSPI_TIMING3_0_DATA2_LINE_TAP_DELAY_WOFFSET                     0x0
#define QSPI_TIMING3_0_DATA2_LINE_TAP_DELAY_DEFAULT                     _MK_MASK_CONST(0x0)
#define QSPI_TIMING3_0_DATA2_LINE_TAP_DELAY_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
#define QSPI_TIMING3_0_DATA2_LINE_TAP_DELAY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_TIMING3_0_DATA2_LINE_TAP_DELAY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define QSPI_TIMING3_0_DATA2_LINE_TAP_DELAY_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define QSPI_TIMING3_0_DATA2_LINE_TAP_DELAY_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define QSPI_TIMING3_0_DATA1_LINE_TAP_DELAY_SHIFT                       _MK_SHIFT_CONST(8)
#define QSPI_TIMING3_0_DATA1_LINE_TAP_DELAY_FIELD                       _MK_FIELD_CONST(0x1f, QSPI_TIMING3_0_DATA1_LINE_TAP_DELAY_SHIFT)
#define QSPI_TIMING3_0_DATA1_LINE_TAP_DELAY_RANGE                       12:8
#define QSPI_TIMING3_0_DATA1_LINE_TAP_DELAY_WOFFSET                     0x0
#define QSPI_TIMING3_0_DATA1_LINE_TAP_DELAY_DEFAULT                     _MK_MASK_CONST(0x0)
#define QSPI_TIMING3_0_DATA1_LINE_TAP_DELAY_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
#define QSPI_TIMING3_0_DATA1_LINE_TAP_DELAY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_TIMING3_0_DATA1_LINE_TAP_DELAY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define QSPI_TIMING3_0_DATA1_LINE_TAP_DELAY_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define QSPI_TIMING3_0_DATA1_LINE_TAP_DELAY_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define QSPI_TIMING3_0_DATA0_LINE_TAP_DELAY_SHIFT                       _MK_SHIFT_CONST(0)
#define QSPI_TIMING3_0_DATA0_LINE_TAP_DELAY_FIELD                       _MK_FIELD_CONST(0x1f, QSPI_TIMING3_0_DATA0_LINE_TAP_DELAY_SHIFT)
#define QSPI_TIMING3_0_DATA0_LINE_TAP_DELAY_RANGE                       4:0
#define QSPI_TIMING3_0_DATA0_LINE_TAP_DELAY_WOFFSET                     0x0
#define QSPI_TIMING3_0_DATA0_LINE_TAP_DELAY_DEFAULT                     _MK_MASK_CONST(0x0)
#define QSPI_TIMING3_0_DATA0_LINE_TAP_DELAY_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
#define QSPI_TIMING3_0_DATA0_LINE_TAP_DELAY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_TIMING3_0_DATA0_LINE_TAP_DELAY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define QSPI_TIMING3_0_DATA0_LINE_TAP_DELAY_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define QSPI_TIMING3_0_DATA0_LINE_TAP_DELAY_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register QSPI_CMB_SEQ_CMD_0
#define QSPI_CMB_SEQ_CMD_0                      _MK_ADDR_CONST(0x19c)
#define QSPI_CMB_SEQ_CMD_0_SECURE                       0x0
#define QSPI_CMB_SEQ_CMD_0_DUAL                         0x0
#define QSPI_CMB_SEQ_CMD_0_SCR                  0
#define QSPI_CMB_SEQ_CMD_0_WORD_COUNT                   0x1
#define QSPI_CMB_SEQ_CMD_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_CMD_0_RESET_MASK                   _MK_MASK_CONST(0xff)
#define QSPI_CMB_SEQ_CMD_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_CMD_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_CMD_0_READ_MASK                    _MK_MASK_CONST(0xff)
#define QSPI_CMB_SEQ_CMD_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
#define QSPI_CMB_SEQ_CMD_0_COMMAND_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define QSPI_CMB_SEQ_CMD_0_COMMAND_VALUE_FIELD                  _MK_FIELD_CONST(0xff, QSPI_CMB_SEQ_CMD_0_COMMAND_VALUE_SHIFT)
#define QSPI_CMB_SEQ_CMD_0_COMMAND_VALUE_RANGE                  7:0
#define QSPI_CMB_SEQ_CMD_0_COMMAND_VALUE_WOFFSET                        0x0
#define QSPI_CMB_SEQ_CMD_0_COMMAND_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_CMD_0_COMMAND_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define QSPI_CMB_SEQ_CMD_0_COMMAND_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_CMD_0_COMMAND_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_CMD_0_COMMAND_VALUE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_CMD_0_COMMAND_VALUE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register QSPI_CMB_SEQ_CMD_CFG_0
#define QSPI_CMB_SEQ_CMD_CFG_0                  _MK_ADDR_CONST(0x1a0)
#define QSPI_CMB_SEQ_CMD_CFG_0_SECURE                   0x0
#define QSPI_CMB_SEQ_CMD_CFG_0_DUAL                     0x0
#define QSPI_CMB_SEQ_CMD_CFG_0_SCR                      0
#define QSPI_CMB_SEQ_CMD_CFG_0_WORD_COUNT                       0x1
#define QSPI_CMB_SEQ_CMD_CFG_0_RESET_VAL                        _MK_MASK_CONST(0x7)
#define QSPI_CMB_SEQ_CMD_CFG_0_RESET_MASK                       _MK_MASK_CONST(0x70ff)
#define QSPI_CMB_SEQ_CMD_CFG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_CMD_CFG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_CMD_CFG_0_READ_MASK                        _MK_MASK_CONST(0x70ff)
#define QSPI_CMB_SEQ_CMD_CFG_0_WRITE_MASK                       _MK_MASK_CONST(0x70ff)
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_X1_X2_X4_SHIFT                   _MK_SHIFT_CONST(13)
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_X1_X2_X4_FIELD                   _MK_FIELD_CONST(0x3, QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_X1_X2_X4_SHIFT)
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_X1_X2_X4_RANGE                   14:13
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_X1_X2_X4_WOFFSET                 0x0
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_X1_X2_X4_DEFAULT                 _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_X1_X2_X4_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_X1_X2_X4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_X1_X2_X4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_X1_X2_X4_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_X1_X2_X4_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_SDR_DDR_SHIFT                    _MK_SHIFT_CONST(12)
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_SDR_DDR_FIELD                    _MK_FIELD_CONST(0x1, QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_SDR_DDR_SHIFT)
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_SDR_DDR_RANGE                    12:12
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_SDR_DDR_WOFFSET                  0x0
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_SDR_DDR_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_SDR_DDR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_SDR_DDR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_SDR_DDR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_SDR_DDR_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_SDR_DDR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_SIZE_SHIFT                       _MK_SHIFT_CONST(0)
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_SIZE_FIELD                       _MK_FIELD_CONST(0xff, QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_SIZE_SHIFT)
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_SIZE_RANGE                       7:0
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_SIZE_WOFFSET                     0x0
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_SIZE_DEFAULT                     _MK_MASK_CONST(0x7)
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_SIZE_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_SIZE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_SIZE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_SIZE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_CMD_CFG_0_COMMAND_SIZE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register QSPI_GLOBAL_CONFIG_0
#define QSPI_GLOBAL_CONFIG_0                    _MK_ADDR_CONST(0x1a4)
#define QSPI_GLOBAL_CONFIG_0_SECURE                     0x0
#define QSPI_GLOBAL_CONFIG_0_DUAL                       0x0
#define QSPI_GLOBAL_CONFIG_0_SCR                        0
#define QSPI_GLOBAL_CONFIG_0_WORD_COUNT                         0x1
#define QSPI_GLOBAL_CONFIG_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define QSPI_GLOBAL_CONFIG_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define QSPI_GLOBAL_CONFIG_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define QSPI_GLOBAL_CONFIG_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QSPI_GLOBAL_CONFIG_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define QSPI_GLOBAL_CONFIG_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define QSPI_GLOBAL_CONFIG_0_CMB_SEQ_EN_SHIFT                   _MK_SHIFT_CONST(0)
#define QSPI_GLOBAL_CONFIG_0_CMB_SEQ_EN_FIELD                   _MK_FIELD_CONST(0x1, QSPI_GLOBAL_CONFIG_0_CMB_SEQ_EN_SHIFT)
#define QSPI_GLOBAL_CONFIG_0_CMB_SEQ_EN_RANGE                   0:0
#define QSPI_GLOBAL_CONFIG_0_CMB_SEQ_EN_WOFFSET                 0x0
#define QSPI_GLOBAL_CONFIG_0_CMB_SEQ_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define QSPI_GLOBAL_CONFIG_0_CMB_SEQ_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define QSPI_GLOBAL_CONFIG_0_CMB_SEQ_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define QSPI_GLOBAL_CONFIG_0_CMB_SEQ_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define QSPI_GLOBAL_CONFIG_0_CMB_SEQ_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define QSPI_GLOBAL_CONFIG_0_CMB_SEQ_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register QSPI_CMB_SEQ_ADDR_0
#define QSPI_CMB_SEQ_ADDR_0                     _MK_ADDR_CONST(0x1a8)
#define QSPI_CMB_SEQ_ADDR_0_SECURE                      0x0
#define QSPI_CMB_SEQ_ADDR_0_DUAL                        0x0
#define QSPI_CMB_SEQ_ADDR_0_SCR                         0
#define QSPI_CMB_SEQ_ADDR_0_WORD_COUNT                  0x1
#define QSPI_CMB_SEQ_ADDR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_ADDR_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define QSPI_CMB_SEQ_ADDR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_ADDR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_ADDR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define QSPI_CMB_SEQ_ADDR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define QSPI_CMB_SEQ_ADDR_0_ADDRESS_VALUE_SHIFT                 _MK_SHIFT_CONST(0)
#define QSPI_CMB_SEQ_ADDR_0_ADDRESS_VALUE_FIELD                 _MK_FIELD_CONST(0xffffffff, QSPI_CMB_SEQ_ADDR_0_ADDRESS_VALUE_SHIFT)
#define QSPI_CMB_SEQ_ADDR_0_ADDRESS_VALUE_RANGE                 31:0
#define QSPI_CMB_SEQ_ADDR_0_ADDRESS_VALUE_WOFFSET                       0x0
#define QSPI_CMB_SEQ_ADDR_0_ADDRESS_VALUE_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_ADDR_0_ADDRESS_VALUE_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define QSPI_CMB_SEQ_ADDR_0_ADDRESS_VALUE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_ADDR_0_ADDRESS_VALUE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_ADDR_0_ADDRESS_VALUE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_ADDR_0_ADDRESS_VALUE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register QSPI_CMB_SEQ_ADDR_CFG_0
#define QSPI_CMB_SEQ_ADDR_CFG_0                 _MK_ADDR_CONST(0x1ac)
#define QSPI_CMB_SEQ_ADDR_CFG_0_SECURE                  0x0
#define QSPI_CMB_SEQ_ADDR_CFG_0_DUAL                    0x0
#define QSPI_CMB_SEQ_ADDR_CFG_0_SCR                     0
#define QSPI_CMB_SEQ_ADDR_CFG_0_WORD_COUNT                      0x1
#define QSPI_CMB_SEQ_ADDR_CFG_0_RESET_VAL                       _MK_MASK_CONST(0x17)
#define QSPI_CMB_SEQ_ADDR_CFG_0_RESET_MASK                      _MK_MASK_CONST(0x70ff)
#define QSPI_CMB_SEQ_ADDR_CFG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_ADDR_CFG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_ADDR_CFG_0_READ_MASK                       _MK_MASK_CONST(0x70ff)
#define QSPI_CMB_SEQ_ADDR_CFG_0_WRITE_MASK                      _MK_MASK_CONST(0x70ff)
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_X1_X2_X4_SHIFT                  _MK_SHIFT_CONST(13)
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_X1_X2_X4_FIELD                  _MK_FIELD_CONST(0x3, QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_X1_X2_X4_SHIFT)
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_X1_X2_X4_RANGE                  14:13
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_X1_X2_X4_WOFFSET                        0x0
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_X1_X2_X4_DEFAULT                        _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_X1_X2_X4_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_X1_X2_X4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_X1_X2_X4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_X1_X2_X4_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_X1_X2_X4_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_SDR_DDR_SHIFT                   _MK_SHIFT_CONST(12)
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_SDR_DDR_FIELD                   _MK_FIELD_CONST(0x1, QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_SDR_DDR_SHIFT)
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_SDR_DDR_RANGE                   12:12
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_SDR_DDR_WOFFSET                 0x0
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_SDR_DDR_DEFAULT                 _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_SDR_DDR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_SDR_DDR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_SDR_DDR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_SDR_DDR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_SDR_DDR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_SIZE_SHIFT                      _MK_SHIFT_CONST(0)
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_SIZE_FIELD                      _MK_FIELD_CONST(0xff, QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_SIZE_SHIFT)
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_SIZE_RANGE                      7:0
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_SIZE_WOFFSET                    0x0
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_SIZE_DEFAULT                    _MK_MASK_CONST(0x17)
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_SIZE_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_SIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_SIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_SIZE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define QSPI_CMB_SEQ_ADDR_CFG_0_ADDRESS_SIZE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Reserved address 0x1b0

// Reserved address 0x1b4

// Reserved address 0x1b8

// Reserved address 0x1bc

// Reserved address 0x1c0

// Reserved address 0x1c4

// Reserved address 0x1c8

// Reserved address 0x1cc

// Reserved address 0x1d0

// Reserved address 0x1d4

// Reserved address 0x1d8

// Reserved address 0x1dc

// Reserved address 0x1e0

// Reserved address 0x1e4

// Reserved address 0x1e8

// Register QSPI_QSPI_COMP_CONTROL_0
#define QSPI_QSPI_COMP_CONTROL_0                        _MK_ADDR_CONST(0x1ec)
#define QSPI_QSPI_COMP_CONTROL_0_SECURE                         0x0
#define QSPI_QSPI_COMP_CONTROL_0_DUAL                   0x0
#define QSPI_QSPI_COMP_CONTROL_0_SCR                    0
#define QSPI_QSPI_COMP_CONTROL_0_WORD_COUNT                     0x1
#define QSPI_QSPI_COMP_CONTROL_0_RESET_VAL                      _MK_MASK_CONST(0xa0a000)
#define QSPI_QSPI_COMP_CONTROL_0_RESET_MASK                     _MK_MASK_CONST(0x7f7f07a)
#define QSPI_QSPI_COMP_CONTROL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define QSPI_QSPI_COMP_CONTROL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QSPI_QSPI_COMP_CONTROL_0_READ_MASK                      _MK_MASK_CONST(0x7f7f07b)
#define QSPI_QSPI_COMP_CONTROL_0_WRITE_MASK                     _MK_MASK_CONST(0x7f7f07a)
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_CALIB_STATUS_SHIFT                   _MK_SHIFT_CONST(0)
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_CALIB_STATUS_FIELD                   _MK_FIELD_CONST(0x1, QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_CALIB_STATUS_SHIFT)
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_CALIB_STATUS_RANGE                   0:0
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_CALIB_STATUS_WOFFSET                 0x0
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_CALIB_STATUS_DEFAULT                 _MK_MASK_CONST(0x0)
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_CALIB_STATUS_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_CALIB_STATUS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_CALIB_STATUS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_CALIB_STATUS_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_CALIB_STATUS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_PAD_E_INPUT_OR_E_PWRD_SHIFT                  _MK_SHIFT_CONST(1)
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_PAD_E_INPUT_OR_E_PWRD_FIELD                  _MK_FIELD_CONST(0x1, QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_PAD_E_INPUT_OR_E_PWRD_SHIFT)
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_PAD_E_INPUT_OR_E_PWRD_RANGE                  1:1
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_PAD_E_INPUT_OR_E_PWRD_WOFFSET                        0x0
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_PAD_E_INPUT_OR_E_PWRD_DEFAULT                        _MK_MASK_CONST(0x0)
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_PAD_E_INPUT_OR_E_PWRD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_PAD_E_INPUT_OR_E_PWRD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_PAD_E_INPUT_OR_E_PWRD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_PAD_E_INPUT_OR_E_PWRD_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_PAD_E_INPUT_OR_E_PWRD_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_PAD_VREF_SEL_SHIFT                   _MK_SHIFT_CONST(3)
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_PAD_VREF_SEL_FIELD                   _MK_FIELD_CONST(0xf, QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_PAD_VREF_SEL_SHIFT)
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_PAD_VREF_SEL_RANGE                   6:3
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_PAD_VREF_SEL_WOFFSET                 0x0
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_PAD_VREF_SEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_PAD_VREF_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_PAD_VREF_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_PAD_VREF_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_PAD_VREF_SEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define QSPI_QSPI_COMP_CONTROL_0_QSPI_COMP_PAD_VREF_SEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define QSPI_QSPI_COMP_CONTROL_0_COMP_PAD_DRVDN_OVR_SHIFT                       _MK_SHIFT_CONST(12)
#define QSPI_QSPI_COMP_CONTROL_0_COMP_PAD_DRVDN_OVR_FIELD                       _MK_FIELD_CONST(0x7f, QSPI_QSPI_COMP_CONTROL_0_COMP_PAD_DRVDN_OVR_SHIFT)
#define QSPI_QSPI_COMP_CONTROL_0_COMP_PAD_DRVDN_OVR_RANGE                       18:12
#define QSPI_QSPI_COMP_CONTROL_0_COMP_PAD_DRVDN_OVR_WOFFSET                     0x0
#define QSPI_QSPI_COMP_CONTROL_0_COMP_PAD_DRVDN_OVR_DEFAULT                     _MK_MASK_CONST(0xa)
#define QSPI_QSPI_COMP_CONTROL_0_COMP_PAD_DRVDN_OVR_DEFAULT_MASK                        _MK_MASK_CONST(0x7f)
#define QSPI_QSPI_COMP_CONTROL_0_COMP_PAD_DRVDN_OVR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_QSPI_COMP_CONTROL_0_COMP_PAD_DRVDN_OVR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define QSPI_QSPI_COMP_CONTROL_0_COMP_PAD_DRVDN_OVR_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define QSPI_QSPI_COMP_CONTROL_0_COMP_PAD_DRVDN_OVR_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define QSPI_QSPI_COMP_CONTROL_0_COMP_PAD_DRVUP_OVR_SHIFT                       _MK_SHIFT_CONST(20)
#define QSPI_QSPI_COMP_CONTROL_0_COMP_PAD_DRVUP_OVR_FIELD                       _MK_FIELD_CONST(0x7f, QSPI_QSPI_COMP_CONTROL_0_COMP_PAD_DRVUP_OVR_SHIFT)
#define QSPI_QSPI_COMP_CONTROL_0_COMP_PAD_DRVUP_OVR_RANGE                       26:20
#define QSPI_QSPI_COMP_CONTROL_0_COMP_PAD_DRVUP_OVR_WOFFSET                     0x0
#define QSPI_QSPI_COMP_CONTROL_0_COMP_PAD_DRVUP_OVR_DEFAULT                     _MK_MASK_CONST(0xa)
#define QSPI_QSPI_COMP_CONTROL_0_COMP_PAD_DRVUP_OVR_DEFAULT_MASK                        _MK_MASK_CONST(0x7f)
#define QSPI_QSPI_COMP_CONTROL_0_COMP_PAD_DRVUP_OVR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_QSPI_COMP_CONTROL_0_COMP_PAD_DRVUP_OVR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define QSPI_QSPI_COMP_CONTROL_0_COMP_PAD_DRVUP_OVR_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define QSPI_QSPI_COMP_CONTROL_0_COMP_PAD_DRVUP_OVR_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register QSPI_AUTO_CAL_CONFIG_0
#define QSPI_AUTO_CAL_CONFIG_0                  _MK_ADDR_CONST(0x1f0)
#define QSPI_AUTO_CAL_CONFIG_0_SECURE                   0x0
#define QSPI_AUTO_CAL_CONFIG_0_DUAL                     0x0
#define QSPI_AUTO_CAL_CONFIG_0_SCR                      0
#define QSPI_AUTO_CAL_CONFIG_0_WORD_COUNT                       0x1
#define QSPI_AUTO_CAL_CONFIG_0_RESET_VAL                        _MK_MASK_CONST(0x10000)
#define QSPI_AUTO_CAL_CONFIG_0_RESET_MASK                       _MK_MASK_CONST(0xf0077f7f)
#define QSPI_AUTO_CAL_CONFIG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_READ_MASK                        _MK_MASK_CONST(0xf0077f7f)
#define QSPI_AUTO_CAL_CONFIG_0_WRITE_MASK                       _MK_MASK_CONST(0xf0077f7f)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_FIELD                 _MK_FIELD_CONST(0x7f, QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_SHIFT)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_RANGE                 6:0
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_WOFFSET                       0x0
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_DEFAULT_MASK                  _MK_MASK_CONST(0x7f)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_SHIFT                 _MK_SHIFT_CONST(8)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_FIELD                 _MK_FIELD_CONST(0x7f, QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_SHIFT)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_RANGE                 14:8
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_WOFFSET                       0x0
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_DEFAULT_MASK                  _MK_MASK_CONST(0x7f)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_SHIFT                      _MK_SHIFT_CONST(16)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_FIELD                      _MK_FIELD_CONST(0x7, QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_SHIFT)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_RANGE                      18:16
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_WOFFSET                    0x0
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_DEFAULT                    _MK_MASK_CONST(0x1)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_SLW_OVERRIDE_SHIFT                      _MK_SHIFT_CONST(28)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_SLW_OVERRIDE_FIELD                      _MK_FIELD_CONST(0x1, QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_SLW_OVERRIDE_SHIFT)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_SLW_OVERRIDE_RANGE                      28:28
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_SLW_OVERRIDE_WOFFSET                    0x0
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_SLW_OVERRIDE_DEFAULT                    _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_SLW_OVERRIDE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_SLW_OVERRIDE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_SLW_OVERRIDE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_SLW_OVERRIDE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_SLW_OVERRIDE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_SLW_OVERRIDE_NORMAL                     _MK_ENUM_CONST(0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_SLW_OVERRIDE_OVERRIDE                   _MK_ENUM_CONST(1)

#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_SHIFT                    _MK_SHIFT_CONST(29)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_SHIFT)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_RANGE                    29:29
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_WOFFSET                  0x0
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_INIT_ENUM                        DISABLED
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_ENABLED                  _MK_ENUM_CONST(1)

#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_SHIFT                  _MK_SHIFT_CONST(30)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_FIELD                  _MK_FIELD_CONST(0x1, QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_SHIFT)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_RANGE                  30:30
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_WOFFSET                        0x0
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_NORMAL                 _MK_ENUM_CONST(0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_OVERRIDE                       _MK_ENUM_CONST(1)

#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_START_SHIFT                     _MK_SHIFT_CONST(31)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_START_FIELD                     _MK_FIELD_CONST(0x1, QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_START_SHIFT)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_START_RANGE                     31:31
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_START_WOFFSET                   0x0
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_START_DEFAULT                   _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_START_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_START_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_START_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_START_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_CONFIG_0_AUTO_CAL_START_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register QSPI_AUTO_CAL_INTERVAL_0
#define QSPI_AUTO_CAL_INTERVAL_0                        _MK_ADDR_CONST(0x1f4)
#define QSPI_AUTO_CAL_INTERVAL_0_SECURE                         0x0
#define QSPI_AUTO_CAL_INTERVAL_0_DUAL                   0x0
#define QSPI_AUTO_CAL_INTERVAL_0_SCR                    0
#define QSPI_AUTO_CAL_INTERVAL_0_WORD_COUNT                     0x1
#define QSPI_AUTO_CAL_INTERVAL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_INTERVAL_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define QSPI_AUTO_CAL_INTERVAL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_INTERVAL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_INTERVAL_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define QSPI_AUTO_CAL_INTERVAL_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define QSPI_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_SHIFT                        _MK_SHIFT_CONST(0)
#define QSPI_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_FIELD                        _MK_FIELD_CONST(0xffffffff, QSPI_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_SHIFT)
#define QSPI_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_RANGE                        31:0
#define QSPI_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_WOFFSET                      0x0
#define QSPI_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define QSPI_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register QSPI_AUTO_CAL_STATUS_0
#define QSPI_AUTO_CAL_STATUS_0                  _MK_ADDR_CONST(0x1f8)
#define QSPI_AUTO_CAL_STATUS_0_SECURE                   0x0
#define QSPI_AUTO_CAL_STATUS_0_DUAL                     0x0
#define QSPI_AUTO_CAL_STATUS_0_SCR                      0
#define QSPI_AUTO_CAL_STATUS_0_WORD_COUNT                       0x1
#define QSPI_AUTO_CAL_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0xff7f7f7f)
#define QSPI_AUTO_CAL_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_STATUS_0_READ_MASK                        _MK_MASK_CONST(0xff7f7f7f)
#define QSPI_AUTO_CAL_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_SHIFT                    _MK_SHIFT_CONST(0)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_FIELD                    _MK_FIELD_CONST(0x7f, QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_SHIFT)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_RANGE                    6:0
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_WOFFSET                  0x0
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_SHIFT                  _MK_SHIFT_CONST(8)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_FIELD                  _MK_FIELD_CONST(0x7f, QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_SHIFT)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_RANGE                  14:8
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_WOFFSET                        0x0
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_DEFAULT                        _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_DEFAULT_MASK                   _MK_MASK_CONST(0x7f)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_SHIFT                        _MK_SHIFT_CONST(16)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_FIELD                        _MK_FIELD_CONST(0x7f, QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_SHIFT)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_RANGE                        22:16
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_WOFFSET                      0x0
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_DEFAULT                      _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_SHIFT                      _MK_SHIFT_CONST(24)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_FIELD                      _MK_FIELD_CONST(0x7f, QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_SHIFT)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_RANGE                      30:24
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_WOFFSET                    0x0
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_DEFAULT                    _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_DEFAULT_MASK                       _MK_MASK_CONST(0x7f)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_SHIFT                    _MK_SHIFT_CONST(31)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_FIELD                    _MK_FIELD_CONST(0x1, QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_SHIFT)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_RANGE                    31:31
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_WOFFSET                  0x0
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_DEFAULT                  _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define QSPI_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


//
// REGISTER LIST
//
#define LIST_ARQSPI_REGS(_op_) \
_op_(QSPI_COMMAND_0) \
_op_(QSPI_COMMAND2_0) \
_op_(QSPI_TIMING_REG1_0) \
_op_(QSPI_TIMING_REG2_0) \
_op_(QSPI_TRANSFER_STATUS_0) \
_op_(QSPI_FIFO_STATUS_0) \
_op_(QSPI_TX_DATA_0) \
_op_(QSPI_RX_DATA_0) \
_op_(QSPI_DMA_CTL_0) \
_op_(QSPI_DMA_BLK_SIZE_0) \
_op_(QSPI_TX_FIFO_0) \
_op_(QSPI_RX_FIFO_0) \
_op_(QSPI_INTR_MASK_0) \
_op_(QSPI_SPARE_CTLR_0) \
_op_(QSPI_MISC_0) \
_op_(QSPI_TIMING3_0) \
_op_(QSPI_CMB_SEQ_CMD_0) \
_op_(QSPI_CMB_SEQ_CMD_CFG_0) \
_op_(QSPI_GLOBAL_CONFIG_0) \
_op_(QSPI_CMB_SEQ_ADDR_0) \
_op_(QSPI_CMB_SEQ_ADDR_CFG_0) \
_op_(QSPI_QSPI_COMP_CONTROL_0) \
_op_(QSPI_AUTO_CAL_CONFIG_0) \
_op_(QSPI_AUTO_CAL_INTERVAL_0) \
_op_(QSPI_AUTO_CAL_STATUS_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_QSPI       0x00000000

//
// ARQSPI REGISTER BANKS
//

#define QSPI0_FIRST_REG 0x0000 // QSPI_COMMAND_0
#define QSPI0_LAST_REG 0x0024 // QSPI_DMA_BLK_SIZE_0
#define QSPI1_FIRST_REG 0x0108 // QSPI_TX_FIFO_0
#define QSPI1_LAST_REG 0x0108 // QSPI_TX_FIFO_0
#define QSPI2_FIRST_REG 0x0188 // QSPI_RX_FIFO_0
#define QSPI2_LAST_REG 0x01ac // QSPI_CMB_SEQ_ADDR_CFG_0
#define QSPI3_FIRST_REG 0x01ec // QSPI_QSPI_COMP_CONTROL_0
#define QSPI3_LAST_REG 0x01f8 // QSPI_AUTO_CAL_STATUS_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif
#ifndef _MK_FIELD_CONST
  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
#endif

#endif // ifndef ___ARQSPI_H_INC_
