//
// Copyright (c) 2018 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ___ARSOR1_H_INC_
#define ___ARSOR1_H_INC_
#define NV_MOBILE_ARSOR1_H_UNIT_OF_OFFSET 1B

// Packet DISPLAY2SOR
#define DISPLAY2SOR_SIZE 45

#define DISPLAY2SOR_R_DATA_SHIFT                        _MK_SHIFT_CONST(0)
#define DISPLAY2SOR_R_DATA_FIELD                        _MK_FIELD_CONST(0xfff, DISPLAY2SOR_R_DATA_SHIFT)
#define DISPLAY2SOR_R_DATA_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
#define DISPLAY2SOR_R_DATA_ROW                  0

#define DISPLAY2SOR_G_DATA_SHIFT                        _MK_SHIFT_CONST(12)
#define DISPLAY2SOR_G_DATA_FIELD                        _MK_FIELD_CONST(0xfff, DISPLAY2SOR_G_DATA_SHIFT)
#define DISPLAY2SOR_G_DATA_RANGE                        _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(12)
#define DISPLAY2SOR_G_DATA_ROW                  0

#define DISPLAY2SOR_B_DATA_SHIFT                        _MK_SHIFT_CONST(24)
#define DISPLAY2SOR_B_DATA_FIELD                        _MK_FIELD_CONST(0xfff, DISPLAY2SOR_B_DATA_SHIFT)
#define DISPLAY2SOR_B_DATA_RANGE                        _MK_SHIFT_CONST(35):_MK_SHIFT_CONST(24)
#define DISPLAY2SOR_B_DATA_ROW                  0

#define DISPLAY2SOR_HBLANK_SHIFT                        _MK_SHIFT_CONST(36)
#define DISPLAY2SOR_HBLANK_FIELD                        _MK_FIELD_CONST(0x1, DISPLAY2SOR_HBLANK_SHIFT)
#define DISPLAY2SOR_HBLANK_RANGE                        _MK_SHIFT_CONST(36):_MK_SHIFT_CONST(36)
#define DISPLAY2SOR_HBLANK_ROW                  0

#define DISPLAY2SOR_VBLANK_SHIFT                        _MK_SHIFT_CONST(37)
#define DISPLAY2SOR_VBLANK_FIELD                        _MK_FIELD_CONST(0x1, DISPLAY2SOR_VBLANK_SHIFT)
#define DISPLAY2SOR_VBLANK_RANGE                        _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(37)
#define DISPLAY2SOR_VBLANK_ROW                  0

#define DISPLAY2SOR_HSYNC_SHIFT                 _MK_SHIFT_CONST(38)
#define DISPLAY2SOR_HSYNC_FIELD                 _MK_FIELD_CONST(0x1, DISPLAY2SOR_HSYNC_SHIFT)
#define DISPLAY2SOR_HSYNC_RANGE                 _MK_SHIFT_CONST(38):_MK_SHIFT_CONST(38)
#define DISPLAY2SOR_HSYNC_ROW                   0

#define DISPLAY2SOR_VSYNC_SHIFT                 _MK_SHIFT_CONST(39)
#define DISPLAY2SOR_VSYNC_FIELD                 _MK_FIELD_CONST(0x1, DISPLAY2SOR_VSYNC_SHIFT)
#define DISPLAY2SOR_VSYNC_RANGE                 _MK_SHIFT_CONST(39):_MK_SHIFT_CONST(39)
#define DISPLAY2SOR_VSYNC_ROW                   0

#define DISPLAY2SOR_LOADV_SHIFT                 _MK_SHIFT_CONST(40)
#define DISPLAY2SOR_LOADV_FIELD                 _MK_FIELD_CONST(0x1, DISPLAY2SOR_LOADV_SHIFT)
#define DISPLAY2SOR_LOADV_RANGE                 _MK_SHIFT_CONST(40):_MK_SHIFT_CONST(40)
#define DISPLAY2SOR_LOADV_ROW                   0

#define DISPLAY2SOR_CRC_SHIFT                   _MK_SHIFT_CONST(41)
#define DISPLAY2SOR_CRC_FIELD                   _MK_FIELD_CONST(0x1, DISPLAY2SOR_CRC_SHIFT)
#define DISPLAY2SOR_CRC_RANGE                   _MK_SHIFT_CONST(41):_MK_SHIFT_CONST(41)
#define DISPLAY2SOR_CRC_ROW                     0

#define DISPLAY2SOR_CSPC_SHIFT                  _MK_SHIFT_CONST(42)
#define DISPLAY2SOR_CSPC_FIELD                  _MK_FIELD_CONST(0x1, DISPLAY2SOR_CSPC_SHIFT)
#define DISPLAY2SOR_CSPC_RANGE                  _MK_SHIFT_CONST(42):_MK_SHIFT_CONST(42)
#define DISPLAY2SOR_CSPC_ROW                    0

#define DISPLAY2SOR_CTL_SHIFT                   _MK_SHIFT_CONST(43)
#define DISPLAY2SOR_CTL_FIELD                   _MK_FIELD_CONST(0x1, DISPLAY2SOR_CTL_SHIFT)
#define DISPLAY2SOR_CTL_RANGE                   _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(43)
#define DISPLAY2SOR_CTL_ROW                     0

#define DISPLAY2SOR_VIDEO_PREAMBLE_SHIFT                        _MK_SHIFT_CONST(44)
#define DISPLAY2SOR_VIDEO_PREAMBLE_FIELD                        _MK_FIELD_CONST(0x1, DISPLAY2SOR_VIDEO_PREAMBLE_SHIFT)
#define DISPLAY2SOR_VIDEO_PREAMBLE_RANGE                        _MK_SHIFT_CONST(44):_MK_SHIFT_CONST(44)
#define DISPLAY2SOR_VIDEO_PREAMBLE_ROW                  0

// Packet HDMI_BFM_HDMI_DECODER_CONFIG
#define HDMI_BFM_HDMI_DECODER_CONFIG_SIZE 7

#define HDMI_BFM_HDMI_DECODER_CONFIG_HDMI_DECODER_EN_SHIFT                      _MK_SHIFT_CONST(9)
#define HDMI_BFM_HDMI_DECODER_CONFIG_HDMI_DECODER_EN_FIELD                      _MK_FIELD_CONST(0x1, HDMI_BFM_HDMI_DECODER_CONFIG_HDMI_DECODER_EN_SHIFT)
#define HDMI_BFM_HDMI_DECODER_CONFIG_HDMI_DECODER_EN_RANGE                      _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(9)
#define HDMI_BFM_HDMI_DECODER_CONFIG_HDMI_DECODER_EN_ROW                        0
#define HDMI_BFM_HDMI_DECODER_CONFIG_HDMI_DECODER_EN_DISABLE                    _MK_ENUM_CONST(0)
#define HDMI_BFM_HDMI_DECODER_CONFIG_HDMI_DECODER_EN_ENABLE                     _MK_ENUM_CONST(1)

#define HDMI_BFM_HDMI_DECODER_CONFIG_DECODE_EN_SHIFT                    _MK_SHIFT_CONST(10)
#define HDMI_BFM_HDMI_DECODER_CONFIG_DECODE_EN_FIELD                    _MK_FIELD_CONST(0x1, HDMI_BFM_HDMI_DECODER_CONFIG_DECODE_EN_SHIFT)
#define HDMI_BFM_HDMI_DECODER_CONFIG_DECODE_EN_RANGE                    _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(10)
#define HDMI_BFM_HDMI_DECODER_CONFIG_DECODE_EN_ROW                      0
#define HDMI_BFM_HDMI_DECODER_CONFIG_DECODE_EN_DISABLE                  _MK_ENUM_CONST(0)
#define HDMI_BFM_HDMI_DECODER_CONFIG_DECODE_EN_ENABLE                   _MK_ENUM_CONST(1)

#define HDMI_BFM_HDMI_DECODER_CONFIG_DUAL_HDCP_EN_SHIFT                 _MK_SHIFT_CONST(11)
#define HDMI_BFM_HDMI_DECODER_CONFIG_DUAL_HDCP_EN_FIELD                 _MK_FIELD_CONST(0x1, HDMI_BFM_HDMI_DECODER_CONFIG_DUAL_HDCP_EN_SHIFT)
#define HDMI_BFM_HDMI_DECODER_CONFIG_DUAL_HDCP_EN_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(11)
#define HDMI_BFM_HDMI_DECODER_CONFIG_DUAL_HDCP_EN_ROW                   0

#define HDMI_BFM_HDMI_DECODER_CONFIG_DUAL_LINK_EN_SHIFT                 _MK_SHIFT_CONST(12)
#define HDMI_BFM_HDMI_DECODER_CONFIG_DUAL_LINK_EN_FIELD                 _MK_FIELD_CONST(0x1, HDMI_BFM_HDMI_DECODER_CONFIG_DUAL_LINK_EN_SHIFT)
#define HDMI_BFM_HDMI_DECODER_CONFIG_DUAL_LINK_EN_RANGE                 _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(12)
#define HDMI_BFM_HDMI_DECODER_CONFIG_DUAL_LINK_EN_ROW                   0

#define HDMI_BFM_HDMI_DECODER_CONFIG_VIDEO_COUNT_EN_SHIFT                       _MK_SHIFT_CONST(13)
#define HDMI_BFM_HDMI_DECODER_CONFIG_VIDEO_COUNT_EN_FIELD                       _MK_FIELD_CONST(0x1, HDMI_BFM_HDMI_DECODER_CONFIG_VIDEO_COUNT_EN_SHIFT)
#define HDMI_BFM_HDMI_DECODER_CONFIG_VIDEO_COUNT_EN_RANGE                       _MK_SHIFT_CONST(13):_MK_SHIFT_CONST(13)
#define HDMI_BFM_HDMI_DECODER_CONFIG_VIDEO_COUNT_EN_ROW                 0
#define HDMI_BFM_HDMI_DECODER_CONFIG_VIDEO_COUNT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define HDMI_BFM_HDMI_DECODER_CONFIG_VIDEO_COUNT_EN_ENABLE                      _MK_ENUM_CONST(1)

#define HDMI_BFM_HDMI_DECODER_CONFIG_DUMP_EN_SHIFT                      _MK_SHIFT_CONST(15)
#define HDMI_BFM_HDMI_DECODER_CONFIG_DUMP_EN_FIELD                      _MK_FIELD_CONST(0x1, HDMI_BFM_HDMI_DECODER_CONFIG_DUMP_EN_SHIFT)
#define HDMI_BFM_HDMI_DECODER_CONFIG_DUMP_EN_RANGE                      _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
#define HDMI_BFM_HDMI_DECODER_CONFIG_DUMP_EN_ROW                        0
#define HDMI_BFM_HDMI_DECODER_CONFIG_DUMP_EN_DISABLE                    _MK_ENUM_CONST(0)
#define HDMI_BFM_HDMI_DECODER_CONFIG_DUMP_EN_ENABLE                     _MK_ENUM_CONST(1)

// Packet HDMI_BFM_HDCP_DECODER_CONFIG
#define HDMI_BFM_HDCP_DECODER_CONFIG_SIZE 32

#define HDMI_BFM_HDCP_DECODER_CONFIG_HDCP_EN_SHIFT                      _MK_SHIFT_CONST(0)
#define HDMI_BFM_HDCP_DECODER_CONFIG_HDCP_EN_FIELD                      _MK_FIELD_CONST(0x1, HDMI_BFM_HDCP_DECODER_CONFIG_HDCP_EN_SHIFT)
#define HDMI_BFM_HDCP_DECODER_CONFIG_HDCP_EN_RANGE                      _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
#define HDMI_BFM_HDCP_DECODER_CONFIG_HDCP_EN_ROW                        0
#define HDMI_BFM_HDCP_DECODER_CONFIG_HDCP_EN_DISABLE                    _MK_ENUM_CONST(0)
#define HDMI_BFM_HDCP_DECODER_CONFIG_HDCP_EN_ENABLE                     _MK_ENUM_CONST(1)

#define HDMI_BFM_HDCP_DECODER_CONFIG_PAIR_SEL_SHIFT                     _MK_SHIFT_CONST(1)
#define HDMI_BFM_HDCP_DECODER_CONFIG_PAIR_SEL_FIELD                     _MK_FIELD_CONST(0x3, HDMI_BFM_HDCP_DECODER_CONFIG_PAIR_SEL_SHIFT)
#define HDMI_BFM_HDCP_DECODER_CONFIG_PAIR_SEL_RANGE                     _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(1)
#define HDMI_BFM_HDCP_DECODER_CONFIG_PAIR_SEL_ROW                       0

#define HDMI_BFM_HDCP_DECODER_CONFIG_REPEATER_SHIFT                     _MK_SHIFT_CONST(3)
#define HDMI_BFM_HDCP_DECODER_CONFIG_REPEATER_FIELD                     _MK_FIELD_CONST(0x1, HDMI_BFM_HDCP_DECODER_CONFIG_REPEATER_SHIFT)
#define HDMI_BFM_HDCP_DECODER_CONFIG_REPEATER_RANGE                     _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
#define HDMI_BFM_HDCP_DECODER_CONFIG_REPEATER_ROW                       0
#define HDMI_BFM_HDCP_DECODER_CONFIG_REPEATER_DISABLE                   _MK_ENUM_CONST(0)
#define HDMI_BFM_HDCP_DECODER_CONFIG_REPEATER_ENABLE                    _MK_ENUM_CONST(1)

#define HDMI_BFM_HDCP_DECODER_CONFIG_KEY_LOAD_SHIFT                     _MK_SHIFT_CONST(4)
#define HDMI_BFM_HDCP_DECODER_CONFIG_KEY_LOAD_FIELD                     _MK_FIELD_CONST(0x1, HDMI_BFM_HDCP_DECODER_CONFIG_KEY_LOAD_SHIFT)
#define HDMI_BFM_HDCP_DECODER_CONFIG_KEY_LOAD_RANGE                     _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4)
#define HDMI_BFM_HDCP_DECODER_CONFIG_KEY_LOAD_ROW                       0

#define HDMI_BFM_HDCP_DECODER_CONFIG_ONEONE_EN_SHIFT                    _MK_SHIFT_CONST(9)
#define HDMI_BFM_HDCP_DECODER_CONFIG_ONEONE_EN_FIELD                    _MK_FIELD_CONST(0x1, HDMI_BFM_HDCP_DECODER_CONFIG_ONEONE_EN_SHIFT)
#define HDMI_BFM_HDCP_DECODER_CONFIG_ONEONE_EN_RANGE                    _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(9)
#define HDMI_BFM_HDCP_DECODER_CONFIG_ONEONE_EN_ROW                      0
#define HDMI_BFM_HDCP_DECODER_CONFIG_ONEONE_EN_DISABLE                  _MK_ENUM_CONST(0)
#define HDMI_BFM_HDCP_DECODER_CONFIG_ONEONE_EN_ENABLE                   _MK_ENUM_CONST(1)

#define HDMI_BFM_HDCP_DECODER_CONFIG_FAST_REAUTH_SHIFT                  _MK_SHIFT_CONST(10)
#define HDMI_BFM_HDCP_DECODER_CONFIG_FAST_REAUTH_FIELD                  _MK_FIELD_CONST(0x1, HDMI_BFM_HDCP_DECODER_CONFIG_FAST_REAUTH_SHIFT)
#define HDMI_BFM_HDCP_DECODER_CONFIG_FAST_REAUTH_RANGE                  _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(10)
#define HDMI_BFM_HDCP_DECODER_CONFIG_FAST_REAUTH_ROW                    0

#define HDMI_BFM_HDCP_DECODER_CONFIG_SW_AUTH_SHIFT                      _MK_SHIFT_CONST(29)
#define HDMI_BFM_HDCP_DECODER_CONFIG_SW_AUTH_FIELD                      _MK_FIELD_CONST(0x1, HDMI_BFM_HDCP_DECODER_CONFIG_SW_AUTH_SHIFT)
#define HDMI_BFM_HDCP_DECODER_CONFIG_SW_AUTH_RANGE                      _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
#define HDMI_BFM_HDCP_DECODER_CONFIG_SW_AUTH_ROW                        0

#define HDMI_BFM_HDCP_DECODER_CONFIG_UNAUTH_MODE_SHIFT                  _MK_SHIFT_CONST(31)
#define HDMI_BFM_HDCP_DECODER_CONFIG_UNAUTH_MODE_FIELD                  _MK_FIELD_CONST(0x1, HDMI_BFM_HDCP_DECODER_CONFIG_UNAUTH_MODE_SHIFT)
#define HDMI_BFM_HDCP_DECODER_CONFIG_UNAUTH_MODE_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
#define HDMI_BFM_HDCP_DECODER_CONFIG_UNAUTH_MODE_ROW                    0

// Packet HDMI_SPDIF_TRANSMITTER_BFM_CONTROL
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_SIZE 32

#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_SAMPLE_LENGTH_MISMATCH_SHIFT                 _MK_SHIFT_CONST(0)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_SAMPLE_LENGTH_MISMATCH_FIELD                 _MK_FIELD_CONST(0x3, HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_SAMPLE_LENGTH_MISMATCH_SHIFT)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_SAMPLE_LENGTH_MISMATCH_RANGE                 _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(0)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_SAMPLE_LENGTH_MISMATCH_ROW                   0

#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_FRAME_SIZE_MISMATCH_SHIFT                    _MK_SHIFT_CONST(2)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_FRAME_SIZE_MISMATCH_FIELD                    _MK_FIELD_CONST(0x3, HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_FRAME_SIZE_MISMATCH_SHIFT)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_FRAME_SIZE_MISMATCH_RANGE                    _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(2)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_FRAME_SIZE_MISMATCH_ROW                      0

#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_BMW_MISMATCH_SHIFT                   _MK_SHIFT_CONST(4)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_BMW_MISMATCH_FIELD                   _MK_FIELD_CONST(0x3, HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_BMW_MISMATCH_SHIFT)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_BMW_MISMATCH_RANGE                   _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(4)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_BMW_MISMATCH_ROW                     0

#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_ADD_GLITCH_SHIFT                     _MK_SHIFT_CONST(6)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_ADD_GLITCH_FIELD                     _MK_FIELD_CONST(0x1, HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_ADD_GLITCH_SHIFT)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_ADD_GLITCH_RANGE                     _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_ADD_GLITCH_ROW                       0

#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_SAMPLE_DATA_TYPE_SHIFT                       _MK_SHIFT_CONST(7)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_SAMPLE_DATA_TYPE_FIELD                       _MK_FIELD_CONST(0x7, HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_SAMPLE_DATA_TYPE_SHIFT)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_SAMPLE_DATA_TYPE_RANGE                       _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(7)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_SAMPLE_DATA_TYPE_ROW                 0

#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_SAMPLING_FREQ_SHIFT                  _MK_SHIFT_CONST(10)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_SAMPLING_FREQ_FIELD                  _MK_FIELD_CONST(0xf, HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_SAMPLING_FREQ_SHIFT)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_SAMPLING_FREQ_RANGE                  _MK_SHIFT_CONST(13):_MK_SHIFT_CONST(10)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_SAMPLING_FREQ_ROW                    0

#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_JITTER_SHIFT                 _MK_SHIFT_CONST(14)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_JITTER_FIELD                 _MK_FIELD_CONST(0x3, HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_JITTER_SHIFT)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_JITTER_RANGE                 _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(14)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_JITTER_ROW                   0

#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_LOOP_CNT_SHIFT                       _MK_SHIFT_CONST(16)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_LOOP_CNT_FIELD                       _MK_FIELD_CONST(0xfff, HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_LOOP_CNT_SHIFT)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_LOOP_CNT_RANGE                       _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(16)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_LOOP_CNT_ROW                 0

#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_POLARITY_SHIFT                       _MK_SHIFT_CONST(28)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_POLARITY_FIELD                       _MK_FIELD_CONST(0x1, HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_POLARITY_SHIFT)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_POLARITY_RANGE                       _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_POLARITY_ROW                 0
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_POLARITY_NORMAL                      _MK_ENUM_CONST(0)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_POLARITY_INVERT                      _MK_ENUM_CONST(1)

#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_VARIABLE_FREQ_SHIFT                  _MK_SHIFT_CONST(29)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_VARIABLE_FREQ_FIELD                  _MK_FIELD_CONST(0x1, HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_VARIABLE_FREQ_SHIFT)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_VARIABLE_FREQ_RANGE                  _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_VARIABLE_FREQ_ROW                    0

#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_ERROR_FREE_SHIFT                     _MK_SHIFT_CONST(30)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_ERROR_FREE_FIELD                     _MK_FIELD_CONST(0x1, HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_ERROR_FREE_SHIFT)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_ERROR_FREE_RANGE                     _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_ERROR_FREE_ROW                       0

#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_LOAD_SHIFT                   _MK_SHIFT_CONST(31)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_LOAD_FIELD                   _MK_FIELD_CONST(0x1, HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_LOAD_SHIFT)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_LOAD_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
#define HDMI_SPDIF_TRANSMITTER_BFM_CONTROL_LOAD_ROW                     0

// Register SOR_NV_PDISP_SOR_SUPER_STATE0_0
#define SOR_NV_PDISP_SOR_SUPER_STATE0_0                 _MK_ADDR_CONST(0x1)
#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_SCR                     0
#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_UPDATE_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_UPDATE_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SUPER_STATE0_0_UPDATE_SHIFT)
#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_UPDATE_RANGE                    0:0
#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_UPDATE_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_UPDATE_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_UPDATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_UPDATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_UPDATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_UPDATE_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_UPDATE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_SUPER_STATE1_0
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0                 _MK_ADDR_CONST(0x2)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_SCR                     0
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_RESET_MASK                      _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_READ_MASK                       _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_WRITE_MASK                      _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ATTACHED_SHIFT                  _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ATTACHED_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SUPER_STATE1_0_ATTACHED_SHIFT)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ATTACHED_RANGE                  3:3
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ATTACHED_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ATTACHED_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ATTACHED_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ATTACHED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ATTACHED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ATTACHED_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ATTACHED_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ATTACHED_INIT_ENUM                      NO
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ATTACHED_NO                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ATTACHED_YES                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_ORMODE_SHIFT                        _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_ORMODE_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_ORMODE_SHIFT)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_ORMODE_RANGE                        2:2
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_ORMODE_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_ORMODE_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_ORMODE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_ORMODE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_ORMODE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_ORMODE_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_ORMODE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_ORMODE_INIT_ENUM                    SAFE
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_ORMODE_SAFE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_ORMODE_NORMAL                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_HEAD_OPMODE_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_HEAD_OPMODE_FIELD                   _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_HEAD_OPMODE_SHIFT)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_HEAD_OPMODE_RANGE                   1:0
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_HEAD_OPMODE_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_HEAD_OPMODE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_HEAD_OPMODE_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_HEAD_OPMODE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_HEAD_OPMODE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_HEAD_OPMODE_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_HEAD_OPMODE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_HEAD_OPMODE_SLEEP                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_HEAD_OPMODE_SNOOZE                  _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_HEAD_OPMODE_AWAKE                   _MK_ENUM_CONST(2)

// Register SOR_NV_PDISP_SOR_STATE0_0
#define SOR_NV_PDISP_SOR_STATE0_0                       _MK_ADDR_CONST(0x3)
#define SOR_NV_PDISP_SOR_STATE0_0_SECURE                        0x0
#define SOR_NV_PDISP_SOR_STATE0_0_DUAL                  0x0
#define SOR_NV_PDISP_SOR_STATE0_0_SCR                   0
#define SOR_NV_PDISP_SOR_STATE0_0_WORD_COUNT                    0x1
#define SOR_NV_PDISP_SOR_STATE0_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE0_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE0_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE0_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE0_0_UPDATE_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_STATE0_0_UPDATE_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_STATE0_0_UPDATE_SHIFT)
#define SOR_NV_PDISP_SOR_STATE0_0_UPDATE_RANGE                  0:0
#define SOR_NV_PDISP_SOR_STATE0_0_UPDATE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_STATE0_0_UPDATE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE0_0_UPDATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE0_0_UPDATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE0_0_UPDATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE0_0_UPDATE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE0_0_UPDATE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_STATE1_0
#define SOR_NV_PDISP_SOR_STATE1_0                       _MK_ADDR_CONST(0x4)
#define SOR_NV_PDISP_SOR_STATE1_0_SECURE                        0x0
#define SOR_NV_PDISP_SOR_STATE1_0_DUAL                  0x0
#define SOR_NV_PDISP_SOR_STATE1_0_SCR                   0
#define SOR_NV_PDISP_SOR_STATE1_0_WORD_COUNT                    0x1
#define SOR_NV_PDISP_SOR_STATE1_0_RESET_VAL                     _MK_MASK_CONST(0x40)
#define SOR_NV_PDISP_SOR_STATE1_0_RESET_MASK                    _MK_MASK_CONST(0x21fffff)
#define SOR_NV_PDISP_SOR_STATE1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_READ_MASK                     _MK_MASK_CONST(0x21fffff)
#define SOR_NV_PDISP_SOR_STATE1_0_WRITE_MASK                    _MK_MASK_CONST(0x21fffff)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CHROMA_V_DECIMATE_SHIFT                   _MK_SHIFT_CONST(25)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CHROMA_V_DECIMATE_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_STATE1_0_ASY_CHROMA_V_DECIMATE_SHIFT)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CHROMA_V_DECIMATE_RANGE                   25:25
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CHROMA_V_DECIMATE_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CHROMA_V_DECIMATE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CHROMA_V_DECIMATE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CHROMA_V_DECIMATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CHROMA_V_DECIMATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CHROMA_V_DECIMATE_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CHROMA_V_DECIMATE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CHROMA_V_DECIMATE_DISABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CHROMA_V_DECIMATE_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_SHIFT                  _MK_SHIFT_CONST(17)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_FIELD                  _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_SHIFT)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_RANGE                  20:17
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_INIT_ENUM                      DEFAULTVAL
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_DEFAULTVAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_16_422                     _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_18_444                     _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_20_422                     _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_24_422                     _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_24_444                     _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_30_444                     _MK_ENUM_CONST(6)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_32_422                     _MK_ENUM_CONST(7)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_36_444                     _MK_ENUM_CONST(8)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_48_444                     _MK_ENUM_CONST(9)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_12_420                     _MK_ENUM_CONST(10)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_15_420                     _MK_ENUM_CONST(11)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_18_420                     _MK_ENUM_CONST(12)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_24_420                     _MK_ENUM_CONST(13)

#define SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_SHIFT                   _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_FIELD                   _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_SHIFT)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_RANGE                   16:15
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_INIT_ENUM                       OFF
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_OFF                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_X2                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_X4                      _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_STATE1_0_ASY_DEPOL_SHIFT                       _MK_SHIFT_CONST(14)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_DEPOL_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_STATE1_0_ASY_DEPOL_SHIFT)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_DEPOL_RANGE                       14:14
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_DEPOL_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_DEPOL_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_DEPOL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_DEPOL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_DEPOL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_DEPOL_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_DEPOL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_DEPOL_POSITIVE_TRUE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_DEPOL_NEGATIVE_TRUE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_SHIFT                    _MK_SHIFT_CONST(13)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_SHIFT)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_RANGE                    13:13
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_POSITIVE_TRUE                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_NEGATIVE_TRUE                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_SHIFT                    _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_SHIFT)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_RANGE                    12:12
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_POSITIVE_TRUE                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_NEGATIVE_TRUE                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_SHIFT                    _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_FIELD                    _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_SHIFT)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_RANGE                    11:8
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_INIT_ENUM                        LVDS_CUSTOM
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_LVDS_CUSTOM                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_SINGLE_TMDS_A                    _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_SINGLE_TMDS_B                    _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_DP_A                     _MK_ENUM_CONST(8)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_DP_B                     _MK_ENUM_CONST(9)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_CUSTOM                   _MK_ENUM_CONST(15)

#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_SHIFT                     _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_FIELD                     _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_SHIFT)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_RANGE                     7:6
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_DEFAULT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_INIT_ENUM                 COMPLETE_RASTER
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_ACTIVE_RASTER                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_COMPLETE_RASTER                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_NON_ACTIVE_RASTER                 _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SHIFT                    _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_FIELD                    _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SHIFT)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_RANGE                    5:4
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_INIT_ENUM                        NONE
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_NONE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SUBHEAD0                 _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SUBHEAD1                 _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_BOTH                     _MK_ENUM_CONST(3)

#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_FIELD                       _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_SHIFT)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_RANGE                       3:0
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_INIT_ENUM                   NONE
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_NONE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_HEAD0                       _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_HEAD1                       _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_HEAD2                       _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_HEAD3                       _MK_ENUM_CONST(4)

// Register SOR_NV_PDISP_SOR_CRC_CNTRL_0
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0                    _MK_ADDR_CONST(0x11)
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_SCR                        0
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_RANGE                       0:0
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_YES                 _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_DIS                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_EN                  _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0
#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0                        _MK_ADDR_CONST(0x12)
#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_SECURE                         0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_DUAL                   0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_SCR                    0
#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_WORD_COUNT                     0x1
#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_RESET_MASK                     _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_READ_MASK                      _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_VALUE_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_VALUE_FIELD                    _MK_FIELD_CONST(0xffffff, SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_VALUE_RANGE                    23:0
#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_VALUE_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_VALUE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_VALUE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_CLK_CNTRL_0
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0                    _MK_ADDR_CONST(0x13)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_SCR                        0
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_RESET_VAL                  _MK_MASK_CONST(0x1b)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_READ_MASK                  _MK_MASK_CONST(0x7f)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_WRITE_MASK                         _MK_MASK_CONST(0x7f)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_FIELD                   _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_SHIFT)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_RANGE                   1:0
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_DEFAULT                 _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_INIT_ENUM                       DIFF_DPCLK
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_SINGLE_PCLK                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_DIFF_PCLK                       _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_SINGLE_DPCLK                    _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_DIFF_DPCLK                      _MK_ENUM_CONST(3)

#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_SHIFT                        _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_FIELD                        _MK_FIELD_CONST(0x1f, SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_SHIFT)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_RANGE                        6:2
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_DEFAULT                      _MK_MASK_CONST(0x6)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_INIT_ENUM                    G1_62
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_G1_62                        _MK_ENUM_CONST(6)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_G2_7                 _MK_ENUM_CONST(10)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_LVDS                 _MK_ENUM_CONST(7)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_G5_4                 _MK_ENUM_CONST(20)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_G8_1                 _MK_ENUM_CONST(30)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_G2_16                        _MK_ENUM_CONST(8)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_G2_43                        _MK_ENUM_CONST(9)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_G3_24                        _MK_ENUM_CONST(12)
#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_G4_32                        _MK_ENUM_CONST(16)

// Register SOR_NV_PDISP_SOR_CAP_0
#define SOR_NV_PDISP_SOR_CAP_0                  _MK_ADDR_CONST(0x14)
#define SOR_NV_PDISP_SOR_CAP_0_SECURE                   0x0
#define SOR_NV_PDISP_SOR_CAP_0_DUAL                     0x0
#define SOR_NV_PDISP_SOR_CAP_0_SCR                      0
#define SOR_NV_PDISP_SOR_CAP_0_WORD_COUNT                       0x1
#define SOR_NV_PDISP_SOR_CAP_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_RESET_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_READ_MASK                        _MK_MASK_CONST(0x83113f0f)
#define SOR_NV_PDISP_SOR_CAP_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_18_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_18_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_18_SHIFT)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_18_RANGE                     0:0
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_18_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_18_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_18_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_18_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_18_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_18_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_18_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_18_FALSE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_18_TRUE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_24_SHIFT                     _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_24_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_24_SHIFT)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_24_RANGE                     1:1
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_24_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_24_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_24_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_24_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_24_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_24_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_24_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_24_FALSE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_24_TRUE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_18_SHIFT                       _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_18_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_18_SHIFT)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_18_RANGE                       2:2
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_18_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_18_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_18_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_18_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_18_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_18_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_18_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_18_FALSE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_18_TRUE                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_24_SHIFT                       _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_24_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_24_SHIFT)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_24_RANGE                       3:3
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_24_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_24_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_24_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_24_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_24_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_24_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_24_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_24_FALSE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_24_TRUE                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_A_SHIFT                      _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_A_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_A_SHIFT)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_A_RANGE                      8:8
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_A_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_A_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_A_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_A_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_A_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_A_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_A_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_A_FALSE                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_A_TRUE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_B_SHIFT                      _MK_SHIFT_CONST(9)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_B_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_B_SHIFT)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_B_RANGE                      9:9
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_B_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_B_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_B_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_B_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_B_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_B_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_B_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_B_FALSE                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_B_TRUE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CAP_0_DUAL_SINGLE_TMDS_SHIFT                   _MK_SHIFT_CONST(10)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_SINGLE_TMDS_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_DUAL_SINGLE_TMDS_SHIFT)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_SINGLE_TMDS_RANGE                   10:10
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_SINGLE_TMDS_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_SINGLE_TMDS_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_SINGLE_TMDS_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_SINGLE_TMDS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_SINGLE_TMDS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_SINGLE_TMDS_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_SINGLE_TMDS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_SINGLE_TMDS_FALSE                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_SINGLE_TMDS_TRUE                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CAP_0_DUAL_TMDS_SHIFT                  _MK_SHIFT_CONST(11)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_TMDS_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_DUAL_TMDS_SHIFT)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_TMDS_RANGE                  11:11
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_TMDS_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_TMDS_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_TMDS_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_TMDS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_TMDS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_TMDS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_TMDS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_TMDS_FALSE                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CAP_0_DUAL_TMDS_TRUE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_225_MHZ_SHIFT                        _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_225_MHZ_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_225_MHZ_SHIFT)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_225_MHZ_RANGE                        12:12
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_225_MHZ_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_225_MHZ_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_225_MHZ_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_225_MHZ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_225_MHZ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_225_MHZ_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_225_MHZ_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_225_MHZ_FALSE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_225_MHZ_TRUE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CAP_0_DISPLAY_OVER_PCIE_SHIFT                  _MK_SHIFT_CONST(13)
#define SOR_NV_PDISP_SOR_CAP_0_DISPLAY_OVER_PCIE_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_DISPLAY_OVER_PCIE_SHIFT)
#define SOR_NV_PDISP_SOR_CAP_0_DISPLAY_OVER_PCIE_RANGE                  13:13
#define SOR_NV_PDISP_SOR_CAP_0_DISPLAY_OVER_PCIE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_CAP_0_DISPLAY_OVER_PCIE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DISPLAY_OVER_PCIE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DISPLAY_OVER_PCIE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DISPLAY_OVER_PCIE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DISPLAY_OVER_PCIE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DISPLAY_OVER_PCIE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CAP_0_DISPLAY_OVER_PCIE_FALSE                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CAP_0_DISPLAY_OVER_PCIE_TRUE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CAP_0_SDI_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_CAP_0_SDI_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_SDI_SHIFT)
#define SOR_NV_PDISP_SOR_CAP_0_SDI_RANGE                        16:16
#define SOR_NV_PDISP_SOR_CAP_0_SDI_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_CAP_0_SDI_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SDI_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SDI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SDI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SDI_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_SDI_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CAP_0_SDI_FALSE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CAP_0_SDI_TRUE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CAP_0_DDI_SHIFT                        _MK_SHIFT_CONST(20)
#define SOR_NV_PDISP_SOR_CAP_0_DDI_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_DDI_SHIFT)
#define SOR_NV_PDISP_SOR_CAP_0_DDI_RANGE                        20:20
#define SOR_NV_PDISP_SOR_CAP_0_DDI_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_CAP_0_DDI_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DDI_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DDI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DDI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DDI_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DDI_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CAP_0_DDI_FALSE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CAP_0_DDI_TRUE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CAP_0_DP_A_SHIFT                       _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_CAP_0_DP_A_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_DP_A_SHIFT)
#define SOR_NV_PDISP_SOR_CAP_0_DP_A_RANGE                       24:24
#define SOR_NV_PDISP_SOR_CAP_0_DP_A_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_CAP_0_DP_A_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DP_A_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DP_A_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DP_A_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DP_A_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DP_A_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CAP_0_DP_A_FALSE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CAP_0_DP_A_TRUE                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CAP_0_DP_B_SHIFT                       _MK_SHIFT_CONST(25)
#define SOR_NV_PDISP_SOR_CAP_0_DP_B_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_DP_B_SHIFT)
#define SOR_NV_PDISP_SOR_CAP_0_DP_B_RANGE                       25:25
#define SOR_NV_PDISP_SOR_CAP_0_DP_B_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_CAP_0_DP_B_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DP_B_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DP_B_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DP_B_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DP_B_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_DP_B_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CAP_0_DP_B_FALSE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CAP_0_DP_B_TRUE                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CAP_0_LVDS_ONLY_SHIFT                  _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_CAP_0_LVDS_ONLY_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_LVDS_ONLY_SHIFT)
#define SOR_NV_PDISP_SOR_CAP_0_LVDS_ONLY_RANGE                  31:31
#define SOR_NV_PDISP_SOR_CAP_0_LVDS_ONLY_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_CAP_0_LVDS_ONLY_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_LVDS_ONLY_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_LVDS_ONLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_LVDS_ONLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_LVDS_ONLY_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CAP_0_LVDS_ONLY_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CAP_0_LVDS_ONLY_FALSE                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CAP_0_LVDS_ONLY_TRUE                   _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_PWR_0
#define SOR_NV_PDISP_SOR_PWR_0                  _MK_ADDR_CONST(0x15)
#define SOR_NV_PDISP_SOR_PWR_0_SECURE                   0x0
#define SOR_NV_PDISP_SOR_PWR_0_DUAL                     0x0
#define SOR_NV_PDISP_SOR_PWR_0_SCR                      0
#define SOR_NV_PDISP_SOR_PWR_0_WORD_COUNT                       0x1
#define SOR_NV_PDISP_SOR_PWR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_RESET_MASK                       _MK_MASK_CONST(0x80030003)
#define SOR_NV_PDISP_SOR_PWR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_READ_MASK                        _MK_MASK_CONST(0x91030003)
#define SOR_NV_PDISP_SOR_PWR_0_WRITE_MASK                       _MK_MASK_CONST(0x80030003)
#define SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_SHIFT                        _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_SHIFT)
#define SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_RANGE                        31:31
#define SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_INIT_ENUM                    DONE
#define SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_DONE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_PENDING                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_TRIGGER                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PWR_0_MODE_SHIFT                       _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_PWR_0_MODE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PWR_0_MODE_SHIFT)
#define SOR_NV_PDISP_SOR_PWR_0_MODE_RANGE                       28:28
#define SOR_NV_PDISP_SOR_PWR_0_MODE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_PWR_0_MODE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_MODE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_MODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_MODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_MODE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_MODE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PWR_0_MODE_NORMAL                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PWR_0_MODE_SAFE                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PWR_0_HALT_DELAY_SHIFT                 _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_PWR_0_HALT_DELAY_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PWR_0_HALT_DELAY_SHIFT)
#define SOR_NV_PDISP_SOR_PWR_0_HALT_DELAY_RANGE                 24:24
#define SOR_NV_PDISP_SOR_PWR_0_HALT_DELAY_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_PWR_0_HALT_DELAY_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_HALT_DELAY_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_HALT_DELAY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_HALT_DELAY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_HALT_DELAY_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_HALT_DELAY_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PWR_0_HALT_DELAY_DONE                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PWR_0_HALT_DELAY_ACTIVE                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PWR_0_SAFE_START_SHIFT                 _MK_SHIFT_CONST(17)
#define SOR_NV_PDISP_SOR_PWR_0_SAFE_START_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PWR_0_SAFE_START_SHIFT)
#define SOR_NV_PDISP_SOR_PWR_0_SAFE_START_RANGE                 17:17
#define SOR_NV_PDISP_SOR_PWR_0_SAFE_START_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_PWR_0_SAFE_START_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_SAFE_START_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PWR_0_SAFE_START_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_SAFE_START_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_SAFE_START_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PWR_0_SAFE_START_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PWR_0_SAFE_START_INIT_ENUM                     NORMAL
#define SOR_NV_PDISP_SOR_PWR_0_SAFE_START_NORMAL                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PWR_0_SAFE_START_ALT                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PWR_0_SAFE_STATE_SHIFT                 _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_PWR_0_SAFE_STATE_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PWR_0_SAFE_STATE_SHIFT)
#define SOR_NV_PDISP_SOR_PWR_0_SAFE_STATE_RANGE                 16:16
#define SOR_NV_PDISP_SOR_PWR_0_SAFE_STATE_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_PWR_0_SAFE_STATE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_SAFE_STATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PWR_0_SAFE_STATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_SAFE_STATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_SAFE_STATE_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PWR_0_SAFE_STATE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PWR_0_SAFE_STATE_INIT_ENUM                     PD
#define SOR_NV_PDISP_SOR_PWR_0_SAFE_STATE_PD                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PWR_0_SAFE_STATE_PU                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_START_SHIFT                       _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_START_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PWR_0_NORMAL_START_SHIFT)
#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_START_RANGE                       1:1
#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_START_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_START_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_START_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_START_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_START_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_START_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_START_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_START_INIT_ENUM                   NORMAL
#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_START_NORMAL                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_START_ALT                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_STATE_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_STATE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PWR_0_NORMAL_STATE_SHIFT)
#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_STATE_RANGE                       0:0
#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_STATE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_STATE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_STATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_STATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_STATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_STATE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_STATE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_STATE_INIT_ENUM                   PD
#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_STATE_PD                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_STATE_PU                  _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_TEST_0
#define SOR_NV_PDISP_SOR_TEST_0                 _MK_ADDR_CONST(0x16)
#define SOR_NV_PDISP_SOR_TEST_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_TEST_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_TEST_0_SCR                     0
#define SOR_NV_PDISP_SOR_TEST_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_TEST_0_RESET_VAL                       _MK_MASK_CONST(0x800000)
#define SOR_NV_PDISP_SOR_TEST_0_RESET_MASK                      _MK_MASK_CONST(0xfff300c0)
#define SOR_NV_PDISP_SOR_TEST_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_READ_MASK                       _MK_MASK_CONST(0xfff3f7c0)
#define SOR_NV_PDISP_SOR_TEST_0_WRITE_MASK                      _MK_MASK_CONST(0xfff300c0)
#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_SHIFT                   _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_TEST_0_TESTMUX_SHIFT)
#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_RANGE                   31:24
#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_INIT_ENUM                       AVSS
#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_AVSS                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_PLL_LOCK                        _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_PLL_VCOLIMIT                    _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_INTR_LOCK                       _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_PLL_VOL                 _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_SLOWCLKINT                      _MK_ENUM_CONST(8)
#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_AVDD                    _MK_ENUM_CONST(16)
#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_VDDREG14                        _MK_ENUM_CONST(32)
#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_AVDD14                  _MK_ENUM_CONST(64)
#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_REGREF_AVDD                     _MK_ENUM_CONST(128)

#define SOR_NV_PDISP_SOR_TEST_0_CRC_SHIFT                       _MK_SHIFT_CONST(23)
#define SOR_NV_PDISP_SOR_TEST_0_CRC_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TEST_0_CRC_SHIFT)
#define SOR_NV_PDISP_SOR_TEST_0_CRC_RANGE                       23:23
#define SOR_NV_PDISP_SOR_TEST_0_CRC_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_TEST_0_CRC_DEFAULT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TEST_0_CRC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TEST_0_CRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_CRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_CRC_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TEST_0_CRC_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TEST_0_CRC_INIT_ENUM                   POST_DESERIALIZE
#define SOR_NV_PDISP_SOR_TEST_0_CRC_PRE_SERIALIZE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TEST_0_CRC_POST_DESERIALIZE                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_TEST_0_TPAT_SHIFT                      _MK_SHIFT_CONST(20)
#define SOR_NV_PDISP_SOR_TEST_0_TPAT_FIELD                      _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_TEST_0_TPAT_SHIFT)
#define SOR_NV_PDISP_SOR_TEST_0_TPAT_RANGE                      22:20
#define SOR_NV_PDISP_SOR_TEST_0_TPAT_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_TEST_0_TPAT_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_TPAT_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define SOR_NV_PDISP_SOR_TEST_0_TPAT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_TPAT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_TPAT_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TEST_0_TPAT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TEST_0_TPAT_INIT_ENUM                  LO
#define SOR_NV_PDISP_SOR_TEST_0_TPAT_LO                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TEST_0_TPAT_TDAT                       _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_TEST_0_TPAT_RAMP                       _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_TEST_0_TPAT_WALK                       _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_TEST_0_TPAT_MAXSTEP                    _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_TEST_0_TPAT_MINSTEP                    _MK_ENUM_CONST(5)

#define SOR_NV_PDISP_SOR_TEST_0_DSRC_SHIFT                      _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_TEST_0_DSRC_FIELD                      _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_TEST_0_DSRC_SHIFT)
#define SOR_NV_PDISP_SOR_TEST_0_DSRC_RANGE                      17:16
#define SOR_NV_PDISP_SOR_TEST_0_DSRC_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_TEST_0_DSRC_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_DSRC_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_TEST_0_DSRC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_DSRC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_DSRC_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TEST_0_DSRC_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TEST_0_DSRC_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_TEST_0_DSRC_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TEST_0_DSRC_DEBUG                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_TEST_0_DSRC_TGEN                       _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_SHIFT                       _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_FIELD                       _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_SHIFT)
#define SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_RANGE                       15:12
#define SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_NONE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_HEAD0                       _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_HEAD1                       _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_HEAD2                       _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_HEAD3                       _MK_ENUM_CONST(4)

#define SOR_NV_PDISP_SOR_TEST_0_ATTACHED_SHIFT                  _MK_SHIFT_CONST(10)
#define SOR_NV_PDISP_SOR_TEST_0_ATTACHED_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TEST_0_ATTACHED_SHIFT)
#define SOR_NV_PDISP_SOR_TEST_0_ATTACHED_RANGE                  10:10
#define SOR_NV_PDISP_SOR_TEST_0_ATTACHED_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_TEST_0_ATTACHED_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_ATTACHED_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_ATTACHED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_ATTACHED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_ATTACHED_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_ATTACHED_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TEST_0_ATTACHED_FALSE                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TEST_0_ATTACHED_TRUE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_TEST_0_ACT_HEAD_OPMODE_SHIFT                   _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_TEST_0_ACT_HEAD_OPMODE_FIELD                   _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_TEST_0_ACT_HEAD_OPMODE_SHIFT)
#define SOR_NV_PDISP_SOR_TEST_0_ACT_HEAD_OPMODE_RANGE                   9:8
#define SOR_NV_PDISP_SOR_TEST_0_ACT_HEAD_OPMODE_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_TEST_0_ACT_HEAD_OPMODE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_ACT_HEAD_OPMODE_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_ACT_HEAD_OPMODE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_ACT_HEAD_OPMODE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_ACT_HEAD_OPMODE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_ACT_HEAD_OPMODE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TEST_0_ACT_HEAD_OPMODE_SLEEP                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TEST_0_ACT_HEAD_OPMODE_SNOOZE                  _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_TEST_0_ACT_HEAD_OPMODE_AWAKE                   _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_TEST_0_DEEP_LOOPBACK_SHIFT                     _MK_SHIFT_CONST(7)
#define SOR_NV_PDISP_SOR_TEST_0_DEEP_LOOPBACK_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TEST_0_DEEP_LOOPBACK_SHIFT)
#define SOR_NV_PDISP_SOR_TEST_0_DEEP_LOOPBACK_RANGE                     7:7
#define SOR_NV_PDISP_SOR_TEST_0_DEEP_LOOPBACK_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_TEST_0_DEEP_LOOPBACK_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_DEEP_LOOPBACK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TEST_0_DEEP_LOOPBACK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_DEEP_LOOPBACK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_DEEP_LOOPBACK_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TEST_0_DEEP_LOOPBACK_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TEST_0_DEEP_LOOPBACK_INIT_ENUM                 DISABLE
#define SOR_NV_PDISP_SOR_TEST_0_DEEP_LOOPBACK_DISABLE                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TEST_0_DEEP_LOOPBACK_ENABLE                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_TEST_0_INVD_SHIFT                      _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_SOR_TEST_0_INVD_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TEST_0_INVD_SHIFT)
#define SOR_NV_PDISP_SOR_TEST_0_INVD_RANGE                      6:6
#define SOR_NV_PDISP_SOR_TEST_0_INVD_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_TEST_0_INVD_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_INVD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TEST_0_INVD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_INVD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TEST_0_INVD_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TEST_0_INVD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TEST_0_INVD_INIT_ENUM                  DISABLE
#define SOR_NV_PDISP_SOR_TEST_0_INVD_DISABLE                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TEST_0_INVD_ENABLE                     _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_CSTM_0
#define SOR_NV_PDISP_SOR_CSTM_0                 _MK_ADDR_CONST(0x1b)
#define SOR_NV_PDISP_SOR_CSTM_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_CSTM_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_CSTM_0_SCR                     0
#define SOR_NV_PDISP_SOR_CSTM_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_CSTM_0_RESET_VAL                       _MK_MASK_CONST(0x1c800)
#define SOR_NV_PDISP_SOR_CSTM_0_RESET_MASK                      _MK_MASK_CONST(0x7f2ffbff)
#define SOR_NV_PDISP_SOR_CSTM_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_READ_MASK                       _MK_MASK_CONST(0x7f2ffbff)
#define SOR_NV_PDISP_SOR_CSTM_0_WRITE_MASK                      _MK_MASK_CONST(0x7f2ffbff)
#define SOR_NV_PDISP_SOR_CSTM_0_ROTDAT_SHIFT                    _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_CSTM_0_ROTDAT_FIELD                    _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_CSTM_0_ROTDAT_SHIFT)
#define SOR_NV_PDISP_SOR_CSTM_0_ROTDAT_RANGE                    30:28
#define SOR_NV_PDISP_SOR_CSTM_0_ROTDAT_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_CSTM_0_ROTDAT_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_ROTDAT_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define SOR_NV_PDISP_SOR_CSTM_0_ROTDAT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_ROTDAT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_ROTDAT_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_ROTDAT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_ROTDAT_INIT_ENUM                        RST
#define SOR_NV_PDISP_SOR_CSTM_0_ROTDAT_RST                      _MK_ENUM_CONST(0)

#define SOR_NV_PDISP_SOR_CSTM_0_ROTCLK_SHIFT                    _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_CSTM_0_ROTCLK_FIELD                    _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_CSTM_0_ROTCLK_SHIFT)
#define SOR_NV_PDISP_SOR_CSTM_0_ROTCLK_RANGE                    27:24
#define SOR_NV_PDISP_SOR_CSTM_0_ROTCLK_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_CSTM_0_ROTCLK_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_ROTCLK_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_CSTM_0_ROTCLK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_ROTCLK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_ROTCLK_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_ROTCLK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_ROTCLK_INIT_ENUM                        RST
#define SOR_NV_PDISP_SOR_CSTM_0_ROTCLK_RST                      _MK_ENUM_CONST(0)

#define SOR_NV_PDISP_SOR_CSTM_0_PLLDIV_SHIFT                    _MK_SHIFT_CONST(21)
#define SOR_NV_PDISP_SOR_CSTM_0_PLLDIV_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_PLLDIV_SHIFT)
#define SOR_NV_PDISP_SOR_CSTM_0_PLLDIV_RANGE                    21:21
#define SOR_NV_PDISP_SOR_CSTM_0_PLLDIV_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_CSTM_0_PLLDIV_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PLLDIV_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PLLDIV_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PLLDIV_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PLLDIV_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PLLDIV_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PLLDIV_INIT_ENUM                        BY_7
#define SOR_NV_PDISP_SOR_CSTM_0_PLLDIV_BY_7                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CSTM_0_PLLDIV_BY_10                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CSTM_0_BALANCED_SHIFT                  _MK_SHIFT_CONST(19)
#define SOR_NV_PDISP_SOR_CSTM_0_BALANCED_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_BALANCED_SHIFT)
#define SOR_NV_PDISP_SOR_CSTM_0_BALANCED_RANGE                  19:19
#define SOR_NV_PDISP_SOR_CSTM_0_BALANCED_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_CSTM_0_BALANCED_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_BALANCED_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_BALANCED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_BALANCED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_BALANCED_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_BALANCED_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_BALANCED_INIT_ENUM                      DISABLE
#define SOR_NV_PDISP_SOR_CSTM_0_BALANCED_DISABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CSTM_0_BALANCED_ENABLE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CSTM_0_NEW_MODE_SHIFT                  _MK_SHIFT_CONST(18)
#define SOR_NV_PDISP_SOR_CSTM_0_NEW_MODE_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_NEW_MODE_SHIFT)
#define SOR_NV_PDISP_SOR_CSTM_0_NEW_MODE_RANGE                  18:18
#define SOR_NV_PDISP_SOR_CSTM_0_NEW_MODE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_CSTM_0_NEW_MODE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_NEW_MODE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_NEW_MODE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_NEW_MODE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_NEW_MODE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_NEW_MODE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_NEW_MODE_INIT_ENUM                      DISABLE
#define SOR_NV_PDISP_SOR_CSTM_0_NEW_MODE_DISABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CSTM_0_NEW_MODE_ENABLE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CSTM_0_DUP_SYNC_SHIFT                  _MK_SHIFT_CONST(17)
#define SOR_NV_PDISP_SOR_CSTM_0_DUP_SYNC_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_DUP_SYNC_SHIFT)
#define SOR_NV_PDISP_SOR_CSTM_0_DUP_SYNC_RANGE                  17:17
#define SOR_NV_PDISP_SOR_CSTM_0_DUP_SYNC_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_CSTM_0_DUP_SYNC_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_DUP_SYNC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_DUP_SYNC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_DUP_SYNC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_DUP_SYNC_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_DUP_SYNC_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_DUP_SYNC_INIT_ENUM                      DISABLE
#define SOR_NV_PDISP_SOR_CSTM_0_DUP_SYNC_DISABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CSTM_0_DUP_SYNC_ENABLE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CSTM_0_LVDS_EN_SHIFT                   _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_CSTM_0_LVDS_EN_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_LVDS_EN_SHIFT)
#define SOR_NV_PDISP_SOR_CSTM_0_LVDS_EN_RANGE                   16:16
#define SOR_NV_PDISP_SOR_CSTM_0_LVDS_EN_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_CSTM_0_LVDS_EN_DEFAULT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_LVDS_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_LVDS_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_LVDS_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_LVDS_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_LVDS_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_LVDS_EN_INIT_ENUM                       ENABLE
#define SOR_NV_PDISP_SOR_CSTM_0_LVDS_EN_DISABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CSTM_0_LVDS_EN_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTB_SHIFT                  _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTB_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_LINKACTB_SHIFT)
#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTB_RANGE                  15:15
#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTB_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTB_DEFAULT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTB_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTB_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTB_INIT_ENUM                      ENABLE
#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTB_DISABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTB_ENABLE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTA_SHIFT                  _MK_SHIFT_CONST(14)
#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTA_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_LINKACTA_SHIFT)
#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTA_RANGE                  14:14
#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTA_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTA_DEFAULT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTA_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTA_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTA_INIT_ENUM                      ENABLE
#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTA_DISABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTA_ENABLE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CSTM_0_MODE_SHIFT                      _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_CSTM_0_MODE_FIELD                      _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_CSTM_0_MODE_SHIFT)
#define SOR_NV_PDISP_SOR_CSTM_0_MODE_RANGE                      13:12
#define SOR_NV_PDISP_SOR_CSTM_0_MODE_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_CSTM_0_MODE_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_MODE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_CSTM_0_MODE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_MODE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_MODE_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_MODE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_MODE_INIT_ENUM                  LVDS
#define SOR_NV_PDISP_SOR_CSTM_0_MODE_LVDS                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CSTM_0_MODE_DP                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CSTM_0_UPPER_SHIFT                     _MK_SHIFT_CONST(11)
#define SOR_NV_PDISP_SOR_CSTM_0_UPPER_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_UPPER_SHIFT)
#define SOR_NV_PDISP_SOR_CSTM_0_UPPER_RANGE                     11:11
#define SOR_NV_PDISP_SOR_CSTM_0_UPPER_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_CSTM_0_UPPER_DEFAULT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_UPPER_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_UPPER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_UPPER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_UPPER_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_UPPER_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_UPPER_INIT_ENUM                 TRUE
#define SOR_NV_PDISP_SOR_CSTM_0_UPPER_FALSE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CSTM_0_UPPER_TRUE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCB_SHIFT                   _MK_SHIFT_CONST(9)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCB_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_PD_TXCB_SHIFT)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCB_RANGE                   9:9
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCB_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCB_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCB_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCB_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCB_INIT_ENUM                       ENABLE
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCB_ENABLE                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCB_DISABLE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCA_SHIFT                   _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCA_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_PD_TXCA_SHIFT)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCA_RANGE                   8:8
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCA_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCA_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCA_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCA_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCA_INIT_ENUM                       ENABLE
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCA_ENABLE                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCA_DISABLE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_3_SHIFT                 _MK_SHIFT_CONST(7)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_3_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_3_SHIFT)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_3_RANGE                 7:7
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_3_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_3_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_3_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_3_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_3_INIT_ENUM                     ENABLE
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_3_ENABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_3_DISABLE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_2_SHIFT                 _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_2_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_2_SHIFT)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_2_RANGE                 6:6
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_2_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_2_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_2_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_2_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_2_INIT_ENUM                     ENABLE
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_2_ENABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_2_DISABLE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_1_SHIFT                 _MK_SHIFT_CONST(5)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_1_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_1_SHIFT)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_1_RANGE                 5:5
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_1_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_1_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_1_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_1_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_1_INIT_ENUM                     ENABLE
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_1_ENABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_1_DISABLE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_0_SHIFT                 _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_0_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_0_SHIFT)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_0_RANGE                 4:4
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_0_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_0_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_0_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_0_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_0_INIT_ENUM                     ENABLE
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_0_ENABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_0_DISABLE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_3_SHIFT                 _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_3_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_3_SHIFT)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_3_RANGE                 3:3
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_3_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_3_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_3_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_3_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_3_INIT_ENUM                     ENABLE
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_3_ENABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_3_DISABLE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_2_SHIFT                 _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_2_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_2_SHIFT)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_2_RANGE                 2:2
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_2_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_2_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_2_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_2_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_2_INIT_ENUM                     ENABLE
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_2_ENABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_2_DISABLE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_1_SHIFT                 _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_1_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_1_SHIFT)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_1_RANGE                 1:1
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_1_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_1_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_1_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_1_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_1_INIT_ENUM                     ENABLE
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_1_ENABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_1_DISABLE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_0_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_0_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_0_SHIFT)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_0_RANGE                 0:0
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_0_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_0_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_0_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_0_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_0_INIT_ENUM                     ENABLE
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_0_ENABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_0_DISABLE                       _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_LVDS_0
#define SOR_NV_PDISP_SOR_LVDS_0                 _MK_ADDR_CONST(0x1c)
#define SOR_NV_PDISP_SOR_LVDS_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_LVDS_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_LVDS_0_SCR                     0
#define SOR_NV_PDISP_SOR_LVDS_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_LVDS_0_RESET_VAL                       _MK_MASK_CONST(0x1c800)
#define SOR_NV_PDISP_SOR_LVDS_0_RESET_MASK                      _MK_MASK_CONST(0x7f2ffbff)
#define SOR_NV_PDISP_SOR_LVDS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_READ_MASK                       _MK_MASK_CONST(0x7f2ffbff)
#define SOR_NV_PDISP_SOR_LVDS_0_WRITE_MASK                      _MK_MASK_CONST(0x7f0e82f8)
#define SOR_NV_PDISP_SOR_LVDS_0_ROTDAT_SHIFT                    _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_LVDS_0_ROTDAT_FIELD                    _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_LVDS_0_ROTDAT_SHIFT)
#define SOR_NV_PDISP_SOR_LVDS_0_ROTDAT_RANGE                    30:28
#define SOR_NV_PDISP_SOR_LVDS_0_ROTDAT_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_LVDS_0_ROTDAT_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_ROTDAT_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define SOR_NV_PDISP_SOR_LVDS_0_ROTDAT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_ROTDAT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_ROTDAT_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_ROTDAT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_ROTDAT_INIT_ENUM                        RST
#define SOR_NV_PDISP_SOR_LVDS_0_ROTDAT_RST                      _MK_ENUM_CONST(0)

#define SOR_NV_PDISP_SOR_LVDS_0_ROTCLK_SHIFT                    _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_LVDS_0_ROTCLK_FIELD                    _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_LVDS_0_ROTCLK_SHIFT)
#define SOR_NV_PDISP_SOR_LVDS_0_ROTCLK_RANGE                    27:24
#define SOR_NV_PDISP_SOR_LVDS_0_ROTCLK_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_LVDS_0_ROTCLK_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_ROTCLK_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_LVDS_0_ROTCLK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_ROTCLK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_ROTCLK_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_ROTCLK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_ROTCLK_INIT_ENUM                        RST
#define SOR_NV_PDISP_SOR_LVDS_0_ROTCLK_RST                      _MK_ENUM_CONST(0)

#define SOR_NV_PDISP_SOR_LVDS_0_PLLDIV_SHIFT                    _MK_SHIFT_CONST(21)
#define SOR_NV_PDISP_SOR_LVDS_0_PLLDIV_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_PLLDIV_SHIFT)
#define SOR_NV_PDISP_SOR_LVDS_0_PLLDIV_RANGE                    21:21
#define SOR_NV_PDISP_SOR_LVDS_0_PLLDIV_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_LVDS_0_PLLDIV_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PLLDIV_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PLLDIV_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PLLDIV_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PLLDIV_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PLLDIV_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PLLDIV_INIT_ENUM                        BY_7
#define SOR_NV_PDISP_SOR_LVDS_0_PLLDIV_BY_7                     _MK_ENUM_CONST(0)

#define SOR_NV_PDISP_SOR_LVDS_0_BALANCED_SHIFT                  _MK_SHIFT_CONST(19)
#define SOR_NV_PDISP_SOR_LVDS_0_BALANCED_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_BALANCED_SHIFT)
#define SOR_NV_PDISP_SOR_LVDS_0_BALANCED_RANGE                  19:19
#define SOR_NV_PDISP_SOR_LVDS_0_BALANCED_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_LVDS_0_BALANCED_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_BALANCED_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_BALANCED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_BALANCED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_BALANCED_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_BALANCED_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_BALANCED_INIT_ENUM                      DISABLE
#define SOR_NV_PDISP_SOR_LVDS_0_BALANCED_DISABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LVDS_0_BALANCED_ENABLE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_LVDS_0_NEW_MODE_SHIFT                  _MK_SHIFT_CONST(18)
#define SOR_NV_PDISP_SOR_LVDS_0_NEW_MODE_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_NEW_MODE_SHIFT)
#define SOR_NV_PDISP_SOR_LVDS_0_NEW_MODE_RANGE                  18:18
#define SOR_NV_PDISP_SOR_LVDS_0_NEW_MODE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_LVDS_0_NEW_MODE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_NEW_MODE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_NEW_MODE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_NEW_MODE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_NEW_MODE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_NEW_MODE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_NEW_MODE_INIT_ENUM                      DISABLE
#define SOR_NV_PDISP_SOR_LVDS_0_NEW_MODE_DISABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LVDS_0_NEW_MODE_ENABLE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_LVDS_0_DUP_SYNC_SHIFT                  _MK_SHIFT_CONST(17)
#define SOR_NV_PDISP_SOR_LVDS_0_DUP_SYNC_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_DUP_SYNC_SHIFT)
#define SOR_NV_PDISP_SOR_LVDS_0_DUP_SYNC_RANGE                  17:17
#define SOR_NV_PDISP_SOR_LVDS_0_DUP_SYNC_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_LVDS_0_DUP_SYNC_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_DUP_SYNC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_DUP_SYNC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_DUP_SYNC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_DUP_SYNC_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_DUP_SYNC_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_DUP_SYNC_INIT_ENUM                      DISABLE
#define SOR_NV_PDISP_SOR_LVDS_0_DUP_SYNC_DISABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LVDS_0_DUP_SYNC_ENABLE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_LVDS_0_LVDS_EN_SHIFT                   _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_LVDS_0_LVDS_EN_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_LVDS_EN_SHIFT)
#define SOR_NV_PDISP_SOR_LVDS_0_LVDS_EN_RANGE                   16:16
#define SOR_NV_PDISP_SOR_LVDS_0_LVDS_EN_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_LVDS_0_LVDS_EN_DEFAULT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_LVDS_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_LVDS_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_LVDS_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_LVDS_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_LVDS_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_LVDS_EN_INIT_ENUM                       ENABLE
#define SOR_NV_PDISP_SOR_LVDS_0_LVDS_EN_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTB_SHIFT                  _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTB_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_LINKACTB_SHIFT)
#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTB_RANGE                  15:15
#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTB_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTB_DEFAULT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTB_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTB_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTB_INIT_ENUM                      ENABLE
#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTB_DISABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTB_ENABLE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTA_SHIFT                  _MK_SHIFT_CONST(14)
#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTA_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_LINKACTA_SHIFT)
#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTA_RANGE                  14:14
#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTA_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTA_DEFAULT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTA_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTA_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTA_INIT_ENUM                      ENABLE
#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTA_ENABLE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_LVDS_0_MODE_SHIFT                      _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_LVDS_0_MODE_FIELD                      _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_LVDS_0_MODE_SHIFT)
#define SOR_NV_PDISP_SOR_LVDS_0_MODE_RANGE                      13:12
#define SOR_NV_PDISP_SOR_LVDS_0_MODE_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_LVDS_0_MODE_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_MODE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_LVDS_0_MODE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_MODE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_MODE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_MODE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_MODE_INIT_ENUM                  LVDS
#define SOR_NV_PDISP_SOR_LVDS_0_MODE_LVDS                       _MK_ENUM_CONST(0)

#define SOR_NV_PDISP_SOR_LVDS_0_UPPER_SHIFT                     _MK_SHIFT_CONST(11)
#define SOR_NV_PDISP_SOR_LVDS_0_UPPER_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_UPPER_SHIFT)
#define SOR_NV_PDISP_SOR_LVDS_0_UPPER_RANGE                     11:11
#define SOR_NV_PDISP_SOR_LVDS_0_UPPER_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_LVDS_0_UPPER_DEFAULT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_UPPER_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_UPPER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_UPPER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_UPPER_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_UPPER_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_UPPER_INIT_ENUM                 TRUE
#define SOR_NV_PDISP_SOR_LVDS_0_UPPER_FALSE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LVDS_0_UPPER_TRUE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCB_SHIFT                   _MK_SHIFT_CONST(9)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCB_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_PD_TXCB_SHIFT)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCB_RANGE                   9:9
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCB_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCB_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCB_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCB_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCB_INIT_ENUM                       ENABLE
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCB_ENABLE                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCB_DISABLE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCA_SHIFT                   _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCA_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_PD_TXCA_SHIFT)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCA_RANGE                   8:8
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCA_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCA_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCA_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCA_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCA_INIT_ENUM                       ENABLE
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCA_ENABLE                  _MK_ENUM_CONST(0)

#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_3_SHIFT                 _MK_SHIFT_CONST(7)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_3_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_3_SHIFT)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_3_RANGE                 7:7
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_3_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_3_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_3_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_3_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_3_INIT_ENUM                     ENABLE
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_3_ENABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_3_DISABLE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_2_SHIFT                 _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_2_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_2_SHIFT)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_2_RANGE                 6:6
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_2_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_2_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_2_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_2_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_2_INIT_ENUM                     ENABLE
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_2_ENABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_2_DISABLE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_1_SHIFT                 _MK_SHIFT_CONST(5)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_1_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_1_SHIFT)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_1_RANGE                 5:5
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_1_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_1_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_1_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_1_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_1_INIT_ENUM                     ENABLE
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_1_ENABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_1_DISABLE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_0_SHIFT                 _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_0_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_0_SHIFT)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_0_RANGE                 4:4
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_0_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_0_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_0_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_0_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_0_INIT_ENUM                     ENABLE
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_0_ENABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_0_DISABLE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_3_SHIFT                 _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_3_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_3_SHIFT)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_3_RANGE                 3:3
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_3_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_3_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_3_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_3_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_3_INIT_ENUM                     ENABLE
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_3_ENABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_3_DISABLE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_2_SHIFT                 _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_2_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_2_SHIFT)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_2_RANGE                 2:2
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_2_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_2_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_2_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_2_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_2_INIT_ENUM                     ENABLE
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_2_ENABLE                        _MK_ENUM_CONST(0)

#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_1_SHIFT                 _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_1_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_1_SHIFT)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_1_RANGE                 1:1
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_1_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_1_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_1_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_1_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_1_INIT_ENUM                     ENABLE
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_1_ENABLE                        _MK_ENUM_CONST(0)

#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_0_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_0_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_0_SHIFT)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_0_RANGE                 0:0
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_0_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_0_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_0_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_0_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_0_INIT_ENUM                     ENABLE
#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_0_ENABLE                        _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_CRCA_0
#define SOR_NV_PDISP_SOR_CRCA_0                 _MK_ADDR_CONST(0x1d)
#define SOR_NV_PDISP_SOR_CRCA_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_CRCA_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_CRCA_0_SCR                     0
#define SOR_NV_PDISP_SOR_CRCA_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_CRCA_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CRCA_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CRCA_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CRCA_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CRCA_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CRCA_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CRCA_0_VALID_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_CRCA_0_VALID_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CRCA_0_VALID_SHIFT)
#define SOR_NV_PDISP_SOR_CRCA_0_VALID_RANGE                     0:0
#define SOR_NV_PDISP_SOR_CRCA_0_VALID_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_CRCA_0_VALID_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CRCA_0_VALID_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CRCA_0_VALID_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CRCA_0_VALID_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CRCA_0_VALID_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CRCA_0_VALID_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_CRCA_0_VALID_INIT_ENUM                 FALSE
#define SOR_NV_PDISP_SOR_CRCA_0_VALID_FALSE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_CRCA_0_VALID_TRUE                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_CRCA_0_VALID_RST                       _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_CRCB_0
#define SOR_NV_PDISP_SOR_CRCB_0                 _MK_ADDR_CONST(0x1e)
#define SOR_NV_PDISP_SOR_CRCB_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_CRCB_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_CRCB_0_SCR                     0
#define SOR_NV_PDISP_SOR_CRCB_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_CRCB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CRCB_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_CRCB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CRCB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CRCB_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_CRCB_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CRCB_0_CRC_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_CRCB_0_CRC_FIELD                       _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_CRCB_0_CRC_SHIFT)
#define SOR_NV_PDISP_SOR_CRCB_0_CRC_RANGE                       31:0
#define SOR_NV_PDISP_SOR_CRCB_0_CRC_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_CRCB_0_CRC_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CRCB_0_CRC_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_CRCB_0_CRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CRCB_0_CRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CRCB_0_CRC_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CRCB_0_CRC_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_BLANK_0
#define SOR_NV_PDISP_SOR_BLANK_0                        _MK_ADDR_CONST(0x1f)
#define SOR_NV_PDISP_SOR_BLANK_0_SECURE                         0x0
#define SOR_NV_PDISP_SOR_BLANK_0_DUAL                   0x0
#define SOR_NV_PDISP_SOR_BLANK_0_SCR                    0
#define SOR_NV_PDISP_SOR_BLANK_0_WORD_COUNT                     0x1
#define SOR_NV_PDISP_SOR_BLANK_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_BLANK_0_RESET_MASK                     _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_BLANK_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_BLANK_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_BLANK_0_READ_MASK                      _MK_MASK_CONST(0x7)
#define SOR_NV_PDISP_SOR_BLANK_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_BLANK_0_STATUS_SHIFT                   _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_BLANK_0_STATUS_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_BLANK_0_STATUS_SHIFT)
#define SOR_NV_PDISP_SOR_BLANK_0_STATUS_RANGE                   2:2
#define SOR_NV_PDISP_SOR_BLANK_0_STATUS_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_BLANK_0_STATUS_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_BLANK_0_STATUS_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_BLANK_0_STATUS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_BLANK_0_STATUS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_BLANK_0_STATUS_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_BLANK_0_STATUS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_BLANK_0_STATUS_NOT_BLANKED                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_BLANK_0_STATUS_BLANKED                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_BLANK_0_TRANSITION_SHIFT                       _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_BLANK_0_TRANSITION_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_BLANK_0_TRANSITION_SHIFT)
#define SOR_NV_PDISP_SOR_BLANK_0_TRANSITION_RANGE                       1:1
#define SOR_NV_PDISP_SOR_BLANK_0_TRANSITION_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_BLANK_0_TRANSITION_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_BLANK_0_TRANSITION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_BLANK_0_TRANSITION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_BLANK_0_TRANSITION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_BLANK_0_TRANSITION_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_BLANK_0_TRANSITION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_BLANK_0_TRANSITION_INIT_ENUM                   IMMEDIATE
#define SOR_NV_PDISP_SOR_BLANK_0_TRANSITION_IMMEDIATE                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_BLANK_0_TRANSITION_NEXT_VSYNC                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_BLANK_0_OVERRIDE_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_BLANK_0_OVERRIDE_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_BLANK_0_OVERRIDE_SHIFT)
#define SOR_NV_PDISP_SOR_BLANK_0_OVERRIDE_RANGE                 0:0
#define SOR_NV_PDISP_SOR_BLANK_0_OVERRIDE_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_BLANK_0_OVERRIDE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_BLANK_0_OVERRIDE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_BLANK_0_OVERRIDE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_BLANK_0_OVERRIDE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_BLANK_0_OVERRIDE_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_BLANK_0_OVERRIDE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_BLANK_0_OVERRIDE_INIT_ENUM                     FALSE
#define SOR_NV_PDISP_SOR_BLANK_0_OVERRIDE_FALSE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_BLANK_0_OVERRIDE_TRUE                  _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_SEQ_CTL_0
#define SOR_NV_PDISP_SOR_SEQ_CTL_0                      _MK_ADDR_CONST(0x20)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SCR                  0
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_RESET_VAL                    _MK_MASK_CONST(0x8800)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_RESET_MASK                   _MK_MASK_CONST(0x1000ffff)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_READ_MASK                    _MK_MASK_CONST(0x500fffff)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_WRITE_MASK                   _MK_MASK_CONST(0x4000fff0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SWITCH_SHIFT                 _MK_SHIFT_CONST(30)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SWITCH_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_CTL_0_SWITCH_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SWITCH_RANGE                 30:30
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SWITCH_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SWITCH_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SWITCH_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SWITCH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SWITCH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SWITCH_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SWITCH_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SWITCH_WAIT                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SWITCH_FORCE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_CTL_0_STATUS_SHIFT                 _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_STATUS_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_CTL_0_STATUS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_STATUS_RANGE                 28:28
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_STATUS_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_STATUS_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_STATUS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_STATUS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_STATUS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_STATUS_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_STATUS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_STATUS_INIT_ENUM                     STOPPED
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_STATUS_STOPPED                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_STATUS_RUNNING                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PC_SHIFT                     _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PC_FIELD                     _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_SEQ_CTL_0_PC_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PC_RANGE                     19:16
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PC_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PC_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PC_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PC_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PC_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_ALT_SHIFT                      _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_ALT_FIELD                      _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_ALT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_ALT_RANGE                      15:12
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_ALT_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_ALT_DEFAULT                    _MK_MASK_CONST(0x8)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_ALT_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_ALT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_ALT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_ALT_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_ALT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_SHIFT                  _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_FIELD                  _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_RANGE                  11:8
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_DEFAULT                        _MK_MASK_CONST(0x8)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_ALT_SHIFT                      _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_ALT_FIELD                      _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_ALT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_ALT_RANGE                      7:4
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_ALT_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_ALT_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_ALT_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_ALT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_ALT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_ALT_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_ALT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_FIELD                  _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_RANGE                  3:0
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0                 _MK_ADDR_CONST(0x21)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SCR                     0
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_RESET_VAL                       _MK_MASK_CONST(0x11000)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_RESET_MASK                      _MK_MASK_CONST(0x8011f000)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_READ_MASK                       _MK_MASK_CONST(0x9011f3ff)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_WRITE_MASK                      _MK_MASK_CONST(0x8011f000)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_SHIFT                       _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_RANGE                       31:31
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_INIT_ENUM                   DONE
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_DONE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_PENDING                     _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_TRIGGER                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQ_STATE_SHIFT                 _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQ_STATE_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQ_STATE_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQ_STATE_RANGE                 28:28
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQ_STATE_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQ_STATE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQ_STATE_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQ_STATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQ_STATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQ_STATE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQ_STATE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQ_STATE_IDLE                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQ_STATE_BUSY                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQUENCE_SHIFT                  _MK_SHIFT_CONST(20)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQUENCE_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQUENCE_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQUENCE_RANGE                  20:20
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQUENCE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQUENCE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQUENCE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQUENCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQUENCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQUENCE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQUENCE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQUENCE_INIT_ENUM                      UP
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQUENCE_UP                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQUENCE_DOWN                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_NEW_POWER_STATE_SHIFT                   _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_NEW_POWER_STATE_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_NEW_POWER_STATE_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_NEW_POWER_STATE_RANGE                   16:16
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_NEW_POWER_STATE_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_NEW_POWER_STATE_DEFAULT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_NEW_POWER_STATE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_NEW_POWER_STATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_NEW_POWER_STATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_NEW_POWER_STATE_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_NEW_POWER_STATE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_NEW_POWER_STATE_INIT_ENUM                       PD
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_NEW_POWER_STATE_PU                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_NEW_POWER_STATE_PD                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_DELAY_SHIFT                     _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_DELAY_FIELD                     _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_DELAY_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_DELAY_RANGE                     15:12
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_DELAY_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_DELAY_DEFAULT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_DELAY_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_DELAY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_DELAY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_DELAY_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_DELAY_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE9_STATE_SHIFT                       _MK_SHIFT_CONST(9)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE9_STATE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE9_STATE_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE9_STATE_RANGE                       9:9
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE9_STATE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE9_STATE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE9_STATE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE9_STATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE9_STATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE9_STATE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE9_STATE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE9_STATE_POWERUP                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE9_STATE_POWERDOWN                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE8_STATE_SHIFT                       _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE8_STATE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE8_STATE_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE8_STATE_RANGE                       8:8
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE8_STATE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE8_STATE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE8_STATE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE8_STATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE8_STATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE8_STATE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE8_STATE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE8_STATE_POWERUP                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE8_STATE_POWERDOWN                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE7_STATE_SHIFT                       _MK_SHIFT_CONST(7)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE7_STATE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE7_STATE_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE7_STATE_RANGE                       7:7
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE7_STATE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE7_STATE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE7_STATE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE7_STATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE7_STATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE7_STATE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE7_STATE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE7_STATE_POWERUP                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE7_STATE_POWERDOWN                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE6_STATE_SHIFT                       _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE6_STATE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE6_STATE_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE6_STATE_RANGE                       6:6
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE6_STATE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE6_STATE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE6_STATE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE6_STATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE6_STATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE6_STATE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE6_STATE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE6_STATE_POWERUP                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE6_STATE_POWERDOWN                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE5_STATE_SHIFT                       _MK_SHIFT_CONST(5)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE5_STATE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE5_STATE_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE5_STATE_RANGE                       5:5
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE5_STATE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE5_STATE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE5_STATE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE5_STATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE5_STATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE5_STATE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE5_STATE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE5_STATE_POWERUP                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE5_STATE_POWERDOWN                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE4_STATE_SHIFT                       _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE4_STATE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE4_STATE_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE4_STATE_RANGE                       4:4
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE4_STATE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE4_STATE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE4_STATE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE4_STATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE4_STATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE4_STATE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE4_STATE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE4_STATE_POWERUP                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE4_STATE_POWERDOWN                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE3_STATE_SHIFT                       _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE3_STATE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE3_STATE_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE3_STATE_RANGE                       3:3
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE3_STATE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE3_STATE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE3_STATE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE3_STATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE3_STATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE3_STATE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE3_STATE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE3_STATE_POWERUP                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE3_STATE_POWERDOWN                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE2_STATE_SHIFT                       _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE2_STATE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE2_STATE_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE2_STATE_RANGE                       2:2
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE2_STATE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE2_STATE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE2_STATE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE2_STATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE2_STATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE2_STATE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE2_STATE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE2_STATE_POWERUP                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE2_STATE_POWERDOWN                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE1_STATE_SHIFT                       _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE1_STATE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE1_STATE_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE1_STATE_RANGE                       1:1
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE1_STATE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE1_STATE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE1_STATE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE1_STATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE1_STATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE1_STATE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE1_STATE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE1_STATE_POWERUP                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE1_STATE_POWERDOWN                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE0_STATE_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE0_STATE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE0_STATE_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE0_STATE_RANGE                       0:0
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE0_STATE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE0_STATE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE0_STATE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE0_STATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE0_STATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE0_STATE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE0_STATE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE0_STATE_POWERUP                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE0_STATE_POWERDOWN                   _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_SEQ_INST0_0
#define SOR_NV_PDISP_SOR_SEQ_INST0_0                    _MK_ADDR_CONST(0x22)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SCR                        0
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_RESET_VAL                  _MK_MASK_CONST(0x1008000)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_RESET_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_READ_MASK                  _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WRITE_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PLL_PULLDOWN_SHIFT                 _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PLL_PULLDOWN_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_PLL_PULLDOWN_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PLL_PULLDOWN_RANGE                 31:31
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PLL_PULLDOWN_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PLL_PULLDOWN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PLL_PULLDOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PLL_PULLDOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PLL_PULLDOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PLL_PULLDOWN_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PLL_PULLDOWN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PLL_PULLDOWN_INIT_ENUM                     DISABLE
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PLL_PULLDOWN_DISABLE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PLL_PULLDOWN_ENABLE                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST0_0_POWERDOWN_MACRO_SHIFT                      _MK_SHIFT_CONST(30)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_POWERDOWN_MACRO_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_POWERDOWN_MACRO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_POWERDOWN_MACRO_RANGE                      30:30
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_POWERDOWN_MACRO_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_POWERDOWN_MACRO_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_POWERDOWN_MACRO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_POWERDOWN_MACRO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_POWERDOWN_MACRO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_POWERDOWN_MACRO_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_POWERDOWN_MACRO_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_POWERDOWN_MACRO_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_POWERDOWN_MACRO_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_POWERDOWN_MACRO_POWERDOWN                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST0_0_ASSERT_PLL_RESET_SHIFT                     _MK_SHIFT_CONST(29)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_ASSERT_PLL_RESET_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_ASSERT_PLL_RESET_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_ASSERT_PLL_RESET_RANGE                     29:29
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_ASSERT_PLL_RESET_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_ASSERT_PLL_RESET_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_ASSERT_PLL_RESET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_ASSERT_PLL_RESET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_ASSERT_PLL_RESET_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_ASSERT_PLL_RESET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_ASSERT_PLL_RESET_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_ASSERT_PLL_RESET_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_ASSERT_PLL_RESET_RST                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_V_SHIFT                      _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_V_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_V_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_V_RANGE                      28:28
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_V_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_V_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_V_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_V_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_V_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_V_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_V_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_V_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_V_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_V_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_H_SHIFT                      _MK_SHIFT_CONST(27)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_H_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_H_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_H_RANGE                      27:27
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_H_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_H_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_H_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_H_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_H_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_H_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_H_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_H_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_H_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_H_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_DE_SHIFT                     _MK_SHIFT_CONST(26)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_DE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_DE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_DE_RANGE                     26:26
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_DE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_DE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_DE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_DE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_DE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_DE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_DE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_DE_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_DE_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_DE_INACTIVE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLACK_DATA_SHIFT                   _MK_SHIFT_CONST(25)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLACK_DATA_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_BLACK_DATA_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLACK_DATA_RANGE                   25:25
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLACK_DATA_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLACK_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLACK_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLACK_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLACK_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLACK_DATA_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLACK_DATA_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLACK_DATA_INIT_ENUM                       NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLACK_DATA_NORMAL                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLACK_DATA_BLACK                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST0_0_TRISTATE_IOS_SHIFT                 _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_TRISTATE_IOS_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_TRISTATE_IOS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_TRISTATE_IOS_RANGE                 24:24
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_TRISTATE_IOS_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_TRISTATE_IOS_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_TRISTATE_IOS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_TRISTATE_IOS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_TRISTATE_IOS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_TRISTATE_IOS_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_TRISTATE_IOS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_TRISTATE_IOS_INIT_ENUM                     TRISTATE
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_TRISTATE_IOS_ENABLE_PINS                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_TRISTATE_IOS_TRISTATE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST0_0_DRIVE_PWM_OUT_LO_SHIFT                     _MK_SHIFT_CONST(23)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_DRIVE_PWM_OUT_LO_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_DRIVE_PWM_OUT_LO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_DRIVE_PWM_OUT_LO_RANGE                     23:23
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_DRIVE_PWM_OUT_LO_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_DRIVE_PWM_OUT_LO_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_DRIVE_PWM_OUT_LO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_DRIVE_PWM_OUT_LO_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_DRIVE_PWM_OUT_LO_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_DRIVE_PWM_OUT_LO_INIT_ENUM                 FALSE
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_DRIVE_PWM_OUT_LO_FALSE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_DRIVE_PWM_OUT_LO_TRUE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_B_SHIFT                        _MK_SHIFT_CONST(22)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_B_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_B_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_B_RANGE                        22:22
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_B_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_B_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_B_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_B_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_B_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_B_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_B_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_A_SHIFT                        _MK_SHIFT_CONST(21)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_A_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_A_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_A_RANGE                        21:21
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_A_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_A_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_A_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_A_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_A_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_A_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_A_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_A_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_A_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_A_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SEQUENCE_SHIFT                     _MK_SHIFT_CONST(19)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SEQUENCE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_SEQUENCE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SEQUENCE_RANGE                     19:19
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SEQUENCE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SEQUENCE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SEQUENCE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SEQUENCE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SEQUENCE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SEQUENCE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SEQUENCE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SEQUENCE_INIT_ENUM                 UP
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SEQUENCE_UP                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SEQUENCE_DOWN                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST0_0_LANE_SEQ_SHIFT                     _MK_SHIFT_CONST(18)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_LANE_SEQ_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_LANE_SEQ_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_LANE_SEQ_RANGE                     18:18
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_LANE_SEQ_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_LANE_SEQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_LANE_SEQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_LANE_SEQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_LANE_SEQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_LANE_SEQ_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_LANE_SEQ_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_LANE_SEQ_INIT_ENUM                 STOP
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_LANE_SEQ_STOP                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_LANE_SEQ_RUN                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPORT_SHIFT                       _MK_SHIFT_CONST(17)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPORT_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPORT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPORT_RANGE                       17:17
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPORT_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPORT_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPORT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPORT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPORT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPORT_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPORT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPORT_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPORT_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPORT_YES                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPLL_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPLL_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPLL_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPLL_RANGE                        16:16
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPLL_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPLL_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPLL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPLL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPLL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPLL_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPLL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPLL_INIT_ENUM                    NO
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPLL_NO                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPLL_YES                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST0_0_HALT_SHIFT                 _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_HALT_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_HALT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_HALT_RANGE                 15:15
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_HALT_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_HALT_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_HALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_HALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_HALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_HALT_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_HALT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_HALT_INIT_ENUM                     TRUE
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_HALT_FALSE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_HALT_TRUE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_SHIFT                   _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_FIELD                   _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_RANGE                   13:12
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_INIT_ENUM                       US
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_US                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_MS                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_VSYNC                   _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_TIME_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_TIME_FIELD                    _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_TIME_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_TIME_RANGE                    9:0
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_TIME_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_TIME_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_TIME_DEFAULT_MASK                     _MK_MASK_CONST(0x3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_TIME_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_TIME_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_TIME_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_TIME_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_SEQ_INST1_0
#define SOR_NV_PDISP_SOR_SEQ_INST1_0                    _MK_ADDR_CONST(0x23)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SCR                        0
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_RESET_VAL                  _MK_MASK_CONST(0x1008000)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_RESET_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_READ_MASK                  _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WRITE_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PLL_PULLDOWN_SHIFT                 _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PLL_PULLDOWN_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_PLL_PULLDOWN_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PLL_PULLDOWN_RANGE                 31:31
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PLL_PULLDOWN_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PLL_PULLDOWN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PLL_PULLDOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PLL_PULLDOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PLL_PULLDOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PLL_PULLDOWN_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PLL_PULLDOWN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PLL_PULLDOWN_INIT_ENUM                     DISABLE
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PLL_PULLDOWN_DISABLE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PLL_PULLDOWN_ENABLE                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST1_0_POWERDOWN_MACRO_SHIFT                      _MK_SHIFT_CONST(30)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_POWERDOWN_MACRO_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_POWERDOWN_MACRO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_POWERDOWN_MACRO_RANGE                      30:30
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_POWERDOWN_MACRO_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_POWERDOWN_MACRO_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_POWERDOWN_MACRO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_POWERDOWN_MACRO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_POWERDOWN_MACRO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_POWERDOWN_MACRO_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_POWERDOWN_MACRO_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_POWERDOWN_MACRO_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_POWERDOWN_MACRO_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_POWERDOWN_MACRO_POWERDOWN                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST1_0_ASSERT_PLL_RESET_SHIFT                     _MK_SHIFT_CONST(29)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_ASSERT_PLL_RESET_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_ASSERT_PLL_RESET_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_ASSERT_PLL_RESET_RANGE                     29:29
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_ASSERT_PLL_RESET_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_ASSERT_PLL_RESET_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_ASSERT_PLL_RESET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_ASSERT_PLL_RESET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_ASSERT_PLL_RESET_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_ASSERT_PLL_RESET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_ASSERT_PLL_RESET_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_ASSERT_PLL_RESET_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_ASSERT_PLL_RESET_RST                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_V_SHIFT                      _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_V_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_V_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_V_RANGE                      28:28
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_V_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_V_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_V_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_V_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_V_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_V_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_V_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_V_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_V_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_V_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_H_SHIFT                      _MK_SHIFT_CONST(27)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_H_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_H_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_H_RANGE                      27:27
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_H_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_H_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_H_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_H_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_H_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_H_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_H_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_H_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_H_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_H_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_DE_SHIFT                     _MK_SHIFT_CONST(26)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_DE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_DE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_DE_RANGE                     26:26
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_DE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_DE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_DE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_DE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_DE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_DE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_DE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_DE_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_DE_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_DE_INACTIVE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLACK_DATA_SHIFT                   _MK_SHIFT_CONST(25)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLACK_DATA_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_BLACK_DATA_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLACK_DATA_RANGE                   25:25
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLACK_DATA_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLACK_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLACK_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLACK_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLACK_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLACK_DATA_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLACK_DATA_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLACK_DATA_INIT_ENUM                       NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLACK_DATA_NORMAL                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLACK_DATA_BLACK                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST1_0_TRISTATE_IOS_SHIFT                 _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_TRISTATE_IOS_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_TRISTATE_IOS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_TRISTATE_IOS_RANGE                 24:24
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_TRISTATE_IOS_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_TRISTATE_IOS_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_TRISTATE_IOS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_TRISTATE_IOS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_TRISTATE_IOS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_TRISTATE_IOS_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_TRISTATE_IOS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_TRISTATE_IOS_INIT_ENUM                     TRISTATE
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_TRISTATE_IOS_ENABLE_PINS                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_TRISTATE_IOS_TRISTATE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST1_0_DRIVE_PWM_OUT_LO_SHIFT                     _MK_SHIFT_CONST(23)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_DRIVE_PWM_OUT_LO_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_DRIVE_PWM_OUT_LO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_DRIVE_PWM_OUT_LO_RANGE                     23:23
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_DRIVE_PWM_OUT_LO_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_DRIVE_PWM_OUT_LO_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_DRIVE_PWM_OUT_LO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_DRIVE_PWM_OUT_LO_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_DRIVE_PWM_OUT_LO_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_DRIVE_PWM_OUT_LO_INIT_ENUM                 FALSE
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_DRIVE_PWM_OUT_LO_FALSE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_DRIVE_PWM_OUT_LO_TRUE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_B_SHIFT                        _MK_SHIFT_CONST(22)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_B_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_B_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_B_RANGE                        22:22
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_B_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_B_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_B_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_B_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_B_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_B_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_B_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_A_SHIFT                        _MK_SHIFT_CONST(21)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_A_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_A_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_A_RANGE                        21:21
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_A_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_A_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_A_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_A_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_A_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_A_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_A_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_A_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_A_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_A_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SEQUENCE_SHIFT                     _MK_SHIFT_CONST(19)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SEQUENCE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_SEQUENCE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SEQUENCE_RANGE                     19:19
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SEQUENCE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SEQUENCE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SEQUENCE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SEQUENCE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SEQUENCE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SEQUENCE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SEQUENCE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SEQUENCE_INIT_ENUM                 UP
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SEQUENCE_UP                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SEQUENCE_DOWN                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST1_0_LANE_SEQ_SHIFT                     _MK_SHIFT_CONST(18)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_LANE_SEQ_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_LANE_SEQ_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_LANE_SEQ_RANGE                     18:18
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_LANE_SEQ_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_LANE_SEQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_LANE_SEQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_LANE_SEQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_LANE_SEQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_LANE_SEQ_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_LANE_SEQ_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_LANE_SEQ_INIT_ENUM                 STOP
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_LANE_SEQ_STOP                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_LANE_SEQ_RUN                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPORT_SHIFT                       _MK_SHIFT_CONST(17)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPORT_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPORT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPORT_RANGE                       17:17
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPORT_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPORT_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPORT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPORT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPORT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPORT_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPORT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPORT_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPORT_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPORT_YES                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPLL_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPLL_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPLL_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPLL_RANGE                        16:16
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPLL_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPLL_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPLL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPLL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPLL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPLL_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPLL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPLL_INIT_ENUM                    NO
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPLL_NO                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPLL_YES                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST1_0_HALT_SHIFT                 _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_HALT_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_HALT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_HALT_RANGE                 15:15
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_HALT_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_HALT_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_HALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_HALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_HALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_HALT_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_HALT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_HALT_INIT_ENUM                     TRUE
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_HALT_FALSE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_HALT_TRUE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_SHIFT                   _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_FIELD                   _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_RANGE                   13:12
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_INIT_ENUM                       US
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_US                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_MS                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_VSYNC                   _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_TIME_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_TIME_FIELD                    _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_TIME_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_TIME_RANGE                    9:0
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_TIME_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_TIME_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_TIME_DEFAULT_MASK                     _MK_MASK_CONST(0x3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_TIME_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_TIME_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_TIME_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_TIME_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_SEQ_INST2_0
#define SOR_NV_PDISP_SOR_SEQ_INST2_0                    _MK_ADDR_CONST(0x24)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SCR                        0
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_RESET_VAL                  _MK_MASK_CONST(0x1008000)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_RESET_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_READ_MASK                  _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WRITE_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PLL_PULLDOWN_SHIFT                 _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PLL_PULLDOWN_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_PLL_PULLDOWN_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PLL_PULLDOWN_RANGE                 31:31
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PLL_PULLDOWN_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PLL_PULLDOWN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PLL_PULLDOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PLL_PULLDOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PLL_PULLDOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PLL_PULLDOWN_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PLL_PULLDOWN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PLL_PULLDOWN_INIT_ENUM                     DISABLE
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PLL_PULLDOWN_DISABLE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PLL_PULLDOWN_ENABLE                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST2_0_POWERDOWN_MACRO_SHIFT                      _MK_SHIFT_CONST(30)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_POWERDOWN_MACRO_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_POWERDOWN_MACRO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_POWERDOWN_MACRO_RANGE                      30:30
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_POWERDOWN_MACRO_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_POWERDOWN_MACRO_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_POWERDOWN_MACRO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_POWERDOWN_MACRO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_POWERDOWN_MACRO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_POWERDOWN_MACRO_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_POWERDOWN_MACRO_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_POWERDOWN_MACRO_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_POWERDOWN_MACRO_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_POWERDOWN_MACRO_POWERDOWN                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST2_0_ASSERT_PLL_RESET_SHIFT                     _MK_SHIFT_CONST(29)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_ASSERT_PLL_RESET_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_ASSERT_PLL_RESET_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_ASSERT_PLL_RESET_RANGE                     29:29
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_ASSERT_PLL_RESET_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_ASSERT_PLL_RESET_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_ASSERT_PLL_RESET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_ASSERT_PLL_RESET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_ASSERT_PLL_RESET_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_ASSERT_PLL_RESET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_ASSERT_PLL_RESET_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_ASSERT_PLL_RESET_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_ASSERT_PLL_RESET_RST                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_V_SHIFT                      _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_V_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_V_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_V_RANGE                      28:28
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_V_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_V_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_V_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_V_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_V_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_V_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_V_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_V_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_V_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_V_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_H_SHIFT                      _MK_SHIFT_CONST(27)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_H_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_H_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_H_RANGE                      27:27
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_H_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_H_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_H_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_H_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_H_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_H_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_H_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_H_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_H_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_H_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_DE_SHIFT                     _MK_SHIFT_CONST(26)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_DE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_DE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_DE_RANGE                     26:26
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_DE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_DE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_DE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_DE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_DE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_DE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_DE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_DE_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_DE_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_DE_INACTIVE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLACK_DATA_SHIFT                   _MK_SHIFT_CONST(25)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLACK_DATA_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_BLACK_DATA_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLACK_DATA_RANGE                   25:25
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLACK_DATA_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLACK_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLACK_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLACK_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLACK_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLACK_DATA_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLACK_DATA_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLACK_DATA_INIT_ENUM                       NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLACK_DATA_NORMAL                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLACK_DATA_BLACK                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST2_0_TRISTATE_IOS_SHIFT                 _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_TRISTATE_IOS_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_TRISTATE_IOS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_TRISTATE_IOS_RANGE                 24:24
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_TRISTATE_IOS_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_TRISTATE_IOS_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_TRISTATE_IOS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_TRISTATE_IOS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_TRISTATE_IOS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_TRISTATE_IOS_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_TRISTATE_IOS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_TRISTATE_IOS_INIT_ENUM                     TRISTATE
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_TRISTATE_IOS_ENABLE_PINS                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_TRISTATE_IOS_TRISTATE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST2_0_DRIVE_PWM_OUT_LO_SHIFT                     _MK_SHIFT_CONST(23)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_DRIVE_PWM_OUT_LO_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_DRIVE_PWM_OUT_LO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_DRIVE_PWM_OUT_LO_RANGE                     23:23
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_DRIVE_PWM_OUT_LO_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_DRIVE_PWM_OUT_LO_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_DRIVE_PWM_OUT_LO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_DRIVE_PWM_OUT_LO_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_DRIVE_PWM_OUT_LO_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_DRIVE_PWM_OUT_LO_INIT_ENUM                 FALSE
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_DRIVE_PWM_OUT_LO_FALSE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_DRIVE_PWM_OUT_LO_TRUE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_B_SHIFT                        _MK_SHIFT_CONST(22)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_B_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_B_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_B_RANGE                        22:22
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_B_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_B_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_B_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_B_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_B_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_B_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_B_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_A_SHIFT                        _MK_SHIFT_CONST(21)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_A_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_A_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_A_RANGE                        21:21
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_A_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_A_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_A_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_A_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_A_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_A_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_A_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_A_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_A_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_A_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SEQUENCE_SHIFT                     _MK_SHIFT_CONST(19)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SEQUENCE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_SEQUENCE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SEQUENCE_RANGE                     19:19
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SEQUENCE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SEQUENCE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SEQUENCE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SEQUENCE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SEQUENCE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SEQUENCE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SEQUENCE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SEQUENCE_INIT_ENUM                 UP
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SEQUENCE_UP                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SEQUENCE_DOWN                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST2_0_LANE_SEQ_SHIFT                     _MK_SHIFT_CONST(18)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_LANE_SEQ_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_LANE_SEQ_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_LANE_SEQ_RANGE                     18:18
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_LANE_SEQ_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_LANE_SEQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_LANE_SEQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_LANE_SEQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_LANE_SEQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_LANE_SEQ_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_LANE_SEQ_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_LANE_SEQ_INIT_ENUM                 STOP
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_LANE_SEQ_STOP                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_LANE_SEQ_RUN                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPORT_SHIFT                       _MK_SHIFT_CONST(17)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPORT_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPORT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPORT_RANGE                       17:17
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPORT_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPORT_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPORT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPORT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPORT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPORT_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPORT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPORT_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPORT_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPORT_YES                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPLL_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPLL_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPLL_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPLL_RANGE                        16:16
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPLL_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPLL_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPLL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPLL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPLL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPLL_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPLL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPLL_INIT_ENUM                    NO
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPLL_NO                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPLL_YES                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST2_0_HALT_SHIFT                 _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_HALT_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_HALT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_HALT_RANGE                 15:15
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_HALT_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_HALT_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_HALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_HALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_HALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_HALT_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_HALT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_HALT_INIT_ENUM                     TRUE
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_HALT_FALSE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_HALT_TRUE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_SHIFT                   _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_FIELD                   _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_RANGE                   13:12
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_INIT_ENUM                       US
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_US                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_MS                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_VSYNC                   _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_TIME_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_TIME_FIELD                    _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_TIME_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_TIME_RANGE                    9:0
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_TIME_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_TIME_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_TIME_DEFAULT_MASK                     _MK_MASK_CONST(0x3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_TIME_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_TIME_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_TIME_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_TIME_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_SEQ_INST3_0
#define SOR_NV_PDISP_SOR_SEQ_INST3_0                    _MK_ADDR_CONST(0x25)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SCR                        0
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_RESET_VAL                  _MK_MASK_CONST(0x1008000)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_RESET_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_READ_MASK                  _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WRITE_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PLL_PULLDOWN_SHIFT                 _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PLL_PULLDOWN_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_PLL_PULLDOWN_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PLL_PULLDOWN_RANGE                 31:31
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PLL_PULLDOWN_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PLL_PULLDOWN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PLL_PULLDOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PLL_PULLDOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PLL_PULLDOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PLL_PULLDOWN_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PLL_PULLDOWN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PLL_PULLDOWN_INIT_ENUM                     DISABLE
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PLL_PULLDOWN_DISABLE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PLL_PULLDOWN_ENABLE                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST3_0_POWERDOWN_MACRO_SHIFT                      _MK_SHIFT_CONST(30)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_POWERDOWN_MACRO_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_POWERDOWN_MACRO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_POWERDOWN_MACRO_RANGE                      30:30
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_POWERDOWN_MACRO_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_POWERDOWN_MACRO_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_POWERDOWN_MACRO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_POWERDOWN_MACRO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_POWERDOWN_MACRO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_POWERDOWN_MACRO_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_POWERDOWN_MACRO_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_POWERDOWN_MACRO_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_POWERDOWN_MACRO_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_POWERDOWN_MACRO_POWERDOWN                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST3_0_ASSERT_PLL_RESET_SHIFT                     _MK_SHIFT_CONST(29)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_ASSERT_PLL_RESET_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_ASSERT_PLL_RESET_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_ASSERT_PLL_RESET_RANGE                     29:29
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_ASSERT_PLL_RESET_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_ASSERT_PLL_RESET_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_ASSERT_PLL_RESET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_ASSERT_PLL_RESET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_ASSERT_PLL_RESET_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_ASSERT_PLL_RESET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_ASSERT_PLL_RESET_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_ASSERT_PLL_RESET_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_ASSERT_PLL_RESET_RST                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_V_SHIFT                      _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_V_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_V_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_V_RANGE                      28:28
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_V_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_V_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_V_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_V_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_V_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_V_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_V_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_V_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_V_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_V_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_H_SHIFT                      _MK_SHIFT_CONST(27)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_H_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_H_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_H_RANGE                      27:27
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_H_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_H_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_H_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_H_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_H_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_H_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_H_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_H_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_H_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_H_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_DE_SHIFT                     _MK_SHIFT_CONST(26)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_DE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_DE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_DE_RANGE                     26:26
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_DE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_DE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_DE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_DE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_DE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_DE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_DE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_DE_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_DE_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_DE_INACTIVE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLACK_DATA_SHIFT                   _MK_SHIFT_CONST(25)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLACK_DATA_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_BLACK_DATA_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLACK_DATA_RANGE                   25:25
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLACK_DATA_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLACK_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLACK_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLACK_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLACK_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLACK_DATA_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLACK_DATA_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLACK_DATA_INIT_ENUM                       NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLACK_DATA_NORMAL                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLACK_DATA_BLACK                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST3_0_TRISTATE_IOS_SHIFT                 _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_TRISTATE_IOS_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_TRISTATE_IOS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_TRISTATE_IOS_RANGE                 24:24
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_TRISTATE_IOS_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_TRISTATE_IOS_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_TRISTATE_IOS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_TRISTATE_IOS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_TRISTATE_IOS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_TRISTATE_IOS_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_TRISTATE_IOS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_TRISTATE_IOS_INIT_ENUM                     TRISTATE
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_TRISTATE_IOS_ENABLE_PINS                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_TRISTATE_IOS_TRISTATE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST3_0_DRIVE_PWM_OUT_LO_SHIFT                     _MK_SHIFT_CONST(23)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_DRIVE_PWM_OUT_LO_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_DRIVE_PWM_OUT_LO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_DRIVE_PWM_OUT_LO_RANGE                     23:23
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_DRIVE_PWM_OUT_LO_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_DRIVE_PWM_OUT_LO_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_DRIVE_PWM_OUT_LO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_DRIVE_PWM_OUT_LO_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_DRIVE_PWM_OUT_LO_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_DRIVE_PWM_OUT_LO_INIT_ENUM                 FALSE
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_DRIVE_PWM_OUT_LO_FALSE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_DRIVE_PWM_OUT_LO_TRUE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_B_SHIFT                        _MK_SHIFT_CONST(22)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_B_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_B_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_B_RANGE                        22:22
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_B_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_B_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_B_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_B_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_B_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_B_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_B_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_A_SHIFT                        _MK_SHIFT_CONST(21)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_A_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_A_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_A_RANGE                        21:21
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_A_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_A_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_A_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_A_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_A_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_A_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_A_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_A_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_A_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_A_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SEQUENCE_SHIFT                     _MK_SHIFT_CONST(19)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SEQUENCE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_SEQUENCE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SEQUENCE_RANGE                     19:19
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SEQUENCE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SEQUENCE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SEQUENCE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SEQUENCE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SEQUENCE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SEQUENCE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SEQUENCE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SEQUENCE_INIT_ENUM                 UP
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SEQUENCE_UP                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SEQUENCE_DOWN                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST3_0_LANE_SEQ_SHIFT                     _MK_SHIFT_CONST(18)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_LANE_SEQ_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_LANE_SEQ_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_LANE_SEQ_RANGE                     18:18
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_LANE_SEQ_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_LANE_SEQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_LANE_SEQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_LANE_SEQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_LANE_SEQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_LANE_SEQ_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_LANE_SEQ_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_LANE_SEQ_INIT_ENUM                 STOP
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_LANE_SEQ_STOP                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_LANE_SEQ_RUN                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPORT_SHIFT                       _MK_SHIFT_CONST(17)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPORT_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPORT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPORT_RANGE                       17:17
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPORT_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPORT_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPORT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPORT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPORT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPORT_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPORT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPORT_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPORT_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPORT_YES                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPLL_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPLL_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPLL_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPLL_RANGE                        16:16
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPLL_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPLL_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPLL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPLL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPLL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPLL_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPLL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPLL_INIT_ENUM                    NO
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPLL_NO                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPLL_YES                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST3_0_HALT_SHIFT                 _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_HALT_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_HALT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_HALT_RANGE                 15:15
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_HALT_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_HALT_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_HALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_HALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_HALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_HALT_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_HALT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_HALT_INIT_ENUM                     TRUE
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_HALT_FALSE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_HALT_TRUE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_SHIFT                   _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_FIELD                   _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_RANGE                   13:12
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_INIT_ENUM                       US
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_US                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_MS                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_VSYNC                   _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_TIME_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_TIME_FIELD                    _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_TIME_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_TIME_RANGE                    9:0
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_TIME_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_TIME_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_TIME_DEFAULT_MASK                     _MK_MASK_CONST(0x3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_TIME_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_TIME_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_TIME_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_TIME_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_SEQ_INST4_0
#define SOR_NV_PDISP_SOR_SEQ_INST4_0                    _MK_ADDR_CONST(0x26)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SCR                        0
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_RESET_VAL                  _MK_MASK_CONST(0x1008000)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_RESET_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_READ_MASK                  _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WRITE_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PLL_PULLDOWN_SHIFT                 _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PLL_PULLDOWN_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_PLL_PULLDOWN_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PLL_PULLDOWN_RANGE                 31:31
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PLL_PULLDOWN_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PLL_PULLDOWN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PLL_PULLDOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PLL_PULLDOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PLL_PULLDOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PLL_PULLDOWN_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PLL_PULLDOWN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PLL_PULLDOWN_INIT_ENUM                     DISABLE
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PLL_PULLDOWN_DISABLE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PLL_PULLDOWN_ENABLE                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST4_0_POWERDOWN_MACRO_SHIFT                      _MK_SHIFT_CONST(30)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_POWERDOWN_MACRO_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_POWERDOWN_MACRO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_POWERDOWN_MACRO_RANGE                      30:30
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_POWERDOWN_MACRO_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_POWERDOWN_MACRO_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_POWERDOWN_MACRO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_POWERDOWN_MACRO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_POWERDOWN_MACRO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_POWERDOWN_MACRO_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_POWERDOWN_MACRO_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_POWERDOWN_MACRO_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_POWERDOWN_MACRO_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_POWERDOWN_MACRO_POWERDOWN                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST4_0_ASSERT_PLL_RESET_SHIFT                     _MK_SHIFT_CONST(29)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_ASSERT_PLL_RESET_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_ASSERT_PLL_RESET_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_ASSERT_PLL_RESET_RANGE                     29:29
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_ASSERT_PLL_RESET_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_ASSERT_PLL_RESET_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_ASSERT_PLL_RESET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_ASSERT_PLL_RESET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_ASSERT_PLL_RESET_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_ASSERT_PLL_RESET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_ASSERT_PLL_RESET_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_ASSERT_PLL_RESET_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_ASSERT_PLL_RESET_RST                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_V_SHIFT                      _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_V_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_V_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_V_RANGE                      28:28
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_V_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_V_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_V_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_V_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_V_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_V_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_V_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_V_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_V_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_V_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_H_SHIFT                      _MK_SHIFT_CONST(27)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_H_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_H_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_H_RANGE                      27:27
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_H_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_H_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_H_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_H_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_H_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_H_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_H_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_H_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_H_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_H_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_DE_SHIFT                     _MK_SHIFT_CONST(26)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_DE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_DE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_DE_RANGE                     26:26
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_DE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_DE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_DE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_DE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_DE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_DE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_DE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_DE_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_DE_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_DE_INACTIVE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLACK_DATA_SHIFT                   _MK_SHIFT_CONST(25)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLACK_DATA_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_BLACK_DATA_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLACK_DATA_RANGE                   25:25
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLACK_DATA_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLACK_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLACK_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLACK_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLACK_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLACK_DATA_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLACK_DATA_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLACK_DATA_INIT_ENUM                       NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLACK_DATA_NORMAL                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLACK_DATA_BLACK                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST4_0_TRISTATE_IOS_SHIFT                 _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_TRISTATE_IOS_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_TRISTATE_IOS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_TRISTATE_IOS_RANGE                 24:24
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_TRISTATE_IOS_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_TRISTATE_IOS_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_TRISTATE_IOS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_TRISTATE_IOS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_TRISTATE_IOS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_TRISTATE_IOS_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_TRISTATE_IOS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_TRISTATE_IOS_INIT_ENUM                     TRISTATE
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_TRISTATE_IOS_ENABLE_PINS                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_TRISTATE_IOS_TRISTATE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST4_0_DRIVE_PWM_OUT_LO_SHIFT                     _MK_SHIFT_CONST(23)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_DRIVE_PWM_OUT_LO_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_DRIVE_PWM_OUT_LO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_DRIVE_PWM_OUT_LO_RANGE                     23:23
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_DRIVE_PWM_OUT_LO_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_DRIVE_PWM_OUT_LO_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_DRIVE_PWM_OUT_LO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_DRIVE_PWM_OUT_LO_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_DRIVE_PWM_OUT_LO_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_DRIVE_PWM_OUT_LO_INIT_ENUM                 FALSE
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_DRIVE_PWM_OUT_LO_FALSE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_DRIVE_PWM_OUT_LO_TRUE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_B_SHIFT                        _MK_SHIFT_CONST(22)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_B_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_B_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_B_RANGE                        22:22
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_B_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_B_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_B_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_B_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_B_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_B_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_B_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_A_SHIFT                        _MK_SHIFT_CONST(21)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_A_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_A_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_A_RANGE                        21:21
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_A_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_A_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_A_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_A_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_A_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_A_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_A_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_A_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_A_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_A_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SEQUENCE_SHIFT                     _MK_SHIFT_CONST(19)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SEQUENCE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_SEQUENCE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SEQUENCE_RANGE                     19:19
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SEQUENCE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SEQUENCE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SEQUENCE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SEQUENCE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SEQUENCE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SEQUENCE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SEQUENCE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SEQUENCE_INIT_ENUM                 UP
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SEQUENCE_UP                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SEQUENCE_DOWN                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST4_0_LANE_SEQ_SHIFT                     _MK_SHIFT_CONST(18)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_LANE_SEQ_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_LANE_SEQ_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_LANE_SEQ_RANGE                     18:18
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_LANE_SEQ_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_LANE_SEQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_LANE_SEQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_LANE_SEQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_LANE_SEQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_LANE_SEQ_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_LANE_SEQ_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_LANE_SEQ_INIT_ENUM                 STOP
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_LANE_SEQ_STOP                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_LANE_SEQ_RUN                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPORT_SHIFT                       _MK_SHIFT_CONST(17)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPORT_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPORT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPORT_RANGE                       17:17
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPORT_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPORT_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPORT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPORT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPORT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPORT_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPORT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPORT_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPORT_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPORT_YES                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPLL_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPLL_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPLL_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPLL_RANGE                        16:16
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPLL_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPLL_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPLL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPLL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPLL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPLL_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPLL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPLL_INIT_ENUM                    NO
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPLL_NO                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPLL_YES                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST4_0_HALT_SHIFT                 _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_HALT_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_HALT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_HALT_RANGE                 15:15
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_HALT_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_HALT_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_HALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_HALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_HALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_HALT_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_HALT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_HALT_INIT_ENUM                     TRUE
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_HALT_FALSE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_HALT_TRUE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_SHIFT                   _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_FIELD                   _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_RANGE                   13:12
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_INIT_ENUM                       US
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_US                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_MS                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_VSYNC                   _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_TIME_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_TIME_FIELD                    _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_TIME_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_TIME_RANGE                    9:0
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_TIME_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_TIME_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_TIME_DEFAULT_MASK                     _MK_MASK_CONST(0x3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_TIME_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_TIME_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_TIME_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_TIME_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_SEQ_INST5_0
#define SOR_NV_PDISP_SOR_SEQ_INST5_0                    _MK_ADDR_CONST(0x27)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SCR                        0
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_RESET_VAL                  _MK_MASK_CONST(0x1008000)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_RESET_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_READ_MASK                  _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WRITE_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PLL_PULLDOWN_SHIFT                 _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PLL_PULLDOWN_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_PLL_PULLDOWN_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PLL_PULLDOWN_RANGE                 31:31
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PLL_PULLDOWN_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PLL_PULLDOWN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PLL_PULLDOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PLL_PULLDOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PLL_PULLDOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PLL_PULLDOWN_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PLL_PULLDOWN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PLL_PULLDOWN_INIT_ENUM                     DISABLE
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PLL_PULLDOWN_DISABLE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PLL_PULLDOWN_ENABLE                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST5_0_POWERDOWN_MACRO_SHIFT                      _MK_SHIFT_CONST(30)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_POWERDOWN_MACRO_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_POWERDOWN_MACRO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_POWERDOWN_MACRO_RANGE                      30:30
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_POWERDOWN_MACRO_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_POWERDOWN_MACRO_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_POWERDOWN_MACRO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_POWERDOWN_MACRO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_POWERDOWN_MACRO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_POWERDOWN_MACRO_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_POWERDOWN_MACRO_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_POWERDOWN_MACRO_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_POWERDOWN_MACRO_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_POWERDOWN_MACRO_POWERDOWN                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST5_0_ASSERT_PLL_RESET_SHIFT                     _MK_SHIFT_CONST(29)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_ASSERT_PLL_RESET_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_ASSERT_PLL_RESET_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_ASSERT_PLL_RESET_RANGE                     29:29
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_ASSERT_PLL_RESET_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_ASSERT_PLL_RESET_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_ASSERT_PLL_RESET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_ASSERT_PLL_RESET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_ASSERT_PLL_RESET_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_ASSERT_PLL_RESET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_ASSERT_PLL_RESET_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_ASSERT_PLL_RESET_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_ASSERT_PLL_RESET_RST                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_V_SHIFT                      _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_V_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_V_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_V_RANGE                      28:28
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_V_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_V_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_V_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_V_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_V_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_V_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_V_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_V_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_V_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_V_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_H_SHIFT                      _MK_SHIFT_CONST(27)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_H_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_H_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_H_RANGE                      27:27
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_H_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_H_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_H_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_H_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_H_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_H_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_H_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_H_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_H_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_H_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_DE_SHIFT                     _MK_SHIFT_CONST(26)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_DE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_DE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_DE_RANGE                     26:26
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_DE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_DE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_DE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_DE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_DE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_DE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_DE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_DE_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_DE_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_DE_INACTIVE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLACK_DATA_SHIFT                   _MK_SHIFT_CONST(25)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLACK_DATA_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_BLACK_DATA_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLACK_DATA_RANGE                   25:25
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLACK_DATA_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLACK_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLACK_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLACK_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLACK_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLACK_DATA_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLACK_DATA_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLACK_DATA_INIT_ENUM                       NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLACK_DATA_NORMAL                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLACK_DATA_BLACK                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST5_0_TRISTATE_IOS_SHIFT                 _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_TRISTATE_IOS_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_TRISTATE_IOS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_TRISTATE_IOS_RANGE                 24:24
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_TRISTATE_IOS_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_TRISTATE_IOS_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_TRISTATE_IOS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_TRISTATE_IOS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_TRISTATE_IOS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_TRISTATE_IOS_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_TRISTATE_IOS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_TRISTATE_IOS_INIT_ENUM                     TRISTATE
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_TRISTATE_IOS_ENABLE_PINS                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_TRISTATE_IOS_TRISTATE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST5_0_DRIVE_PWM_OUT_LO_SHIFT                     _MK_SHIFT_CONST(23)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_DRIVE_PWM_OUT_LO_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_DRIVE_PWM_OUT_LO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_DRIVE_PWM_OUT_LO_RANGE                     23:23
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_DRIVE_PWM_OUT_LO_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_DRIVE_PWM_OUT_LO_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_DRIVE_PWM_OUT_LO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_DRIVE_PWM_OUT_LO_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_DRIVE_PWM_OUT_LO_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_DRIVE_PWM_OUT_LO_INIT_ENUM                 FALSE
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_DRIVE_PWM_OUT_LO_FALSE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_DRIVE_PWM_OUT_LO_TRUE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_B_SHIFT                        _MK_SHIFT_CONST(22)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_B_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_B_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_B_RANGE                        22:22
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_B_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_B_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_B_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_B_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_B_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_B_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_B_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_A_SHIFT                        _MK_SHIFT_CONST(21)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_A_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_A_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_A_RANGE                        21:21
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_A_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_A_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_A_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_A_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_A_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_A_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_A_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_A_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_A_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_A_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SEQUENCE_SHIFT                     _MK_SHIFT_CONST(19)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SEQUENCE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_SEQUENCE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SEQUENCE_RANGE                     19:19
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SEQUENCE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SEQUENCE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SEQUENCE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SEQUENCE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SEQUENCE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SEQUENCE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SEQUENCE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SEQUENCE_INIT_ENUM                 UP
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SEQUENCE_UP                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SEQUENCE_DOWN                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST5_0_LANE_SEQ_SHIFT                     _MK_SHIFT_CONST(18)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_LANE_SEQ_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_LANE_SEQ_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_LANE_SEQ_RANGE                     18:18
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_LANE_SEQ_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_LANE_SEQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_LANE_SEQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_LANE_SEQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_LANE_SEQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_LANE_SEQ_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_LANE_SEQ_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_LANE_SEQ_INIT_ENUM                 STOP
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_LANE_SEQ_STOP                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_LANE_SEQ_RUN                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPORT_SHIFT                       _MK_SHIFT_CONST(17)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPORT_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPORT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPORT_RANGE                       17:17
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPORT_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPORT_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPORT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPORT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPORT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPORT_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPORT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPORT_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPORT_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPORT_YES                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPLL_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPLL_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPLL_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPLL_RANGE                        16:16
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPLL_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPLL_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPLL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPLL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPLL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPLL_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPLL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPLL_INIT_ENUM                    NO
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPLL_NO                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPLL_YES                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST5_0_HALT_SHIFT                 _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_HALT_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_HALT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_HALT_RANGE                 15:15
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_HALT_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_HALT_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_HALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_HALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_HALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_HALT_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_HALT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_HALT_INIT_ENUM                     TRUE
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_HALT_FALSE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_HALT_TRUE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_SHIFT                   _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_FIELD                   _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_RANGE                   13:12
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_INIT_ENUM                       US
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_US                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_MS                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_VSYNC                   _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_TIME_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_TIME_FIELD                    _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_TIME_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_TIME_RANGE                    9:0
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_TIME_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_TIME_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_TIME_DEFAULT_MASK                     _MK_MASK_CONST(0x3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_TIME_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_TIME_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_TIME_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_TIME_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_SEQ_INST6_0
#define SOR_NV_PDISP_SOR_SEQ_INST6_0                    _MK_ADDR_CONST(0x28)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SCR                        0
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_RESET_VAL                  _MK_MASK_CONST(0x1008000)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_RESET_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_READ_MASK                  _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WRITE_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PLL_PULLDOWN_SHIFT                 _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PLL_PULLDOWN_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_PLL_PULLDOWN_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PLL_PULLDOWN_RANGE                 31:31
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PLL_PULLDOWN_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PLL_PULLDOWN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PLL_PULLDOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PLL_PULLDOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PLL_PULLDOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PLL_PULLDOWN_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PLL_PULLDOWN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PLL_PULLDOWN_INIT_ENUM                     DISABLE
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PLL_PULLDOWN_DISABLE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PLL_PULLDOWN_ENABLE                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST6_0_POWERDOWN_MACRO_SHIFT                      _MK_SHIFT_CONST(30)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_POWERDOWN_MACRO_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_POWERDOWN_MACRO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_POWERDOWN_MACRO_RANGE                      30:30
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_POWERDOWN_MACRO_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_POWERDOWN_MACRO_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_POWERDOWN_MACRO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_POWERDOWN_MACRO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_POWERDOWN_MACRO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_POWERDOWN_MACRO_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_POWERDOWN_MACRO_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_POWERDOWN_MACRO_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_POWERDOWN_MACRO_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_POWERDOWN_MACRO_POWERDOWN                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST6_0_ASSERT_PLL_RESET_SHIFT                     _MK_SHIFT_CONST(29)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_ASSERT_PLL_RESET_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_ASSERT_PLL_RESET_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_ASSERT_PLL_RESET_RANGE                     29:29
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_ASSERT_PLL_RESET_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_ASSERT_PLL_RESET_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_ASSERT_PLL_RESET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_ASSERT_PLL_RESET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_ASSERT_PLL_RESET_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_ASSERT_PLL_RESET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_ASSERT_PLL_RESET_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_ASSERT_PLL_RESET_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_ASSERT_PLL_RESET_RST                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_V_SHIFT                      _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_V_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_V_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_V_RANGE                      28:28
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_V_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_V_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_V_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_V_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_V_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_V_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_V_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_V_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_V_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_V_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_H_SHIFT                      _MK_SHIFT_CONST(27)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_H_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_H_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_H_RANGE                      27:27
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_H_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_H_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_H_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_H_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_H_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_H_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_H_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_H_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_H_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_H_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_DE_SHIFT                     _MK_SHIFT_CONST(26)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_DE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_DE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_DE_RANGE                     26:26
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_DE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_DE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_DE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_DE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_DE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_DE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_DE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_DE_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_DE_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_DE_INACTIVE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLACK_DATA_SHIFT                   _MK_SHIFT_CONST(25)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLACK_DATA_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_BLACK_DATA_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLACK_DATA_RANGE                   25:25
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLACK_DATA_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLACK_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLACK_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLACK_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLACK_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLACK_DATA_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLACK_DATA_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLACK_DATA_INIT_ENUM                       NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLACK_DATA_NORMAL                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLACK_DATA_BLACK                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST6_0_TRISTATE_IOS_SHIFT                 _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_TRISTATE_IOS_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_TRISTATE_IOS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_TRISTATE_IOS_RANGE                 24:24
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_TRISTATE_IOS_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_TRISTATE_IOS_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_TRISTATE_IOS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_TRISTATE_IOS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_TRISTATE_IOS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_TRISTATE_IOS_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_TRISTATE_IOS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_TRISTATE_IOS_INIT_ENUM                     TRISTATE
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_TRISTATE_IOS_ENABLE_PINS                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_TRISTATE_IOS_TRISTATE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST6_0_DRIVE_PWM_OUT_LO_SHIFT                     _MK_SHIFT_CONST(23)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_DRIVE_PWM_OUT_LO_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_DRIVE_PWM_OUT_LO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_DRIVE_PWM_OUT_LO_RANGE                     23:23
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_DRIVE_PWM_OUT_LO_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_DRIVE_PWM_OUT_LO_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_DRIVE_PWM_OUT_LO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_DRIVE_PWM_OUT_LO_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_DRIVE_PWM_OUT_LO_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_DRIVE_PWM_OUT_LO_INIT_ENUM                 FALSE
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_DRIVE_PWM_OUT_LO_FALSE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_DRIVE_PWM_OUT_LO_TRUE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_B_SHIFT                        _MK_SHIFT_CONST(22)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_B_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_B_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_B_RANGE                        22:22
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_B_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_B_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_B_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_B_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_B_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_B_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_B_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_A_SHIFT                        _MK_SHIFT_CONST(21)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_A_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_A_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_A_RANGE                        21:21
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_A_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_A_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_A_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_A_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_A_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_A_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_A_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_A_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_A_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_A_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SEQUENCE_SHIFT                     _MK_SHIFT_CONST(19)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SEQUENCE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_SEQUENCE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SEQUENCE_RANGE                     19:19
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SEQUENCE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SEQUENCE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SEQUENCE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SEQUENCE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SEQUENCE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SEQUENCE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SEQUENCE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SEQUENCE_INIT_ENUM                 UP
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SEQUENCE_UP                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SEQUENCE_DOWN                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST6_0_LANE_SEQ_SHIFT                     _MK_SHIFT_CONST(18)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_LANE_SEQ_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_LANE_SEQ_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_LANE_SEQ_RANGE                     18:18
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_LANE_SEQ_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_LANE_SEQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_LANE_SEQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_LANE_SEQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_LANE_SEQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_LANE_SEQ_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_LANE_SEQ_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_LANE_SEQ_INIT_ENUM                 STOP
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_LANE_SEQ_STOP                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_LANE_SEQ_RUN                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPORT_SHIFT                       _MK_SHIFT_CONST(17)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPORT_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPORT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPORT_RANGE                       17:17
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPORT_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPORT_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPORT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPORT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPORT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPORT_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPORT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPORT_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPORT_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPORT_YES                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPLL_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPLL_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPLL_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPLL_RANGE                        16:16
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPLL_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPLL_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPLL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPLL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPLL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPLL_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPLL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPLL_INIT_ENUM                    NO
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPLL_NO                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPLL_YES                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST6_0_HALT_SHIFT                 _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_HALT_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_HALT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_HALT_RANGE                 15:15
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_HALT_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_HALT_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_HALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_HALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_HALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_HALT_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_HALT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_HALT_INIT_ENUM                     TRUE
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_HALT_FALSE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_HALT_TRUE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_SHIFT                   _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_FIELD                   _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_RANGE                   13:12
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_INIT_ENUM                       US
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_US                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_MS                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_VSYNC                   _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_TIME_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_TIME_FIELD                    _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_TIME_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_TIME_RANGE                    9:0
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_TIME_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_TIME_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_TIME_DEFAULT_MASK                     _MK_MASK_CONST(0x3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_TIME_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_TIME_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_TIME_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_TIME_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_SEQ_INST7_0
#define SOR_NV_PDISP_SOR_SEQ_INST7_0                    _MK_ADDR_CONST(0x29)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SCR                        0
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_RESET_VAL                  _MK_MASK_CONST(0x1008000)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_RESET_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_READ_MASK                  _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WRITE_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PLL_PULLDOWN_SHIFT                 _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PLL_PULLDOWN_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_PLL_PULLDOWN_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PLL_PULLDOWN_RANGE                 31:31
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PLL_PULLDOWN_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PLL_PULLDOWN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PLL_PULLDOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PLL_PULLDOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PLL_PULLDOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PLL_PULLDOWN_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PLL_PULLDOWN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PLL_PULLDOWN_INIT_ENUM                     DISABLE
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PLL_PULLDOWN_DISABLE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PLL_PULLDOWN_ENABLE                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST7_0_POWERDOWN_MACRO_SHIFT                      _MK_SHIFT_CONST(30)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_POWERDOWN_MACRO_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_POWERDOWN_MACRO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_POWERDOWN_MACRO_RANGE                      30:30
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_POWERDOWN_MACRO_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_POWERDOWN_MACRO_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_POWERDOWN_MACRO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_POWERDOWN_MACRO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_POWERDOWN_MACRO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_POWERDOWN_MACRO_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_POWERDOWN_MACRO_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_POWERDOWN_MACRO_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_POWERDOWN_MACRO_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_POWERDOWN_MACRO_POWERDOWN                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST7_0_ASSERT_PLL_RESET_SHIFT                     _MK_SHIFT_CONST(29)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_ASSERT_PLL_RESET_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_ASSERT_PLL_RESET_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_ASSERT_PLL_RESET_RANGE                     29:29
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_ASSERT_PLL_RESET_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_ASSERT_PLL_RESET_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_ASSERT_PLL_RESET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_ASSERT_PLL_RESET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_ASSERT_PLL_RESET_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_ASSERT_PLL_RESET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_ASSERT_PLL_RESET_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_ASSERT_PLL_RESET_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_ASSERT_PLL_RESET_RST                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_V_SHIFT                      _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_V_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_V_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_V_RANGE                      28:28
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_V_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_V_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_V_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_V_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_V_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_V_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_V_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_V_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_V_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_V_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_H_SHIFT                      _MK_SHIFT_CONST(27)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_H_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_H_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_H_RANGE                      27:27
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_H_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_H_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_H_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_H_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_H_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_H_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_H_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_H_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_H_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_H_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_DE_SHIFT                     _MK_SHIFT_CONST(26)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_DE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_DE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_DE_RANGE                     26:26
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_DE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_DE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_DE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_DE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_DE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_DE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_DE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_DE_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_DE_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_DE_INACTIVE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLACK_DATA_SHIFT                   _MK_SHIFT_CONST(25)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLACK_DATA_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_BLACK_DATA_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLACK_DATA_RANGE                   25:25
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLACK_DATA_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLACK_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLACK_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLACK_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLACK_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLACK_DATA_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLACK_DATA_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLACK_DATA_INIT_ENUM                       NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLACK_DATA_NORMAL                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLACK_DATA_BLACK                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST7_0_TRISTATE_IOS_SHIFT                 _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_TRISTATE_IOS_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_TRISTATE_IOS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_TRISTATE_IOS_RANGE                 24:24
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_TRISTATE_IOS_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_TRISTATE_IOS_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_TRISTATE_IOS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_TRISTATE_IOS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_TRISTATE_IOS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_TRISTATE_IOS_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_TRISTATE_IOS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_TRISTATE_IOS_INIT_ENUM                     TRISTATE
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_TRISTATE_IOS_ENABLE_PINS                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_TRISTATE_IOS_TRISTATE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST7_0_DRIVE_PWM_OUT_LO_SHIFT                     _MK_SHIFT_CONST(23)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_DRIVE_PWM_OUT_LO_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_DRIVE_PWM_OUT_LO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_DRIVE_PWM_OUT_LO_RANGE                     23:23
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_DRIVE_PWM_OUT_LO_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_DRIVE_PWM_OUT_LO_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_DRIVE_PWM_OUT_LO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_DRIVE_PWM_OUT_LO_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_DRIVE_PWM_OUT_LO_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_DRIVE_PWM_OUT_LO_INIT_ENUM                 FALSE
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_DRIVE_PWM_OUT_LO_FALSE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_DRIVE_PWM_OUT_LO_TRUE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_B_SHIFT                        _MK_SHIFT_CONST(22)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_B_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_B_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_B_RANGE                        22:22
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_B_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_B_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_B_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_B_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_B_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_B_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_B_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_A_SHIFT                        _MK_SHIFT_CONST(21)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_A_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_A_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_A_RANGE                        21:21
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_A_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_A_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_A_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_A_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_A_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_A_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_A_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_A_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_A_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_A_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SEQUENCE_SHIFT                     _MK_SHIFT_CONST(19)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SEQUENCE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_SEQUENCE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SEQUENCE_RANGE                     19:19
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SEQUENCE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SEQUENCE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SEQUENCE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SEQUENCE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SEQUENCE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SEQUENCE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SEQUENCE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SEQUENCE_INIT_ENUM                 UP
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SEQUENCE_UP                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SEQUENCE_DOWN                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST7_0_LANE_SEQ_SHIFT                     _MK_SHIFT_CONST(18)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_LANE_SEQ_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_LANE_SEQ_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_LANE_SEQ_RANGE                     18:18
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_LANE_SEQ_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_LANE_SEQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_LANE_SEQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_LANE_SEQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_LANE_SEQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_LANE_SEQ_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_LANE_SEQ_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_LANE_SEQ_INIT_ENUM                 STOP
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_LANE_SEQ_STOP                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_LANE_SEQ_RUN                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPORT_SHIFT                       _MK_SHIFT_CONST(17)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPORT_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPORT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPORT_RANGE                       17:17
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPORT_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPORT_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPORT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPORT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPORT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPORT_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPORT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPORT_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPORT_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPORT_YES                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPLL_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPLL_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPLL_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPLL_RANGE                        16:16
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPLL_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPLL_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPLL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPLL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPLL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPLL_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPLL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPLL_INIT_ENUM                    NO
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPLL_NO                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPLL_YES                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST7_0_HALT_SHIFT                 _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_HALT_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_HALT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_HALT_RANGE                 15:15
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_HALT_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_HALT_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_HALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_HALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_HALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_HALT_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_HALT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_HALT_INIT_ENUM                     TRUE
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_HALT_FALSE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_HALT_TRUE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_SHIFT                   _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_FIELD                   _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_RANGE                   13:12
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_INIT_ENUM                       US
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_US                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_MS                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_VSYNC                   _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_TIME_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_TIME_FIELD                    _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_TIME_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_TIME_RANGE                    9:0
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_TIME_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_TIME_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_TIME_DEFAULT_MASK                     _MK_MASK_CONST(0x3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_TIME_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_TIME_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_TIME_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_TIME_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_SEQ_INST8_0
#define SOR_NV_PDISP_SOR_SEQ_INST8_0                    _MK_ADDR_CONST(0x2a)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SCR                        0
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_RESET_VAL                  _MK_MASK_CONST(0x1008000)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_RESET_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_READ_MASK                  _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WRITE_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PLL_PULLDOWN_SHIFT                 _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PLL_PULLDOWN_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_PLL_PULLDOWN_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PLL_PULLDOWN_RANGE                 31:31
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PLL_PULLDOWN_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PLL_PULLDOWN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PLL_PULLDOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PLL_PULLDOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PLL_PULLDOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PLL_PULLDOWN_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PLL_PULLDOWN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PLL_PULLDOWN_INIT_ENUM                     DISABLE
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PLL_PULLDOWN_DISABLE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PLL_PULLDOWN_ENABLE                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST8_0_POWERDOWN_MACRO_SHIFT                      _MK_SHIFT_CONST(30)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_POWERDOWN_MACRO_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_POWERDOWN_MACRO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_POWERDOWN_MACRO_RANGE                      30:30
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_POWERDOWN_MACRO_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_POWERDOWN_MACRO_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_POWERDOWN_MACRO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_POWERDOWN_MACRO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_POWERDOWN_MACRO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_POWERDOWN_MACRO_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_POWERDOWN_MACRO_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_POWERDOWN_MACRO_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_POWERDOWN_MACRO_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_POWERDOWN_MACRO_POWERDOWN                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST8_0_ASSERT_PLL_RESET_SHIFT                     _MK_SHIFT_CONST(29)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_ASSERT_PLL_RESET_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_ASSERT_PLL_RESET_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_ASSERT_PLL_RESET_RANGE                     29:29
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_ASSERT_PLL_RESET_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_ASSERT_PLL_RESET_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_ASSERT_PLL_RESET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_ASSERT_PLL_RESET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_ASSERT_PLL_RESET_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_ASSERT_PLL_RESET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_ASSERT_PLL_RESET_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_ASSERT_PLL_RESET_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_ASSERT_PLL_RESET_RST                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_V_SHIFT                      _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_V_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_V_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_V_RANGE                      28:28
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_V_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_V_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_V_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_V_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_V_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_V_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_V_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_V_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_V_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_V_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_H_SHIFT                      _MK_SHIFT_CONST(27)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_H_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_H_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_H_RANGE                      27:27
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_H_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_H_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_H_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_H_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_H_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_H_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_H_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_H_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_H_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_H_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_DE_SHIFT                     _MK_SHIFT_CONST(26)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_DE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_DE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_DE_RANGE                     26:26
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_DE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_DE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_DE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_DE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_DE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_DE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_DE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_DE_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_DE_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_DE_INACTIVE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLACK_DATA_SHIFT                   _MK_SHIFT_CONST(25)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLACK_DATA_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_BLACK_DATA_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLACK_DATA_RANGE                   25:25
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLACK_DATA_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLACK_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLACK_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLACK_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLACK_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLACK_DATA_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLACK_DATA_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLACK_DATA_INIT_ENUM                       NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLACK_DATA_NORMAL                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLACK_DATA_BLACK                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST8_0_TRISTATE_IOS_SHIFT                 _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_TRISTATE_IOS_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_TRISTATE_IOS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_TRISTATE_IOS_RANGE                 24:24
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_TRISTATE_IOS_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_TRISTATE_IOS_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_TRISTATE_IOS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_TRISTATE_IOS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_TRISTATE_IOS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_TRISTATE_IOS_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_TRISTATE_IOS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_TRISTATE_IOS_INIT_ENUM                     TRISTATE
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_TRISTATE_IOS_ENABLE_PINS                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_TRISTATE_IOS_TRISTATE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST8_0_DRIVE_PWM_OUT_LO_SHIFT                     _MK_SHIFT_CONST(23)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_DRIVE_PWM_OUT_LO_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_DRIVE_PWM_OUT_LO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_DRIVE_PWM_OUT_LO_RANGE                     23:23
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_DRIVE_PWM_OUT_LO_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_DRIVE_PWM_OUT_LO_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_DRIVE_PWM_OUT_LO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_DRIVE_PWM_OUT_LO_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_DRIVE_PWM_OUT_LO_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_DRIVE_PWM_OUT_LO_INIT_ENUM                 FALSE
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_DRIVE_PWM_OUT_LO_FALSE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_DRIVE_PWM_OUT_LO_TRUE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_B_SHIFT                        _MK_SHIFT_CONST(22)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_B_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_B_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_B_RANGE                        22:22
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_B_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_B_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_B_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_B_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_B_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_B_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_B_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_A_SHIFT                        _MK_SHIFT_CONST(21)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_A_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_A_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_A_RANGE                        21:21
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_A_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_A_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_A_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_A_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_A_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_A_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_A_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_A_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_A_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_A_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SEQUENCE_SHIFT                     _MK_SHIFT_CONST(19)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SEQUENCE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_SEQUENCE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SEQUENCE_RANGE                     19:19
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SEQUENCE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SEQUENCE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SEQUENCE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SEQUENCE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SEQUENCE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SEQUENCE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SEQUENCE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SEQUENCE_INIT_ENUM                 UP
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SEQUENCE_UP                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SEQUENCE_DOWN                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST8_0_LANE_SEQ_SHIFT                     _MK_SHIFT_CONST(18)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_LANE_SEQ_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_LANE_SEQ_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_LANE_SEQ_RANGE                     18:18
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_LANE_SEQ_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_LANE_SEQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_LANE_SEQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_LANE_SEQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_LANE_SEQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_LANE_SEQ_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_LANE_SEQ_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_LANE_SEQ_INIT_ENUM                 STOP
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_LANE_SEQ_STOP                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_LANE_SEQ_RUN                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPORT_SHIFT                       _MK_SHIFT_CONST(17)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPORT_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPORT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPORT_RANGE                       17:17
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPORT_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPORT_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPORT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPORT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPORT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPORT_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPORT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPORT_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPORT_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPORT_YES                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPLL_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPLL_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPLL_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPLL_RANGE                        16:16
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPLL_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPLL_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPLL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPLL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPLL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPLL_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPLL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPLL_INIT_ENUM                    NO
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPLL_NO                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPLL_YES                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST8_0_HALT_SHIFT                 _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_HALT_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_HALT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_HALT_RANGE                 15:15
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_HALT_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_HALT_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_HALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_HALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_HALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_HALT_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_HALT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_HALT_INIT_ENUM                     TRUE
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_HALT_FALSE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_HALT_TRUE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_SHIFT                   _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_FIELD                   _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_RANGE                   13:12
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_INIT_ENUM                       US
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_US                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_MS                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_VSYNC                   _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_TIME_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_TIME_FIELD                    _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_TIME_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_TIME_RANGE                    9:0
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_TIME_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_TIME_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_TIME_DEFAULT_MASK                     _MK_MASK_CONST(0x3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_TIME_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_TIME_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_TIME_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_TIME_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_SEQ_INST9_0
#define SOR_NV_PDISP_SOR_SEQ_INST9_0                    _MK_ADDR_CONST(0x2b)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SCR                        0
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_RESET_VAL                  _MK_MASK_CONST(0x1008000)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_RESET_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_READ_MASK                  _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WRITE_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PLL_PULLDOWN_SHIFT                 _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PLL_PULLDOWN_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_PLL_PULLDOWN_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PLL_PULLDOWN_RANGE                 31:31
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PLL_PULLDOWN_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PLL_PULLDOWN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PLL_PULLDOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PLL_PULLDOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PLL_PULLDOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PLL_PULLDOWN_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PLL_PULLDOWN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PLL_PULLDOWN_INIT_ENUM                     DISABLE
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PLL_PULLDOWN_DISABLE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PLL_PULLDOWN_ENABLE                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST9_0_POWERDOWN_MACRO_SHIFT                      _MK_SHIFT_CONST(30)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_POWERDOWN_MACRO_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_POWERDOWN_MACRO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_POWERDOWN_MACRO_RANGE                      30:30
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_POWERDOWN_MACRO_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_POWERDOWN_MACRO_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_POWERDOWN_MACRO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_POWERDOWN_MACRO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_POWERDOWN_MACRO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_POWERDOWN_MACRO_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_POWERDOWN_MACRO_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_POWERDOWN_MACRO_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_POWERDOWN_MACRO_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_POWERDOWN_MACRO_POWERDOWN                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST9_0_ASSERT_PLL_RESET_SHIFT                     _MK_SHIFT_CONST(29)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_ASSERT_PLL_RESET_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_ASSERT_PLL_RESET_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_ASSERT_PLL_RESET_RANGE                     29:29
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_ASSERT_PLL_RESET_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_ASSERT_PLL_RESET_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_ASSERT_PLL_RESET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_ASSERT_PLL_RESET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_ASSERT_PLL_RESET_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_ASSERT_PLL_RESET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_ASSERT_PLL_RESET_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_ASSERT_PLL_RESET_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_ASSERT_PLL_RESET_RST                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_V_SHIFT                      _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_V_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_V_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_V_RANGE                      28:28
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_V_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_V_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_V_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_V_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_V_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_V_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_V_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_V_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_V_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_V_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_H_SHIFT                      _MK_SHIFT_CONST(27)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_H_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_H_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_H_RANGE                      27:27
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_H_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_H_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_H_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_H_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_H_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_H_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_H_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_H_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_H_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_H_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_DE_SHIFT                     _MK_SHIFT_CONST(26)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_DE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_DE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_DE_RANGE                     26:26
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_DE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_DE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_DE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_DE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_DE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_DE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_DE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_DE_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_DE_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_DE_INACTIVE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLACK_DATA_SHIFT                   _MK_SHIFT_CONST(25)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLACK_DATA_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_BLACK_DATA_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLACK_DATA_RANGE                   25:25
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLACK_DATA_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLACK_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLACK_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLACK_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLACK_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLACK_DATA_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLACK_DATA_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLACK_DATA_INIT_ENUM                       NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLACK_DATA_NORMAL                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLACK_DATA_BLACK                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST9_0_TRISTATE_IOS_SHIFT                 _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_TRISTATE_IOS_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_TRISTATE_IOS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_TRISTATE_IOS_RANGE                 24:24
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_TRISTATE_IOS_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_TRISTATE_IOS_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_TRISTATE_IOS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_TRISTATE_IOS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_TRISTATE_IOS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_TRISTATE_IOS_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_TRISTATE_IOS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_TRISTATE_IOS_INIT_ENUM                     TRISTATE
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_TRISTATE_IOS_ENABLE_PINS                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_TRISTATE_IOS_TRISTATE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST9_0_DRIVE_PWM_OUT_LO_SHIFT                     _MK_SHIFT_CONST(23)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_DRIVE_PWM_OUT_LO_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_DRIVE_PWM_OUT_LO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_DRIVE_PWM_OUT_LO_RANGE                     23:23
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_DRIVE_PWM_OUT_LO_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_DRIVE_PWM_OUT_LO_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_DRIVE_PWM_OUT_LO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_DRIVE_PWM_OUT_LO_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_DRIVE_PWM_OUT_LO_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_DRIVE_PWM_OUT_LO_INIT_ENUM                 FALSE
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_DRIVE_PWM_OUT_LO_FALSE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_DRIVE_PWM_OUT_LO_TRUE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_B_SHIFT                        _MK_SHIFT_CONST(22)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_B_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_B_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_B_RANGE                        22:22
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_B_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_B_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_B_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_B_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_B_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_B_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_B_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_A_SHIFT                        _MK_SHIFT_CONST(21)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_A_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_A_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_A_RANGE                        21:21
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_A_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_A_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_A_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_A_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_A_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_A_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_A_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_A_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_A_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_A_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SEQUENCE_SHIFT                     _MK_SHIFT_CONST(19)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SEQUENCE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_SEQUENCE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SEQUENCE_RANGE                     19:19
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SEQUENCE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SEQUENCE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SEQUENCE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SEQUENCE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SEQUENCE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SEQUENCE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SEQUENCE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SEQUENCE_INIT_ENUM                 UP
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SEQUENCE_UP                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SEQUENCE_DOWN                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST9_0_LANE_SEQ_SHIFT                     _MK_SHIFT_CONST(18)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_LANE_SEQ_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_LANE_SEQ_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_LANE_SEQ_RANGE                     18:18
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_LANE_SEQ_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_LANE_SEQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_LANE_SEQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_LANE_SEQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_LANE_SEQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_LANE_SEQ_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_LANE_SEQ_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_LANE_SEQ_INIT_ENUM                 STOP
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_LANE_SEQ_STOP                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_LANE_SEQ_RUN                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPORT_SHIFT                       _MK_SHIFT_CONST(17)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPORT_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPORT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPORT_RANGE                       17:17
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPORT_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPORT_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPORT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPORT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPORT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPORT_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPORT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPORT_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPORT_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPORT_YES                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPLL_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPLL_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPLL_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPLL_RANGE                        16:16
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPLL_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPLL_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPLL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPLL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPLL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPLL_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPLL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPLL_INIT_ENUM                    NO
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPLL_NO                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPLL_YES                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST9_0_HALT_SHIFT                 _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_HALT_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_HALT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_HALT_RANGE                 15:15
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_HALT_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_HALT_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_HALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_HALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_HALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_HALT_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_HALT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_HALT_INIT_ENUM                     TRUE
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_HALT_FALSE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_HALT_TRUE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_SHIFT                   _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_FIELD                   _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_RANGE                   13:12
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_INIT_ENUM                       US
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_US                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_MS                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_VSYNC                   _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_TIME_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_TIME_FIELD                    _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_TIME_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_TIME_RANGE                    9:0
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_TIME_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_TIME_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_TIME_DEFAULT_MASK                     _MK_MASK_CONST(0x3ff)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_TIME_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_TIME_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_TIME_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_TIME_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_SEQ_INSTA_0
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0                    _MK_ADDR_CONST(0x2c)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SCR                        0
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_RESET_VAL                  _MK_MASK_CONST(0x1008000)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_RESET_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_READ_MASK                  _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WRITE_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PLL_PULLDOWN_SHIFT                 _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PLL_PULLDOWN_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_PLL_PULLDOWN_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PLL_PULLDOWN_RANGE                 31:31
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PLL_PULLDOWN_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PLL_PULLDOWN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PLL_PULLDOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PLL_PULLDOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PLL_PULLDOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PLL_PULLDOWN_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PLL_PULLDOWN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PLL_PULLDOWN_INIT_ENUM                     DISABLE
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PLL_PULLDOWN_DISABLE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PLL_PULLDOWN_ENABLE                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_POWERDOWN_MACRO_SHIFT                      _MK_SHIFT_CONST(30)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_POWERDOWN_MACRO_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_POWERDOWN_MACRO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_POWERDOWN_MACRO_RANGE                      30:30
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_POWERDOWN_MACRO_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_POWERDOWN_MACRO_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_POWERDOWN_MACRO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_POWERDOWN_MACRO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_POWERDOWN_MACRO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_POWERDOWN_MACRO_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_POWERDOWN_MACRO_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_POWERDOWN_MACRO_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_POWERDOWN_MACRO_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_POWERDOWN_MACRO_POWERDOWN                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_ASSERT_PLL_RESET_SHIFT                     _MK_SHIFT_CONST(29)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_ASSERT_PLL_RESET_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_ASSERT_PLL_RESET_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_ASSERT_PLL_RESET_RANGE                     29:29
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_ASSERT_PLL_RESET_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_ASSERT_PLL_RESET_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_ASSERT_PLL_RESET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_ASSERT_PLL_RESET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_ASSERT_PLL_RESET_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_ASSERT_PLL_RESET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_ASSERT_PLL_RESET_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_ASSERT_PLL_RESET_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_ASSERT_PLL_RESET_RST                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_V_SHIFT                      _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_V_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_V_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_V_RANGE                      28:28
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_V_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_V_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_V_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_V_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_V_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_V_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_V_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_V_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_V_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_V_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_H_SHIFT                      _MK_SHIFT_CONST(27)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_H_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_H_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_H_RANGE                      27:27
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_H_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_H_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_H_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_H_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_H_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_H_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_H_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_H_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_H_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_H_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_DE_SHIFT                     _MK_SHIFT_CONST(26)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_DE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_DE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_DE_RANGE                     26:26
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_DE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_DE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_DE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_DE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_DE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_DE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_DE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_DE_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_DE_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_DE_INACTIVE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLACK_DATA_SHIFT                   _MK_SHIFT_CONST(25)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLACK_DATA_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLACK_DATA_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLACK_DATA_RANGE                   25:25
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLACK_DATA_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLACK_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLACK_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLACK_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLACK_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLACK_DATA_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLACK_DATA_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLACK_DATA_INIT_ENUM                       NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLACK_DATA_NORMAL                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLACK_DATA_BLACK                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_TRISTATE_IOS_SHIFT                 _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_TRISTATE_IOS_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_TRISTATE_IOS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_TRISTATE_IOS_RANGE                 24:24
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_TRISTATE_IOS_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_TRISTATE_IOS_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_TRISTATE_IOS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_TRISTATE_IOS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_TRISTATE_IOS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_TRISTATE_IOS_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_TRISTATE_IOS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_TRISTATE_IOS_INIT_ENUM                     TRISTATE
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_TRISTATE_IOS_ENABLE_PINS                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_TRISTATE_IOS_TRISTATE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_DRIVE_PWM_OUT_LO_SHIFT                     _MK_SHIFT_CONST(23)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_DRIVE_PWM_OUT_LO_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_DRIVE_PWM_OUT_LO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_DRIVE_PWM_OUT_LO_RANGE                     23:23
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_DRIVE_PWM_OUT_LO_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_DRIVE_PWM_OUT_LO_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_DRIVE_PWM_OUT_LO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_DRIVE_PWM_OUT_LO_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_DRIVE_PWM_OUT_LO_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_DRIVE_PWM_OUT_LO_INIT_ENUM                 FALSE
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_DRIVE_PWM_OUT_LO_FALSE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_DRIVE_PWM_OUT_LO_TRUE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_B_SHIFT                        _MK_SHIFT_CONST(22)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_B_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_B_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_B_RANGE                        22:22
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_B_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_B_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_B_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_B_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_B_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_B_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_B_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_A_SHIFT                        _MK_SHIFT_CONST(21)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_A_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_A_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_A_RANGE                        21:21
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_A_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_A_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_A_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_A_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_A_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_A_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_A_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_A_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_A_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_A_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SEQUENCE_SHIFT                     _MK_SHIFT_CONST(19)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SEQUENCE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_SEQUENCE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SEQUENCE_RANGE                     19:19
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SEQUENCE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SEQUENCE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SEQUENCE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SEQUENCE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SEQUENCE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SEQUENCE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SEQUENCE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SEQUENCE_INIT_ENUM                 UP
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SEQUENCE_UP                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SEQUENCE_DOWN                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_LANE_SEQ_SHIFT                     _MK_SHIFT_CONST(18)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_LANE_SEQ_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_LANE_SEQ_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_LANE_SEQ_RANGE                     18:18
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_LANE_SEQ_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_LANE_SEQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_LANE_SEQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_LANE_SEQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_LANE_SEQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_LANE_SEQ_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_LANE_SEQ_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_LANE_SEQ_INIT_ENUM                 STOP
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_LANE_SEQ_STOP                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_LANE_SEQ_RUN                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPORT_SHIFT                       _MK_SHIFT_CONST(17)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPORT_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPORT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPORT_RANGE                       17:17
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPORT_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPORT_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPORT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPORT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPORT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPORT_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPORT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPORT_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPORT_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPORT_YES                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPLL_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPLL_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPLL_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPLL_RANGE                        16:16
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPLL_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPLL_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPLL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPLL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPLL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPLL_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPLL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPLL_INIT_ENUM                    NO
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPLL_NO                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPLL_YES                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_HALT_SHIFT                 _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_HALT_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_HALT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_HALT_RANGE                 15:15
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_HALT_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_HALT_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_HALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_HALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_HALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_HALT_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_HALT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_HALT_INIT_ENUM                     TRUE
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_HALT_FALSE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_HALT_TRUE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_SHIFT                   _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_FIELD                   _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_RANGE                   13:12
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_INIT_ENUM                       US
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_US                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_MS                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_VSYNC                   _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_TIME_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_TIME_FIELD                    _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_TIME_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_TIME_RANGE                    9:0
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_TIME_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_TIME_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_TIME_DEFAULT_MASK                     _MK_MASK_CONST(0x3ff)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_TIME_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_TIME_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_TIME_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_TIME_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_SEQ_INSTB_0
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0                    _MK_ADDR_CONST(0x2d)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SCR                        0
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_RESET_VAL                  _MK_MASK_CONST(0x1008000)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_RESET_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_READ_MASK                  _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WRITE_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PLL_PULLDOWN_SHIFT                 _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PLL_PULLDOWN_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_PLL_PULLDOWN_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PLL_PULLDOWN_RANGE                 31:31
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PLL_PULLDOWN_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PLL_PULLDOWN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PLL_PULLDOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PLL_PULLDOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PLL_PULLDOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PLL_PULLDOWN_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PLL_PULLDOWN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PLL_PULLDOWN_INIT_ENUM                     DISABLE
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PLL_PULLDOWN_DISABLE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PLL_PULLDOWN_ENABLE                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_POWERDOWN_MACRO_SHIFT                      _MK_SHIFT_CONST(30)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_POWERDOWN_MACRO_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_POWERDOWN_MACRO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_POWERDOWN_MACRO_RANGE                      30:30
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_POWERDOWN_MACRO_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_POWERDOWN_MACRO_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_POWERDOWN_MACRO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_POWERDOWN_MACRO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_POWERDOWN_MACRO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_POWERDOWN_MACRO_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_POWERDOWN_MACRO_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_POWERDOWN_MACRO_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_POWERDOWN_MACRO_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_POWERDOWN_MACRO_POWERDOWN                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_ASSERT_PLL_RESET_SHIFT                     _MK_SHIFT_CONST(29)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_ASSERT_PLL_RESET_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_ASSERT_PLL_RESET_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_ASSERT_PLL_RESET_RANGE                     29:29
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_ASSERT_PLL_RESET_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_ASSERT_PLL_RESET_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_ASSERT_PLL_RESET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_ASSERT_PLL_RESET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_ASSERT_PLL_RESET_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_ASSERT_PLL_RESET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_ASSERT_PLL_RESET_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_ASSERT_PLL_RESET_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_ASSERT_PLL_RESET_RST                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_V_SHIFT                      _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_V_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_V_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_V_RANGE                      28:28
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_V_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_V_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_V_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_V_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_V_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_V_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_V_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_V_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_V_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_V_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_H_SHIFT                      _MK_SHIFT_CONST(27)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_H_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_H_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_H_RANGE                      27:27
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_H_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_H_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_H_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_H_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_H_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_H_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_H_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_H_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_H_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_H_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_DE_SHIFT                     _MK_SHIFT_CONST(26)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_DE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_DE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_DE_RANGE                     26:26
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_DE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_DE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_DE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_DE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_DE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_DE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_DE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_DE_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_DE_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_DE_INACTIVE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLACK_DATA_SHIFT                   _MK_SHIFT_CONST(25)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLACK_DATA_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLACK_DATA_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLACK_DATA_RANGE                   25:25
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLACK_DATA_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLACK_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLACK_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLACK_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLACK_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLACK_DATA_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLACK_DATA_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLACK_DATA_INIT_ENUM                       NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLACK_DATA_NORMAL                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLACK_DATA_BLACK                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_TRISTATE_IOS_SHIFT                 _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_TRISTATE_IOS_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_TRISTATE_IOS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_TRISTATE_IOS_RANGE                 24:24
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_TRISTATE_IOS_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_TRISTATE_IOS_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_TRISTATE_IOS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_TRISTATE_IOS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_TRISTATE_IOS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_TRISTATE_IOS_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_TRISTATE_IOS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_TRISTATE_IOS_INIT_ENUM                     TRISTATE
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_TRISTATE_IOS_ENABLE_PINS                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_TRISTATE_IOS_TRISTATE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_DRIVE_PWM_OUT_LO_SHIFT                     _MK_SHIFT_CONST(23)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_DRIVE_PWM_OUT_LO_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_DRIVE_PWM_OUT_LO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_DRIVE_PWM_OUT_LO_RANGE                     23:23
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_DRIVE_PWM_OUT_LO_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_DRIVE_PWM_OUT_LO_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_DRIVE_PWM_OUT_LO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_DRIVE_PWM_OUT_LO_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_DRIVE_PWM_OUT_LO_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_DRIVE_PWM_OUT_LO_INIT_ENUM                 FALSE
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_DRIVE_PWM_OUT_LO_FALSE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_DRIVE_PWM_OUT_LO_TRUE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_B_SHIFT                        _MK_SHIFT_CONST(22)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_B_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_B_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_B_RANGE                        22:22
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_B_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_B_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_B_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_B_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_B_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_B_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_B_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_A_SHIFT                        _MK_SHIFT_CONST(21)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_A_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_A_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_A_RANGE                        21:21
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_A_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_A_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_A_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_A_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_A_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_A_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_A_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_A_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_A_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_A_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SEQUENCE_SHIFT                     _MK_SHIFT_CONST(19)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SEQUENCE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_SEQUENCE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SEQUENCE_RANGE                     19:19
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SEQUENCE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SEQUENCE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SEQUENCE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SEQUENCE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SEQUENCE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SEQUENCE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SEQUENCE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SEQUENCE_INIT_ENUM                 UP
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SEQUENCE_UP                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SEQUENCE_DOWN                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_LANE_SEQ_SHIFT                     _MK_SHIFT_CONST(18)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_LANE_SEQ_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_LANE_SEQ_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_LANE_SEQ_RANGE                     18:18
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_LANE_SEQ_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_LANE_SEQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_LANE_SEQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_LANE_SEQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_LANE_SEQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_LANE_SEQ_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_LANE_SEQ_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_LANE_SEQ_INIT_ENUM                 STOP
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_LANE_SEQ_STOP                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_LANE_SEQ_RUN                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPORT_SHIFT                       _MK_SHIFT_CONST(17)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPORT_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPORT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPORT_RANGE                       17:17
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPORT_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPORT_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPORT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPORT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPORT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPORT_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPORT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPORT_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPORT_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPORT_YES                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPLL_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPLL_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPLL_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPLL_RANGE                        16:16
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPLL_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPLL_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPLL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPLL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPLL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPLL_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPLL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPLL_INIT_ENUM                    NO
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPLL_NO                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPLL_YES                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_HALT_SHIFT                 _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_HALT_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_HALT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_HALT_RANGE                 15:15
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_HALT_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_HALT_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_HALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_HALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_HALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_HALT_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_HALT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_HALT_INIT_ENUM                     TRUE
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_HALT_FALSE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_HALT_TRUE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_SHIFT                   _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_FIELD                   _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_RANGE                   13:12
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_INIT_ENUM                       US
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_US                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_MS                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_VSYNC                   _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_TIME_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_TIME_FIELD                    _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_TIME_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_TIME_RANGE                    9:0
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_TIME_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_TIME_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_TIME_DEFAULT_MASK                     _MK_MASK_CONST(0x3ff)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_TIME_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_TIME_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_TIME_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_TIME_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_SEQ_INSTC_0
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0                    _MK_ADDR_CONST(0x2e)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SCR                        0
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_RESET_VAL                  _MK_MASK_CONST(0x1008000)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_RESET_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_READ_MASK                  _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WRITE_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PLL_PULLDOWN_SHIFT                 _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PLL_PULLDOWN_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_PLL_PULLDOWN_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PLL_PULLDOWN_RANGE                 31:31
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PLL_PULLDOWN_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PLL_PULLDOWN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PLL_PULLDOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PLL_PULLDOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PLL_PULLDOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PLL_PULLDOWN_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PLL_PULLDOWN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PLL_PULLDOWN_INIT_ENUM                     DISABLE
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PLL_PULLDOWN_DISABLE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PLL_PULLDOWN_ENABLE                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_POWERDOWN_MACRO_SHIFT                      _MK_SHIFT_CONST(30)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_POWERDOWN_MACRO_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_POWERDOWN_MACRO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_POWERDOWN_MACRO_RANGE                      30:30
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_POWERDOWN_MACRO_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_POWERDOWN_MACRO_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_POWERDOWN_MACRO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_POWERDOWN_MACRO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_POWERDOWN_MACRO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_POWERDOWN_MACRO_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_POWERDOWN_MACRO_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_POWERDOWN_MACRO_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_POWERDOWN_MACRO_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_POWERDOWN_MACRO_POWERDOWN                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_ASSERT_PLL_RESET_SHIFT                     _MK_SHIFT_CONST(29)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_ASSERT_PLL_RESET_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_ASSERT_PLL_RESET_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_ASSERT_PLL_RESET_RANGE                     29:29
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_ASSERT_PLL_RESET_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_ASSERT_PLL_RESET_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_ASSERT_PLL_RESET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_ASSERT_PLL_RESET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_ASSERT_PLL_RESET_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_ASSERT_PLL_RESET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_ASSERT_PLL_RESET_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_ASSERT_PLL_RESET_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_ASSERT_PLL_RESET_RST                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_V_SHIFT                      _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_V_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_V_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_V_RANGE                      28:28
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_V_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_V_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_V_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_V_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_V_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_V_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_V_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_V_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_V_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_V_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_H_SHIFT                      _MK_SHIFT_CONST(27)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_H_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_H_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_H_RANGE                      27:27
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_H_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_H_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_H_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_H_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_H_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_H_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_H_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_H_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_H_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_H_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_DE_SHIFT                     _MK_SHIFT_CONST(26)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_DE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_DE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_DE_RANGE                     26:26
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_DE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_DE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_DE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_DE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_DE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_DE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_DE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_DE_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_DE_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_DE_INACTIVE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLACK_DATA_SHIFT                   _MK_SHIFT_CONST(25)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLACK_DATA_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLACK_DATA_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLACK_DATA_RANGE                   25:25
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLACK_DATA_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLACK_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLACK_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLACK_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLACK_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLACK_DATA_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLACK_DATA_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLACK_DATA_INIT_ENUM                       NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLACK_DATA_NORMAL                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLACK_DATA_BLACK                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_TRISTATE_IOS_SHIFT                 _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_TRISTATE_IOS_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_TRISTATE_IOS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_TRISTATE_IOS_RANGE                 24:24
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_TRISTATE_IOS_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_TRISTATE_IOS_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_TRISTATE_IOS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_TRISTATE_IOS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_TRISTATE_IOS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_TRISTATE_IOS_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_TRISTATE_IOS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_TRISTATE_IOS_INIT_ENUM                     TRISTATE
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_TRISTATE_IOS_ENABLE_PINS                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_TRISTATE_IOS_TRISTATE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_DRIVE_PWM_OUT_LO_SHIFT                     _MK_SHIFT_CONST(23)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_DRIVE_PWM_OUT_LO_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_DRIVE_PWM_OUT_LO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_DRIVE_PWM_OUT_LO_RANGE                     23:23
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_DRIVE_PWM_OUT_LO_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_DRIVE_PWM_OUT_LO_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_DRIVE_PWM_OUT_LO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_DRIVE_PWM_OUT_LO_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_DRIVE_PWM_OUT_LO_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_DRIVE_PWM_OUT_LO_INIT_ENUM                 FALSE
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_DRIVE_PWM_OUT_LO_FALSE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_DRIVE_PWM_OUT_LO_TRUE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_B_SHIFT                        _MK_SHIFT_CONST(22)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_B_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_B_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_B_RANGE                        22:22
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_B_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_B_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_B_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_B_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_B_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_B_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_B_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_A_SHIFT                        _MK_SHIFT_CONST(21)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_A_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_A_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_A_RANGE                        21:21
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_A_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_A_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_A_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_A_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_A_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_A_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_A_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_A_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_A_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_A_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SEQUENCE_SHIFT                     _MK_SHIFT_CONST(19)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SEQUENCE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_SEQUENCE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SEQUENCE_RANGE                     19:19
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SEQUENCE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SEQUENCE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SEQUENCE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SEQUENCE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SEQUENCE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SEQUENCE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SEQUENCE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SEQUENCE_INIT_ENUM                 UP
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SEQUENCE_UP                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SEQUENCE_DOWN                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_LANE_SEQ_SHIFT                     _MK_SHIFT_CONST(18)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_LANE_SEQ_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_LANE_SEQ_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_LANE_SEQ_RANGE                     18:18
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_LANE_SEQ_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_LANE_SEQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_LANE_SEQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_LANE_SEQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_LANE_SEQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_LANE_SEQ_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_LANE_SEQ_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_LANE_SEQ_INIT_ENUM                 STOP
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_LANE_SEQ_STOP                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_LANE_SEQ_RUN                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPORT_SHIFT                       _MK_SHIFT_CONST(17)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPORT_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPORT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPORT_RANGE                       17:17
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPORT_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPORT_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPORT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPORT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPORT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPORT_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPORT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPORT_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPORT_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPORT_YES                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPLL_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPLL_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPLL_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPLL_RANGE                        16:16
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPLL_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPLL_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPLL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPLL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPLL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPLL_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPLL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPLL_INIT_ENUM                    NO
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPLL_NO                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPLL_YES                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_HALT_SHIFT                 _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_HALT_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_HALT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_HALT_RANGE                 15:15
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_HALT_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_HALT_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_HALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_HALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_HALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_HALT_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_HALT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_HALT_INIT_ENUM                     TRUE
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_HALT_FALSE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_HALT_TRUE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_SHIFT                   _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_FIELD                   _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_RANGE                   13:12
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_INIT_ENUM                       US
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_US                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_MS                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_VSYNC                   _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_TIME_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_TIME_FIELD                    _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_TIME_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_TIME_RANGE                    9:0
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_TIME_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_TIME_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_TIME_DEFAULT_MASK                     _MK_MASK_CONST(0x3ff)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_TIME_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_TIME_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_TIME_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_TIME_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_SEQ_INSTD_0
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0                    _MK_ADDR_CONST(0x2f)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SCR                        0
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_RESET_VAL                  _MK_MASK_CONST(0x1008000)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_RESET_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_READ_MASK                  _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WRITE_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PLL_PULLDOWN_SHIFT                 _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PLL_PULLDOWN_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_PLL_PULLDOWN_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PLL_PULLDOWN_RANGE                 31:31
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PLL_PULLDOWN_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PLL_PULLDOWN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PLL_PULLDOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PLL_PULLDOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PLL_PULLDOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PLL_PULLDOWN_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PLL_PULLDOWN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PLL_PULLDOWN_INIT_ENUM                     DISABLE
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PLL_PULLDOWN_DISABLE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PLL_PULLDOWN_ENABLE                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_POWERDOWN_MACRO_SHIFT                      _MK_SHIFT_CONST(30)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_POWERDOWN_MACRO_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_POWERDOWN_MACRO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_POWERDOWN_MACRO_RANGE                      30:30
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_POWERDOWN_MACRO_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_POWERDOWN_MACRO_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_POWERDOWN_MACRO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_POWERDOWN_MACRO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_POWERDOWN_MACRO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_POWERDOWN_MACRO_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_POWERDOWN_MACRO_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_POWERDOWN_MACRO_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_POWERDOWN_MACRO_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_POWERDOWN_MACRO_POWERDOWN                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_ASSERT_PLL_RESET_SHIFT                     _MK_SHIFT_CONST(29)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_ASSERT_PLL_RESET_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_ASSERT_PLL_RESET_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_ASSERT_PLL_RESET_RANGE                     29:29
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_ASSERT_PLL_RESET_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_ASSERT_PLL_RESET_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_ASSERT_PLL_RESET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_ASSERT_PLL_RESET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_ASSERT_PLL_RESET_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_ASSERT_PLL_RESET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_ASSERT_PLL_RESET_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_ASSERT_PLL_RESET_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_ASSERT_PLL_RESET_RST                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_V_SHIFT                      _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_V_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_V_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_V_RANGE                      28:28
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_V_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_V_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_V_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_V_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_V_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_V_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_V_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_V_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_V_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_V_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_H_SHIFT                      _MK_SHIFT_CONST(27)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_H_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_H_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_H_RANGE                      27:27
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_H_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_H_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_H_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_H_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_H_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_H_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_H_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_H_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_H_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_H_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_DE_SHIFT                     _MK_SHIFT_CONST(26)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_DE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_DE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_DE_RANGE                     26:26
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_DE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_DE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_DE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_DE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_DE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_DE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_DE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_DE_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_DE_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_DE_INACTIVE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLACK_DATA_SHIFT                   _MK_SHIFT_CONST(25)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLACK_DATA_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLACK_DATA_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLACK_DATA_RANGE                   25:25
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLACK_DATA_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLACK_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLACK_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLACK_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLACK_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLACK_DATA_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLACK_DATA_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLACK_DATA_INIT_ENUM                       NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLACK_DATA_NORMAL                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLACK_DATA_BLACK                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_TRISTATE_IOS_SHIFT                 _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_TRISTATE_IOS_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_TRISTATE_IOS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_TRISTATE_IOS_RANGE                 24:24
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_TRISTATE_IOS_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_TRISTATE_IOS_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_TRISTATE_IOS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_TRISTATE_IOS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_TRISTATE_IOS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_TRISTATE_IOS_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_TRISTATE_IOS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_TRISTATE_IOS_INIT_ENUM                     TRISTATE
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_TRISTATE_IOS_ENABLE_PINS                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_TRISTATE_IOS_TRISTATE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_DRIVE_PWM_OUT_LO_SHIFT                     _MK_SHIFT_CONST(23)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_DRIVE_PWM_OUT_LO_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_DRIVE_PWM_OUT_LO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_DRIVE_PWM_OUT_LO_RANGE                     23:23
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_DRIVE_PWM_OUT_LO_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_DRIVE_PWM_OUT_LO_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_DRIVE_PWM_OUT_LO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_DRIVE_PWM_OUT_LO_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_DRIVE_PWM_OUT_LO_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_DRIVE_PWM_OUT_LO_INIT_ENUM                 FALSE
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_DRIVE_PWM_OUT_LO_FALSE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_DRIVE_PWM_OUT_LO_TRUE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_B_SHIFT                        _MK_SHIFT_CONST(22)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_B_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_B_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_B_RANGE                        22:22
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_B_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_B_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_B_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_B_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_B_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_B_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_B_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_A_SHIFT                        _MK_SHIFT_CONST(21)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_A_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_A_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_A_RANGE                        21:21
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_A_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_A_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_A_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_A_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_A_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_A_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_A_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_A_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_A_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_A_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SEQUENCE_SHIFT                     _MK_SHIFT_CONST(19)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SEQUENCE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_SEQUENCE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SEQUENCE_RANGE                     19:19
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SEQUENCE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SEQUENCE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SEQUENCE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SEQUENCE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SEQUENCE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SEQUENCE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SEQUENCE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SEQUENCE_INIT_ENUM                 UP
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SEQUENCE_UP                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SEQUENCE_DOWN                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_LANE_SEQ_SHIFT                     _MK_SHIFT_CONST(18)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_LANE_SEQ_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_LANE_SEQ_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_LANE_SEQ_RANGE                     18:18
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_LANE_SEQ_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_LANE_SEQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_LANE_SEQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_LANE_SEQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_LANE_SEQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_LANE_SEQ_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_LANE_SEQ_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_LANE_SEQ_INIT_ENUM                 STOP
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_LANE_SEQ_STOP                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_LANE_SEQ_RUN                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPORT_SHIFT                       _MK_SHIFT_CONST(17)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPORT_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPORT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPORT_RANGE                       17:17
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPORT_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPORT_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPORT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPORT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPORT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPORT_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPORT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPORT_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPORT_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPORT_YES                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPLL_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPLL_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPLL_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPLL_RANGE                        16:16
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPLL_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPLL_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPLL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPLL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPLL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPLL_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPLL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPLL_INIT_ENUM                    NO
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPLL_NO                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPLL_YES                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_HALT_SHIFT                 _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_HALT_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_HALT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_HALT_RANGE                 15:15
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_HALT_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_HALT_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_HALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_HALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_HALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_HALT_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_HALT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_HALT_INIT_ENUM                     TRUE
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_HALT_FALSE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_HALT_TRUE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_SHIFT                   _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_FIELD                   _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_RANGE                   13:12
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_INIT_ENUM                       US
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_US                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_MS                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_VSYNC                   _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_TIME_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_TIME_FIELD                    _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_TIME_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_TIME_RANGE                    9:0
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_TIME_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_TIME_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_TIME_DEFAULT_MASK                     _MK_MASK_CONST(0x3ff)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_TIME_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_TIME_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_TIME_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_TIME_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_SEQ_INSTE_0
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0                    _MK_ADDR_CONST(0x30)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SCR                        0
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_RESET_VAL                  _MK_MASK_CONST(0x1008000)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_RESET_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_READ_MASK                  _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WRITE_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PLL_PULLDOWN_SHIFT                 _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PLL_PULLDOWN_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_PLL_PULLDOWN_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PLL_PULLDOWN_RANGE                 31:31
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PLL_PULLDOWN_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PLL_PULLDOWN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PLL_PULLDOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PLL_PULLDOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PLL_PULLDOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PLL_PULLDOWN_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PLL_PULLDOWN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PLL_PULLDOWN_INIT_ENUM                     DISABLE
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PLL_PULLDOWN_DISABLE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PLL_PULLDOWN_ENABLE                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_POWERDOWN_MACRO_SHIFT                      _MK_SHIFT_CONST(30)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_POWERDOWN_MACRO_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_POWERDOWN_MACRO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_POWERDOWN_MACRO_RANGE                      30:30
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_POWERDOWN_MACRO_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_POWERDOWN_MACRO_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_POWERDOWN_MACRO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_POWERDOWN_MACRO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_POWERDOWN_MACRO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_POWERDOWN_MACRO_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_POWERDOWN_MACRO_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_POWERDOWN_MACRO_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_POWERDOWN_MACRO_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_POWERDOWN_MACRO_POWERDOWN                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_ASSERT_PLL_RESET_SHIFT                     _MK_SHIFT_CONST(29)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_ASSERT_PLL_RESET_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_ASSERT_PLL_RESET_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_ASSERT_PLL_RESET_RANGE                     29:29
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_ASSERT_PLL_RESET_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_ASSERT_PLL_RESET_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_ASSERT_PLL_RESET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_ASSERT_PLL_RESET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_ASSERT_PLL_RESET_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_ASSERT_PLL_RESET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_ASSERT_PLL_RESET_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_ASSERT_PLL_RESET_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_ASSERT_PLL_RESET_RST                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_V_SHIFT                      _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_V_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_V_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_V_RANGE                      28:28
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_V_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_V_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_V_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_V_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_V_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_V_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_V_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_V_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_V_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_V_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_H_SHIFT                      _MK_SHIFT_CONST(27)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_H_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_H_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_H_RANGE                      27:27
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_H_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_H_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_H_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_H_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_H_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_H_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_H_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_H_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_H_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_H_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_DE_SHIFT                     _MK_SHIFT_CONST(26)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_DE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_DE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_DE_RANGE                     26:26
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_DE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_DE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_DE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_DE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_DE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_DE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_DE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_DE_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_DE_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_DE_INACTIVE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLACK_DATA_SHIFT                   _MK_SHIFT_CONST(25)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLACK_DATA_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLACK_DATA_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLACK_DATA_RANGE                   25:25
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLACK_DATA_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLACK_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLACK_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLACK_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLACK_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLACK_DATA_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLACK_DATA_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLACK_DATA_INIT_ENUM                       NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLACK_DATA_NORMAL                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLACK_DATA_BLACK                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_TRISTATE_IOS_SHIFT                 _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_TRISTATE_IOS_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_TRISTATE_IOS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_TRISTATE_IOS_RANGE                 24:24
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_TRISTATE_IOS_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_TRISTATE_IOS_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_TRISTATE_IOS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_TRISTATE_IOS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_TRISTATE_IOS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_TRISTATE_IOS_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_TRISTATE_IOS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_TRISTATE_IOS_INIT_ENUM                     TRISTATE
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_TRISTATE_IOS_ENABLE_PINS                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_TRISTATE_IOS_TRISTATE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_DRIVE_PWM_OUT_LO_SHIFT                     _MK_SHIFT_CONST(23)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_DRIVE_PWM_OUT_LO_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_DRIVE_PWM_OUT_LO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_DRIVE_PWM_OUT_LO_RANGE                     23:23
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_DRIVE_PWM_OUT_LO_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_DRIVE_PWM_OUT_LO_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_DRIVE_PWM_OUT_LO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_DRIVE_PWM_OUT_LO_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_DRIVE_PWM_OUT_LO_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_DRIVE_PWM_OUT_LO_INIT_ENUM                 FALSE
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_DRIVE_PWM_OUT_LO_FALSE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_DRIVE_PWM_OUT_LO_TRUE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_B_SHIFT                        _MK_SHIFT_CONST(22)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_B_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_B_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_B_RANGE                        22:22
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_B_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_B_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_B_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_B_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_B_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_B_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_B_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_A_SHIFT                        _MK_SHIFT_CONST(21)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_A_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_A_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_A_RANGE                        21:21
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_A_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_A_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_A_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_A_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_A_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_A_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_A_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_A_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_A_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_A_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SEQUENCE_SHIFT                     _MK_SHIFT_CONST(19)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SEQUENCE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_SEQUENCE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SEQUENCE_RANGE                     19:19
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SEQUENCE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SEQUENCE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SEQUENCE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SEQUENCE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SEQUENCE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SEQUENCE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SEQUENCE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SEQUENCE_INIT_ENUM                 UP
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SEQUENCE_UP                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SEQUENCE_DOWN                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_LANE_SEQ_SHIFT                     _MK_SHIFT_CONST(18)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_LANE_SEQ_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_LANE_SEQ_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_LANE_SEQ_RANGE                     18:18
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_LANE_SEQ_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_LANE_SEQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_LANE_SEQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_LANE_SEQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_LANE_SEQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_LANE_SEQ_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_LANE_SEQ_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_LANE_SEQ_INIT_ENUM                 STOP
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_LANE_SEQ_STOP                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_LANE_SEQ_RUN                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPORT_SHIFT                       _MK_SHIFT_CONST(17)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPORT_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPORT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPORT_RANGE                       17:17
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPORT_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPORT_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPORT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPORT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPORT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPORT_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPORT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPORT_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPORT_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPORT_YES                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPLL_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPLL_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPLL_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPLL_RANGE                        16:16
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPLL_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPLL_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPLL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPLL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPLL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPLL_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPLL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPLL_INIT_ENUM                    NO
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPLL_NO                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPLL_YES                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_HALT_SHIFT                 _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_HALT_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_HALT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_HALT_RANGE                 15:15
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_HALT_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_HALT_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_HALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_HALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_HALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_HALT_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_HALT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_HALT_INIT_ENUM                     TRUE
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_HALT_FALSE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_HALT_TRUE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_SHIFT                   _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_FIELD                   _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_RANGE                   13:12
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_INIT_ENUM                       US
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_US                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_MS                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_VSYNC                   _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_TIME_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_TIME_FIELD                    _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_TIME_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_TIME_RANGE                    9:0
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_TIME_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_TIME_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_TIME_DEFAULT_MASK                     _MK_MASK_CONST(0x3ff)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_TIME_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_TIME_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_TIME_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_TIME_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_SEQ_INSTF_0
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0                    _MK_ADDR_CONST(0x31)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SCR                        0
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_RESET_VAL                  _MK_MASK_CONST(0x1008000)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_RESET_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_READ_MASK                  _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WRITE_MASK                         _MK_MASK_CONST(0xffefb3ff)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PLL_PULLDOWN_SHIFT                 _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PLL_PULLDOWN_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_PLL_PULLDOWN_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PLL_PULLDOWN_RANGE                 31:31
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PLL_PULLDOWN_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PLL_PULLDOWN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PLL_PULLDOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PLL_PULLDOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PLL_PULLDOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PLL_PULLDOWN_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PLL_PULLDOWN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PLL_PULLDOWN_INIT_ENUM                     DISABLE
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PLL_PULLDOWN_DISABLE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PLL_PULLDOWN_ENABLE                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_POWERDOWN_MACRO_SHIFT                      _MK_SHIFT_CONST(30)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_POWERDOWN_MACRO_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_POWERDOWN_MACRO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_POWERDOWN_MACRO_RANGE                      30:30
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_POWERDOWN_MACRO_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_POWERDOWN_MACRO_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_POWERDOWN_MACRO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_POWERDOWN_MACRO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_POWERDOWN_MACRO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_POWERDOWN_MACRO_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_POWERDOWN_MACRO_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_POWERDOWN_MACRO_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_POWERDOWN_MACRO_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_POWERDOWN_MACRO_POWERDOWN                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_ASSERT_PLL_RESET_SHIFT                     _MK_SHIFT_CONST(29)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_ASSERT_PLL_RESET_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_ASSERT_PLL_RESET_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_ASSERT_PLL_RESET_RANGE                     29:29
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_ASSERT_PLL_RESET_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_ASSERT_PLL_RESET_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_ASSERT_PLL_RESET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_ASSERT_PLL_RESET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_ASSERT_PLL_RESET_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_ASSERT_PLL_RESET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_ASSERT_PLL_RESET_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_ASSERT_PLL_RESET_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_ASSERT_PLL_RESET_RST                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_V_SHIFT                      _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_V_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_V_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_V_RANGE                      28:28
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_V_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_V_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_V_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_V_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_V_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_V_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_V_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_V_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_V_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_V_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_H_SHIFT                      _MK_SHIFT_CONST(27)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_H_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_H_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_H_RANGE                      27:27
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_H_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_H_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_H_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_H_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_H_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_H_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_H_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_H_INIT_ENUM                  NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_H_NORMAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_H_INACTIVE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_DE_SHIFT                     _MK_SHIFT_CONST(26)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_DE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_DE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_DE_RANGE                     26:26
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_DE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_DE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_DE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_DE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_DE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_DE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_DE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_DE_INIT_ENUM                 NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_DE_NORMAL                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_DE_INACTIVE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLACK_DATA_SHIFT                   _MK_SHIFT_CONST(25)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLACK_DATA_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLACK_DATA_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLACK_DATA_RANGE                   25:25
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLACK_DATA_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLACK_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLACK_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLACK_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLACK_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLACK_DATA_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLACK_DATA_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLACK_DATA_INIT_ENUM                       NORMAL
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLACK_DATA_NORMAL                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLACK_DATA_BLACK                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_TRISTATE_IOS_SHIFT                 _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_TRISTATE_IOS_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_TRISTATE_IOS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_TRISTATE_IOS_RANGE                 24:24
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_TRISTATE_IOS_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_TRISTATE_IOS_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_TRISTATE_IOS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_TRISTATE_IOS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_TRISTATE_IOS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_TRISTATE_IOS_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_TRISTATE_IOS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_TRISTATE_IOS_INIT_ENUM                     TRISTATE
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_TRISTATE_IOS_ENABLE_PINS                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_TRISTATE_IOS_TRISTATE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_DRIVE_PWM_OUT_LO_SHIFT                     _MK_SHIFT_CONST(23)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_DRIVE_PWM_OUT_LO_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_DRIVE_PWM_OUT_LO_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_DRIVE_PWM_OUT_LO_RANGE                     23:23
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_DRIVE_PWM_OUT_LO_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_DRIVE_PWM_OUT_LO_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_DRIVE_PWM_OUT_LO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_DRIVE_PWM_OUT_LO_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_DRIVE_PWM_OUT_LO_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_DRIVE_PWM_OUT_LO_INIT_ENUM                 FALSE
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_DRIVE_PWM_OUT_LO_FALSE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_DRIVE_PWM_OUT_LO_TRUE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_B_SHIFT                        _MK_SHIFT_CONST(22)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_B_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_B_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_B_RANGE                        22:22
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_B_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_B_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_B_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_B_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_B_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_B_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_B_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_A_SHIFT                        _MK_SHIFT_CONST(21)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_A_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_A_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_A_RANGE                        21:21
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_A_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_A_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_A_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_A_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_A_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_A_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_A_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_A_INIT_ENUM                    LOW
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_A_LOW                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_A_HIGH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SEQUENCE_SHIFT                     _MK_SHIFT_CONST(19)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SEQUENCE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_SEQUENCE_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SEQUENCE_RANGE                     19:19
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SEQUENCE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SEQUENCE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SEQUENCE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SEQUENCE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SEQUENCE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SEQUENCE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SEQUENCE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SEQUENCE_INIT_ENUM                 UP
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SEQUENCE_UP                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SEQUENCE_DOWN                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_LANE_SEQ_SHIFT                     _MK_SHIFT_CONST(18)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_LANE_SEQ_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_LANE_SEQ_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_LANE_SEQ_RANGE                     18:18
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_LANE_SEQ_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_LANE_SEQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_LANE_SEQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_LANE_SEQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_LANE_SEQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_LANE_SEQ_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_LANE_SEQ_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_LANE_SEQ_INIT_ENUM                 STOP
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_LANE_SEQ_STOP                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_LANE_SEQ_RUN                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPORT_SHIFT                       _MK_SHIFT_CONST(17)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPORT_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPORT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPORT_RANGE                       17:17
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPORT_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPORT_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPORT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPORT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPORT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPORT_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPORT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPORT_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPORT_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPORT_YES                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPLL_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPLL_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPLL_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPLL_RANGE                        16:16
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPLL_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPLL_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPLL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPLL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPLL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPLL_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPLL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPLL_INIT_ENUM                    NO
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPLL_NO                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPLL_YES                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_HALT_SHIFT                 _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_HALT_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_HALT_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_HALT_RANGE                 15:15
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_HALT_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_HALT_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_HALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_HALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_HALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_HALT_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_HALT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_HALT_INIT_ENUM                     TRUE
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_HALT_FALSE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_HALT_TRUE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_SHIFT                   _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_FIELD                   _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_RANGE                   13:12
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_INIT_ENUM                       US
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_US                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_MS                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_VSYNC                   _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_TIME_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_TIME_FIELD                    _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_TIME_SHIFT)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_TIME_RANGE                    9:0
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_TIME_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_TIME_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_TIME_DEFAULT_MASK                     _MK_MASK_CONST(0x3ff)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_TIME_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_TIME_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_TIME_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_TIME_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_PWM_DIV_0
#define SOR_NV_PDISP_SOR_PWM_DIV_0                      _MK_ADDR_CONST(0x32)
#define SOR_NV_PDISP_SOR_PWM_DIV_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_PWM_DIV_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_PWM_DIV_0_SCR                  0
#define SOR_NV_PDISP_SOR_PWM_DIV_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_PWM_DIV_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWM_DIV_0_RESET_MASK                   _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_PWM_DIV_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWM_DIV_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWM_DIV_0_READ_MASK                    _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_PWM_DIV_0_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_PWM_DIV_0_DIVIDE_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_PWM_DIV_0_DIVIDE_FIELD                 _MK_FIELD_CONST(0xffffff, SOR_NV_PDISP_SOR_PWM_DIV_0_DIVIDE_SHIFT)
#define SOR_NV_PDISP_SOR_PWM_DIV_0_DIVIDE_RANGE                 23:0
#define SOR_NV_PDISP_SOR_PWM_DIV_0_DIVIDE_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_PWM_DIV_0_DIVIDE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWM_DIV_0_DIVIDE_DEFAULT_MASK                  _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_PWM_DIV_0_DIVIDE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWM_DIV_0_DIVIDE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWM_DIV_0_DIVIDE_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PWM_DIV_0_DIVIDE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_PWM_CTL_0
#define SOR_NV_PDISP_SOR_PWM_CTL_0                      _MK_ADDR_CONST(0x33)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_PWM_CTL_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_PWM_CTL_0_SCR                  0
#define SOR_NV_PDISP_SOR_PWM_CTL_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_PWM_CTL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_RESET_MASK                   _MK_MASK_CONST(0xc0ffffff)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_READ_MASK                    _MK_MASK_CONST(0xc0ffffff)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_WRITE_MASK                   _MK_MASK_CONST(0xc0ffffff)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_SHIFT                    _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_SHIFT)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_RANGE                    31:31
#define SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_INIT_ENUM                        DONE
#define SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_DONE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_PENDING                  _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_TRIGGER                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PWM_CTL_0_CLKSEL_SHIFT                 _MK_SHIFT_CONST(30)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_CLKSEL_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PWM_CTL_0_CLKSEL_SHIFT)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_CLKSEL_RANGE                 30:30
#define SOR_NV_PDISP_SOR_PWM_CTL_0_CLKSEL_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_PWM_CTL_0_CLKSEL_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_CLKSEL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_CLKSEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_CLKSEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_CLKSEL_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_CLKSEL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_CLKSEL_INIT_ENUM                     PCLK
#define SOR_NV_PDISP_SOR_PWM_CTL_0_CLKSEL_PCLK                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_CLKSEL_XTAL                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PWM_CTL_0_DUTY_CYCLE_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_DUTY_CYCLE_FIELD                     _MK_FIELD_CONST(0xffffff, SOR_NV_PDISP_SOR_PWM_CTL_0_DUTY_CYCLE_SHIFT)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_DUTY_CYCLE_RANGE                     23:0
#define SOR_NV_PDISP_SOR_PWM_CTL_0_DUTY_CYCLE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_PWM_CTL_0_DUTY_CYCLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_DUTY_CYCLE_DEFAULT_MASK                      _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_DUTY_CYCLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_DUTY_CYCLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_DUTY_CYCLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PWM_CTL_0_DUTY_CYCLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_VCRCA0_0
#define SOR_NV_PDISP_SOR_VCRCA0_0                       _MK_ADDR_CONST(0x34)
#define SOR_NV_PDISP_SOR_VCRCA0_0_SECURE                        0x0
#define SOR_NV_PDISP_SOR_VCRCA0_0_DUAL                  0x0
#define SOR_NV_PDISP_SOR_VCRCA0_0_SCR                   0
#define SOR_NV_PDISP_SOR_VCRCA0_0_WORD_COUNT                    0x1
#define SOR_NV_PDISP_SOR_VCRCA0_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCA0_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCA0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCA0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCA0_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_VCRCA0_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCM_SHIFT                    _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCM_FIELD                    _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_VCRCA0_0_CRCM_SHIFT)
#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCM_RANGE                    31:16
#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCM_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCM_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCM_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCM_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCM_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCL_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCL_FIELD                    _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_VCRCA0_0_CRCL_SHIFT)
#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCL_RANGE                    15:0
#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCL_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCL_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCL_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_VCRCA1_0
#define SOR_NV_PDISP_SOR_VCRCA1_0                       _MK_ADDR_CONST(0x35)
#define SOR_NV_PDISP_SOR_VCRCA1_0_SECURE                        0x0
#define SOR_NV_PDISP_SOR_VCRCA1_0_DUAL                  0x0
#define SOR_NV_PDISP_SOR_VCRCA1_0_SCR                   0
#define SOR_NV_PDISP_SOR_VCRCA1_0_WORD_COUNT                    0x1
#define SOR_NV_PDISP_SOR_VCRCA1_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCA1_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCA1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCA1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCA1_0_READ_MASK                     _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_VCRCA1_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCA1_0_CRCH_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_VCRCA1_0_CRCH_FIELD                    _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_VCRCA1_0_CRCH_SHIFT)
#define SOR_NV_PDISP_SOR_VCRCA1_0_CRCH_RANGE                    15:0
#define SOR_NV_PDISP_SOR_VCRCA1_0_CRCH_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_VCRCA1_0_CRCH_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCA1_0_CRCH_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCA1_0_CRCH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCA1_0_CRCH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCA1_0_CRCH_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCA1_0_CRCH_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_VCRCB0_0
#define SOR_NV_PDISP_SOR_VCRCB0_0                       _MK_ADDR_CONST(0x36)
#define SOR_NV_PDISP_SOR_VCRCB0_0_SECURE                        0x0
#define SOR_NV_PDISP_SOR_VCRCB0_0_DUAL                  0x0
#define SOR_NV_PDISP_SOR_VCRCB0_0_SCR                   0
#define SOR_NV_PDISP_SOR_VCRCB0_0_WORD_COUNT                    0x1
#define SOR_NV_PDISP_SOR_VCRCB0_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCB0_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCB0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCB0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCB0_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_VCRCB0_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCM_SHIFT                    _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCM_FIELD                    _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_VCRCB0_0_CRCM_SHIFT)
#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCM_RANGE                    31:16
#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCM_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCM_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCM_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCM_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCM_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCL_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCL_FIELD                    _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_VCRCB0_0_CRCL_SHIFT)
#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCL_RANGE                    15:0
#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCL_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCL_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCL_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_VCRCB1_0
#define SOR_NV_PDISP_SOR_VCRCB1_0                       _MK_ADDR_CONST(0x37)
#define SOR_NV_PDISP_SOR_VCRCB1_0_SECURE                        0x0
#define SOR_NV_PDISP_SOR_VCRCB1_0_DUAL                  0x0
#define SOR_NV_PDISP_SOR_VCRCB1_0_SCR                   0
#define SOR_NV_PDISP_SOR_VCRCB1_0_WORD_COUNT                    0x1
#define SOR_NV_PDISP_SOR_VCRCB1_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCB1_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCB1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCB1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCB1_0_READ_MASK                     _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_VCRCB1_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCB1_0_CRCH_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_VCRCB1_0_CRCH_FIELD                    _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_VCRCB1_0_CRCH_SHIFT)
#define SOR_NV_PDISP_SOR_VCRCB1_0_CRCH_RANGE                    15:0
#define SOR_NV_PDISP_SOR_VCRCB1_0_CRCH_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_VCRCB1_0_CRCH_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCB1_0_CRCH_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCB1_0_CRCH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCB1_0_CRCH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCB1_0_CRCH_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VCRCB1_0_CRCH_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_CCRCA0_0
#define SOR_NV_PDISP_SOR_CCRCA0_0                       _MK_ADDR_CONST(0x38)
#define SOR_NV_PDISP_SOR_CCRCA0_0_SECURE                        0x0
#define SOR_NV_PDISP_SOR_CCRCA0_0_DUAL                  0x0
#define SOR_NV_PDISP_SOR_CCRCA0_0_SCR                   0
#define SOR_NV_PDISP_SOR_CCRCA0_0_WORD_COUNT                    0x1
#define SOR_NV_PDISP_SOR_CCRCA0_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCA0_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCA0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCA0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCA0_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_CCRCA0_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCM_SHIFT                    _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCM_FIELD                    _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_CCRCA0_0_CRCM_SHIFT)
#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCM_RANGE                    31:16
#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCM_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCM_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCM_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCM_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCM_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCL_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCL_FIELD                    _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_CCRCA0_0_CRCL_SHIFT)
#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCL_RANGE                    15:0
#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCL_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCL_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCL_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_CCRCA1_0
#define SOR_NV_PDISP_SOR_CCRCA1_0                       _MK_ADDR_CONST(0x39)
#define SOR_NV_PDISP_SOR_CCRCA1_0_SECURE                        0x0
#define SOR_NV_PDISP_SOR_CCRCA1_0_DUAL                  0x0
#define SOR_NV_PDISP_SOR_CCRCA1_0_SCR                   0
#define SOR_NV_PDISP_SOR_CCRCA1_0_WORD_COUNT                    0x1
#define SOR_NV_PDISP_SOR_CCRCA1_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCA1_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCA1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCA1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCA1_0_READ_MASK                     _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_CCRCA1_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCA1_0_CRCH_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_CCRCA1_0_CRCH_FIELD                    _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_CCRCA1_0_CRCH_SHIFT)
#define SOR_NV_PDISP_SOR_CCRCA1_0_CRCH_RANGE                    15:0
#define SOR_NV_PDISP_SOR_CCRCA1_0_CRCH_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_CCRCA1_0_CRCH_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCA1_0_CRCH_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCA1_0_CRCH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCA1_0_CRCH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCA1_0_CRCH_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCA1_0_CRCH_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_CCRCB0_0
#define SOR_NV_PDISP_SOR_CCRCB0_0                       _MK_ADDR_CONST(0x3a)
#define SOR_NV_PDISP_SOR_CCRCB0_0_SECURE                        0x0
#define SOR_NV_PDISP_SOR_CCRCB0_0_DUAL                  0x0
#define SOR_NV_PDISP_SOR_CCRCB0_0_SCR                   0
#define SOR_NV_PDISP_SOR_CCRCB0_0_WORD_COUNT                    0x1
#define SOR_NV_PDISP_SOR_CCRCB0_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCB0_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCB0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCB0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCB0_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_CCRCB0_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCM_SHIFT                    _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCM_FIELD                    _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_CCRCB0_0_CRCM_SHIFT)
#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCM_RANGE                    31:16
#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCM_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCM_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCM_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCM_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCM_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCL_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCL_FIELD                    _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_CCRCB0_0_CRCL_SHIFT)
#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCL_RANGE                    15:0
#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCL_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCL_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCL_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_CCRCB1_0
#define SOR_NV_PDISP_SOR_CCRCB1_0                       _MK_ADDR_CONST(0x3b)
#define SOR_NV_PDISP_SOR_CCRCB1_0_SECURE                        0x0
#define SOR_NV_PDISP_SOR_CCRCB1_0_DUAL                  0x0
#define SOR_NV_PDISP_SOR_CCRCB1_0_SCR                   0
#define SOR_NV_PDISP_SOR_CCRCB1_0_WORD_COUNT                    0x1
#define SOR_NV_PDISP_SOR_CCRCB1_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCB1_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCB1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCB1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCB1_0_READ_MASK                     _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_CCRCB1_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCB1_0_CRCH_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_CCRCB1_0_CRCH_FIELD                    _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_CCRCB1_0_CRCH_SHIFT)
#define SOR_NV_PDISP_SOR_CCRCB1_0_CRCH_RANGE                    15:0
#define SOR_NV_PDISP_SOR_CCRCB1_0_CRCH_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_CCRCB1_0_CRCH_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCB1_0_CRCH_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCB1_0_CRCH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCB1_0_CRCH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCB1_0_CRCH_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_CCRCB1_0_CRCH_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_EDATAA0_0
#define SOR_NV_PDISP_SOR_EDATAA0_0                      _MK_ADDR_CONST(0x3c)
#define SOR_NV_PDISP_SOR_EDATAA0_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_EDATAA0_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_EDATAA0_0_SCR                  0
#define SOR_NV_PDISP_SOR_EDATAA0_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_EDATAA0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAA0_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAA0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAA0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAA0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_EDATAA0_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAA0_0_VAL_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_EDATAA0_0_VAL_FIELD                    _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_EDATAA0_0_VAL_SHIFT)
#define SOR_NV_PDISP_SOR_EDATAA0_0_VAL_RANGE                    31:0
#define SOR_NV_PDISP_SOR_EDATAA0_0_VAL_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_EDATAA0_0_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAA0_0_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAA0_0_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAA0_0_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAA0_0_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAA0_0_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_EDATAA1_0
#define SOR_NV_PDISP_SOR_EDATAA1_0                      _MK_ADDR_CONST(0x3d)
#define SOR_NV_PDISP_SOR_EDATAA1_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_EDATAA1_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_EDATAA1_0_SCR                  0
#define SOR_NV_PDISP_SOR_EDATAA1_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_EDATAA1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAA1_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAA1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAA1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAA1_0_READ_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_EDATAA1_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAA1_0_VAL_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_EDATAA1_0_VAL_FIELD                    _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_EDATAA1_0_VAL_SHIFT)
#define SOR_NV_PDISP_SOR_EDATAA1_0_VAL_RANGE                    7:0
#define SOR_NV_PDISP_SOR_EDATAA1_0_VAL_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_EDATAA1_0_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAA1_0_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAA1_0_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAA1_0_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAA1_0_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAA1_0_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_EDATAB0_0
#define SOR_NV_PDISP_SOR_EDATAB0_0                      _MK_ADDR_CONST(0x3e)
#define SOR_NV_PDISP_SOR_EDATAB0_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_EDATAB0_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_EDATAB0_0_SCR                  0
#define SOR_NV_PDISP_SOR_EDATAB0_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_EDATAB0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAB0_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAB0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAB0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAB0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_EDATAB0_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAB0_0_VAL_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_EDATAB0_0_VAL_FIELD                    _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_EDATAB0_0_VAL_SHIFT)
#define SOR_NV_PDISP_SOR_EDATAB0_0_VAL_RANGE                    31:0
#define SOR_NV_PDISP_SOR_EDATAB0_0_VAL_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_EDATAB0_0_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAB0_0_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAB0_0_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAB0_0_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAB0_0_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAB0_0_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_EDATAB1_0
#define SOR_NV_PDISP_SOR_EDATAB1_0                      _MK_ADDR_CONST(0x3f)
#define SOR_NV_PDISP_SOR_EDATAB1_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_EDATAB1_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_EDATAB1_0_SCR                  0
#define SOR_NV_PDISP_SOR_EDATAB1_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_EDATAB1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAB1_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAB1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAB1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAB1_0_READ_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_EDATAB1_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAB1_0_VAL_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_EDATAB1_0_VAL_FIELD                    _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_EDATAB1_0_VAL_SHIFT)
#define SOR_NV_PDISP_SOR_EDATAB1_0_VAL_RANGE                    7:0
#define SOR_NV_PDISP_SOR_EDATAB1_0_VAL_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_EDATAB1_0_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAB1_0_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAB1_0_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAB1_0_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAB1_0_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_EDATAB1_0_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_COUNTA0_0
#define SOR_NV_PDISP_SOR_COUNTA0_0                      _MK_ADDR_CONST(0x40)
#define SOR_NV_PDISP_SOR_COUNTA0_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_COUNTA0_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_COUNTA0_0_SCR                  0
#define SOR_NV_PDISP_SOR_COUNTA0_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_COUNTA0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTA0_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTA0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTA0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTA0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_COUNTA0_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTA0_0_TX1_SHIFT                    _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_COUNTA0_0_TX1_FIELD                    _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_COUNTA0_0_TX1_SHIFT)
#define SOR_NV_PDISP_SOR_COUNTA0_0_TX1_RANGE                    31:16
#define SOR_NV_PDISP_SOR_COUNTA0_0_TX1_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_COUNTA0_0_TX1_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTA0_0_TX1_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTA0_0_TX1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTA0_0_TX1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTA0_0_TX1_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTA0_0_TX1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_COUNTA0_0_TX0_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_COUNTA0_0_TX0_FIELD                    _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_COUNTA0_0_TX0_SHIFT)
#define SOR_NV_PDISP_SOR_COUNTA0_0_TX0_RANGE                    15:0
#define SOR_NV_PDISP_SOR_COUNTA0_0_TX0_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_COUNTA0_0_TX0_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTA0_0_TX0_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTA0_0_TX0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTA0_0_TX0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTA0_0_TX0_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTA0_0_TX0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_COUNTA1_0
#define SOR_NV_PDISP_SOR_COUNTA1_0                      _MK_ADDR_CONST(0x41)
#define SOR_NV_PDISP_SOR_COUNTA1_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_COUNTA1_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_COUNTA1_0_SCR                  0
#define SOR_NV_PDISP_SOR_COUNTA1_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_COUNTA1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTA1_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTA1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTA1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTA1_0_READ_MASK                    _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_COUNTA1_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTA1_0_TX2_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_COUNTA1_0_TX2_FIELD                    _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_COUNTA1_0_TX2_SHIFT)
#define SOR_NV_PDISP_SOR_COUNTA1_0_TX2_RANGE                    15:0
#define SOR_NV_PDISP_SOR_COUNTA1_0_TX2_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_COUNTA1_0_TX2_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTA1_0_TX2_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTA1_0_TX2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTA1_0_TX2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTA1_0_TX2_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTA1_0_TX2_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_COUNTB0_0
#define SOR_NV_PDISP_SOR_COUNTB0_0                      _MK_ADDR_CONST(0x42)
#define SOR_NV_PDISP_SOR_COUNTB0_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_COUNTB0_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_COUNTB0_0_SCR                  0
#define SOR_NV_PDISP_SOR_COUNTB0_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_COUNTB0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTB0_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTB0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTB0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTB0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_COUNTB0_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTB0_0_TX1_SHIFT                    _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_COUNTB0_0_TX1_FIELD                    _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_COUNTB0_0_TX1_SHIFT)
#define SOR_NV_PDISP_SOR_COUNTB0_0_TX1_RANGE                    31:16
#define SOR_NV_PDISP_SOR_COUNTB0_0_TX1_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_COUNTB0_0_TX1_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTB0_0_TX1_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTB0_0_TX1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTB0_0_TX1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTB0_0_TX1_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTB0_0_TX1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_COUNTB0_0_TX0_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_COUNTB0_0_TX0_FIELD                    _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_COUNTB0_0_TX0_SHIFT)
#define SOR_NV_PDISP_SOR_COUNTB0_0_TX0_RANGE                    15:0
#define SOR_NV_PDISP_SOR_COUNTB0_0_TX0_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_COUNTB0_0_TX0_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTB0_0_TX0_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTB0_0_TX0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTB0_0_TX0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTB0_0_TX0_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTB0_0_TX0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_COUNTB1_0
#define SOR_NV_PDISP_SOR_COUNTB1_0                      _MK_ADDR_CONST(0x43)
#define SOR_NV_PDISP_SOR_COUNTB1_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_COUNTB1_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_COUNTB1_0_SCR                  0
#define SOR_NV_PDISP_SOR_COUNTB1_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_COUNTB1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTB1_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTB1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTB1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTB1_0_READ_MASK                    _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_COUNTB1_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTB1_0_TX2_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_COUNTB1_0_TX2_FIELD                    _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_COUNTB1_0_TX2_SHIFT)
#define SOR_NV_PDISP_SOR_COUNTB1_0_TX2_RANGE                    15:0
#define SOR_NV_PDISP_SOR_COUNTB1_0_TX2_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_COUNTB1_0_TX2_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTB1_0_TX2_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTB1_0_TX2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTB1_0_TX2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTB1_0_TX2_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_COUNTB1_0_TX2_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DEBUGA0_0
#define SOR_NV_PDISP_SOR_DEBUGA0_0                      _MK_ADDR_CONST(0x44)
#define SOR_NV_PDISP_SOR_DEBUGA0_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_DEBUGA0_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_DEBUGA0_0_SCR                  0
#define SOR_NV_PDISP_SOR_DEBUGA0_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_DEBUGA0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DEBUGA0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DEBUGA0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DEBUGA0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DEBUGA0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DEBUGA0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DEBUGA0_0_VAL_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DEBUGA0_0_VAL_FIELD                    _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_DEBUGA0_0_VAL_SHIFT)
#define SOR_NV_PDISP_SOR_DEBUGA0_0_VAL_RANGE                    31:0
#define SOR_NV_PDISP_SOR_DEBUGA0_0_VAL_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DEBUGA0_0_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DEBUGA0_0_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DEBUGA0_0_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DEBUGA0_0_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DEBUGA0_0_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DEBUGA0_0_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DEBUGA0_0_VAL_INIT_ENUM                        RST
#define SOR_NV_PDISP_SOR_DEBUGA0_0_VAL_RST                      _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_DEBUGA1_0
#define SOR_NV_PDISP_SOR_DEBUGA1_0                      _MK_ADDR_CONST(0x45)
#define SOR_NV_PDISP_SOR_DEBUGA1_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_DEBUGA1_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_DEBUGA1_0_SCR                  0
#define SOR_NV_PDISP_SOR_DEBUGA1_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_DEBUGA1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DEBUGA1_0_RESET_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DEBUGA1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DEBUGA1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DEBUGA1_0_READ_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DEBUGA1_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DEBUGA1_0_VAL_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DEBUGA1_0_VAL_FIELD                    _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DEBUGA1_0_VAL_SHIFT)
#define SOR_NV_PDISP_SOR_DEBUGA1_0_VAL_RANGE                    7:0
#define SOR_NV_PDISP_SOR_DEBUGA1_0_VAL_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DEBUGA1_0_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DEBUGA1_0_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DEBUGA1_0_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DEBUGA1_0_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DEBUGA1_0_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DEBUGA1_0_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DEBUGA1_0_VAL_INIT_ENUM                        RST
#define SOR_NV_PDISP_SOR_DEBUGA1_0_VAL_RST                      _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_DEBUGB0_0
#define SOR_NV_PDISP_SOR_DEBUGB0_0                      _MK_ADDR_CONST(0x46)
#define SOR_NV_PDISP_SOR_DEBUGB0_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_DEBUGB0_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_DEBUGB0_0_SCR                  0
#define SOR_NV_PDISP_SOR_DEBUGB0_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_DEBUGB0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DEBUGB0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DEBUGB0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DEBUGB0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DEBUGB0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DEBUGB0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DEBUGB0_0_VAL_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DEBUGB0_0_VAL_FIELD                    _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_DEBUGB0_0_VAL_SHIFT)
#define SOR_NV_PDISP_SOR_DEBUGB0_0_VAL_RANGE                    31:0
#define SOR_NV_PDISP_SOR_DEBUGB0_0_VAL_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DEBUGB0_0_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DEBUGB0_0_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DEBUGB0_0_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DEBUGB0_0_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DEBUGB0_0_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DEBUGB0_0_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DEBUGB0_0_VAL_INIT_ENUM                        RST
#define SOR_NV_PDISP_SOR_DEBUGB0_0_VAL_RST                      _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_DEBUGB1_0
#define SOR_NV_PDISP_SOR_DEBUGB1_0                      _MK_ADDR_CONST(0x47)
#define SOR_NV_PDISP_SOR_DEBUGB1_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_DEBUGB1_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_DEBUGB1_0_SCR                  0
#define SOR_NV_PDISP_SOR_DEBUGB1_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_DEBUGB1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DEBUGB1_0_RESET_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DEBUGB1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DEBUGB1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DEBUGB1_0_READ_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DEBUGB1_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DEBUGB1_0_VAL_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DEBUGB1_0_VAL_FIELD                    _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DEBUGB1_0_VAL_SHIFT)
#define SOR_NV_PDISP_SOR_DEBUGB1_0_VAL_RANGE                    7:0
#define SOR_NV_PDISP_SOR_DEBUGB1_0_VAL_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DEBUGB1_0_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DEBUGB1_0_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DEBUGB1_0_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DEBUGB1_0_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DEBUGB1_0_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DEBUGB1_0_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DEBUGB1_0_VAL_INIT_ENUM                        RST
#define SOR_NV_PDISP_SOR_DEBUGB1_0_VAL_RST                      _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_TRIG_0
#define SOR_NV_PDISP_SOR_TRIG_0                 _MK_ADDR_CONST(0x48)
#define SOR_NV_PDISP_SOR_TRIG_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_TRIG_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_TRIG_0_SCR                     0
#define SOR_NV_PDISP_SOR_TRIG_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_TRIG_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TRIG_0_RESET_MASK                      _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_TRIG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TRIG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TRIG_0_READ_MASK                       _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_TRIG_0_WRITE_MASK                      _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_TRIG_0_VAL_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_TRIG_0_VAL_FIELD                       _MK_FIELD_CONST(0xffffff, SOR_NV_PDISP_SOR_TRIG_0_VAL_SHIFT)
#define SOR_NV_PDISP_SOR_TRIG_0_VAL_RANGE                       23:0
#define SOR_NV_PDISP_SOR_TRIG_0_VAL_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_TRIG_0_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TRIG_0_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_TRIG_0_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TRIG_0_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TRIG_0_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TRIG_0_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TRIG_0_VAL_INIT_ENUM                   RST
#define SOR_NV_PDISP_SOR_TRIG_0_VAL_RST                 _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_MSCHECK_0
#define SOR_NV_PDISP_SOR_MSCHECK_0                      _MK_ADDR_CONST(0x49)
#define SOR_NV_PDISP_SOR_MSCHECK_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_MSCHECK_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_MSCHECK_0_SCR                  0
#define SOR_NV_PDISP_SOR_MSCHECK_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_MSCHECK_0_RESET_VAL                    _MK_MASK_CONST(0x80000000)
#define SOR_NV_PDISP_SOR_MSCHECK_0_RESET_MASK                   _MK_MASK_CONST(0x80000000)
#define SOR_NV_PDISP_SOR_MSCHECK_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_MSCHECK_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_MSCHECK_0_READ_MASK                    _MK_MASK_CONST(0x8000ffff)
#define SOR_NV_PDISP_SOR_MSCHECK_0_WRITE_MASK                   _MK_MASK_CONST(0x80000000)
#define SOR_NV_PDISP_SOR_MSCHECK_0_CTL_SHIFT                    _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_MSCHECK_0_CTL_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_MSCHECK_0_CTL_SHIFT)
#define SOR_NV_PDISP_SOR_MSCHECK_0_CTL_RANGE                    31:31
#define SOR_NV_PDISP_SOR_MSCHECK_0_CTL_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_MSCHECK_0_CTL_DEFAULT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_MSCHECK_0_CTL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_MSCHECK_0_CTL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_MSCHECK_0_CTL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_MSCHECK_0_CTL_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_MSCHECK_0_CTL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_MSCHECK_0_CTL_INIT_ENUM                        RUN
#define SOR_NV_PDISP_SOR_MSCHECK_0_CTL_CLEAR                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_MSCHECK_0_CTL_RUN                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_T2F_SHIFT                        _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_T2F_FIELD                        _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_T2F_SHIFT)
#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_T2F_RANGE                        15:12
#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_T2F_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_T2F_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_T2F_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_T2F_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_T2F_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_T2F_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_T2F_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_F2T_SHIFT                        _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_F2T_FIELD                        _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_F2T_SHIFT)
#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_F2T_RANGE                        11:8
#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_F2T_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_F2T_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_F2T_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_F2T_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_F2T_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_F2T_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_F2T_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_T2F_SHIFT                 _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_T2F_FIELD                 _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_T2F_SHIFT)
#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_T2F_RANGE                 7:4
#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_T2F_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_T2F_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_T2F_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_T2F_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_T2F_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_T2F_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_T2F_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_F2T_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_F2T_FIELD                 _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_F2T_SHIFT)
#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_F2T_RANGE                 3:0
#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_F2T_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_F2T_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_F2T_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_F2T_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_F2T_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_F2T_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_F2T_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_XBAR_CTRL_0
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0                    _MK_ADDR_CONST(0x4a)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_SCR                        0
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_RESET_VAL                  _MK_MASK_CONST(0x8d111a23)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_4_SHIFT                 _MK_SHIFT_CONST(29)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_4_FIELD                 _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_4_SHIFT)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_4_RANGE                 31:29
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_4_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_4_DEFAULT                       _MK_MASK_CONST(0x4)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_4_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_4_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_4_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_4_ZERO                  _MK_ENUM_CONST(7)

#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_3_SHIFT                 _MK_SHIFT_CONST(26)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_3_FIELD                 _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_3_SHIFT)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_3_RANGE                 28:26
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_3_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_3_DEFAULT                       _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_3_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_3_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_3_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_3_ZERO                  _MK_ENUM_CONST(7)

#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_2_SHIFT                 _MK_SHIFT_CONST(23)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_2_FIELD                 _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_2_SHIFT)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_2_RANGE                 25:23
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_2_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_2_DEFAULT                       _MK_MASK_CONST(0x2)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_2_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_2_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_2_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_2_ZERO                  _MK_ENUM_CONST(7)

#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_1_SHIFT                 _MK_SHIFT_CONST(20)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_1_FIELD                 _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_1_SHIFT)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_1_RANGE                 22:20
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_1_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_1_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_1_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_1_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_1_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_1_ZERO                  _MK_ENUM_CONST(7)

#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_0_SHIFT                 _MK_SHIFT_CONST(17)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_0_FIELD                 _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_0_SHIFT)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_0_RANGE                 19:17
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_0_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_0_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_0_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_0_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_0_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_0_ZERO                  _MK_ENUM_CONST(7)

#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_4_SHIFT                 _MK_SHIFT_CONST(14)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_4_FIELD                 _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_4_SHIFT)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_4_RANGE                 16:14
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_4_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_4_DEFAULT                       _MK_MASK_CONST(0x4)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_4_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_4_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_4_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_4_ZERO                  _MK_ENUM_CONST(7)

#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_3_SHIFT                 _MK_SHIFT_CONST(11)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_3_FIELD                 _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_3_SHIFT)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_3_RANGE                 13:11
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_3_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_3_DEFAULT                       _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_3_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_3_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_3_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_3_ZERO                  _MK_ENUM_CONST(7)

#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_2_SHIFT                 _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_2_FIELD                 _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_2_SHIFT)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_2_RANGE                 10:8
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_2_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_2_DEFAULT                       _MK_MASK_CONST(0x2)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_2_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_2_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_2_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_2_ZERO                  _MK_ENUM_CONST(7)

#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_1_SHIFT                 _MK_SHIFT_CONST(5)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_1_FIELD                 _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_1_SHIFT)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_1_RANGE                 7:5
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_1_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_1_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_1_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_1_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_1_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_1_ZERO                  _MK_ENUM_CONST(7)

#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_0_SHIFT                 _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_0_FIELD                 _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_0_SHIFT)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_0_RANGE                 4:2
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_0_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_0_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_0_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_0_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_0_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_0_ZERO                  _MK_ENUM_CONST(7)

#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK_SWAP_SHIFT                    _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK_SWAP_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK_SWAP_SHIFT)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK_SWAP_RANGE                    1:1
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK_SWAP_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK_SWAP_DEFAULT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK_SWAP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK_SWAP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK_SWAP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK_SWAP_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK_SWAP_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_BYPASS_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_BYPASS_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_XBAR_CTRL_0_BYPASS_SHIFT)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_BYPASS_RANGE                       0:0
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_BYPASS_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_BYPASS_DEFAULT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_BYPASS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_BYPASS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_BYPASS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_BYPASS_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_BYPASS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_XBAR_POL_0
#define SOR_NV_PDISP_SOR_XBAR_POL_0                     _MK_ADDR_CONST(0x4b)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_SECURE                      0x0
#define SOR_NV_PDISP_SOR_XBAR_POL_0_DUAL                        0x0
#define SOR_NV_PDISP_SOR_XBAR_POL_0_SCR                         0
#define SOR_NV_PDISP_SOR_XBAR_POL_0_WORD_COUNT                  0x1
#define SOR_NV_PDISP_SOR_XBAR_POL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_RESET_MASK                  _MK_MASK_CONST(0x3ff)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_READ_MASK                   _MK_MASK_CONST(0x3ff)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_4_SHIFT                   _MK_SHIFT_CONST(9)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_4_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_4_SHIFT)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_4_RANGE                   9:9
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_4_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_4_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_4_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_4_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_4_INIT_ENUM                       NORMAL
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_4_NORMAL                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_4_INVERT                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_3_SHIFT                   _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_3_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_3_SHIFT)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_3_RANGE                   8:8
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_3_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_3_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_3_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_3_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_3_INIT_ENUM                       NORMAL
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_3_NORMAL                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_3_INVERT                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_2_SHIFT                   _MK_SHIFT_CONST(7)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_2_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_2_SHIFT)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_2_RANGE                   7:7
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_2_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_2_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_2_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_2_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_2_INIT_ENUM                       NORMAL
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_2_NORMAL                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_2_INVERT                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_1_SHIFT                   _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_1_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_1_SHIFT)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_1_RANGE                   6:6
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_1_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_1_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_1_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_1_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_1_INIT_ENUM                       NORMAL
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_1_NORMAL                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_1_INVERT                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_0_SHIFT                   _MK_SHIFT_CONST(5)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_0_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_0_SHIFT)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_0_RANGE                   5:5
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_0_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_0_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_0_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_0_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_0_INIT_ENUM                       NORMAL
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_0_NORMAL                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_0_INVERT                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_4_SHIFT                   _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_4_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_4_SHIFT)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_4_RANGE                   4:4
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_4_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_4_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_4_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_4_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_4_INIT_ENUM                       NORMAL
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_4_NORMAL                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_4_INVERT                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_3_SHIFT                   _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_3_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_3_SHIFT)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_3_RANGE                   3:3
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_3_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_3_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_3_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_3_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_3_INIT_ENUM                       NORMAL
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_3_NORMAL                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_3_INVERT                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_2_SHIFT                   _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_2_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_2_SHIFT)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_2_RANGE                   2:2
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_2_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_2_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_2_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_2_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_2_INIT_ENUM                       NORMAL
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_2_NORMAL                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_2_INVERT                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_1_SHIFT                   _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_1_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_1_SHIFT)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_1_RANGE                   1:1
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_1_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_1_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_1_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_1_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_1_INIT_ENUM                       NORMAL
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_1_NORMAL                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_1_INVERT                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_0_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_0_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_0_SHIFT)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_0_RANGE                   0:0
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_0_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_0_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_0_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_0_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_0_INIT_ENUM                       NORMAL
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_0_NORMAL                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_0_INVERT                  _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_DP_LINKCTL0_0
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0                  _MK_ADDR_CONST(0x4c)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SECURE                   0x0
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_DUAL                     0x0
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SCR                      0
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_WORD_COUNT                       0x1
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_RESET_VAL                        _MK_MASK_CONST(0x100)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_RESET_MASK                       _MK_MASK_CONST(0x901f45ff)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_READ_MASK                        _MK_MASK_CONST(0x901f45ff)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_WRITE_MASK                       _MK_MASK_CONST(0x901f45ff)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_FORCE_IDLEPTTRN_SHIFT                    _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_FORCE_IDLEPTTRN_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_LINKCTL0_0_FORCE_IDLEPTTRN_SHIFT)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_FORCE_IDLEPTTRN_RANGE                    31:31
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_FORCE_IDLEPTTRN_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_FORCE_IDLEPTTRN_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_FORCE_IDLEPTTRN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_FORCE_IDLEPTTRN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_FORCE_IDLEPTTRN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_FORCE_IDLEPTTRN_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_FORCE_IDLEPTTRN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_FORCE_IDLEPTTRN_INIT_ENUM                        NO
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_FORCE_IDLEPTTRN_NO                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_FORCE_IDLEPTTRN_YES                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_COMPLIANCEPTTRN_SHIFT                    _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_COMPLIANCEPTTRN_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_LINKCTL0_0_COMPLIANCEPTTRN_SHIFT)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_COMPLIANCEPTTRN_RANGE                    28:28
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_COMPLIANCEPTTRN_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_COMPLIANCEPTTRN_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_COMPLIANCEPTTRN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_COMPLIANCEPTTRN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_COMPLIANCEPTTRN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_COMPLIANCEPTTRN_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_COMPLIANCEPTTRN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_COMPLIANCEPTTRN_INIT_ENUM                        NOPATTERN
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_COMPLIANCEPTTRN_NOPATTERN                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_COMPLIANCEPTTRN_COLORSQARE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_SHIFT                  _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_FIELD                  _MK_FIELD_CONST(0x1f, SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_SHIFT)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_RANGE                  20:16
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_INIT_ENUM                      ZERO
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_ZERO                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_ONE                    _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_TWO                    _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_FOUR                   _MK_ENUM_CONST(15)

#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENHANCEDFRAME_SHIFT                      _MK_SHIFT_CONST(14)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENHANCEDFRAME_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENHANCEDFRAME_SHIFT)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENHANCEDFRAME_RANGE                      14:14
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENHANCEDFRAME_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENHANCEDFRAME_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENHANCEDFRAME_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENHANCEDFRAME_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENHANCEDFRAME_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENHANCEDFRAME_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENHANCEDFRAME_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENHANCEDFRAME_INIT_ENUM                  DISABLE
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENHANCEDFRAME_DISABLE                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENHANCEDFRAME_ENABLE                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SYNCMODE_SHIFT                   _MK_SHIFT_CONST(10)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SYNCMODE_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SYNCMODE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SYNCMODE_RANGE                   10:10
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SYNCMODE_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SYNCMODE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SYNCMODE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SYNCMODE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SYNCMODE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SYNCMODE_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SYNCMODE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SYNCMODE_INIT_ENUM                       DISABLE
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SYNCMODE_DISABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SYNCMODE_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_SHIFT                     _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_FIELD                     _MK_FIELD_CONST(0x7f, SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_RANGE                     8:2
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_DEFAULT                   _MK_MASK_CONST(0x40)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ASYNC_FIFO_BLOCK_SHIFT                   _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ASYNC_FIFO_BLOCK_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ASYNC_FIFO_BLOCK_SHIFT)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ASYNC_FIFO_BLOCK_RANGE                   1:1
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ASYNC_FIFO_BLOCK_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ASYNC_FIFO_BLOCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ASYNC_FIFO_BLOCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ASYNC_FIFO_BLOCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ASYNC_FIFO_BLOCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ASYNC_FIFO_BLOCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ASYNC_FIFO_BLOCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ASYNC_FIFO_BLOCK_INIT_ENUM                       NO
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ASYNC_FIFO_BLOCK_NO                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ASYNC_FIFO_BLOCK_YES                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENABLE_RANGE                     0:0
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENABLE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENABLE_INIT_ENUM                 NO
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENABLE_NO                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENABLE_YES                       _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_DP_LINKCTL1_0
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0                  _MK_ADDR_CONST(0x4d)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SECURE                   0x0
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_DUAL                     0x0
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SCR                      0
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_WORD_COUNT                       0x1
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_RESET_VAL                        _MK_MASK_CONST(0x100)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_RESET_MASK                       _MK_MASK_CONST(0x901f45ff)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_READ_MASK                        _MK_MASK_CONST(0x901f45ff)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_WRITE_MASK                       _MK_MASK_CONST(0x901f45ff)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_FORCE_IDLEPTTRN_SHIFT                    _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_FORCE_IDLEPTTRN_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_LINKCTL1_0_FORCE_IDLEPTTRN_SHIFT)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_FORCE_IDLEPTTRN_RANGE                    31:31
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_FORCE_IDLEPTTRN_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_FORCE_IDLEPTTRN_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_FORCE_IDLEPTTRN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_FORCE_IDLEPTTRN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_FORCE_IDLEPTTRN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_FORCE_IDLEPTTRN_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_FORCE_IDLEPTTRN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_FORCE_IDLEPTTRN_INIT_ENUM                        NO
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_FORCE_IDLEPTTRN_NO                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_FORCE_IDLEPTTRN_YES                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_COMPLIANCEPTTRN_SHIFT                    _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_COMPLIANCEPTTRN_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_LINKCTL1_0_COMPLIANCEPTTRN_SHIFT)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_COMPLIANCEPTTRN_RANGE                    28:28
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_COMPLIANCEPTTRN_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_COMPLIANCEPTTRN_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_COMPLIANCEPTTRN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_COMPLIANCEPTTRN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_COMPLIANCEPTTRN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_COMPLIANCEPTTRN_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_COMPLIANCEPTTRN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_COMPLIANCEPTTRN_INIT_ENUM                        NOPATTERN
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_COMPLIANCEPTTRN_NOPATTERN                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_COMPLIANCEPTTRN_COLORSQARE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_SHIFT                  _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_FIELD                  _MK_FIELD_CONST(0x1f, SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_SHIFT)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_RANGE                  20:16
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_INIT_ENUM                      ZERO
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_ZERO                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_ONE                    _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_TWO                    _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_FOUR                   _MK_ENUM_CONST(15)

#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENHANCEDFRAME_SHIFT                      _MK_SHIFT_CONST(14)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENHANCEDFRAME_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENHANCEDFRAME_SHIFT)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENHANCEDFRAME_RANGE                      14:14
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENHANCEDFRAME_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENHANCEDFRAME_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENHANCEDFRAME_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENHANCEDFRAME_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENHANCEDFRAME_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENHANCEDFRAME_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENHANCEDFRAME_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENHANCEDFRAME_INIT_ENUM                  DISABLE
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENHANCEDFRAME_DISABLE                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENHANCEDFRAME_ENABLE                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SYNCMODE_SHIFT                   _MK_SHIFT_CONST(10)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SYNCMODE_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SYNCMODE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SYNCMODE_RANGE                   10:10
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SYNCMODE_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SYNCMODE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SYNCMODE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SYNCMODE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SYNCMODE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SYNCMODE_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SYNCMODE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SYNCMODE_INIT_ENUM                       DISABLE
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SYNCMODE_DISABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SYNCMODE_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_TUSIZE_SHIFT                     _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_TUSIZE_FIELD                     _MK_FIELD_CONST(0x7f, SOR_NV_PDISP_SOR_DP_LINKCTL1_0_TUSIZE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_TUSIZE_RANGE                     8:2
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_TUSIZE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_TUSIZE_DEFAULT                   _MK_MASK_CONST(0x40)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_TUSIZE_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_TUSIZE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_TUSIZE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_TUSIZE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_TUSIZE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ASYNC_FIFO_BLOCK_SHIFT                   _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ASYNC_FIFO_BLOCK_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ASYNC_FIFO_BLOCK_SHIFT)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ASYNC_FIFO_BLOCK_RANGE                   1:1
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ASYNC_FIFO_BLOCK_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ASYNC_FIFO_BLOCK_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ASYNC_FIFO_BLOCK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ASYNC_FIFO_BLOCK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ASYNC_FIFO_BLOCK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ASYNC_FIFO_BLOCK_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ASYNC_FIFO_BLOCK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ASYNC_FIFO_BLOCK_INIT_ENUM                       NO
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ASYNC_FIFO_BLOCK_NO                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ASYNC_FIFO_BLOCK_YES                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENABLE_RANGE                     0:0
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENABLE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENABLE_INIT_ENUM                 NO
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENABLE_NO                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENABLE_YES                       _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0                  _MK_ADDR_CONST(0x4e)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_SECURE                   0x0
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_DUAL                     0x0
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_SCR                      0
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_WORD_COUNT                       0x1
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_SHIFT                     _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_RANGE                     31:24
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3__PROD_C_R_HDMI_0M_54M                     _MK_ENUM_CONST(51)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3__PROD_C_R_HDMI_54M_111M                   _MK_ENUM_CONST(51)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3__PROD_C_R_HDMI_111M_223M                  _MK_ENUM_CONST(55)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3__PROD_C_R_HDMI_223M_300M                  _MK_ENUM_CONST(51)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3__PROD_C_R_HDMI_300M_600M                  _MK_ENUM_CONST(51)

#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_SHIFT                     _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_RANGE                     23:16
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0__PROD_C_R_HDMI_0M_54M                     _MK_ENUM_CONST(58)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0__PROD_C_R_HDMI_54M_111M                   _MK_ENUM_CONST(58)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0__PROD_C_R_HDMI_111M_223M                  _MK_ENUM_CONST(58)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0__PROD_C_R_HDMI_223M_300M                  _MK_ENUM_CONST(61)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0__PROD_C_R_HDMI_300M_600M                  _MK_ENUM_CONST(61)

#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_SHIFT                     _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_RANGE                     15:8
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1__PROD_C_R_HDMI_0M_54M                     _MK_ENUM_CONST(58)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1__PROD_C_R_HDMI_54M_111M                   _MK_ENUM_CONST(58)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1__PROD_C_R_HDMI_111M_223M                  _MK_ENUM_CONST(58)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1__PROD_C_R_HDMI_223M_300M                  _MK_ENUM_CONST(61)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1__PROD_C_R_HDMI_300M_600M                  _MK_ENUM_CONST(61)

#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_RANGE                     7:0
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2__PROD_C_R_HDMI_0M_54M                     _MK_ENUM_CONST(58)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2__PROD_C_R_HDMI_54M_111M                   _MK_ENUM_CONST(58)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2__PROD_C_R_HDMI_111M_223M                  _MK_ENUM_CONST(58)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2__PROD_C_R_HDMI_223M_300M                  _MK_ENUM_CONST(61)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2__PROD_C_R_HDMI_300M_600M                  _MK_ENUM_CONST(61)

// Register SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0                  _MK_ADDR_CONST(0x4f)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_SECURE                   0x0
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_DUAL                     0x0
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_SCR                      0
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_WORD_COUNT                       0x1
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_SHIFT                     _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_RANGE                     31:24
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_SHIFT                     _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_RANGE                     23:16
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_SHIFT                     _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_RANGE                     15:8
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_RANGE                     7:0
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0                 _MK_ADDR_CONST(0x50)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_SCR                     0
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_LANE4_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_LANE4_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_LANE4_SHIFT)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_LANE4_RANGE                     7:0
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_LANE4_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_LANE4_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_LANE4_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_LANE4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_LANE4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_LANE4_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_LANE4_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0                 _MK_ADDR_CONST(0x51)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_SCR                     0
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_LANE4_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_LANE4_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_LANE4_SHIFT)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_LANE4_RANGE                     7:0
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_LANE4_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_LANE4_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_LANE4_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_LANE4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_LANE4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_LANE4_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_LANE4_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0                    _MK_ADDR_CONST(0x52)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_SCR                        0
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_SHIFT                       _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_FIELD                       _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_RANGE                       31:24
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3__PROD_C_R_HDMI_0M_54M                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3__PROD_C_R_HDMI_54M_111M                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3__PROD_C_R_HDMI_111M_223M                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3__PROD_C_R_HDMI_223M_300M                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3__PROD_C_R_HDMI_300M_600M                    _MK_ENUM_CONST(0)

#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_SHIFT                       _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_FIELD                       _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_RANGE                       23:16
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0__PROD_C_R_HDMI_0M_54M                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0__PROD_C_R_HDMI_54M_111M                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0__PROD_C_R_HDMI_111M_223M                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0__PROD_C_R_HDMI_223M_300M                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0__PROD_C_R_HDMI_300M_600M                    _MK_ENUM_CONST(0)

#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_SHIFT                       _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_FIELD                       _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_RANGE                       15:8
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1__PROD_C_R_HDMI_0M_54M                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1__PROD_C_R_HDMI_54M_111M                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1__PROD_C_R_HDMI_111M_223M                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1__PROD_C_R_HDMI_223M_300M                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1__PROD_C_R_HDMI_300M_600M                    _MK_ENUM_CONST(0)

#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_FIELD                       _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_RANGE                       7:0
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2__PROD_C_R_HDMI_0M_54M                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2__PROD_C_R_HDMI_54M_111M                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2__PROD_C_R_HDMI_111M_223M                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2__PROD_C_R_HDMI_223M_300M                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2__PROD_C_R_HDMI_300M_600M                    _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0                    _MK_ADDR_CONST(0x53)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_SCR                        0
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_SHIFT                       _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_FIELD                       _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_RANGE                       31:24
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_SHIFT                       _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_FIELD                       _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_RANGE                       23:16
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_SHIFT                       _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_FIELD                       _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_RANGE                       15:8
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_FIELD                       _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_SHIFT)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_RANGE                       7:0
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0                   _MK_ADDR_CONST(0x54)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_SCR                       0
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_RESET_MASK                        _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_READ_MASK                         _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_LANE4_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_LANE4_FIELD                       _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_LANE4_SHIFT)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_LANE4_RANGE                       7:0
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_LANE4_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_LANE4_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_LANE4_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_LANE4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_LANE4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_LANE4_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_LANE4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0                   _MK_ADDR_CONST(0x55)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_SCR                       0
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_RESET_MASK                        _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_READ_MASK                         _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_LANE4_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_LANE4_FIELD                       _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_LANE4_SHIFT)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_LANE4_RANGE                       7:0
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_LANE4_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_LANE4_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_LANE4_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_LANE4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_LANE4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_LANE4_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_LANE4_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_POSTCURSOR0_0
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0                  _MK_ADDR_CONST(0x56)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_SECURE                   0x0
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_DUAL                     0x0
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_SCR                      0
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_WORD_COUNT                       0x1
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE3_DP_LANE3_SHIFT                     _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE3_DP_LANE3_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE3_DP_LANE3_SHIFT)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE3_DP_LANE3_RANGE                     31:24
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE3_DP_LANE3_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE3_DP_LANE3_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE3_DP_LANE3_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE3_DP_LANE3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE3_DP_LANE3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE3_DP_LANE3_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE3_DP_LANE3_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE2_DP_LANE0_SHIFT                     _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE2_DP_LANE0_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE2_DP_LANE0_SHIFT)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE2_DP_LANE0_RANGE                     23:16
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE2_DP_LANE0_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE2_DP_LANE0_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE2_DP_LANE0_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE2_DP_LANE0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE2_DP_LANE0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE2_DP_LANE0_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE2_DP_LANE0_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE1_DP_LANE1_SHIFT                     _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE1_DP_LANE1_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE1_DP_LANE1_SHIFT)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE1_DP_LANE1_RANGE                     15:8
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE1_DP_LANE1_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE1_DP_LANE1_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE1_DP_LANE1_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE1_DP_LANE1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE1_DP_LANE1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE1_DP_LANE1_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE1_DP_LANE1_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE0_DP_LANE2_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE0_DP_LANE2_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE0_DP_LANE2_SHIFT)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE0_DP_LANE2_RANGE                     7:0
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE0_DP_LANE2_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE0_DP_LANE2_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE0_DP_LANE2_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE0_DP_LANE2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE0_DP_LANE2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE0_DP_LANE2_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE0_DP_LANE2_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_POSTCURSOR1_0
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0                  _MK_ADDR_CONST(0x57)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_SECURE                   0x0
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_DUAL                     0x0
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_SCR                      0
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_WORD_COUNT                       0x1
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE3_DP_LANE3_SHIFT                     _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE3_DP_LANE3_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE3_DP_LANE3_SHIFT)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE3_DP_LANE3_RANGE                     31:24
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE3_DP_LANE3_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE3_DP_LANE3_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE3_DP_LANE3_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE3_DP_LANE3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE3_DP_LANE3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE3_DP_LANE3_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE3_DP_LANE3_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE2_DP_LANE0_SHIFT                     _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE2_DP_LANE0_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE2_DP_LANE0_SHIFT)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE2_DP_LANE0_RANGE                     23:16
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE2_DP_LANE0_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE2_DP_LANE0_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE2_DP_LANE0_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE2_DP_LANE0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE2_DP_LANE0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE2_DP_LANE0_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE2_DP_LANE0_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE1_DP_LANE1_SHIFT                     _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE1_DP_LANE1_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE1_DP_LANE1_SHIFT)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE1_DP_LANE1_RANGE                     15:8
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE1_DP_LANE1_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE1_DP_LANE1_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE1_DP_LANE1_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE1_DP_LANE1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE1_DP_LANE1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE1_DP_LANE1_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE1_DP_LANE1_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE0_DP_LANE2_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE0_DP_LANE2_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE0_DP_LANE2_SHIFT)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE0_DP_LANE2_RANGE                     7:0
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE0_DP_LANE2_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE0_DP_LANE2_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE0_DP_LANE2_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE0_DP_LANE2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE0_DP_LANE2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE0_DP_LANE2_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE0_DP_LANE2_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_CONFIG0_0
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0                   _MK_ADDR_CONST(0x58)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_SCR                       0
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RESET_VAL                         _MK_MASK_CONST(0x94000000)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RESET_MASK                        _MK_MASK_CONST(0x950f7f3f)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_READ_MASK                         _MK_MASK_CONST(0x950f7f3f)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WRITE_MASK                        _MK_MASK_CONST(0x950f7f3f)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RD_RESET_VAL_SHIFT                        _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RD_RESET_VAL_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_CONFIG0_0_RD_RESET_VAL_SHIFT)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RD_RESET_VAL_RANGE                        31:31
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RD_RESET_VAL_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RD_RESET_VAL_DEFAULT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RD_RESET_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RD_RESET_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RD_RESET_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RD_RESET_VAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RD_RESET_VAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RD_RESET_VAL_INIT_ENUM                    NEGATIVE
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RD_RESET_VAL_POSITIVE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RD_RESET_VAL_NEGATIVE                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_IDLE_BEFORE_ATTACH_SHIFT                  _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_IDLE_BEFORE_ATTACH_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_CONFIG0_0_IDLE_BEFORE_ATTACH_SHIFT)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_IDLE_BEFORE_ATTACH_RANGE                  28:28
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_IDLE_BEFORE_ATTACH_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_IDLE_BEFORE_ATTACH_DEFAULT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_IDLE_BEFORE_ATTACH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_IDLE_BEFORE_ATTACH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_IDLE_BEFORE_ATTACH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_IDLE_BEFORE_ATTACH_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_IDLE_BEFORE_ATTACH_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_IDLE_BEFORE_ATTACH_INIT_ENUM                      ENABLE
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_IDLE_BEFORE_ATTACH_DISABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_IDLE_BEFORE_ATTACH_ENABLE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_CNTL_SHIFT                      _MK_SHIFT_CONST(26)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_CNTL_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_CNTL_SHIFT)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_CNTL_RANGE                      26:26
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_CNTL_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_CNTL_DEFAULT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_CNTL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_CNTL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_CNTL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_CNTL_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_CNTL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_CNTL_INIT_ENUM                  ENABLE
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_CNTL_DISABLE                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_CNTL_ENABLE                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_SHIFT                  _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_SHIFT)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_RANGE                  24:24
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_INIT_ENUM                      NEGATIVE
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_NEGATIVE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_POSITIVE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_SHIFT                      _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_FIELD                      _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_SHIFT)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_RANGE                      19:16
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_SHIFT                     _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_FIELD                     _MK_FIELD_CONST(0x7f, SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_SHIFT)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_RANGE                     14:8
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_FIELD                   _MK_FIELD_CONST(0x3f, SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_SHIFT)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_RANGE                   5:0
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_CONFIG1_0
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0                   _MK_ADDR_CONST(0x59)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_SCR                       0
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RESET_VAL                         _MK_MASK_CONST(0x94000000)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RESET_MASK                        _MK_MASK_CONST(0x950f7f3f)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_READ_MASK                         _MK_MASK_CONST(0x950f7f3f)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_WRITE_MASK                        _MK_MASK_CONST(0x950f7f3f)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RD_RESET_VAL_SHIFT                        _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RD_RESET_VAL_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_CONFIG1_0_RD_RESET_VAL_SHIFT)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RD_RESET_VAL_RANGE                        31:31
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RD_RESET_VAL_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RD_RESET_VAL_DEFAULT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RD_RESET_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RD_RESET_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RD_RESET_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RD_RESET_VAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RD_RESET_VAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RD_RESET_VAL_INIT_ENUM                    NEGATIVE
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RD_RESET_VAL_POSITIVE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RD_RESET_VAL_NEGATIVE                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_IDLE_BEFORE_ATTACH_SHIFT                  _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_IDLE_BEFORE_ATTACH_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_CONFIG1_0_IDLE_BEFORE_ATTACH_SHIFT)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_IDLE_BEFORE_ATTACH_RANGE                  28:28
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_IDLE_BEFORE_ATTACH_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_IDLE_BEFORE_ATTACH_DEFAULT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_IDLE_BEFORE_ATTACH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_IDLE_BEFORE_ATTACH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_IDLE_BEFORE_ATTACH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_IDLE_BEFORE_ATTACH_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_IDLE_BEFORE_ATTACH_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_IDLE_BEFORE_ATTACH_INIT_ENUM                      ENABLE
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_IDLE_BEFORE_ATTACH_DISABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_IDLE_BEFORE_ATTACH_ENABLE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_CNTL_SHIFT                      _MK_SHIFT_CONST(26)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_CNTL_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_CNTL_SHIFT)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_CNTL_RANGE                      26:26
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_CNTL_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_CNTL_DEFAULT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_CNTL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_CNTL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_CNTL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_CNTL_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_CNTL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_CNTL_INIT_ENUM                  ENABLE
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_CNTL_DISABLE                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_CNTL_ENABLE                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_POLARITY_SHIFT                  _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_POLARITY_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_POLARITY_SHIFT)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_POLARITY_RANGE                  24:24
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_POLARITY_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_POLARITY_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_POLARITY_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_POLARITY_INIT_ENUM                      NEGATIVE
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_POLARITY_NEGATIVE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_POLARITY_POSITIVE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_FRAC_SHIFT                      _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_FRAC_FIELD                      _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_FRAC_SHIFT)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_FRAC_RANGE                      19:16
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_FRAC_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_FRAC_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_FRAC_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_FRAC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_FRAC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_FRAC_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_FRAC_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_COUNT_SHIFT                     _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_COUNT_FIELD                     _MK_FIELD_CONST(0x7f, SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_COUNT_SHIFT)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_COUNT_RANGE                     14:8
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_COUNT_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_COUNT_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_COUNT_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_COUNT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_WATERMARK_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_WATERMARK_FIELD                   _MK_FIELD_CONST(0x3f, SOR_NV_PDISP_SOR_DP_CONFIG1_0_WATERMARK_SHIFT)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_WATERMARK_RANGE                   5:0
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_WATERMARK_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_WATERMARK_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_WATERMARK_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_WATERMARK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_WATERMARK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_WATERMARK_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_WATERMARK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_MN0_0
#define SOR_NV_PDISP_SOR_DP_MN0_0                       _MK_ADDR_CONST(0x5a)
#define SOR_NV_PDISP_SOR_DP_MN0_0_SECURE                        0x0
#define SOR_NV_PDISP_SOR_DP_MN0_0_DUAL                  0x0
#define SOR_NV_PDISP_SOR_DP_MN0_0_SCR                   0
#define SOR_NV_PDISP_SOR_DP_MN0_0_WORD_COUNT                    0x1
#define SOR_NV_PDISP_SOR_DP_MN0_0_RESET_VAL                     _MK_MASK_CONST(0x8000)
#define SOR_NV_PDISP_SOR_DP_MN0_0_RESET_MASK                    _MK_MASK_CONST(0xcfffffff)
#define SOR_NV_PDISP_SOR_DP_MN0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MN0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MN0_0_READ_MASK                     _MK_MASK_CONST(0xcfffffff)
#define SOR_NV_PDISP_SOR_DP_MN0_0_WRITE_MASK                    _MK_MASK_CONST(0xcfffffff)
#define SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_SHIFT                   _MK_SHIFT_CONST(30)
#define SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_FIELD                   _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_SHIFT)
#define SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_RANGE                   31:30
#define SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_INIT_ENUM                       NONE
#define SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_NONE                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_INC                     _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_DEC                     _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_DP_MN0_0_M_DELTA_SHIFT                 _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_DP_MN0_0_M_DELTA_FIELD                 _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_MN0_0_M_DELTA_SHIFT)
#define SOR_NV_PDISP_SOR_DP_MN0_0_M_DELTA_RANGE                 27:24
#define SOR_NV_PDISP_SOR_DP_MN0_0_M_DELTA_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_DP_MN0_0_M_DELTA_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MN0_0_M_DELTA_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_DP_MN0_0_M_DELTA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MN0_0_M_DELTA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MN0_0_M_DELTA_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_MN0_0_M_DELTA_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_MN0_0_N_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_MN0_0_N_VAL_FIELD                   _MK_FIELD_CONST(0xffffff, SOR_NV_PDISP_SOR_DP_MN0_0_N_VAL_SHIFT)
#define SOR_NV_PDISP_SOR_DP_MN0_0_N_VAL_RANGE                   23:0
#define SOR_NV_PDISP_SOR_DP_MN0_0_N_VAL_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_MN0_0_N_VAL_DEFAULT                 _MK_MASK_CONST(0x8000)
#define SOR_NV_PDISP_SOR_DP_MN0_0_N_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_DP_MN0_0_N_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MN0_0_N_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MN0_0_N_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_MN0_0_N_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_MN1_0
#define SOR_NV_PDISP_SOR_DP_MN1_0                       _MK_ADDR_CONST(0x5b)
#define SOR_NV_PDISP_SOR_DP_MN1_0_SECURE                        0x0
#define SOR_NV_PDISP_SOR_DP_MN1_0_DUAL                  0x0
#define SOR_NV_PDISP_SOR_DP_MN1_0_SCR                   0
#define SOR_NV_PDISP_SOR_DP_MN1_0_WORD_COUNT                    0x1
#define SOR_NV_PDISP_SOR_DP_MN1_0_RESET_VAL                     _MK_MASK_CONST(0x8000)
#define SOR_NV_PDISP_SOR_DP_MN1_0_RESET_MASK                    _MK_MASK_CONST(0xcfffffff)
#define SOR_NV_PDISP_SOR_DP_MN1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MN1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MN1_0_READ_MASK                     _MK_MASK_CONST(0xcfffffff)
#define SOR_NV_PDISP_SOR_DP_MN1_0_WRITE_MASK                    _MK_MASK_CONST(0xcfffffff)
#define SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_SHIFT                   _MK_SHIFT_CONST(30)
#define SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_FIELD                   _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_SHIFT)
#define SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_RANGE                   31:30
#define SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_INIT_ENUM                       NONE
#define SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_NONE                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_INC                     _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_DEC                     _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_DP_MN1_0_M_DELTA_SHIFT                 _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_DP_MN1_0_M_DELTA_FIELD                 _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_MN1_0_M_DELTA_SHIFT)
#define SOR_NV_PDISP_SOR_DP_MN1_0_M_DELTA_RANGE                 27:24
#define SOR_NV_PDISP_SOR_DP_MN1_0_M_DELTA_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_DP_MN1_0_M_DELTA_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MN1_0_M_DELTA_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_DP_MN1_0_M_DELTA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MN1_0_M_DELTA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MN1_0_M_DELTA_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_MN1_0_M_DELTA_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_MN1_0_N_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_MN1_0_N_VAL_FIELD                   _MK_FIELD_CONST(0xffffff, SOR_NV_PDISP_SOR_DP_MN1_0_N_VAL_SHIFT)
#define SOR_NV_PDISP_SOR_DP_MN1_0_N_VAL_RANGE                   23:0
#define SOR_NV_PDISP_SOR_DP_MN1_0_N_VAL_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_MN1_0_N_VAL_DEFAULT                 _MK_MASK_CONST(0x8000)
#define SOR_NV_PDISP_SOR_DP_MN1_0_N_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_DP_MN1_0_N_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MN1_0_N_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MN1_0_N_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_MN1_0_N_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_DEBUG0_0
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0                    _MK_ADDR_CONST(0x5e)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SCR                        0
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_RESET_MASK                         _MK_MASK_CONST(0x1ffff)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_READ_MASK                  _MK_MASK_CONST(0x1ffff)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_WRITE_MASK                         _MK_MASK_CONST(0x1ffff)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_SHIFT                  _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_RANGE                  16:16
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_INIT_ENUM                      NO
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_NO                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_YES                    _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_RST                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_SHIFT                  _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_RANGE                  15:15
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_INIT_ENUM                      NO
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_NO                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_YES                    _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_RST                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_SHIFT                  _MK_SHIFT_CONST(14)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_RANGE                  14:14
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_INIT_ENUM                      NO
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_NO                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_YES                    _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_RST                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_SHIFT                  _MK_SHIFT_CONST(13)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_RANGE                  13:13
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_INIT_ENUM                      NO
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_NO                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_YES                    _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_RST                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_SHIFT                 _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_RANGE                 12:12
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_INIT_ENUM                     NO
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_NO                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_YES                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_RST                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_SHIFT                    _MK_SHIFT_CONST(11)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_RANGE                    11:11
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_INIT_ENUM                        NO
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_NO                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_YES                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_RST                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_SHIFT                    _MK_SHIFT_CONST(10)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_RANGE                    10:10
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_INIT_ENUM                        NO
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_NO                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_YES                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_RST                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_SHIFT                    _MK_SHIFT_CONST(9)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_RANGE                    9:9
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_INIT_ENUM                        NO
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_NO                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_YES                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_RST                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_SHIFT                    _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_RANGE                    8:8
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_INIT_ENUM                        NO
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_NO                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_YES                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_RST                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_SHIFT                       _MK_SHIFT_CONST(7)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_RANGE                       7:7
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_YES                 _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_RST                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_SHIFT                       _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_RANGE                       6:6
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_YES                 _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_RST                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_SHIFT                       _MK_SHIFT_CONST(5)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_RANGE                       5:5
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_YES                 _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_RST                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_SHIFT                       _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_RANGE                       4:4
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_YES                 _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_RST                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_SHIFT                 _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_RANGE                 3:3
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_INIT_ENUM                     NO
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_NO                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_YES                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_RST                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_SHIFT                 _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_RANGE                 2:2
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_INIT_ENUM                     NO
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_NO                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_YES                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_RST                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_SHIFT                 _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_RANGE                 1:1
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_INIT_ENUM                     NO
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_NO                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_YES                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_RST                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_RANGE                 0:0
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_INIT_ENUM                     NO
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_NO                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_YES                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_RST                   _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_DP_DEBUG1_0
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0                    _MK_ADDR_CONST(0x5f)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SCR                        0
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_RESET_MASK                         _MK_MASK_CONST(0x1ffff)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_READ_MASK                  _MK_MASK_CONST(0x1ffff)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_WRITE_MASK                         _MK_MASK_CONST(0x1ffff)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_SHIFT                  _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_RANGE                  16:16
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_INIT_ENUM                      NO
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_NO                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_YES                    _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_RST                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_SHIFT                  _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_RANGE                  15:15
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_INIT_ENUM                      NO
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_NO                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_YES                    _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_RST                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_SHIFT                  _MK_SHIFT_CONST(14)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_RANGE                  14:14
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_INIT_ENUM                      NO
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_NO                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_YES                    _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_RST                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_SHIFT                  _MK_SHIFT_CONST(13)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_RANGE                  13:13
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_INIT_ENUM                      NO
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_NO                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_YES                    _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_RST                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_SHIFT                 _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_RANGE                 12:12
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_INIT_ENUM                     NO
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_NO                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_YES                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_RST                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_SHIFT                    _MK_SHIFT_CONST(11)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_RANGE                    11:11
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_INIT_ENUM                        NO
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_NO                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_YES                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_RST                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_SHIFT                    _MK_SHIFT_CONST(10)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_RANGE                    10:10
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_INIT_ENUM                        NO
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_NO                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_YES                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_RST                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_SHIFT                    _MK_SHIFT_CONST(9)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_RANGE                    9:9
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_INIT_ENUM                        NO
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_NO                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_YES                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_RST                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_SHIFT                    _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_RANGE                    8:8
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_INIT_ENUM                        NO
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_NO                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_YES                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_RST                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_SHIFT                       _MK_SHIFT_CONST(7)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_RANGE                       7:7
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_YES                 _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_RST                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_SHIFT                       _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_RANGE                       6:6
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_YES                 _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_RST                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_SHIFT                       _MK_SHIFT_CONST(5)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_RANGE                       5:5
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_YES                 _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_RST                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_SHIFT                       _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_RANGE                       4:4
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_YES                 _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_RST                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_SHIFT                 _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_RANGE                 3:3
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_INIT_ENUM                     NO
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_NO                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_YES                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_RST                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_SHIFT                 _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_RANGE                 2:2
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_INIT_ENUM                     NO
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_NO                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_YES                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_RST                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_SHIFT                 _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_RANGE                 1:1
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_INIT_ENUM                     NO
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_NO                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_YES                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_RST                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_SHIFT)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_RANGE                 0:0
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_INIT_ENUM                     NO
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_NO                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_YES                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_RST                   _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_DP_SPARE0_0
#define SOR_NV_PDISP_SOR_DP_SPARE0_0                    _MK_ADDR_CONST(0x60)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SCR                        0
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_RESET_VAL                  _MK_MASK_CONST(0x40000002)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_RESET_MASK                         _MK_MASK_CONST(0xfffff00f)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_WRITE_MASK                         _MK_MASK_CONST(0xfffff00f)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_PSR_DIABLE_CYA_SHIFT                   _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_PSR_DIABLE_CYA_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_PSR_DIABLE_CYA_SHIFT)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_PSR_DIABLE_CYA_RANGE                   31:31
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_PSR_DIABLE_CYA_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_PSR_DIABLE_CYA_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_PSR_DIABLE_CYA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_PSR_DIABLE_CYA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_PSR_DIABLE_CYA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_PSR_DIABLE_CYA_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_PSR_DIABLE_CYA_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_PSR_DIABLE_CYA_INIT_ENUM                       DISABLE
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_PSR_DIABLE_CYA_DISABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_PSR_DIABLE_CYA_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_MSA_SOURCE_SEL_SHIFT                   _MK_SHIFT_CONST(30)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_MSA_SOURCE_SEL_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_MSA_SOURCE_SEL_SHIFT)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_MSA_SOURCE_SEL_RANGE                   30:30
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_MSA_SOURCE_SEL_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_MSA_SOURCE_SEL_DEFAULT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_MSA_SOURCE_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_MSA_SOURCE_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_MSA_SOURCE_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_MSA_SOURCE_SEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_MSA_SOURCE_SEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_MSA_SOURCE_SEL_INIT_ENUM                       RG
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_MSA_SOURCE_SEL_SOR                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_MSA_SOURCE_SEL_RG                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_SPARE0_0_REG_SHIFT                  _MK_SHIFT_CONST(14)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_REG_FIELD                  _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_DP_SPARE0_0_REG_SHIFT)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_REG_RANGE                  29:14
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_REG_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_REG_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_REG_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_REG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_REG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_REG_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_REG_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DEBUG_MODE_SHIFT                   _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DEBUG_MODE_FIELD                   _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_DP_SPARE0_0_DEBUG_MODE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DEBUG_MODE_RANGE                   13:12
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DEBUG_MODE_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DEBUG_MODE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DEBUG_MODE_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DEBUG_MODE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DEBUG_MODE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DEBUG_MODE_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DEBUG_MODE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DEBUG_OUT_SHIFT                    _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DEBUG_OUT_FIELD                    _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_SPARE0_0_DEBUG_OUT_SHIFT)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DEBUG_OUT_RANGE                    11:4
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DEBUG_OUT_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DEBUG_OUT_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DEBUG_OUT_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DEBUG_OUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DEBUG_OUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DEBUG_OUT_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DEBUG_OUT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DISP_VIDEO_PREAMBLE_CYA_SHIFT                      _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DISP_VIDEO_PREAMBLE_CYA_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_SPARE0_0_DISP_VIDEO_PREAMBLE_CYA_SHIFT)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DISP_VIDEO_PREAMBLE_CYA_RANGE                      3:3
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DISP_VIDEO_PREAMBLE_CYA_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DISP_VIDEO_PREAMBLE_CYA_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DISP_VIDEO_PREAMBLE_CYA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DISP_VIDEO_PREAMBLE_CYA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DISP_VIDEO_PREAMBLE_CYA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DISP_VIDEO_PREAMBLE_CYA_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DISP_VIDEO_PREAMBLE_CYA_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DISP_VIDEO_PREAMBLE_CYA_INIT_ENUM                  DISABLE
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DISP_VIDEO_PREAMBLE_CYA_DISABLE                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_DISP_VIDEO_PREAMBLE_CYA_ENABLE                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_CLK_SEL_SHIFT                  _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_CLK_SEL_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_CLK_SEL_SHIFT)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_CLK_SEL_RANGE                  2:2
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_CLK_SEL_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_CLK_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_CLK_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_CLK_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_CLK_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_CLK_SEL_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_CLK_SEL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_CLK_SEL_INIT_ENUM                      SAFE_SORCLK
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_CLK_SEL_SAFE_SORCLK                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_CLK_SEL_MACRO_SORCLK                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_SPARE0_0_PANEL_SHIFT                        _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_PANEL_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_SPARE0_0_PANEL_SHIFT)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_PANEL_RANGE                        1:1
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_PANEL_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_PANEL_DEFAULT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_PANEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_PANEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_PANEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_PANEL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_PANEL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_PANEL_INIT_ENUM                    INTERNAL
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_PANEL_EXTERNAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_PANEL_INTERNAL                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SEQ_ENABLE_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SEQ_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_SPARE0_0_SEQ_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SEQ_ENABLE_RANGE                   0:0
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SEQ_ENABLE_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SEQ_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SEQ_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SEQ_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SEQ_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SEQ_ENABLE_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SEQ_ENABLE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SEQ_ENABLE_INIT_ENUM                       NO
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SEQ_ENABLE_NO                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SEQ_ENABLE_YES                     _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_DP_SPARE1_0
#define SOR_NV_PDISP_SOR_DP_SPARE1_0                    _MK_ADDR_CONST(0x61)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SCR                        0
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_REG_SHIFT                  _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_REG_FIELD                  _MK_FIELD_CONST(0xfffffff, SOR_NV_PDISP_SOR_DP_SPARE1_0_REG_SHIFT)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_REG_RANGE                  31:4
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_REG_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_REG_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_REG_DEFAULT_MASK                   _MK_MASK_CONST(0xfffffff)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_REG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_REG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_REG_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_REG_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_OVR_ON_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_OVR_ON_SHIFT)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_OVR_ON_RANGE                       3:3
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_OVR_ON_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_OVR_ON_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_OVR_ON_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_OVR_ON_INIT_ENUM                   FALSE
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_OVR_ON_TRUE                        _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_OVR_ON_FALSE                       _MK_ENUM_CONST(0)

#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_SEL_SHIFT                  _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_SEL_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_SEL_SHIFT)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_SEL_RANGE                  2:2
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_SEL_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_SEL_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_SEL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_SEL_INIT_ENUM                      SAFE_SORCLK
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_SEL_SAFE_SORCLK                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_SEL_MACRO_SORCLK                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_SPARE1_0_PANEL_SHIFT                        _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_PANEL_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_SPARE1_0_PANEL_SHIFT)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_PANEL_RANGE                        1:1
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_PANEL_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_PANEL_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_PANEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_PANEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_PANEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_PANEL_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_PANEL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_PANEL_INIT_ENUM                    EXTERNAL
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_PANEL_EXTERNAL                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_PANEL_INTERNAL                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SEQ_ENABLE_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SEQ_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_SPARE1_0_SEQ_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SEQ_ENABLE_RANGE                   0:0
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SEQ_ENABLE_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SEQ_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SEQ_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SEQ_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SEQ_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SEQ_ENABLE_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SEQ_ENABLE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SEQ_ENABLE_INIT_ENUM                       NO
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SEQ_ENABLE_NO                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SEQ_ENABLE_YES                     _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0                        _MK_ADDR_CONST(0x62)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SECURE                         0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_DUAL                   0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SCR                    0
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_WORD_COUNT                     0x1
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_RESET_VAL                      _MK_MASK_CONST(0x1f0001)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_RESET_MASK                     _MK_MASK_CONST(0x801fffcd)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_READ_MASK                      _MK_MASK_CONST(0x803fffcd)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_WRITE_MASK                     _MK_MASK_CONST(0x801fffcd)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_SHIFT                     _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_RANGE                     31:31
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_INIT_ENUM                 DONE
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_DONE                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_PENDING                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_TRIGGER                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_STATUS_SHIFT                      _MK_SHIFT_CONST(21)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_STATUS_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_STATUS_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_STATUS_RANGE                      21:21
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_STATUS_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_STATUS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_STATUS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_STATUS_DISABLE                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_STATUS_ENABLE                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CA_SELECT_SHIFT                        _MK_SHIFT_CONST(20)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CA_SELECT_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CA_SELECT_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CA_SELECT_RANGE                        20:20
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CA_SELECT_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CA_SELECT_DEFAULT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CA_SELECT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CA_SELECT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CA_SELECT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CA_SELECT_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CA_SELECT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CA_SELECT_INIT_ENUM                    HW
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CA_SELECT_SW                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CA_SELECT_HW                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SS_SELECT_SHIFT                        _MK_SHIFT_CONST(19)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SS_SELECT_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SS_SELECT_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SS_SELECT_RANGE                        19:19
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SS_SELECT_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SS_SELECT_DEFAULT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SS_SELECT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SS_SELECT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SS_SELECT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SS_SELECT_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SS_SELECT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SS_SELECT_INIT_ENUM                    HW
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SS_SELECT_SW                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SS_SELECT_HW                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SF_SELECT_SHIFT                        _MK_SHIFT_CONST(18)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SF_SELECT_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SF_SELECT_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SF_SELECT_RANGE                        18:18
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SF_SELECT_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SF_SELECT_DEFAULT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SF_SELECT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SF_SELECT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SF_SELECT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SF_SELECT_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SF_SELECT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SF_SELECT_INIT_ENUM                    HW
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SF_SELECT_SW                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SF_SELECT_HW                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CC_SELECT_SHIFT                        _MK_SHIFT_CONST(17)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CC_SELECT_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CC_SELECT_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CC_SELECT_RANGE                        17:17
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CC_SELECT_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CC_SELECT_DEFAULT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CC_SELECT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CC_SELECT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CC_SELECT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CC_SELECT_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CC_SELECT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CC_SELECT_INIT_ENUM                    HW
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CC_SELECT_SW                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CC_SELECT_HW                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CT_SELECT_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CT_SELECT_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CT_SELECT_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CT_SELECT_RANGE                        16:16
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CT_SELECT_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CT_SELECT_DEFAULT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CT_SELECT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CT_SELECT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CT_SELECT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CT_SELECT_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CT_SELECT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CT_SELECT_INIT_ENUM                    HW
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CT_SELECT_SW                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CT_SELECT_HW                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_PACKET_ID_SHIFT                        _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_PACKET_ID_FIELD                        _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_PACKET_ID_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_PACKET_ID_RANGE                        15:8
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_PACKET_ID_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_PACKET_ID_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_PACKET_ID_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_PACKET_ID_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_PACKET_ID_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_PACKET_ID_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_PACKET_ID_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_GENERIC_INFOFRAME_ENABLE_SHIFT                 _MK_SHIFT_CONST(7)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_GENERIC_INFOFRAME_ENABLE_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_GENERIC_INFOFRAME_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_GENERIC_INFOFRAME_ENABLE_RANGE                 7:7
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_GENERIC_INFOFRAME_ENABLE_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_GENERIC_INFOFRAME_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_GENERIC_INFOFRAME_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_GENERIC_INFOFRAME_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_GENERIC_INFOFRAME_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_GENERIC_INFOFRAME_ENABLE_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_GENERIC_INFOFRAME_ENABLE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_GENERIC_INFOFRAME_ENABLE_INIT_ENUM                     NO
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_GENERIC_INFOFRAME_ENABLE_NO                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_GENERIC_INFOFRAME_ENABLE_YES                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_INFOFRAME_HEADER_OVERRIDE_SHIFT                        _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_INFOFRAME_HEADER_OVERRIDE_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_INFOFRAME_HEADER_OVERRIDE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_INFOFRAME_HEADER_OVERRIDE_RANGE                        6:6
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_INFOFRAME_HEADER_OVERRIDE_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_INFOFRAME_HEADER_OVERRIDE_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_INFOFRAME_HEADER_OVERRIDE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_INFOFRAME_HEADER_OVERRIDE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_INFOFRAME_HEADER_OVERRIDE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_INFOFRAME_HEADER_OVERRIDE_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_INFOFRAME_HEADER_OVERRIDE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_INFOFRAME_HEADER_OVERRIDE_INIT_ENUM                    DISABLE
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_INFOFRAME_HEADER_OVERRIDE_DISABLE                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_INFOFRAME_HEADER_OVERRIDE_ENABLE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_SHIFT                     _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_FIELD                     _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_RANGE                     3:2
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_INIT_ENUM                 AUTO
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_AUTO                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_DISABLE                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_ENABLE                    _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_ENABLE_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_ENABLE_RANGE                   0:0
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_ENABLE_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_ENABLE_DEFAULT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_ENABLE_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_ENABLE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_ENABLE_INIT_ENUM                       YES
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_ENABLE_NO                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_ENABLE_YES                     _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0
#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0                      _MK_ADDR_CONST(0x63)
#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_SCR                  0
#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_RESET_MASK                   _MK_MASK_CONST(0x1ffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_READ_MASK                    _MK_MASK_CONST(0x1ffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_WRITE_MASK                   _MK_MASK_CONST(0x1ffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_VALUE_FIELD                  _MK_FIELD_CONST(0x1ffff, SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_VALUE_RANGE                  16:0
#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_VALUE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0x1ffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_VALUE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_VALUE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0
#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0                      _MK_ADDR_CONST(0x64)
#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_SCR                  0
#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_RESET_MASK                   _MK_MASK_CONST(0x1fffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_READ_MASK                    _MK_MASK_CONST(0x1fffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_WRITE_MASK                   _MK_MASK_CONST(0x1fffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_VALUE_FIELD                  _MK_FIELD_CONST(0x1fffff, SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_VALUE_RANGE                  20:0
#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_VALUE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0x1fffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_VALUE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_VALUE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0                  _MK_ADDR_CONST(0x65)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_SECURE                   0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_DUAL                     0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_SCR                      0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_WORD_COUNT                       0x1
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB3_SHIFT                        _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB3_FIELD                        _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB3_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB3_RANGE                        31:24
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB3_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB3_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB3_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB3_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB2_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB2_FIELD                        _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB2_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB2_RANGE                        23:16
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB2_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB2_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB2_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB2_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB1_SHIFT                        _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB1_FIELD                        _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB1_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB1_RANGE                        15:8
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB1_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB1_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB1_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB1_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB0_SHIFT                        _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB0_FIELD                        _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB0_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB0_RANGE                        7:0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB0_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB0_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB0_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB0_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB0_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0                        _MK_ADDR_CONST(0x66)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_SECURE                         0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DUAL                   0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_SCR                    0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_WORD_COUNT                     0x1
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB3_SHIFT                      _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB3_FIELD                      _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB3_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB3_RANGE                      31:24
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB3_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB3_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB3_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB3_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB3_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB2_SHIFT                      _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB2_FIELD                      _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB2_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB2_RANGE                      23:16
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB2_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB2_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB2_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB2_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB2_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB1_SHIFT                      _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB1_FIELD                      _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB1_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB1_RANGE                      15:8
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB1_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB1_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB1_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB1_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB1_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB0_SHIFT                      _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB0_FIELD                      _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB0_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB0_RANGE                      7:0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB0_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB0_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB0_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB0_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB0_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0                        _MK_ADDR_CONST(0x67)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_SECURE                         0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DUAL                   0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_SCR                    0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_WORD_COUNT                     0x1
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB7_SHIFT                      _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB7_FIELD                      _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB7_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB7_RANGE                      31:24
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB7_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB7_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB7_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB7_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB7_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB6_SHIFT                      _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB6_FIELD                      _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB6_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB6_RANGE                      23:16
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB6_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB6_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB6_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB6_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB6_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB5_SHIFT                      _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB5_FIELD                      _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB5_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB5_RANGE                      15:8
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB5_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB5_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB5_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB5_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB5_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB4_SHIFT                      _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB4_FIELD                      _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB4_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB4_RANGE                      7:0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB4_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB4_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB4_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB4_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB4_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0                        _MK_ADDR_CONST(0x68)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_SECURE                         0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DUAL                   0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_SCR                    0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_WORD_COUNT                     0x1
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB11_SHIFT                     _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB11_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB11_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB11_RANGE                     31:24
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB11_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB11_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB11_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB11_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB11_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB11_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB11_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB10_SHIFT                     _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB10_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB10_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB10_RANGE                     23:16
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB10_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB10_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB10_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB10_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB10_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB10_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB10_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB9_SHIFT                      _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB9_FIELD                      _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB9_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB9_RANGE                      15:8
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB9_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB9_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB9_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB9_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB9_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB9_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB9_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB8_SHIFT                      _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB8_FIELD                      _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB8_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB8_RANGE                      7:0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB8_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB8_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB8_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB8_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB8_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB8_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB8_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0                        _MK_ADDR_CONST(0x69)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_SECURE                         0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DUAL                   0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_SCR                    0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_WORD_COUNT                     0x1
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB15_SHIFT                     _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB15_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB15_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB15_RANGE                     31:24
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB15_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB15_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB15_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB15_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB15_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB15_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB15_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB14_SHIFT                     _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB14_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB14_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB14_RANGE                     23:16
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB14_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB14_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB14_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB14_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB14_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB14_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB14_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB13_SHIFT                     _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB13_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB13_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB13_RANGE                     15:8
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB13_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB13_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB13_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB13_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB13_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB13_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB13_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB12_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB12_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB12_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB12_RANGE                     7:0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB12_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB12_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB12_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB12_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB12_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB12_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB12_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0                        _MK_ADDR_CONST(0x6a)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_SECURE                         0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DUAL                   0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_SCR                    0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_WORD_COUNT                     0x1
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB19_SHIFT                     _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB19_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB19_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB19_RANGE                     31:24
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB19_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB19_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB19_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB19_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB19_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB19_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB19_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB18_SHIFT                     _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB18_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB18_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB18_RANGE                     23:16
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB18_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB18_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB18_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB18_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB18_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB18_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB18_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB17_SHIFT                     _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB17_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB17_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB17_RANGE                     15:8
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB17_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB17_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB17_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB17_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB17_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB17_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB17_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB16_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB16_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB16_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB16_RANGE                     7:0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB16_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB16_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB16_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB16_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB16_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB16_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB16_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0                        _MK_ADDR_CONST(0x6b)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_SECURE                         0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DUAL                   0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_SCR                    0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_WORD_COUNT                     0x1
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB23_SHIFT                     _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB23_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB23_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB23_RANGE                     31:24
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB23_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB23_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB23_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB23_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB23_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB23_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB23_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB22_SHIFT                     _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB22_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB22_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB22_RANGE                     23:16
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB22_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB22_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB22_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB22_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB22_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB22_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB22_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB21_SHIFT                     _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB21_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB21_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB21_RANGE                     15:8
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB21_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB21_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB21_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB21_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB21_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB21_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB21_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB20_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB20_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB20_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB20_RANGE                     7:0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB20_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB20_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB20_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB20_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB20_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB20_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB20_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0                        _MK_ADDR_CONST(0x6c)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_SECURE                         0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DUAL                   0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_SCR                    0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_WORD_COUNT                     0x1
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB27_SHIFT                     _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB27_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB27_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB27_RANGE                     31:24
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB27_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB27_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB27_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB27_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB27_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB27_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB27_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB26_SHIFT                     _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB26_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB26_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB26_RANGE                     23:16
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB26_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB26_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB26_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB26_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB26_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB26_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB26_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB25_SHIFT                     _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB25_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB25_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB25_RANGE                     15:8
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB25_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB25_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB25_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB25_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB25_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB25_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB25_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB24_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB24_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB24_SHIFT)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB24_RANGE                     7:0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB24_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB24_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB24_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB24_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB24_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB24_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB24_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_TPG_0
#define SOR_NV_PDISP_SOR_DP_TPG_0                       _MK_ADDR_CONST(0x6d)
#define SOR_NV_PDISP_SOR_DP_TPG_0_SECURE                        0x0
#define SOR_NV_PDISP_SOR_DP_TPG_0_DUAL                  0x0
#define SOR_NV_PDISP_SOR_DP_TPG_0_SCR                   0
#define SOR_NV_PDISP_SOR_DP_TPG_0_WORD_COUNT                    0x1
#define SOR_NV_PDISP_SOR_DP_TPG_0_RESET_VAL                     _MK_MASK_CONST(0x50505050)
#define SOR_NV_PDISP_SOR_DP_TPG_0_RESET_MASK                    _MK_MASK_CONST(0x7f7f7f7f)
#define SOR_NV_PDISP_SOR_DP_TPG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_READ_MASK                     _MK_MASK_CONST(0x7f7f7f7f)
#define SOR_NV_PDISP_SOR_DP_TPG_0_WRITE_MASK                    _MK_MASK_CONST(0x7f7f7f7f)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_CHANNELCODING_SHIFT                     _MK_SHIFT_CONST(30)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_CHANNELCODING_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_CHANNELCODING_SHIFT)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_CHANNELCODING_RANGE                     30:30
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_CHANNELCODING_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_CHANNELCODING_DEFAULT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_CHANNELCODING_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_CHANNELCODING_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_CHANNELCODING_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_CHANNELCODING_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_CHANNELCODING_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_CHANNELCODING_INIT_ENUM                 ENABLE
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_CHANNELCODING_DISABLE                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_CHANNELCODING_ENABLE                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_SHIFT                       _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_FIELD                       _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_SHIFT)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_RANGE                       29:28
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_DEFAULT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_INIT_ENUM                   ENABLE_GALIOS
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_DISABLE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_ENABLE_GALIOS                       _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_ENABLE_FIBONACCI                    _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_SHIFT                   _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_FIELD                   _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_SHIFT)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_RANGE                   27:24
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_INIT_ENUM                       NOPATTERN
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_NOPATTERN                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_TRAINING1                       _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_TRAINING2                       _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_TRAINING3                       _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_D102                    _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_SBLERRRATE                      _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_PRBS7                   _MK_ENUM_CONST(6)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_CSTM                    _MK_ENUM_CONST(7)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_HBR2_COMPLIANCE                 _MK_ENUM_CONST(8)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_CP2520_PAT1                     _MK_ENUM_CONST(9)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_CP2520_PAT3                     _MK_ENUM_CONST(10)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_TRAINING4                       _MK_ENUM_CONST(11)

#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_CHANNELCODING_SHIFT                     _MK_SHIFT_CONST(22)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_CHANNELCODING_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_CHANNELCODING_SHIFT)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_CHANNELCODING_RANGE                     22:22
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_CHANNELCODING_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_CHANNELCODING_DEFAULT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_CHANNELCODING_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_CHANNELCODING_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_CHANNELCODING_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_CHANNELCODING_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_CHANNELCODING_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_CHANNELCODING_INIT_ENUM                 ENABLE
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_CHANNELCODING_DISABLE                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_CHANNELCODING_ENABLE                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_SHIFT                       _MK_SHIFT_CONST(20)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_FIELD                       _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_SHIFT)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_RANGE                       21:20
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_DEFAULT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_INIT_ENUM                   ENABLE_GALIOS
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_DISABLE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_ENABLE_GALIOS                       _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_ENABLE_FIBONACCI                    _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_SHIFT                   _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_FIELD                   _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_SHIFT)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_RANGE                   19:16
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_INIT_ENUM                       NOPATTERN
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_NOPATTERN                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_TRAINING1                       _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_TRAINING2                       _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_TRAINING3                       _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_D102                    _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_SBLERRRATE                      _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_PRBS7                   _MK_ENUM_CONST(6)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_CSTM                    _MK_ENUM_CONST(7)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_HBR2_COMPLIANCE                 _MK_ENUM_CONST(8)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_CP2520_PAT1                     _MK_ENUM_CONST(9)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_CP2520_PAT3                     _MK_ENUM_CONST(10)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_TRAINING4                       _MK_ENUM_CONST(11)

#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_CHANNELCODING_SHIFT                     _MK_SHIFT_CONST(14)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_CHANNELCODING_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_CHANNELCODING_SHIFT)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_CHANNELCODING_RANGE                     14:14
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_CHANNELCODING_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_CHANNELCODING_DEFAULT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_CHANNELCODING_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_CHANNELCODING_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_CHANNELCODING_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_CHANNELCODING_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_CHANNELCODING_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_CHANNELCODING_INIT_ENUM                 ENABLE
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_CHANNELCODING_DISABLE                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_CHANNELCODING_ENABLE                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_SHIFT                       _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_FIELD                       _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_SHIFT)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_RANGE                       13:12
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_DEFAULT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_INIT_ENUM                   ENABLE_GALIOS
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_DISABLE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_ENABLE_GALIOS                       _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_ENABLE_FIBONACCI                    _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_SHIFT                   _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_FIELD                   _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_SHIFT)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_RANGE                   11:8
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_INIT_ENUM                       NOPATTERN
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_NOPATTERN                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_TRAINING1                       _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_TRAINING2                       _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_TRAINING3                       _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_D102                    _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_SBLERRRATE                      _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_PRBS7                   _MK_ENUM_CONST(6)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_CSTM                    _MK_ENUM_CONST(7)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_HBR2_COMPLIANCE                 _MK_ENUM_CONST(8)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_CP2520_PAT1                     _MK_ENUM_CONST(9)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_CP2520_PAT3                     _MK_ENUM_CONST(10)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_TRAINING4                       _MK_ENUM_CONST(11)

#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_CHANNELCODING_SHIFT                     _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_CHANNELCODING_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_CHANNELCODING_SHIFT)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_CHANNELCODING_RANGE                     6:6
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_CHANNELCODING_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_CHANNELCODING_DEFAULT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_CHANNELCODING_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_CHANNELCODING_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_CHANNELCODING_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_CHANNELCODING_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_CHANNELCODING_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_CHANNELCODING_INIT_ENUM                 ENABLE
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_CHANNELCODING_DISABLE                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_CHANNELCODING_ENABLE                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_SHIFT                       _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_FIELD                       _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_SHIFT)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_RANGE                       5:4
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_DEFAULT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_INIT_ENUM                   ENABLE_GALIOS
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_DISABLE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_ENABLE_GALIOS                       _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_ENABLE_FIBONACCI                    _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_FIELD                   _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_SHIFT)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_RANGE                   3:0
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_INIT_ENUM                       NOPATTERN
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_NOPATTERN                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_TRAINING1                       _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_TRAINING2                       _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_TRAINING3                       _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_D102                    _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_SBLERRRATE                      _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_PRBS7                   _MK_ENUM_CONST(6)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_CSTM                    _MK_ENUM_CONST(7)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_HBR2_COMPLIANCE                 _MK_ENUM_CONST(8)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_CP2520_PAT1                     _MK_ENUM_CONST(9)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_CP2520_PAT3                     _MK_ENUM_CONST(10)
#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_TRAINING4                       _MK_ENUM_CONST(11)

// Register SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0
#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0                        _MK_ADDR_CONST(0x6e)
#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_SECURE                         0x0
#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_DUAL                   0x0
#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_SCR                    0
#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_WORD_COUNT                     0x1
#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_RESET_MASK                     _MK_MASK_CONST(0x1ffff)
#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_READ_MASK                      _MK_MASK_CONST(0x1ffff)
#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_WRITE_MASK                     _MK_MASK_CONST(0x1ffff)
#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_HBR2_COMPLIANCE_PERIOD_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_HBR2_COMPLIANCE_PERIOD_FIELD                   _MK_FIELD_CONST(0x1ffff, SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_HBR2_COMPLIANCE_PERIOD_SHIFT)
#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_HBR2_COMPLIANCE_PERIOD_RANGE                   16:0
#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_HBR2_COMPLIANCE_PERIOD_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_HBR2_COMPLIANCE_PERIOD_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_HBR2_COMPLIANCE_PERIOD_DEFAULT_MASK                    _MK_MASK_CONST(0x1ffff)
#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_HBR2_COMPLIANCE_PERIOD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_HBR2_COMPLIANCE_PERIOD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_HBR2_COMPLIANCE_PERIOD_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_HBR2_COMPLIANCE_PERIOD_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0                  _MK_ADDR_CONST(0x6f)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_SECURE                   0x0
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_DUAL                     0x0
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_SCR                      0
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_WORD_COUNT                       0x1
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_SYM_SHIFT                        _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_SYM_FIELD                        _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_SYM_SHIFT)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_SYM_RANGE                        31:0
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_SYM_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_SYM_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_SYM_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_SYM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_SYM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_SYM_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_SYM_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0                  _MK_ADDR_CONST(0x70)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_SECURE                   0x0
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_DUAL                     0x0
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_SCR                      0
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_WORD_COUNT                       0x1
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_SYM_SHIFT                        _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_SYM_FIELD                        _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_SYM_SHIFT)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_SYM_RANGE                        31:0
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_SYM_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_SYM_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_SYM_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_SYM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_SYM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_SYM_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_SYM_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0                  _MK_ADDR_CONST(0x71)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_SECURE                   0x0
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_DUAL                     0x0
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_SCR                      0
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_WORD_COUNT                       0x1
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_SYM_SHIFT                        _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_SYM_FIELD                        _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_SYM_SHIFT)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_SYM_RANGE                        31:0
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_SYM_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_SYM_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_SYM_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_SYM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_SYM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_SYM_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_SYM_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_HDCP_AN_MSB_0
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_MSB_0                       _MK_ADDR_CONST(0x75)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_MSB_0_SECURE                        0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_MSB_0_DUAL                  0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_MSB_0_SCR                   0
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_MSB_0_WORD_COUNT                    0x1
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_MSB_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_MSB_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_MSB_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_MSB_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_MSB_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_MSB_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_MSB_0_VALUE_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_MSB_0_VALUE_FIELD                   _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_DP_HDCP_AN_MSB_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_MSB_0_VALUE_RANGE                   31:0
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_MSB_0_VALUE_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_MSB_0_VALUE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_MSB_0_VALUE_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_MSB_0_VALUE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_MSB_0_VALUE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_MSB_0_VALUE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_MSB_0_VALUE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_MSB_0_VALUE_INIT_ENUM                       ZERO
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_MSB_0_VALUE_ZERO                    _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_DP_HDCP_AN_LSB_0
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_LSB_0                       _MK_ADDR_CONST(0x76)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_LSB_0_SECURE                        0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_LSB_0_DUAL                  0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_LSB_0_SCR                   0
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_LSB_0_WORD_COUNT                    0x1
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_LSB_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_LSB_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_LSB_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_LSB_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_LSB_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_LSB_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_LSB_0_VALUE_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_LSB_0_VALUE_FIELD                   _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_DP_HDCP_AN_LSB_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_LSB_0_VALUE_RANGE                   31:0
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_LSB_0_VALUE_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_LSB_0_VALUE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_LSB_0_VALUE_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_LSB_0_VALUE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_LSB_0_VALUE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_LSB_0_VALUE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_LSB_0_VALUE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_LSB_0_VALUE_INIT_ENUM                       ZERO
#define SOR_NV_PDISP_SOR_DP_HDCP_AN_LSB_0_VALUE_ZERO                    _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_DP_HDCP_AKSV_MSB_0
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_MSB_0                     _MK_ADDR_CONST(0x77)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_MSB_0_SECURE                      0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_MSB_0_DUAL                        0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_MSB_0_SCR                         0
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_MSB_0_WORD_COUNT                  0x1
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_MSB_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_MSB_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_MSB_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_MSB_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_MSB_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_MSB_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_MSB_0_VALUE_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_MSB_0_VALUE_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_HDCP_AKSV_MSB_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_MSB_0_VALUE_RANGE                 7:0
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_MSB_0_VALUE_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_MSB_0_VALUE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_MSB_0_VALUE_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_MSB_0_VALUE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_MSB_0_VALUE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_MSB_0_VALUE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_MSB_0_VALUE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_MSB_0_VALUE_INIT_ENUM                     ZERO
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_MSB_0_VALUE_ZERO                  _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_DP_HDCP_AKSV_LSB_0
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_LSB_0                     _MK_ADDR_CONST(0x78)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_LSB_0_SECURE                      0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_LSB_0_DUAL                        0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_LSB_0_SCR                         0
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_LSB_0_WORD_COUNT                  0x1
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_LSB_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_LSB_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_LSB_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_LSB_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_LSB_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_LSB_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_LSB_0_VALUE_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_LSB_0_VALUE_FIELD                 _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_DP_HDCP_AKSV_LSB_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_LSB_0_VALUE_RANGE                 31:0
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_LSB_0_VALUE_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_LSB_0_VALUE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_LSB_0_VALUE_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_LSB_0_VALUE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_LSB_0_VALUE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_LSB_0_VALUE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_LSB_0_VALUE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_LSB_0_VALUE_INIT_ENUM                     ZERO
#define SOR_NV_PDISP_SOR_DP_HDCP_AKSV_LSB_0_VALUE_ZERO                  _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0                     _MK_ADDR_CONST(0x79)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_SECURE                      0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_DUAL                        0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_SCR                         0
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_WORD_COUNT                  0x1
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_RESET_MASK                  _MK_MASK_CONST(0x800000ff)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_READ_MASK                   _MK_MASK_CONST(0x800000ff)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_WRITE_MASK                  _MK_MASK_CONST(0x800000ff)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_VALUE_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_VALUE_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_VALUE_RANGE                 7:0
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_VALUE_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_VALUE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_VALUE_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_VALUE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_VALUE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_VALUE_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_VALUE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_VALUE_INIT_ENUM                     ZERO
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_VALUE_ZERO                  _MK_ENUM_CONST(0)

#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_REPEATER_SHIFT                      _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_REPEATER_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_REPEATER_SHIFT)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_REPEATER_RANGE                      31:31
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_REPEATER_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_REPEATER_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_REPEATER_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_REPEATER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_REPEATER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_REPEATER_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0_REPEATER_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB_0
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB_0                     _MK_ADDR_CONST(0x7a)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB_0_SECURE                      0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB_0_DUAL                        0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB_0_SCR                         0
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB_0_WORD_COUNT                  0x1
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB_0_VALUE_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB_0_VALUE_FIELD                 _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB_0_VALUE_RANGE                 31:0
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB_0_VALUE_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB_0_VALUE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB_0_VALUE_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB_0_VALUE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB_0_VALUE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB_0_VALUE_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB_0_VALUE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB_0_VALUE_INIT_ENUM                     ZERO
#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB_0_VALUE_ZERO                  _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0                 _MK_ADDR_CONST(0x7b)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SCR                     0
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0xc00)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0xbf0f)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_READ_MASK                       _MK_MASK_CONST(0xbf0f)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0x800f)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_RUN_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_RUN_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_RUN_SHIFT)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_RUN_RANGE                       0:0
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_RUN_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_RUN_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_RUN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_RUN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_RUN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_RUN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_RUN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_RUN_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_RUN_YES                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_CRYPT_SHIFT                     _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_CRYPT_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_CRYPT_SHIFT)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_CRYPT_RANGE                     1:1
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_CRYPT_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_CRYPT_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_CRYPT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_CRYPT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_CRYPT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_CRYPT_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_CRYPT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_CRYPT_DISABLED                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_CRYPT_ENABLED                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_DUAL_LINK_EN_SHIFT                      _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_DUAL_LINK_EN_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_DUAL_LINK_EN_SHIFT)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_DUAL_LINK_EN_RANGE                      2:2
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_DUAL_LINK_EN_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_DUAL_LINK_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_DUAL_LINK_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_DUAL_LINK_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_DUAL_LINK_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_DUAL_LINK_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_DUAL_LINK_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_DUAL_LINK_EN_DISABLED                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_DUAL_LINK_EN_ENABLED                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_ONEONE_SHIFT                    _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_ONEONE_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_ONEONE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_ONEONE_RANGE                    3:3
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_ONEONE_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_ONEONE_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_ONEONE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_ONEONE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_ONEONE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_ONEONE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_ONEONE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_ONEONE_DISABLED                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_ONEONE_ENABLED                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_AN_SHIFT                        _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_AN_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_AN_SHIFT)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_AN_RANGE                        8:8
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_AN_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_AN_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_AN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_AN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_AN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_AN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_AN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_AN_INVALID                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_AN_VALID                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_R0_SHIFT                        _MK_SHIFT_CONST(9)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_R0_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_R0_SHIFT)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_R0_RANGE                        9:9
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_R0_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_R0_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_R0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_R0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_R0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_R0_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_R0_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_R0_INVALID                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_R0_VALID                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SPRIME_SHIFT                    _MK_SHIFT_CONST(10)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SPRIME_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SPRIME_SHIFT)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SPRIME_RANGE                    10:10
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SPRIME_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SPRIME_DEFAULT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SPRIME_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SPRIME_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SPRIME_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SPRIME_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SPRIME_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SPRIME_INVALID                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SPRIME_VALID                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_MPRIME_SHIFT                    _MK_SHIFT_CONST(11)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_MPRIME_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_MPRIME_SHIFT)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_MPRIME_RANGE                    11:11
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_MPRIME_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_MPRIME_DEFAULT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_MPRIME_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_MPRIME_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_MPRIME_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_MPRIME_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_MPRIME_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_MPRIME_INVALID                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_MPRIME_VALID                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SROM_EN_SHIFT                   _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SROM_EN_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SROM_EN_SHIFT)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SROM_EN_RANGE                   12:12
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SROM_EN_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SROM_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SROM_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SROM_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SROM_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SROM_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SROM_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SROM_EN_DISABLED                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SROM_EN_ENABLED                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SROM_ERR_SHIFT                  _MK_SHIFT_CONST(13)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SROM_ERR_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SROM_ERR_SHIFT)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SROM_ERR_RANGE                  13:13
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SROM_ERR_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SROM_ERR_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SROM_ERR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SROM_ERR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SROM_ERR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SROM_ERR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SROM_ERR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SROM_ERR_NOERROR                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_SROM_ERR_ERROR                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_UPSTREAM_SHIFT                  _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_UPSTREAM_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_UPSTREAM_SHIFT)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_UPSTREAM_RANGE                  15:15
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_UPSTREAM_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_UPSTREAM_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_UPSTREAM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_UPSTREAM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_UPSTREAM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_UPSTREAM_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_UPSTREAM_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_UPSTREAM_TMDS_MODE                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0_UPSTREAM_DP_MODE                        _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_DP_HDCP_RI_0
#define SOR_NV_PDISP_SOR_DP_HDCP_RI_0                   _MK_ADDR_CONST(0x7c)
#define SOR_NV_PDISP_SOR_DP_HDCP_RI_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_RI_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_RI_0_SCR                       0
#define SOR_NV_PDISP_SOR_DP_HDCP_RI_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_DP_HDCP_RI_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_RI_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_RI_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_RI_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_RI_0_READ_MASK                         _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_RI_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_RI_0_VALUE_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_HDCP_RI_0_VALUE_FIELD                       _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_DP_HDCP_RI_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_HDCP_RI_0_VALUE_RANGE                       15:0
#define SOR_NV_PDISP_SOR_DP_HDCP_RI_0_VALUE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_RI_0_VALUE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_RI_0_VALUE_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_RI_0_VALUE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_RI_0_VALUE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_RI_0_VALUE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_RI_0_VALUE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_RI_0_VALUE_INIT_ENUM                   ZERO
#define SOR_NV_PDISP_SOR_DP_HDCP_RI_0_VALUE_ZERO                        _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_DP_HDCP_EMU0_0
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU0_0                 _MK_ADDR_CONST(0x7d)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU0_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU0_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU0_0_SCR                     0
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU0_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU0_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU0_0_REG_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU0_0_REG_FIELD                       _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_DP_HDCP_EMU0_0_REG_SHIFT)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU0_0_REG_RANGE                       31:0
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU0_0_REG_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU0_0_REG_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU0_0_REG_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU0_0_REG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU0_0_REG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU0_0_REG_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU0_0_REG_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_HDCP_EMU1_0
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU1_0                 _MK_ADDR_CONST(0x7e)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU1_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU1_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU1_0_SCR                     0
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU1_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU1_0_VALUE_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU1_0_VALUE_FIELD                     _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_DP_HDCP_EMU1_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU1_0_VALUE_RANGE                     31:0
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU1_0_VALUE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU1_0_VALUE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU1_0_VALUE_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU1_0_VALUE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU1_0_VALUE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU1_0_VALUE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU1_0_VALUE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU1_0_VALUE_INIT_ENUM                 ZERO
#define SOR_NV_PDISP_SOR_DP_HDCP_EMU1_0_VALUE_ZERO                      _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_DP_HDCP_CYA_0
#define SOR_NV_PDISP_SOR_DP_HDCP_CYA_0                  _MK_ADDR_CONST(0x7f)
#define SOR_NV_PDISP_SOR_DP_HDCP_CYA_0_SECURE                   0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_CYA_0_DUAL                     0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_CYA_0_SCR                      0
#define SOR_NV_PDISP_SOR_DP_HDCP_CYA_0_WORD_COUNT                       0x1
#define SOR_NV_PDISP_SOR_DP_HDCP_CYA_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CYA_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_CYA_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CYA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CYA_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_CYA_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_CYA_0_REG_SHIFT                        _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CYA_0_REG_FIELD                        _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_DP_HDCP_CYA_0_REG_SHIFT)
#define SOR_NV_PDISP_SOR_DP_HDCP_CYA_0_REG_RANGE                        31:0
#define SOR_NV_PDISP_SOR_DP_HDCP_CYA_0_REG_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_HDCP_CYA_0_REG_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CYA_0_REG_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_HDCP_CYA_0_REG_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CYA_0_REG_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_HDCP_CYA_0_REG_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_HDCP_CYA_0_REG_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_TMDS_HDCP_AN_MSB_0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_MSB_0                     _MK_ADDR_CONST(0x80)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_MSB_0_SECURE                      0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_MSB_0_DUAL                        0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_MSB_0_SCR                         0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_MSB_0_WORD_COUNT                  0x1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_MSB_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_MSB_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_MSB_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_MSB_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_MSB_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_MSB_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_MSB_0_VALUE_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_MSB_0_VALUE_FIELD                 _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_TMDS_HDCP_AN_MSB_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_MSB_0_VALUE_RANGE                 31:0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_MSB_0_VALUE_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_MSB_0_VALUE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_MSB_0_VALUE_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_MSB_0_VALUE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_MSB_0_VALUE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_MSB_0_VALUE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_MSB_0_VALUE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_MSB_0_VALUE_ZERO                  _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_TMDS_HDCP_AN_LSB_0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_LSB_0                     _MK_ADDR_CONST(0x81)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_LSB_0_SECURE                      0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_LSB_0_DUAL                        0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_LSB_0_SCR                         0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_LSB_0_WORD_COUNT                  0x1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_LSB_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_LSB_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_LSB_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_LSB_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_LSB_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_LSB_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_LSB_0_VALUE_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_LSB_0_VALUE_FIELD                 _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_TMDS_HDCP_AN_LSB_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_LSB_0_VALUE_RANGE                 31:0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_LSB_0_VALUE_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_LSB_0_VALUE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_LSB_0_VALUE_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_LSB_0_VALUE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_LSB_0_VALUE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_LSB_0_VALUE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_LSB_0_VALUE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AN_LSB_0_VALUE_ZERO                  _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB_0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB_0                     _MK_ADDR_CONST(0x82)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB_0_SECURE                      0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB_0_DUAL                        0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB_0_SCR                         0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB_0_WORD_COUNT                  0x1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB_0_VALUE_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB_0_VALUE_FIELD                 _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB_0_VALUE_RANGE                 31:0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB_0_VALUE_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB_0_VALUE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB_0_VALUE_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB_0_VALUE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB_0_VALUE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB_0_VALUE_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB_0_VALUE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB_0_VALUE_ZERO                  _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB_0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB_0                     _MK_ADDR_CONST(0x83)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB_0_SECURE                      0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB_0_DUAL                        0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB_0_SCR                         0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB_0_WORD_COUNT                  0x1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB_0_VALUE_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB_0_VALUE_FIELD                 _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB_0_VALUE_RANGE                 31:0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB_0_VALUE_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB_0_VALUE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB_0_VALUE_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB_0_VALUE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB_0_VALUE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB_0_VALUE_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB_0_VALUE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB_0_VALUE_ZERO                  _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_MSB_0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_MSB_0                   _MK_ADDR_CONST(0x84)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_MSB_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_MSB_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_MSB_0_SCR                       0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_MSB_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_MSB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_MSB_0_RESET_MASK                        _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_MSB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_MSB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_MSB_0_READ_MASK                         _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_MSB_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_MSB_0_VALUE_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_MSB_0_VALUE_FIELD                       _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_MSB_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_MSB_0_VALUE_RANGE                       7:0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_MSB_0_VALUE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_MSB_0_VALUE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_MSB_0_VALUE_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_MSB_0_VALUE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_MSB_0_VALUE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_MSB_0_VALUE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_MSB_0_VALUE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_MSB_0_VALUE_ZERO                        _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_LSB_0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_LSB_0                   _MK_ADDR_CONST(0x85)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_LSB_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_LSB_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_LSB_0_SCR                       0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_LSB_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_LSB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_LSB_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_LSB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_LSB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_LSB_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_LSB_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_LSB_0_VALUE_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_LSB_0_VALUE_FIELD                       _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_LSB_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_LSB_0_VALUE_RANGE                       31:0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_LSB_0_VALUE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_LSB_0_VALUE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_LSB_0_VALUE_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_LSB_0_VALUE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_LSB_0_VALUE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_LSB_0_VALUE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_LSB_0_VALUE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_LSB_0_VALUE_ZERO                        _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0                   _MK_ADDR_CONST(0x86)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_SCR                       0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_RESET_MASK                        _MK_MASK_CONST(0x800000ff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_READ_MASK                         _MK_MASK_CONST(0x800000ff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_WRITE_MASK                        _MK_MASK_CONST(0x800000ff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_VALUE_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_VALUE_FIELD                       _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_VALUE_RANGE                       7:0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_VALUE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_VALUE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_VALUE_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_VALUE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_VALUE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_VALUE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_VALUE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_VALUE_ZERO                        _MK_ENUM_CONST(0)

#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_REPEATER_SHIFT                    _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_REPEATER_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_REPEATER_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_REPEATER_RANGE                    31:31
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_REPEATER_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_REPEATER_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_REPEATER_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_REPEATER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_REPEATER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_REPEATER_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_REPEATER_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0_REPEATER_VALUE                    _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB_0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB_0                   _MK_ADDR_CONST(0x87)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB_0_SCR                       0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB_0_VALUE_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB_0_VALUE_FIELD                       _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB_0_VALUE_RANGE                       31:0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB_0_VALUE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB_0_VALUE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB_0_VALUE_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB_0_VALUE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB_0_VALUE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB_0_VALUE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB_0_VALUE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB_0_VALUE_ZERO                        _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_MSB_0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_MSB_0                   _MK_ADDR_CONST(0x88)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_MSB_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_MSB_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_MSB_0_SCR                       0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_MSB_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_MSB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_MSB_0_RESET_MASK                        _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_MSB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_MSB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_MSB_0_READ_MASK                         _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_MSB_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_MSB_0_VALUE_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_MSB_0_VALUE_FIELD                       _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_MSB_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_MSB_0_VALUE_RANGE                       7:0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_MSB_0_VALUE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_MSB_0_VALUE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_MSB_0_VALUE_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_MSB_0_VALUE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_MSB_0_VALUE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_MSB_0_VALUE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_MSB_0_VALUE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_MSB_0_VALUE_ZERO                        _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_LSB_0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_LSB_0                   _MK_ADDR_CONST(0x89)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_LSB_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_LSB_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_LSB_0_SCR                       0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_LSB_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_LSB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_LSB_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_LSB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_LSB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_LSB_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_LSB_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_LSB_0_VALUE_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_LSB_0_VALUE_FIELD                       _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_LSB_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_LSB_0_VALUE_RANGE                       31:0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_LSB_0_VALUE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_LSB_0_VALUE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_LSB_0_VALUE_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_LSB_0_VALUE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_LSB_0_VALUE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_LSB_0_VALUE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_LSB_0_VALUE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_LSB_0_VALUE_ZERO                        _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_MSB_0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_MSB_0                   _MK_ADDR_CONST(0x8a)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_MSB_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_MSB_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_MSB_0_SCR                       0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_MSB_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_MSB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_MSB_0_RESET_MASK                        _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_MSB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_MSB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_MSB_0_READ_MASK                         _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_MSB_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_MSB_0_VALUE_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_MSB_0_VALUE_FIELD                       _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_MSB_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_MSB_0_VALUE_RANGE                       7:0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_MSB_0_VALUE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_MSB_0_VALUE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_MSB_0_VALUE_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_MSB_0_VALUE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_MSB_0_VALUE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_MSB_0_VALUE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_MSB_0_VALUE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_MSB_0_VALUE_ZERO                        _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_LSB_0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_LSB_0                   _MK_ADDR_CONST(0x8b)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_LSB_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_LSB_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_LSB_0_SCR                       0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_LSB_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_LSB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_LSB_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_LSB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_LSB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_LSB_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_LSB_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_LSB_0_VALUE_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_LSB_0_VALUE_FIELD                       _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_LSB_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_LSB_0_VALUE_RANGE                       31:0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_LSB_0_VALUE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_LSB_0_VALUE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_LSB_0_VALUE_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_LSB_0_VALUE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_LSB_0_VALUE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_LSB_0_VALUE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_LSB_0_VALUE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_LSB_0_VALUE_ZERO                        _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0                       _MK_ADDR_CONST(0x8c)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SECURE                        0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_DUAL                  0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SCR                   0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_WORD_COUNT                    0x1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_RESET_VAL                     _MK_MASK_CONST(0xc00)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_RESET_MASK                    _MK_MASK_CONST(0x3f0f)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_READ_MASK                     _MK_MASK_CONST(0x3f0f)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_WRITE_MASK                    _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_RUN_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_RUN_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_RUN_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_RUN_RANGE                     0:0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_RUN_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_RUN_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_RUN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_RUN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_RUN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_RUN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_RUN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_RUN_NO                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_RUN_YES                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_CRYPT_SHIFT                   _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_CRYPT_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_CRYPT_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_CRYPT_RANGE                   1:1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_CRYPT_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_CRYPT_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_CRYPT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_CRYPT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_CRYPT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_CRYPT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_CRYPT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_CRYPT_DISABLED                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_CRYPT_ENABLED                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_DUAL_LINK_EN_SHIFT                    _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_DUAL_LINK_EN_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_DUAL_LINK_EN_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_DUAL_LINK_EN_RANGE                    2:2
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_DUAL_LINK_EN_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_DUAL_LINK_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_DUAL_LINK_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_DUAL_LINK_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_DUAL_LINK_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_DUAL_LINK_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_DUAL_LINK_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_DUAL_LINK_EN_DISABLED                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_DUAL_LINK_EN_ENABLED                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_ONEONE_SHIFT                  _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_ONEONE_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_ONEONE_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_ONEONE_RANGE                  3:3
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_ONEONE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_ONEONE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_ONEONE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_ONEONE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_ONEONE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_ONEONE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_ONEONE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_ONEONE_DISABLED                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_ONEONE_ENABLED                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_AN_SHIFT                      _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_AN_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_AN_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_AN_RANGE                      8:8
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_AN_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_AN_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_AN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_AN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_AN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_AN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_AN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_AN_INVALID                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_AN_VALID                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_R0_SHIFT                      _MK_SHIFT_CONST(9)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_R0_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_R0_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_R0_RANGE                      9:9
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_R0_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_R0_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_R0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_R0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_R0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_R0_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_R0_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_R0_INVALID                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_R0_VALID                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SPRIME_SHIFT                  _MK_SHIFT_CONST(10)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SPRIME_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SPRIME_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SPRIME_RANGE                  10:10
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SPRIME_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SPRIME_DEFAULT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SPRIME_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SPRIME_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SPRIME_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SPRIME_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SPRIME_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SPRIME_INVALID                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SPRIME_VALID                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_MPRIME_SHIFT                  _MK_SHIFT_CONST(11)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_MPRIME_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_MPRIME_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_MPRIME_RANGE                  11:11
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_MPRIME_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_MPRIME_DEFAULT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_MPRIME_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_MPRIME_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_MPRIME_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_MPRIME_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_MPRIME_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_MPRIME_INVALID                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_MPRIME_VALID                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SROM_EN_SHIFT                 _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SROM_EN_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SROM_EN_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SROM_EN_RANGE                 12:12
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SROM_EN_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SROM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SROM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SROM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SROM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SROM_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SROM_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SROM_EN_DISABLED                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SROM_EN_ENABLED                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SROM_ERR_SHIFT                        _MK_SHIFT_CONST(13)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SROM_ERR_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SROM_ERR_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SROM_ERR_RANGE                        13:13
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SROM_ERR_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SROM_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SROM_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SROM_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SROM_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SROM_ERR_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SROM_ERR_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SROM_ERR_NOERROR                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0_SROM_ERR_ERROR                        _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0                      _MK_ADDR_CONST(0x8d)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_SCR                  0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_RESET_VAL                    _MK_MASK_CONST(0x11)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_RESET_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_READ_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_MODE_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_MODE_FIELD                   _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_MODE_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_MODE_RANGE                   3:0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_MODE_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_MODE_DEFAULT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_MODE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_MODE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_MODE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_MODE_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_MODE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_MODE_READ_S                  _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_MODE_READ_M                  _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_SHIFT                  _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_FIELD                  _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_RANGE                  7:4
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_DEFAULT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_INIT_ENUM                      SOR1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_SOR0                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_SOR1                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_SOR2                   _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_SOR3                   _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_SOR4                   _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_SOR5                   _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_SOR6                   _MK_ENUM_CONST(6)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_SOR7                   _MK_ENUM_CONST(7)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_DAC0                   _MK_ENUM_CONST(8)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_DAC1                   _MK_ENUM_CONST(9)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_DAC2                   _MK_ENUM_CONST(10)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_PIOR0                  _MK_ENUM_CONST(11)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_PIOR1                  _MK_ENUM_CONST(12)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_PIOR2                  _MK_ENUM_CONST(13)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_PIOR3                  _MK_ENUM_CONST(14)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_PIOR4                  _MK_ENUM_CONST(15)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0_INDEX_MAX                    _MK_ENUM_CONST(15)

// Register SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_MSB_0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_MSB_0                 _MK_ADDR_CONST(0x8e)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_MSB_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_MSB_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_MSB_0_SCR                     0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_MSB_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_MSB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_MSB_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_MSB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_MSB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_MSB_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_MSB_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_MSB_0_VALUE_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_MSB_0_VALUE_FIELD                     _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_MSB_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_MSB_0_VALUE_RANGE                     31:0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_MSB_0_VALUE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_MSB_0_VALUE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_MSB_0_VALUE_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_MSB_0_VALUE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_MSB_0_VALUE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_MSB_0_VALUE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_MSB_0_VALUE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_MSB_0_VALUE_ZERO                      _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_LSB_0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_LSB_0                 _MK_ADDR_CONST(0x8f)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_LSB_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_LSB_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_LSB_0_SCR                     0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_LSB_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_LSB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_LSB_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_LSB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_LSB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_LSB_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_LSB_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_LSB_0_VALUE_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_LSB_0_VALUE_FIELD                     _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_LSB_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_LSB_0_VALUE_RANGE                     31:0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_LSB_0_VALUE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_LSB_0_VALUE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_LSB_0_VALUE_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_LSB_0_VALUE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_LSB_0_VALUE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_LSB_0_VALUE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_LSB_0_VALUE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_LSB_0_VALUE_ZERO                      _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0                 _MK_ADDR_CONST(0x90)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_SCR                     0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_RESET_MASK                      _MK_MASK_CONST(0xf0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_READZ_SHIFT                      _MK_SHIFT_CONST(7)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_READZ_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_READZ_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_READZ_RANGE                      7:7
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_READZ_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_READZ_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_READZ_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_READZ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_READZ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_READZ_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_READZ_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_READZ_NOT_IMPL                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_READZ_IMPLMNTD                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_CS_SHIFT                 _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_CS_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_CS_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_CS_RANGE                 6:6
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_CS_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_CS_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_CS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_CS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_CS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_CS_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_CS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_CS_NOT_IMPL                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_CS_IMPLMNTD                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_SCOPE_SHIFT                      _MK_SHIFT_CONST(5)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_SCOPE_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_SCOPE_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_SCOPE_RANGE                      5:5
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_SCOPE_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_SCOPE_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_SCOPE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_SCOPE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_SCOPE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_SCOPE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_SCOPE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_SCOPE_SCOPE_TWO_HEADS                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_SCOPE_SCOPE_1_HEAD                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_INTPNL_SHIFT                     _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_INTPNL_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_INTPNL_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_INTPNL_RANGE                     4:4
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_INTPNL_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_INTPNL_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_INTPNL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_INTPNL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_INTPNL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_INTPNL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_INTPNL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_INTPNL_INACTV                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_INTPNL_ACTV                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_MAX_CMODE_IDX_SHIFT                      _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_MAX_CMODE_IDX_FIELD                      _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_MAX_CMODE_IDX_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_MAX_CMODE_IDX_RANGE                      3:0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_MAX_CMODE_IDX_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_MAX_CMODE_IDX_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_MAX_CMODE_IDX_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_MAX_CMODE_IDX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_MAX_CMODE_IDX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_MAX_CMODE_IDX_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0_STATUS_MAX_CMODE_IDX_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0                        _MK_ADDR_CONST(0x91)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_SECURE                         0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_DUAL                   0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_SCR                    0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_WORD_COUNT                     0x1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_CMODE_IDX_SHIFT                 _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_CMODE_IDX_FIELD                 _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_CMODE_IDX_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_CMODE_IDX_RANGE                 31:28
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_CMODE_IDX_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_CMODE_IDX_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_CMODE_IDX_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_CMODE_IDX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_CMODE_IDX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_CMODE_IDX_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_CMODE_IDX_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_UNPROTECTED_SHIFT                       _MK_SHIFT_CONST(27)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_UNPROTECTED_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_UNPROTECTED_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_UNPROTECTED_RANGE                       27:27
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_UNPROTECTED_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_UNPROTECTED_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_UNPROTECTED_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_UNPROTECTED_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_UNPROTECTED_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_UNPROTECTED_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_UNPROTECTED_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_UNPROTECTED_N                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_UNPROTECTED_Y                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_EXTPNL_SHIFT                    _MK_SHIFT_CONST(26)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_EXTPNL_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_EXTPNL_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_EXTPNL_RANGE                    26:26
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_EXTPNL_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_EXTPNL_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_EXTPNL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_EXTPNL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_EXTPNL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_EXTPNL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_EXTPNL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_EXTPNL_INACTV                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_EXTPNL_ACTV                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_RPTR_SHIFT                      _MK_SHIFT_CONST(25)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_RPTR_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_RPTR_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_RPTR_RANGE                      25:25
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_RPTR_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_RPTR_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_RPTR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_RPTR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_RPTR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_RPTR_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_RPTR_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_RPTR_INACTV                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_RPTR_ACTV                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_ENCRYPTING_SHIFT                        _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_ENCRYPTING_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_ENCRYPTING_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_ENCRYPTING_RANGE                        24:24
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_ENCRYPTING_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_ENCRYPTING_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_ENCRYPTING_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_ENCRYPTING_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_ENCRYPTING_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_ENCRYPTING_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_ENCRYPTING_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_ENCRYPTING_N                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_STATUS_ENCRYPTING_Y                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_VALUE_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_VALUE_FIELD                    _MK_FIELD_CONST(0xffffff, SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_VALUE_RANGE                    23:0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_VALUE_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_VALUE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_VALUE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0_VALUE_ZERO                     _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB1_0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB1_0                        _MK_ADDR_CONST(0x92)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB1_0_SECURE                         0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB1_0_DUAL                   0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB1_0_SCR                    0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB1_0_WORD_COUNT                     0x1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB1_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB1_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB1_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB1_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB1_0_VALUE_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB1_0_VALUE_FIELD                    _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB1_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB1_0_VALUE_RANGE                    31:0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB1_0_VALUE_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB1_0_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB1_0_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB1_0_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB1_0_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB1_0_VALUE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB1_0_VALUE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB1_0_VALUE_ZERO                     _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_TMDS_HDCP_RI_0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_RI_0                 _MK_ADDR_CONST(0x93)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_RI_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_RI_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_RI_0_SCR                     0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_RI_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_RI_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_RI_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_RI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_RI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_RI_0_READ_MASK                       _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_RI_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_RI_0_VALUE_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_RI_0_VALUE_FIELD                     _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_TMDS_HDCP_RI_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_RI_0_VALUE_RANGE                     15:0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_RI_0_VALUE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_RI_0_VALUE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_RI_0_VALUE_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_RI_0_VALUE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_RI_0_VALUE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_RI_0_VALUE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_RI_0_VALUE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_RI_0_VALUE_ZERO                      _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_TMDS_HDCP_CS_MSB_0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_MSB_0                     _MK_ADDR_CONST(0x94)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_MSB_0_SECURE                      0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_MSB_0_DUAL                        0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_MSB_0_SCR                         0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_MSB_0_WORD_COUNT                  0x1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_MSB_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_MSB_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_MSB_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_MSB_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_MSB_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_MSB_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_MSB_0_RESERVED_SHIFT                      _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_MSB_0_RESERVED_FIELD                      _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_TMDS_HDCP_CS_MSB_0_RESERVED_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_MSB_0_RESERVED_RANGE                      7:0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_MSB_0_RESERVED_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_MSB_0_RESERVED_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_MSB_0_RESERVED_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_MSB_0_RESERVED_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_MSB_0_RESERVED_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_MSB_0_RESERVED_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_MSB_0_RESERVED_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_TMDS_HDCP_CS_LSB_0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_LSB_0                     _MK_ADDR_CONST(0x95)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_LSB_0_SECURE                      0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_LSB_0_DUAL                        0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_LSB_0_SCR                         0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_LSB_0_WORD_COUNT                  0x1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_LSB_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_LSB_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_LSB_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_LSB_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_LSB_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_LSB_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_LSB_0_RESERVED_SHIFT                      _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_LSB_0_RESERVED_FIELD                      _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_TMDS_HDCP_CS_LSB_0_RESERVED_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_LSB_0_RESERVED_RANGE                      31:0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_LSB_0_RESERVED_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_LSB_0_RESERVED_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_LSB_0_RESERVED_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_LSB_0_RESERVED_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_LSB_0_RESERVED_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_LSB_0_RESERVED_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_CS_LSB_0_RESERVED_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU0_0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU0_0                      _MK_ADDR_CONST(0x96)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU0_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU0_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU0_0_SCR                  0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU0_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU0_0_READ_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU0_0_REGX_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU0_0_REGX_FIELD                   _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU0_0_REGX_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU0_0_REGX_RANGE                   31:0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU0_0_REGX_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU0_0_REGX_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU0_0_REGX_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU0_0_REGX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU0_0_REGX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU0_0_REGX_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU0_0_REGX_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU_RDATA0_0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU_RDATA0_0                        _MK_ADDR_CONST(0x97)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU_RDATA0_0_SECURE                         0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU_RDATA0_0_DUAL                   0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU_RDATA0_0_SCR                    0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU_RDATA0_0_WORD_COUNT                     0x1
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU_RDATA0_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU_RDATA0_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU_RDATA0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU_RDATA0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU_RDATA0_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU_RDATA0_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU_RDATA0_0_RDATA_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU_RDATA0_0_RDATA_FIELD                    _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU_RDATA0_0_RDATA_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU_RDATA0_0_RDATA_RANGE                    31:0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU_RDATA0_0_RDATA_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU_RDATA0_0_RDATA_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU_RDATA0_0_RDATA_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU_RDATA0_0_RDATA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU_RDATA0_0_RDATA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU_RDATA0_0_RDATA_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU_RDATA0_0_RDATA_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0                      _MK_ADDR_CONST(0x98)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_SCR                  0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_RESET_MASK                   _MK_MASK_CONST(0x800000ff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_READ_MASK                    _MK_MASK_CONST(0x800000ff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_WRITE_MASK                   _MK_MASK_CONST(0x800000ff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_RANGE                   7:0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_CNT_22                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_CNT_24                  _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_CNT_32                  _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_CNT_44                  _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_CNT_48                  _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_CNT_88                  _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_CNT_96                  _MK_ENUM_CONST(6)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_CNT_176                 _MK_ENUM_CONST(7)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_CNT_192                 _MK_ENUM_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_JIT_05_22                       _MK_ENUM_CONST(9)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_JIT_05_24                       _MK_ENUM_CONST(10)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_JIT_05_32                       _MK_ENUM_CONST(11)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_JIT_05_44                       _MK_ENUM_CONST(12)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_JIT_05_48                       _MK_ENUM_CONST(13)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_JIT_05_88                       _MK_ENUM_CONST(14)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_JIT_05_96                       _MK_ENUM_CONST(15)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_JIT_05_176                      _MK_ENUM_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_JIT_05_192                      _MK_ENUM_CONST(17)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_JIT_10_22                       _MK_ENUM_CONST(18)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_JIT_10_24                       _MK_ENUM_CONST(19)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_JIT_10_32                       _MK_ENUM_CONST(20)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_JIT_10_44                       _MK_ENUM_CONST(21)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_JIT_10_48                       _MK_ENUM_CONST(22)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_JIT_10_88                       _MK_ENUM_CONST(23)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_JIT_10_96                       _MK_ENUM_CONST(24)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_JIT_10_176                      _MK_ENUM_CONST(25)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_JIT_10_192                      _MK_ENUM_CONST(26)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_JIT_11_22                       _MK_ENUM_CONST(27)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_JIT_11_24                       _MK_ENUM_CONST(28)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_JIT_11_32                       _MK_ENUM_CONST(29)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_JIT_11_44                       _MK_ENUM_CONST(30)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_JIT_11_48                       _MK_ENUM_CONST(31)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_JIT_11_88                       _MK_ENUM_CONST(32)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_JIT_11_96                       _MK_ENUM_CONST(33)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_JIT_11_176                      _MK_ENUM_CONST(34)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_JIT_11_192                      _MK_ENUM_CONST(35)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_GLITCH_PERIOD_22                        _MK_ENUM_CONST(36)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_GLITCH_PERIOD_24                        _MK_ENUM_CONST(37)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_GLITCH_PERIOD_32                        _MK_ENUM_CONST(38)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_GLITCH_PERIOD_44                        _MK_ENUM_CONST(39)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_GLITCH_PERIOD_48                        _MK_ENUM_CONST(40)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_GLITCH_PERIOD_88                        _MK_ENUM_CONST(41)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_GLITCH_PERIOD_96                        _MK_ENUM_CONST(42)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_GLITCH_PERIOD_176                       _MK_ENUM_CONST(43)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_GLITCH_PERIOD_192                       _MK_ENUM_CONST(44)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_GLITCH_CNT_22                   _MK_ENUM_CONST(45)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_GLITCH_CNT_24                   _MK_ENUM_CONST(46)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_GLITCH_CNT_32                   _MK_ENUM_CONST(47)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_GLITCH_CNT_44                   _MK_ENUM_CONST(48)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_GLITCH_CNT_48                   _MK_ENUM_CONST(49)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_GLITCH_CNT_88                   _MK_ENUM_CONST(50)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_GLITCH_CNT_96                   _MK_ENUM_CONST(51)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_GLITCH_CNT_176                  _MK_ENUM_CONST(52)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_ADDR_GLITCH_CNT_192                  _MK_ENUM_CONST(53)

#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_WRITE_SHIFT                  _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_WRITE_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_WRITE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_WRITE_RANGE                  31:31
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_WRITE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_WRITE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_WRITE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_WRITE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_WRITE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_WRITE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0_WRITE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU2_0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU2_0                      _MK_ADDR_CONST(0x99)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU2_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU2_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU2_0_SCR                  0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU2_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU2_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU2_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU2_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU2_0_DATA_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU2_0_DATA_FIELD                   _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU2_0_DATA_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU2_0_DATA_RANGE                   31:0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU2_0_DATA_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU2_0_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU2_0_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU2_0_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU2_0_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU2_0_DATA_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU2_0_DATA_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0                    _MK_ADDR_CONST(0x9a)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_SCR                        0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_RESET_VAL                  _MK_MASK_CONST(0x200)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_RESET_MASK                         _MK_MASK_CONST(0x311)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_READ_MASK                  _MK_MASK_CONST(0x311)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_WRITE_MASK                         _MK_MASK_CONST(0x311)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_ENABLE_RANGE                       0:0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_ENABLE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_ENABLE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_ENABLE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_ENABLE_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_ENABLE_YES                 _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_ENABLE_DIS                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_ENABLE_EN                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_OTHER_SHIFT                        _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_OTHER_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_OTHER_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_OTHER_RANGE                        4:4
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_OTHER_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_OTHER_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_OTHER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_OTHER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_OTHER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_OTHER_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_OTHER_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_OTHER_DIS                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_OTHER_EN                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_SINGLE_SHIFT                       _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_SINGLE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_SINGLE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_SINGLE_RANGE                       8:8
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_SINGLE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_SINGLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_SINGLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_SINGLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_SINGLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_SINGLE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_SINGLE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_SINGLE_DIS                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_SINGLE_EN                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_CHKSUM_HW_SHIFT                    _MK_SHIFT_CONST(9)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_CHKSUM_HW_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_CHKSUM_HW_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_CHKSUM_HW_RANGE                    9:9
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_CHKSUM_HW_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_CHKSUM_HW_DEFAULT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_CHKSUM_HW_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_CHKSUM_HW_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_CHKSUM_HW_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_CHKSUM_HW_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_CHKSUM_HW_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_CHKSUM_HW_INIT_ENUM                        ENABLE
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_CHKSUM_HW_DISABLE                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0_CHKSUM_HW_ENABLE                   _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_STATUS_0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_STATUS_0                  _MK_ADDR_CONST(0x9b)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_STATUS_0_SECURE                   0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_STATUS_0_DUAL                     0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_STATUS_0_SCR                      0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_STATUS_0_WORD_COUNT                       0x1
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_STATUS_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_STATUS_0_SENT_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_STATUS_0_SENT_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_STATUS_0_SENT_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_STATUS_0_SENT_RANGE                       0:0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_STATUS_0_SENT_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_STATUS_0_SENT_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_STATUS_0_SENT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_STATUS_0_SENT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_STATUS_0_SENT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_STATUS_0_SENT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_STATUS_0_SENT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_STATUS_0_SENT_DONE                        _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_STATUS_0_SENT_WAITING                     _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0                  _MK_ADDR_CONST(0x9c)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_SECURE                   0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_DUAL                     0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_SCR                      0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_WORD_COUNT                       0x1
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_RESET_MASK                       _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_READ_MASK                        _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_WRITE_MASK                       _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB0_SHIFT                        _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB0_FIELD                        _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB0_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB0_RANGE                        7:0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB0_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB0_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB0_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB0_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB0_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB1_SHIFT                        _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB1_FIELD                        _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB1_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB1_RANGE                        15:8
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB1_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB1_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB1_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB1_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB2_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB2_FIELD                        _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB2_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB2_RANGE                        23:16
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB2_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB2_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB2_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB2_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0_HB2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0                    _MK_ADDR_CONST(0x9d)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_SCR                        0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB0_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB0_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB0_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB0_RANGE                  7:0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB0_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB0_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB0_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB0_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB0_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB1_SHIFT                  _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB1_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB1_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB1_RANGE                  15:8
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB1_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB1_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB1_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB1_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB1_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB2_SHIFT                  _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB2_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB2_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB2_RANGE                  23:16
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB2_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB2_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB2_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB2_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB2_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB3_SHIFT                  _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB3_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB3_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB3_RANGE                  31:24
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB3_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB3_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB3_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB3_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB3_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0                   _MK_ADDR_CONST(0x9e)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_SCR                       0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_READ_MASK                         _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB4_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB4_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB4_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB4_RANGE                 7:0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB4_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB4_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB4_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB4_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB4_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB5_SHIFT                 _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB5_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB5_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB5_RANGE                 15:8
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB5_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB5_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB5_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB5_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB5_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0                      _MK_ADDR_CONST(0x9f)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_SCR                  0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_RESET_VAL                    _MK_MASK_CONST(0x200)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_RESET_MASK                   _MK_MASK_CONST(0x311)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_READ_MASK                    _MK_MASK_CONST(0x311)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_WRITE_MASK                   _MK_MASK_CONST(0x311)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_ENABLE_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_ENABLE_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_ENABLE_RANGE                 0:0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_ENABLE_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_ENABLE_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_ENABLE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_ENABLE_INIT_ENUM                     NO
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_ENABLE_NO                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_ENABLE_YES                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_ENABLE_DIS                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_ENABLE_EN                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_OTHER_SHIFT                  _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_OTHER_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_OTHER_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_OTHER_RANGE                  4:4
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_OTHER_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_OTHER_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_OTHER_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_OTHER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_OTHER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_OTHER_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_OTHER_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_OTHER_INIT_ENUM                      DIS
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_OTHER_DIS                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_OTHER_EN                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_SINGLE_SHIFT                 _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_SINGLE_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_SINGLE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_SINGLE_RANGE                 8:8
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_SINGLE_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_SINGLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_SINGLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_SINGLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_SINGLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_SINGLE_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_SINGLE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_SINGLE_INIT_ENUM                     DIS
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_SINGLE_DIS                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_SINGLE_EN                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_CHKSUM_HW_SHIFT                      _MK_SHIFT_CONST(9)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_CHKSUM_HW_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_CHKSUM_HW_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_CHKSUM_HW_RANGE                      9:9
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_CHKSUM_HW_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_CHKSUM_HW_DEFAULT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_CHKSUM_HW_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_CHKSUM_HW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_CHKSUM_HW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_CHKSUM_HW_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_CHKSUM_HW_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_CHKSUM_HW_INIT_ENUM                  ENABLE
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_CHKSUM_HW_DISABLE                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0_CHKSUM_HW_ENABLE                     _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_STATUS_0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_STATUS_0                    _MK_ADDR_CONST(0xa0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_STATUS_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_STATUS_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_STATUS_0_SCR                        0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_STATUS_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_STATUS_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_STATUS_0_SENT_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_STATUS_0_SENT_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_STATUS_0_SENT_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_STATUS_0_SENT_RANGE                 0:0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_STATUS_0_SENT_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_STATUS_0_SENT_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_STATUS_0_SENT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_STATUS_0_SENT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_STATUS_0_SENT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_STATUS_0_SENT_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_STATUS_0_SENT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_STATUS_0_SENT_DONE                  _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_STATUS_0_SENT_WAITING                       _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0                    _MK_ADDR_CONST(0xa1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_SCR                        0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_RESET_MASK                         _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_READ_MASK                  _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_WRITE_MASK                         _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB0_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB0_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB0_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB0_RANGE                  7:0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB0_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB0_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB0_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB0_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB0_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB1_SHIFT                  _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB1_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB1_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB1_RANGE                  15:8
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB1_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB1_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB1_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB1_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB1_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB2_SHIFT                  _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB2_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB2_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB2_RANGE                  23:16
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB2_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB2_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB2_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB2_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0_HB2_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0                      _MK_ADDR_CONST(0xa2)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_SCR                  0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB0_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB0_FIELD                    _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB0_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB0_RANGE                    7:0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB0_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB0_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB0_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB0_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB1_SHIFT                    _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB1_FIELD                    _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB1_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB1_RANGE                    15:8
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB1_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB1_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB1_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB1_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB2_SHIFT                    _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB2_FIELD                    _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB2_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB2_RANGE                    23:16
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB2_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB2_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB2_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB2_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB2_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB3_SHIFT                    _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB3_FIELD                    _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB3_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB3_RANGE                    31:24
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB3_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB3_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB3_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB3_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0_PB3_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0                     _MK_ADDR_CONST(0xa3)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_SECURE                      0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_DUAL                        0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_SCR                         0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_WORD_COUNT                  0x1
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_RESET_MASK                  _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_READ_MASK                   _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB4_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB4_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB4_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB4_RANGE                   7:0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB4_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB4_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB4_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB4_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB4_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB5_SHIFT                   _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB5_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB5_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB5_RANGE                   15:8
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB5_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB5_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB5_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB5_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB5_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB6_SHIFT                   _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB6_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB6_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB6_RANGE                   23:16
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB6_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB6_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB6_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB6_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0_PB6_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0                      _MK_ADDR_CONST(0xa4)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_SCR                  0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB7_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB7_FIELD                    _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB7_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB7_RANGE                    7:0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB7_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB7_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB7_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB7_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB7_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB8_SHIFT                    _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB8_FIELD                    _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB8_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB8_RANGE                    15:8
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB8_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB8_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB8_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB8_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB8_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB8_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB8_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB9_SHIFT                    _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB9_FIELD                    _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB9_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB9_RANGE                    23:16
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB9_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB9_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB9_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB9_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB9_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB9_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB9_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB10_SHIFT                   _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB10_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB10_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB10_RANGE                   31:24
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB10_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB10_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB10_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB10_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB10_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB10_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0_PB10_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0                     _MK_ADDR_CONST(0xa5)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_SECURE                      0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_DUAL                        0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_SCR                         0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_WORD_COUNT                  0x1
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_RESET_MASK                  _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_READ_MASK                   _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB11_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB11_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB11_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB11_RANGE                  7:0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB11_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB11_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB11_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB11_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB11_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB11_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB11_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB12_SHIFT                  _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB12_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB12_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB12_RANGE                  15:8
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB12_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB12_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB12_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB12_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB12_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB12_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB12_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB13_SHIFT                  _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB13_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB13_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB13_RANGE                  23:16
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB13_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB13_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB13_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB13_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB13_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB13_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0_PB13_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0                    _MK_ADDR_CONST(0xa6)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_SCR                        0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_RESET_VAL                  _MK_MASK_CONST(0x10000)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_RESET_MASK                         _MK_MASK_CONST(0x11111)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_READ_MASK                  _MK_MASK_CONST(0x11111)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_WRITE_MASK                         _MK_MASK_CONST(0x11111)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_ENABLE_RANGE                       0:0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_ENABLE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_ENABLE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_ENABLE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_ENABLE_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_ENABLE_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_ENABLE_YES                 _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_ENABLE_DIS                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_ENABLE_EN                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_OTHER_SHIFT                        _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_OTHER_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_OTHER_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_OTHER_RANGE                        4:4
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_OTHER_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_OTHER_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_OTHER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_OTHER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_OTHER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_OTHER_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_OTHER_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_OTHER_INIT_ENUM                    DIS
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_OTHER_DIS                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_OTHER_EN                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_SINGLE_SHIFT                       _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_SINGLE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_SINGLE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_SINGLE_RANGE                       8:8
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_SINGLE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_SINGLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_SINGLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_SINGLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_SINGLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_SINGLE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_SINGLE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_SINGLE_INIT_ENUM                   DIS
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_SINGLE_DIS                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_SINGLE_EN                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_HBLANK_SHIFT                       _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_HBLANK_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_HBLANK_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_HBLANK_RANGE                       12:12
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_HBLANK_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_HBLANK_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_HBLANK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_HBLANK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_HBLANK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_HBLANK_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_HBLANK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_HBLANK_INIT_ENUM                   DIS
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_HBLANK_DIS                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_HBLANK_EN                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_AUDIO_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_AUDIO_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_AUDIO_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_AUDIO_RANGE                        16:16
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_AUDIO_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_AUDIO_DEFAULT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_AUDIO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_AUDIO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_AUDIO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_AUDIO_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_AUDIO_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_AUDIO_INIT_ENUM                    EN
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_AUDIO_DIS                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0_AUDIO_EN                   _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_HDMI_GENERIC_STATUS_0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_STATUS_0                  _MK_ADDR_CONST(0xa7)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_STATUS_0_SECURE                   0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_STATUS_0_DUAL                     0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_STATUS_0_SCR                      0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_STATUS_0_WORD_COUNT                       0x1
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_STATUS_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_STATUS_0_SENT_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_STATUS_0_SENT_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_GENERIC_STATUS_0_SENT_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_STATUS_0_SENT_RANGE                       0:0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_STATUS_0_SENT_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_STATUS_0_SENT_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_STATUS_0_SENT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_STATUS_0_SENT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_STATUS_0_SENT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_STATUS_0_SENT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_STATUS_0_SENT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_STATUS_0_SENT_DONE                        _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_STATUS_0_SENT_WAITING                     _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0                  _MK_ADDR_CONST(0xa8)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_SECURE                   0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_DUAL                     0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_SCR                      0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_WORD_COUNT                       0x1
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_RESET_MASK                       _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_READ_MASK                        _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_WRITE_MASK                       _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB0_SHIFT                        _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB0_FIELD                        _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB0_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB0_RANGE                        7:0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB0_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB0_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB0_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB0_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB0_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB1_SHIFT                        _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB1_FIELD                        _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB1_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB1_RANGE                        15:8
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB1_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB1_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB1_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB1_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB2_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB2_FIELD                        _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB2_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB2_RANGE                        23:16
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB2_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB2_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB2_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB2_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0_HB2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0                    _MK_ADDR_CONST(0xa9)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_SCR                        0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB0_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB0_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB0_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB0_RANGE                  7:0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB0_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB0_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB0_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB0_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB0_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB1_SHIFT                  _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB1_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB1_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB1_RANGE                  15:8
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB1_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB1_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB1_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB1_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB1_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB2_SHIFT                  _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB2_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB2_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB2_RANGE                  23:16
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB2_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB2_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB2_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB2_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB2_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB3_SHIFT                  _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB3_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB3_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB3_RANGE                  31:24
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB3_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB3_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB3_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB3_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0_PB3_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0                   _MK_ADDR_CONST(0xaa)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_SCR                       0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_RESET_MASK                        _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_READ_MASK                         _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_WRITE_MASK                        _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB4_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB4_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB4_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB4_RANGE                 7:0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB4_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB4_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB4_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB4_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB4_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB5_SHIFT                 _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB5_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB5_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB5_RANGE                 15:8
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB5_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB5_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB5_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB5_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB5_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB6_SHIFT                 _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB6_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB6_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB6_RANGE                 23:16
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB6_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB6_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB6_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB6_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0_PB6_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0                    _MK_ADDR_CONST(0xab)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_SCR                        0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB7_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB7_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB7_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB7_RANGE                  7:0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB7_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB7_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB7_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB7_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB7_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB8_SHIFT                  _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB8_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB8_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB8_RANGE                  15:8
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB8_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB8_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB8_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB8_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB8_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB8_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB8_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB9_SHIFT                  _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB9_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB9_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB9_RANGE                  23:16
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB9_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB9_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB9_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB9_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB9_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB9_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB9_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB10_SHIFT                 _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB10_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB10_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB10_RANGE                 31:24
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB10_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB10_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB10_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB10_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB10_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB10_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0_PB10_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0                   _MK_ADDR_CONST(0xac)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_SCR                       0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_RESET_MASK                        _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_READ_MASK                         _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_WRITE_MASK                        _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB11_SHIFT                        _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB11_FIELD                        _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB11_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB11_RANGE                        7:0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB11_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB11_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB11_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB11_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB11_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB11_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB11_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB12_SHIFT                        _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB12_FIELD                        _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB12_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB12_RANGE                        15:8
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB12_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB12_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB12_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB12_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB12_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB12_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB12_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB13_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB13_FIELD                        _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB13_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB13_RANGE                        23:16
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB13_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB13_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB13_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB13_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB13_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB13_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0_PB13_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0                    _MK_ADDR_CONST(0xad)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_SCR                        0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB14_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB14_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB14_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB14_RANGE                 7:0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB14_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB14_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB14_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB14_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB14_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB14_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB14_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB15_SHIFT                 _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB15_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB15_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB15_RANGE                 15:8
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB15_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB15_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB15_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB15_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB15_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB15_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB15_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB16_SHIFT                 _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB16_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB16_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB16_RANGE                 23:16
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB16_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB16_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB16_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB16_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB16_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB16_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB16_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB17_SHIFT                 _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB17_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB17_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB17_RANGE                 31:24
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB17_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB17_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB17_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB17_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB17_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB17_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0_PB17_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0                   _MK_ADDR_CONST(0xae)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_SCR                       0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_RESET_MASK                        _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_READ_MASK                         _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_WRITE_MASK                        _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB18_SHIFT                        _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB18_FIELD                        _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB18_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB18_RANGE                        7:0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB18_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB18_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB18_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB18_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB18_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB18_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB18_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB19_SHIFT                        _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB19_FIELD                        _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB19_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB19_RANGE                        15:8
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB19_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB19_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB19_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB19_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB19_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB19_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB19_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB20_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB20_FIELD                        _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB20_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB20_RANGE                        23:16
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB20_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB20_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB20_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB20_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB20_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB20_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0_PB20_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0                    _MK_ADDR_CONST(0xaf)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_SCR                        0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB21_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB21_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB21_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB21_RANGE                 7:0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB21_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB21_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB21_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB21_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB21_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB21_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB21_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB22_SHIFT                 _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB22_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB22_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB22_RANGE                 15:8
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB22_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB22_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB22_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB22_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB22_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB22_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB22_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB23_SHIFT                 _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB23_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB23_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB23_RANGE                 23:16
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB23_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB23_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB23_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB23_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB23_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB23_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB23_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB24_SHIFT                 _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB24_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB24_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB24_RANGE                 31:24
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB24_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB24_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB24_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB24_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB24_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB24_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0_PB24_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0                   _MK_ADDR_CONST(0xb0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_SCR                       0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_RESET_MASK                        _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_READ_MASK                         _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_WRITE_MASK                        _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB25_SHIFT                        _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB25_FIELD                        _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB25_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB25_RANGE                        7:0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB25_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB25_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB25_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB25_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB25_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB25_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB25_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB26_SHIFT                        _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB26_FIELD                        _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB26_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB26_RANGE                        15:8
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB26_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB26_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB26_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB26_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB26_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB26_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB26_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB27_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB27_FIELD                        _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB27_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB27_RANGE                        23:16
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB27_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB27_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB27_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB27_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB27_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB27_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0_PB27_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0                        _MK_ADDR_CONST(0xb1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_SECURE                         0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_DUAL                   0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_SCR                    0
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_WORD_COUNT                     0x1
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_RESET_VAL                      _MK_MASK_CONST(0x2010000)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_RESET_MASK                     _MK_MASK_CONST(0xf010101)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_READ_MASK                      _MK_MASK_CONST(0xf010101)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_WRITE_MASK                     _MK_MASK_CONST(0xf010101)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_PACKET_ENABLE_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_PACKET_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_PACKET_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_PACKET_ENABLE_RANGE                    0:0
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_PACKET_ENABLE_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_PACKET_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_PACKET_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_PACKET_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_PACKET_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_PACKET_ENABLE_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_PACKET_ENABLE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_PACKET_ENABLE_INIT_ENUM                        NO
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_PACKET_ENABLE_NO                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_PACKET_ENABLE_YES                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_PACKET_ENABLE_DIS                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_PACKET_ENABLE_EN                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_MEASURE_ENABLE_SHIFT                   _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_MEASURE_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_MEASURE_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_MEASURE_ENABLE_RANGE                   8:8
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_MEASURE_ENABLE_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_MEASURE_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_MEASURE_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_MEASURE_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_MEASURE_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_MEASURE_ENABLE_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_MEASURE_ENABLE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_MEASURE_ENABLE_INIT_ENUM                       NO
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_MEASURE_ENABLE_NO                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_MEASURE_ENABLE_YES                     _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_MEASURE_ENABLE_DIS                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_MEASURE_ENABLE_EN                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_ENABLE_SHIFT                     _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_ENABLE_RANGE                     16:16
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_ENABLE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_ENABLE_DEFAULT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_ENABLE_INIT_ENUM                 YES
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_ENABLE_NO                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_ENABLE_YES                       _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_ENABLE_DIS                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_ENABLE_EN                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_SHIFT                    _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_FIELD                    _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_RANGE                    27:24
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_DEFAULT                  _MK_MASK_CONST(0x2)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_INIT_ENUM                        FREQ_48KHZ
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_FREQ_32KHZ                       _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_FREQ_44_1KHZ                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_FREQ_48KHZ                       _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_FREQ_88_2KHZ                     _MK_ENUM_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_FREQ_96KHZ                       _MK_ENUM_CONST(10)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_FREQ_176_4KHZ                    _MK_ENUM_CONST(12)
#define SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0_FREQS_FREQ_192KHZ                      _MK_ENUM_CONST(14)

// Register SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0                    _MK_ADDR_CONST(0xb2)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SCR                        0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_RESET_MASK                         _MK_MASK_CONST(0xffffff00)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_READ_MASK                  _MK_MASK_CONST(0xffffff00)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_WRITE_MASK                         _MK_MASK_CONST(0xffffff00)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB1_SHIFT                  _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB1_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB1_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB1_RANGE                  31:24
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB1_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB1_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB1_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB1_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB1_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB2_SHIFT                  _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB2_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB2_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB2_RANGE                  23:16
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB2_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB2_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB2_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB2_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB2_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB3_SHIFT                  _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB3_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB3_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB3_RANGE                  15:8
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB3_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB3_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB3_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB3_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0_SB3_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0                   _MK_ADDR_CONST(0xb3)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SCR                       0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_RESET_MASK                        _MK_MASK_CONST(0x80ffffff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_READ_MASK                         _MK_MASK_CONST(0x80ffffff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_WRITE_MASK                        _MK_MASK_CONST(0x80ffffff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB6_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB6_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB6_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB6_RANGE                 7:0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB6_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB6_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB6_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB6_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB6_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB5_SHIFT                 _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB5_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB5_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB5_RANGE                 15:8
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB5_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB5_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB5_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB5_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB5_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB4_SHIFT                 _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB4_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB4_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB4_RANGE                 23:16
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB4_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB4_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB4_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB4_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_SB4_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_ENABLE_SHIFT                      _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_ENABLE_RANGE                      31:31
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_ENABLE_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_ENABLE_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_ENABLE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_ENABLE_INIT_ENUM                  NO
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_ENABLE_NO                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_ENABLE_YES                        _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_ENABLE_DIS                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0_ENABLE_EN                 _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0                    _MK_ADDR_CONST(0xb4)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SCR                        0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_RESET_MASK                         _MK_MASK_CONST(0xffffff00)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_READ_MASK                  _MK_MASK_CONST(0xffffff00)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_WRITE_MASK                         _MK_MASK_CONST(0xffffff00)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB3_SHIFT                  _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB3_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB3_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB3_RANGE                  15:8
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB3_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB3_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB3_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB3_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB3_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB2_SHIFT                  _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB2_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB2_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB2_RANGE                  23:16
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB2_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB2_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB2_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB2_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB2_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB1_SHIFT                  _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB1_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB1_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB1_RANGE                  31:24
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB1_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB1_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB1_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB1_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB1_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0_SB1_USE_HW_CTS_VAL                 _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0                   _MK_ADDR_CONST(0xb5)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SCR                       0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_RESET_MASK                        _MK_MASK_CONST(0x80ffffff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_READ_MASK                         _MK_MASK_CONST(0x80ffffff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_WRITE_MASK                        _MK_MASK_CONST(0x80ffffff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB6_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB6_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB6_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB6_RANGE                 7:0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB6_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB6_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB6_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB6_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB6_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB5_SHIFT                 _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB5_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB5_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB5_RANGE                 15:8
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB5_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB5_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB5_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB5_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB5_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB4_SHIFT                 _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB4_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB4_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB4_RANGE                 23:16
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB4_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB4_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB4_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB4_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_SB4_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_ENABLE_SHIFT                      _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_ENABLE_RANGE                      31:31
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_ENABLE_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_ENABLE_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_ENABLE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_ENABLE_INIT_ENUM                  NO
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_ENABLE_NO                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_ENABLE_YES                        _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_ENABLE_DIS                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0_ENABLE_EN                 _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0                    _MK_ADDR_CONST(0xb6)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SCR                        0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_RESET_MASK                         _MK_MASK_CONST(0xffffff00)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_READ_MASK                  _MK_MASK_CONST(0xffffff00)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_WRITE_MASK                         _MK_MASK_CONST(0xffffff00)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB3_SHIFT                  _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB3_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB3_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB3_RANGE                  15:8
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB3_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB3_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB3_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB3_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB3_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB2_SHIFT                  _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB2_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB2_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB2_RANGE                  23:16
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB2_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB2_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB2_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB2_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB2_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB1_SHIFT                  _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB1_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB1_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB1_RANGE                  31:24
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB1_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB1_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB1_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB1_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0_SB1_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0                   _MK_ADDR_CONST(0xb7)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SCR                       0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_RESET_MASK                        _MK_MASK_CONST(0x80ffffff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_READ_MASK                         _MK_MASK_CONST(0x80ffffff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_WRITE_MASK                        _MK_MASK_CONST(0x80ffffff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB6_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB6_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB6_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB6_RANGE                 7:0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB6_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB6_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB6_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB6_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB6_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB5_SHIFT                 _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB5_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB5_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB5_RANGE                 15:8
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB5_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB5_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB5_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB5_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB5_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB4_SHIFT                 _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB4_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB4_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB4_RANGE                 23:16
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB4_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB4_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB4_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB4_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_SB4_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_ENABLE_SHIFT                      _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_ENABLE_RANGE                      31:31
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_ENABLE_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_ENABLE_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_ENABLE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_ENABLE_INIT_ENUM                  NO
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_ENABLE_NO                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_ENABLE_YES                        _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_ENABLE_DIS                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0_ENABLE_EN                 _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0                    _MK_ADDR_CONST(0xb8)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SCR                        0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_RESET_MASK                         _MK_MASK_CONST(0xffffff00)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_READ_MASK                  _MK_MASK_CONST(0xffffff00)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_WRITE_MASK                         _MK_MASK_CONST(0xffffff00)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB3_SHIFT                  _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB3_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB3_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB3_RANGE                  15:8
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB3_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB3_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB3_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB3_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB3_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB2_SHIFT                  _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB2_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB2_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB2_RANGE                  23:16
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB2_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB2_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB2_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB2_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB2_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB1_SHIFT                  _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB1_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB1_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB1_RANGE                  31:24
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB1_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB1_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB1_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB1_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0_SB1_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0                   _MK_ADDR_CONST(0xb9)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SCR                       0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_RESET_MASK                        _MK_MASK_CONST(0x80ffffff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_READ_MASK                         _MK_MASK_CONST(0x80ffffff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_WRITE_MASK                        _MK_MASK_CONST(0x80ffffff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB6_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB6_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB6_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB6_RANGE                 7:0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB6_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB6_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB6_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB6_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB6_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB5_SHIFT                 _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB5_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB5_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB5_RANGE                 15:8
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB5_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB5_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB5_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB5_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB5_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB4_SHIFT                 _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB4_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB4_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB4_RANGE                 23:16
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB4_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB4_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB4_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB4_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_SB4_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_ENABLE_SHIFT                      _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_ENABLE_RANGE                      31:31
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_ENABLE_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_ENABLE_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_ENABLE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_ENABLE_INIT_ENUM                  NO
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_ENABLE_NO                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_ENABLE_YES                        _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_ENABLE_DIS                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0_ENABLE_EN                 _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0                    _MK_ADDR_CONST(0xba)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SCR                        0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_RESET_MASK                         _MK_MASK_CONST(0xffffff00)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_READ_MASK                  _MK_MASK_CONST(0xffffff00)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_WRITE_MASK                         _MK_MASK_CONST(0xffffff00)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB3_SHIFT                  _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB3_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB3_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB3_RANGE                  15:8
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB3_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB3_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB3_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB3_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB3_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB2_SHIFT                  _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB2_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB2_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB2_RANGE                  23:16
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB2_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB2_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB2_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB2_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB2_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB1_SHIFT                  _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB1_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB1_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB1_RANGE                  31:24
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB1_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB1_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB1_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB1_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0_SB1_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0                   _MK_ADDR_CONST(0xbb)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SCR                       0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_RESET_MASK                        _MK_MASK_CONST(0x80ffffff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_READ_MASK                         _MK_MASK_CONST(0x80ffffff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_WRITE_MASK                        _MK_MASK_CONST(0x80ffffff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB6_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB6_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB6_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB6_RANGE                 7:0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB6_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB6_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB6_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB6_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB6_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB5_SHIFT                 _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB5_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB5_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB5_RANGE                 15:8
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB5_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB5_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB5_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB5_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB5_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB4_SHIFT                 _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB4_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB4_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB4_RANGE                 23:16
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB4_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB4_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB4_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB4_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_SB4_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_ENABLE_SHIFT                      _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_ENABLE_RANGE                      31:31
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_ENABLE_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_ENABLE_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_ENABLE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_ENABLE_INIT_ENUM                  NO
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_ENABLE_NO                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_ENABLE_YES                        _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_ENABLE_DIS                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0_ENABLE_EN                 _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0                    _MK_ADDR_CONST(0xbc)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SCR                        0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_RESET_MASK                         _MK_MASK_CONST(0xffffff00)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_READ_MASK                  _MK_MASK_CONST(0xffffff00)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_WRITE_MASK                         _MK_MASK_CONST(0xffffff00)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB3_SHIFT                  _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB3_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB3_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB3_RANGE                  15:8
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB3_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB3_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB3_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB3_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB3_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB2_SHIFT                  _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB2_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB2_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB2_RANGE                  23:16
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB2_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB2_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB2_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB2_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB2_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB1_SHIFT                  _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB1_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB1_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB1_RANGE                  31:24
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB1_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB1_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB1_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB1_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0_SB1_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0                   _MK_ADDR_CONST(0xbd)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SCR                       0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_RESET_MASK                        _MK_MASK_CONST(0x80ffffff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_READ_MASK                         _MK_MASK_CONST(0x80ffffff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_WRITE_MASK                        _MK_MASK_CONST(0x80ffffff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB6_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB6_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB6_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB6_RANGE                 7:0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB6_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB6_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB6_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB6_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB6_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB5_SHIFT                 _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB5_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB5_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB5_RANGE                 15:8
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB5_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB5_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB5_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB5_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB5_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB4_SHIFT                 _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB4_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB4_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB4_RANGE                 23:16
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB4_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB4_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB4_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB4_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_SB4_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_ENABLE_SHIFT                      _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_ENABLE_RANGE                      31:31
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_ENABLE_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_ENABLE_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_ENABLE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_ENABLE_INIT_ENUM                  NO
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_ENABLE_NO                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_ENABLE_YES                        _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_ENABLE_DIS                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0_ENABLE_EN                 _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0                    _MK_ADDR_CONST(0xbe)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SCR                        0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_RESET_MASK                         _MK_MASK_CONST(0xffffff00)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_READ_MASK                  _MK_MASK_CONST(0xffffff00)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_WRITE_MASK                         _MK_MASK_CONST(0xffffff00)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB3_SHIFT                  _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB3_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB3_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB3_RANGE                  15:8
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB3_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB3_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB3_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB3_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB3_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB2_SHIFT                  _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB2_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB2_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB2_RANGE                  23:16
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB2_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB2_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB2_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB2_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB2_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB1_SHIFT                  _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB1_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB1_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB1_RANGE                  31:24
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB1_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB1_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB1_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB1_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0_SB1_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0                   _MK_ADDR_CONST(0xbf)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SCR                       0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_RESET_MASK                        _MK_MASK_CONST(0x80ffffff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_READ_MASK                         _MK_MASK_CONST(0x80ffffff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_WRITE_MASK                        _MK_MASK_CONST(0x80ffffff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB6_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB6_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB6_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB6_RANGE                 7:0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB6_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB6_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB6_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB6_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB6_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB5_SHIFT                 _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB5_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB5_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB5_RANGE                 15:8
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB5_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB5_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB5_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB5_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB5_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB4_SHIFT                 _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB4_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB4_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB4_RANGE                 23:16
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB4_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB4_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB4_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB4_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_SB4_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_ENABLE_SHIFT                      _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_ENABLE_RANGE                      31:31
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_ENABLE_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_ENABLE_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_ENABLE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_ENABLE_INIT_ENUM                  NO
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_ENABLE_NO                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_ENABLE_YES                        _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_ENABLE_DIS                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0_ENABLE_EN                 _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_HDMI_CTRL_0
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0                    _MK_ADDR_CONST(0xc0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SCR                        0
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_RESET_VAL                  _MK_MASK_CONST(0x20038)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_RESET_MASK                         _MK_MASK_CONST(0x5f1f157f)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_READ_MASK                  _MK_MASK_CONST(0x5f1f157f)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_WRITE_MASK                         _MK_MASK_CONST(0x5f1f157f)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_REKEY_SHIFT                        _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_REKEY_FIELD                        _MK_FIELD_CONST(0x7f, SOR_NV_PDISP_SOR_HDMI_CTRL_0_REKEY_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_REKEY_RANGE                        6:0
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_REKEY_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_REKEY_DEFAULT                      _MK_MASK_CONST(0x38)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_REKEY_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_REKEY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_REKEY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_REKEY_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_REKEY_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_SHIFT                 _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_RANGE                 8:8
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_INIT_ENUM                     LAYOUT_2CH
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_LAYOUT_2CH                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_LAYOUT_8CH                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_SELECT_SHIFT                  _MK_SHIFT_CONST(10)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_SELECT_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_SELECT_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_SELECT_RANGE                  10:10
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_SELECT_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_SELECT_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_SELECT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_SELECT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_SELECT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_SELECT_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_SELECT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_SELECT_INIT_ENUM                      HW_BASED
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_SELECT_HW_BASED                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_AUDIO_LAYOUT_SELECT_SW_BASED                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SAMPLE_FLAT_SHIFT                  _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SAMPLE_FLAT_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_CTRL_0_SAMPLE_FLAT_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SAMPLE_FLAT_RANGE                  12:12
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SAMPLE_FLAT_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SAMPLE_FLAT_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SAMPLE_FLAT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SAMPLE_FLAT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SAMPLE_FLAT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SAMPLE_FLAT_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SAMPLE_FLAT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SAMPLE_FLAT_INIT_ENUM                      CLR
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SAMPLE_FLAT_CLR                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SAMPLE_FLAT_SET                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_MAX_AC_PACKET_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_MAX_AC_PACKET_FIELD                        _MK_FIELD_CONST(0x1f, SOR_NV_PDISP_SOR_HDMI_CTRL_0_MAX_AC_PACKET_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_MAX_AC_PACKET_RANGE                        20:16
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_MAX_AC_PACKET_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_MAX_AC_PACKET_DEFAULT                      _MK_MASK_CONST(0x2)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_MAX_AC_PACKET_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_MAX_AC_PACKET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_MAX_AC_PACKET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_MAX_AC_PACKET_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_MAX_AC_PACKET_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CT_SELECT_SHIFT                    _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CT_SELECT_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_CTRL_0_CT_SELECT_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CT_SELECT_RANGE                    24:24
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CT_SELECT_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CT_SELECT_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CT_SELECT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CT_SELECT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CT_SELECT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CT_SELECT_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CT_SELECT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CT_SELECT_INIT_ENUM                        SW
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CT_SELECT_SW                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CT_SELECT_HW                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CC_SELECT_SHIFT                    _MK_SHIFT_CONST(25)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CC_SELECT_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_CTRL_0_CC_SELECT_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CC_SELECT_RANGE                    25:25
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CC_SELECT_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CC_SELECT_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CC_SELECT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CC_SELECT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CC_SELECT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CC_SELECT_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CC_SELECT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CC_SELECT_INIT_ENUM                        SW
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CC_SELECT_SW                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CC_SELECT_HW                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SF_SELECT_SHIFT                    _MK_SHIFT_CONST(26)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SF_SELECT_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_CTRL_0_SF_SELECT_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SF_SELECT_RANGE                    26:26
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SF_SELECT_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SF_SELECT_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SF_SELECT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SF_SELECT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SF_SELECT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SF_SELECT_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SF_SELECT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SF_SELECT_INIT_ENUM                        SW
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SF_SELECT_SW                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SF_SELECT_HW                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SS_SELECT_SHIFT                    _MK_SHIFT_CONST(27)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SS_SELECT_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_CTRL_0_SS_SELECT_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SS_SELECT_RANGE                    27:27
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SS_SELECT_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SS_SELECT_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SS_SELECT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SS_SELECT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SS_SELECT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SS_SELECT_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SS_SELECT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SS_SELECT_INIT_ENUM                        SW
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SS_SELECT_SW                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_SS_SELECT_HW                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CA_SELECT_SHIFT                    _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CA_SELECT_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_CTRL_0_CA_SELECT_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CA_SELECT_RANGE                    28:28
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CA_SELECT_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CA_SELECT_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CA_SELECT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CA_SELECT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CA_SELECT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CA_SELECT_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CA_SELECT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CA_SELECT_INIT_ENUM                        SW
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CA_SELECT_SW                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_CA_SELECT_HW                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_ENABLE_SHIFT                       _MK_SHIFT_CONST(30)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_CTRL_0_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_ENABLE_RANGE                       30:30
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_ENABLE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_ENABLE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_ENABLE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_ENABLE_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_ENABLE_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_ENABLE_YES                 _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_ENABLE_DIS                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_CTRL_0_ENABLE_EN                  _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0                   _MK_ADDR_CONST(0xc1)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_SCR                       0
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_RESET_VAL                         _MK_MASK_CONST(0x819a028a)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_RESET_MASK                        _MK_MASK_CONST(0x83ff03ff)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_READ_MASK                         _MK_MASK_CONST(0x83ff03ff)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_WRITE_MASK                        _MK_MASK_CONST(0x83ff03ff)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_END_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_END_FIELD                 _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_END_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_END_RANGE                 9:0
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_END_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_END_DEFAULT                       _MK_MASK_CONST(0x28a)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_END_DEFAULT_MASK                  _MK_MASK_CONST(0x3ff)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_END_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_END_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_END_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_END_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_START_SHIFT                       _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_START_FIELD                       _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_START_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_START_RANGE                       25:16
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_START_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_START_DEFAULT                     _MK_MASK_CONST(0x19a)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_START_DEFAULT_MASK                        _MK_MASK_CONST(0x3ff)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_START_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_START_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_START_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_START_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_ENABLE_SHIFT                      _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_ENABLE_RANGE                      31:31
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_ENABLE_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_ENABLE_DEFAULT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_ENABLE_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_ENABLE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_ENABLE_INIT_ENUM                  YES
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_ENABLE_NO                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_ENABLE_YES                        _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_ENABLE_DIS                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0_ENABLE_EN                 _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0                    _MK_ADDR_CONST(0xc2)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_SCR                        0
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_RESET_VAL                  _MK_MASK_CONST(0x82000210)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_RESET_MASK                         _MK_MASK_CONST(0x83ff03ff)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_READ_MASK                  _MK_MASK_CONST(0x83ff03ff)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_WRITE_MASK                         _MK_MASK_CONST(0x83ff03ff)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_END_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_END_FIELD                  _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_END_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_END_RANGE                  9:0
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_END_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_END_DEFAULT                        _MK_MASK_CONST(0x210)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_END_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_END_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_END_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_END_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_END_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_START_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_START_FIELD                        _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_START_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_START_RANGE                        25:16
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_START_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_START_DEFAULT                      _MK_MASK_CONST(0x200)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_START_DEFAULT_MASK                 _MK_MASK_CONST(0x3ff)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_START_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_START_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_START_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_START_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_ENABLE_SHIFT                       _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_ENABLE_RANGE                       31:31
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_ENABLE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_ENABLE_DEFAULT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_ENABLE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_ENABLE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_ENABLE_INIT_ENUM                   YES
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_ENABLE_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_ENABLE_YES                 _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_ENABLE_DIS                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0_ENABLE_EN                  _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0                        _MK_ADDR_CONST(0xc3)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_SECURE                         0x0
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_DUAL                   0x0
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_SCR                    0
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_WORD_COUNT                     0x1
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_RESET_MASK                     _MK_MASK_CONST(0x111)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_READ_MASK                      _MK_MASK_CONST(0x111)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_WRITE_MASK                     _MK_MASK_CONST(0x111)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_ENABLE_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_ENABLE_RANGE                   0:0
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_ENABLE_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_ENABLE_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_ENABLE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_ENABLE_INIT_ENUM                       NO
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_ENABLE_NO                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_ENABLE_YES                     _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_ENABLE_DIS                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_ENABLE_EN                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_OTHER_SHIFT                    _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_OTHER_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_OTHER_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_OTHER_RANGE                    4:4
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_OTHER_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_OTHER_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_OTHER_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_OTHER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_OTHER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_OTHER_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_OTHER_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_OTHER_INIT_ENUM                        DIS
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_OTHER_DIS                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_OTHER_EN                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_SINGLE_SHIFT                   _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_SINGLE_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_SINGLE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_SINGLE_RANGE                   8:8
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_SINGLE_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_SINGLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_SINGLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_SINGLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_SINGLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_SINGLE_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_SINGLE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_SINGLE_INIT_ENUM                       DIS
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_SINGLE_DIS                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0_SINGLE_EN                      _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0                      _MK_ADDR_CONST(0xc4)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_SCR                  0
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_READ_MASK                    _MK_MASK_CONST(0x7777771)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_SENT_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_SENT_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_SENT_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_SENT_RANGE                   0:0
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_SENT_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_SENT_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_SENT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_SENT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_SENT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_SENT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_SENT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_SENT_WAITING                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_SENT_DONE                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_START_PP_SHIFT                        _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_START_PP_FIELD                        _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_START_PP_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_START_PP_RANGE                        6:4
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_START_PP_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_START_PP_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_START_PP_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_START_PP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_START_PP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_START_PP_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_START_PP_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_START_PP_PP_1                 _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_START_PP_PP_2                 _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_START_PP_PP_3                 _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_START_PP_PP_0                 _MK_ENUM_CONST(4)

#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_END_PP_SHIFT                  _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_END_PP_FIELD                  _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_END_PP_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_END_PP_RANGE                  10:8
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_END_PP_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_END_PP_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_END_PP_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_END_PP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_END_PP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_END_PP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_END_PP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_END_PP_PP_1                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_END_PP_PP_2                   _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_END_PP_PP_3                   _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_ACTIVE_END_PP_PP_0                   _MK_ENUM_CONST(4)

#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_START_PP_SHIFT                 _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_START_PP_FIELD                 _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_START_PP_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_START_PP_RANGE                 14:12
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_START_PP_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_START_PP_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_START_PP_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_START_PP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_START_PP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_START_PP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_START_PP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_START_PP_PP_1                  _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_START_PP_PP_2                  _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_START_PP_PP_3                  _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_START_PP_PP_0                  _MK_ENUM_CONST(4)

#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_END_PP_SHIFT                   _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_END_PP_FIELD                   _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_END_PP_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_END_PP_RANGE                   18:16
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_END_PP_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_END_PP_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_END_PP_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_END_PP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_END_PP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_END_PP_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_END_PP_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_END_PP_PP_1                    _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_END_PP_PP_2                    _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_END_PP_PP_3                    _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_VSYNC_END_PP_PP_0                    _MK_ENUM_CONST(4)

#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_START_PP_SHIFT                 _MK_SHIFT_CONST(20)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_START_PP_FIELD                 _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_START_PP_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_START_PP_RANGE                 22:20
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_START_PP_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_START_PP_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_START_PP_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_START_PP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_START_PP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_START_PP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_START_PP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_START_PP_PP_1                  _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_START_PP_PP_2                  _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_START_PP_PP_3                  _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_START_PP_PP_0                  _MK_ENUM_CONST(4)

#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_END_PP_SHIFT                   _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_END_PP_FIELD                   _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_END_PP_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_END_PP_RANGE                   26:24
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_END_PP_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_END_PP_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_END_PP_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_END_PP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_END_PP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_END_PP_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_END_PP_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_END_PP_PP_1                    _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_END_PP_PP_2                    _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_END_PP_PP_3                    _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0_HSYNC_END_PP_PP_0                    _MK_ENUM_CONST(4)

// Register SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0                     _MK_ADDR_CONST(0xc5)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SECURE                      0x0
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_DUAL                        0x0
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SCR                         0
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_WORD_COUNT                  0x1
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_RESET_MASK                  _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_READ_MASK                   _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB0_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB0_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB0_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB0_RANGE                   7:0
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB0_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB0_DEFAULT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB0_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB0_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB0_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB0_SET_AVMUTE                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB0_CLR_AVMUTE                      _MK_ENUM_CONST(16)

#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB1_SHIFT                   _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB1_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB1_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB1_RANGE                   15:8
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB1_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB1_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB1_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB1_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB1_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB2_SHIFT                   _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB2_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB2_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB2_RANGE                   23:16
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB2_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB2_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB2_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB2_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0_SB2_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0                 _MK_ADDR_CONST(0xc6)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_SCR                     0
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_RESET_VAL                       _MK_MASK_CONST(0xf2ffffff)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_ABCDM_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_ABCDM_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_ABCDM_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_ABCDM_RANGE                     7:0
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_ABCDM_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_ABCDM_DEFAULT                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_ABCDM_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_ABCDM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_ABCDM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_ABCDM_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_ABCDM_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_CODE_SHIFT                      _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_CODE_FIELD                      _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_CODE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_CODE_RANGE                      15:8
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_CODE_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_CODE_DEFAULT                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_CODE_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_CODE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_CODE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_CODE_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_CODE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_SOURCE_SHIFT                    _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_SOURCE_FIELD                    _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_SOURCE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_SOURCE_RANGE                    19:16
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_SOURCE_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_SOURCE_DEFAULT                  _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_SOURCE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_SOURCE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_SOURCE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_SOURCE_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_SOURCE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_CHANNEL_SHIFT                   _MK_SHIFT_CONST(20)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_CHANNEL_FIELD                   _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_CHANNEL_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_CHANNEL_RANGE                   23:20
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_CHANNEL_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_CHANNEL_DEFAULT                 _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_CHANNEL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_CHANNEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_CHANNEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_CHANNEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_CHANNEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_SFREQ_SHIFT                     _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_SFREQ_FIELD                     _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_SFREQ_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_SFREQ_RANGE                     27:24
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_SFREQ_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_SFREQ_DEFAULT                   _MK_MASK_CONST(0x2)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_SFREQ_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_SFREQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_SFREQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_SFREQ_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_SFREQ_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_SFREQ_UNDEFINED                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_ACCURACY_SHIFT                  _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_ACCURACY_FIELD                  _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_ACCURACY_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_ACCURACY_RANGE                  31:28
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_ACCURACY_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_ACCURACY_DEFAULT                        _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_ACCURACY_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_ACCURACY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_ACCURACY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_ACCURACY_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_ACCURACY_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_ACCURACY_LVL1                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_ACCURACY_LVL2                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_ACCURACY_LVL3                   _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0_ACCURACY_OTHER                  _MK_ENUM_CONST(3)

// Register SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0                 _MK_ADDR_CONST(0xc7)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_SCR                     0
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_RESET_VAL                       _MK_MASK_CONST(0xf1)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_RESET_MASK                      _MK_MASK_CONST(0x800000ff)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_READ_MASK                       _MK_MASK_CONST(0x800000ff)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_WRITE_MASK                      _MK_MASK_CONST(0x800000ff)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_MAX_LENGTH_SHIFT                        _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_MAX_LENGTH_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_MAX_LENGTH_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_MAX_LENGTH_RANGE                        0:0
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_MAX_LENGTH_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_MAX_LENGTH_DEFAULT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_MAX_LENGTH_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_MAX_LENGTH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_MAX_LENGTH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_MAX_LENGTH_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_MAX_LENGTH_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_LENGTH_SHIFT                    _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_LENGTH_FIELD                    _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_LENGTH_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_LENGTH_RANGE                    3:1
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_LENGTH_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_LENGTH_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_LENGTH_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_LENGTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_LENGTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_LENGTH_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_LENGTH_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_LENGTH_MAX20_UNDEF                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_LENGTH_MAX20_16BITS                     _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_LENGTH_MAX20_18BITS                     _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_LENGTH_MAX20_19BITS                     _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_LENGTH_MAX20_20BITS                     _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_LENGTH_MAX20_17BITS                     _MK_ENUM_CONST(6)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_LENGTH_MAX24_UNDEF                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_LENGTH_MAX24_20BITS                     _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_LENGTH_MAX24_22BITS                     _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_LENGTH_MAX24_23BITS                     _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_LENGTH_MAX24_24BITS                     _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_LENGTH_MAX24_21BITS                     _MK_ENUM_CONST(6)

#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ORIGINAL_SHIFT                  _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ORIGINAL_FIELD                  _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ORIGINAL_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ORIGINAL_RANGE                  7:4
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ORIGINAL_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ORIGINAL_DEFAULT                        _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ORIGINAL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ORIGINAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ORIGINAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ORIGINAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ORIGINAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ORIGINAL_UNDEFINED                      _MK_ENUM_CONST(0)

#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ENABLE_SHIFT                    _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ENABLE_RANGE                    31:31
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ENABLE_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ENABLE_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ENABLE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ENABLE_INIT_ENUM                        NO
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ENABLE_NO                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ENABLE_YES                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ENABLE_DIS                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0_ENABLE_EN                       _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_HDMI_EMU0_0
#define SOR_NV_PDISP_SOR_HDMI_EMU0_0                    _MK_ADDR_CONST(0xc8)
#define SOR_NV_PDISP_SOR_HDMI_EMU0_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_HDMI_EMU0_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_HDMI_EMU0_0_SCR                        0
#define SOR_NV_PDISP_SOR_HDMI_EMU0_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_HDMI_EMU0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_EMU0_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_EMU0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_EMU0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_EMU0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_EMU0_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_EMU0_0_regx_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_EMU0_0_regx_FIELD                 _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_HDMI_EMU0_0_regx_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_EMU0_0_regx_RANGE                 31:0
#define SOR_NV_PDISP_SOR_HDMI_EMU0_0_regx_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_EMU0_0_regx_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_EMU0_0_regx_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_EMU0_0_regx_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_EMU0_0_regx_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_EMU0_0_regx_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_EMU0_0_regx_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_EMU1_0
#define SOR_NV_PDISP_SOR_HDMI_EMU1_0                    _MK_ADDR_CONST(0xc9)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_HDMI_EMU1_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_HDMI_EMU1_0_SCR                        0
#define SOR_NV_PDISP_SOR_HDMI_EMU1_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_HDMI_EMU1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_0_regx_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_0_regx_FIELD                 _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_HDMI_EMU1_0_regx_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_0_regx_RANGE                 31:0
#define SOR_NV_PDISP_SOR_HDMI_EMU1_0_regx_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_EMU1_0_regx_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_0_regx_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_0_regx_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_0_regx_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_0_regx_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_0_regx_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_EMU1_RDATA_0
#define SOR_NV_PDISP_SOR_HDMI_EMU1_RDATA_0                      _MK_ADDR_CONST(0xca)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_RDATA_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_HDMI_EMU1_RDATA_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_HDMI_EMU1_RDATA_0_SCR                  0
#define SOR_NV_PDISP_SOR_HDMI_EMU1_RDATA_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_HDMI_EMU1_RDATA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_RDATA_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_RDATA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_RDATA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_RDATA_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_RDATA_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_RDATA_0_rdata_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_RDATA_0_rdata_FIELD                  _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_HDMI_EMU1_RDATA_0_rdata_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_RDATA_0_rdata_RANGE                  31:0
#define SOR_NV_PDISP_SOR_HDMI_EMU1_RDATA_0_rdata_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_EMU1_RDATA_0_rdata_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_RDATA_0_rdata_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_RDATA_0_rdata_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_RDATA_0_rdata_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_RDATA_0_rdata_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_EMU1_RDATA_0_rdata_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_SPARE_0
#define SOR_NV_PDISP_SOR_HDMI_SPARE_0                   _MK_ADDR_CONST(0xcb)
#define SOR_NV_PDISP_SOR_HDMI_SPARE_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_HDMI_SPARE_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_HDMI_SPARE_0_SCR                       0
#define SOR_NV_PDISP_SOR_HDMI_SPARE_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_HDMI_SPARE_0_RESET_VAL                         _MK_MASK_CONST(0x10000)
#define SOR_NV_PDISP_SOR_HDMI_SPARE_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_SPARE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPARE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPARE_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_SPARE_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_SPARE_0_ECO_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_SPARE_0_ECO_FIELD                 _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_HDMI_SPARE_0_ECO_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_SPARE_0_ECO_RANGE                 31:0
#define SOR_NV_PDISP_SOR_HDMI_SPARE_0_ECO_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_SPARE_0_ECO_DEFAULT                       _MK_MASK_CONST(0x10000)
#define SOR_NV_PDISP_SOR_HDMI_SPARE_0_ECO_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_SPARE_0_ECO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPARE_0_ECO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPARE_0_ECO_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_SPARE_0_ECO_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0                       _MK_ADDR_CONST(0xcc)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SECURE                        0x0
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_DUAL                  0x0
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SCR                   0
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_WORD_COUNT                    0x1
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_USE_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_USE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_USE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_USE_RANGE                     0:0
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_USE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_USE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_USE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_USE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_USE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_USE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_USE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_USE_CONSUMER                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_USE_PRO                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_TYPE_SHIFT                    _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_TYPE_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_TYPE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_TYPE_RANGE                    1:1
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_TYPE_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_TYPE_PCM                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_TYPE_OTHER                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_COPYRIGHT_SHIFT                       _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_COPYRIGHT_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_COPYRIGHT_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_COPYRIGHT_RANGE                       2:2
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_COPYRIGHT_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_COPYRIGHT_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_COPYRIGHT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_COPYRIGHT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_COPYRIGHT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_COPYRIGHT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_COPYRIGHT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_COPYRIGHT_YES                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_COPYRIGHT_NO                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_D_SHIFT                       _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_D_FIELD                       _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_D_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_D_RANGE                       5:3
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_D_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_D_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_D_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_D_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_D_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_D_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_D_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_D_NO_PREEMPHASIS                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_D_PREEMPHASIS                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_MODE_SHIFT                    _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_MODE_FIELD                    _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_MODE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_MODE_RANGE                    7:6
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_MODE_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_MODE_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_MODE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_MODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_MODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_MODE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_MODE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_CODE_SHIFT                    _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_CODE_FIELD                    _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_CODE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_CODE_RANGE                    15:8
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_CODE_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_CODE_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_CODE_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_CODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_CODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_CODE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_CODE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SOURCE_SHIFT                  _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SOURCE_FIELD                  _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SOURCE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SOURCE_RANGE                  19:16
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SOURCE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SOURCE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SOURCE_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SOURCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SOURCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SOURCE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SOURCE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SOURCE_UNDEFINED                      _MK_ENUM_CONST(0)

#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_CHANNEL_SHIFT                 _MK_SHIFT_CONST(20)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_CHANNEL_FIELD                 _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_CHANNEL_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_CHANNEL_RANGE                 23:20
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_CHANNEL_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_CHANNEL_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_CHANNEL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_CHANNEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_CHANNEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_CHANNEL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_CHANNEL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_CHANNEL_UNDEFINED                     _MK_ENUM_CONST(0)

#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SFREQ_SHIFT                   _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SFREQ_FIELD                   _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SFREQ_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SFREQ_RANGE                   27:24
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SFREQ_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SFREQ_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SFREQ_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SFREQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SFREQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SFREQ_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SFREQ_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_SFREQ_UNDEFINED                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_ACCURACY_SHIFT                        _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_ACCURACY_FIELD                        _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_ACCURACY_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_ACCURACY_RANGE                        31:28
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_ACCURACY_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_ACCURACY_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_ACCURACY_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_ACCURACY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_ACCURACY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_ACCURACY_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_ACCURACY_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_ACCURACY_LVL1                 _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_ACCURACY_LVL2                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_ACCURACY_LVL3                 _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0_ACCURACY_OTHER                        _MK_ENUM_CONST(3)

// Register SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0                       _MK_ADDR_CONST(0xcd)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_SECURE                        0x0
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_DUAL                  0x0
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_SCR                   0
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_WORD_COUNT                    0x1
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_MAX_LENGTH_SHIFT                      _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_MAX_LENGTH_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_MAX_LENGTH_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_MAX_LENGTH_RANGE                      0:0
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_MAX_LENGTH_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_MAX_LENGTH_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_MAX_LENGTH_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_MAX_LENGTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_MAX_LENGTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_MAX_LENGTH_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_MAX_LENGTH_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_LENGTH_SHIFT                  _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_LENGTH_FIELD                  _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_LENGTH_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_LENGTH_RANGE                  3:1
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_LENGTH_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_LENGTH_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_LENGTH_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_LENGTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_LENGTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_LENGTH_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_LENGTH_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_LENGTH_MAX20_UNDEF                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_LENGTH_MAX20_16BITS                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_LENGTH_MAX20_18BITS                   _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_LENGTH_MAX20_19BITS                   _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_LENGTH_MAX20_20BITS                   _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_LENGTH_MAX20_17BITS                   _MK_ENUM_CONST(6)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_LENGTH_MAX24_UNDEF                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_LENGTH_MAX24_20BITS                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_LENGTH_MAX24_22BITS                   _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_LENGTH_MAX24_23BITS                   _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_LENGTH_MAX24_24BITS                   _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_LENGTH_MAX24_21BITS                   _MK_ENUM_CONST(6)

#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_ORIGINAL_SHIFT                        _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_ORIGINAL_FIELD                        _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_ORIGINAL_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_ORIGINAL_RANGE                        7:4
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_ORIGINAL_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_ORIGINAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_ORIGINAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_ORIGINAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_ORIGINAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_ORIGINAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_ORIGINAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0_ORIGINAL_UNDEFINED                    _MK_ENUM_CONST(0)

// Reserved address 0xce

// Register SOR_NV_PDISP_HDCPRIF_ROM_CTRL_0
#define SOR_NV_PDISP_HDCPRIF_ROM_CTRL_0                 _MK_ADDR_CONST(0xcf)
#define SOR_NV_PDISP_HDCPRIF_ROM_CTRL_0_SECURE                  0x0
#define SOR_NV_PDISP_HDCPRIF_ROM_CTRL_0_DUAL                    0x0
#define SOR_NV_PDISP_HDCPRIF_ROM_CTRL_0_SCR                     0
#define SOR_NV_PDISP_HDCPRIF_ROM_CTRL_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_HDCPRIF_ROM_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0x3ff)
#define SOR_NV_PDISP_HDCPRIF_ROM_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_HDCPRIF_ROM_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDCPRIF_ROM_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDCPRIF_ROM_CTRL_0_READ_MASK                       _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_HDCPRIF_ROM_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_HDCPRIF_ROM_CTRL_0_ACK_ATTEMPTS_SHIFT                      _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HDCPRIF_ROM_CTRL_0_ACK_ATTEMPTS_FIELD                      _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_HDCPRIF_ROM_CTRL_0_ACK_ATTEMPTS_SHIFT)
#define SOR_NV_PDISP_HDCPRIF_ROM_CTRL_0_ACK_ATTEMPTS_RANGE                      15:0
#define SOR_NV_PDISP_HDCPRIF_ROM_CTRL_0_ACK_ATTEMPTS_WOFFSET                    0x0
#define SOR_NV_PDISP_HDCPRIF_ROM_CTRL_0_ACK_ATTEMPTS_DEFAULT                    _MK_MASK_CONST(0x3ff)
#define SOR_NV_PDISP_HDCPRIF_ROM_CTRL_0_ACK_ATTEMPTS_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_HDCPRIF_ROM_CTRL_0_ACK_ATTEMPTS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDCPRIF_ROM_CTRL_0_ACK_ATTEMPTS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDCPRIF_ROM_CTRL_0_ACK_ATTEMPTS_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HDCPRIF_ROM_CTRL_0_ACK_ATTEMPTS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Reserved address 0xd0

// Reserved address 0xd1

// Reserved address 0xd2

// Reserved address 0xd3

// Reserved address 0xd4

// Reserved address 0xd5

// Reserved address 0xd6

// Reserved address 0xd7

// Reserved address 0xd8

// Reserved address 0xd9

// Reserved address 0xda

// Reserved address 0xdb

// Reserved address 0xdc

// Reserved address 0xdd

// Reserved address 0xde

// Reserved address 0xdf

// Reserved address 0xe0

// Reserved address 0xe1

// Reserved address 0xe2

// Reserved address 0xe3

// Reserved address 0xe4

// Register SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0                       _MK_ADDR_CONST(0xe5)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_SECURE                        0x0
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_DUAL                  0x0
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_SCR                   0
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_WORD_COUNT                    0x1
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_RESET_VAL                     _MK_MASK_CONST(0xf080e13)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_RESET_MASK                    _MK_MASK_CONST(0xfffffff)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_READ_MASK                     _MK_MASK_CONST(0xfffffff)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_WRITE_MASK                    _MK_MASK_CONST(0xfffffff)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_PRESCALE_SHIFT                        _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_PRESCALE_FIELD                        _MK_FIELD_CONST(0xf, SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_PRESCALE_SHIFT)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_PRESCALE_RANGE                        27:24
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_PRESCALE_WOFFSET                      0x0
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_PRESCALE_DEFAULT                      _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_PRESCALE_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_PRESCALE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_PRESCALE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_PRESCALE_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_PRESCALE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_START_DLY_SHIFT                       _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_START_DLY_FIELD                       _MK_FIELD_CONST(0xff, SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_START_DLY_SHIFT)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_START_DLY_RANGE                       23:16
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_START_DLY_WOFFSET                     0x0
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_START_DLY_DEFAULT                     _MK_MASK_CONST(0x8)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_START_DLY_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_START_DLY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_START_DLY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_START_DLY_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_START_DLY_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_DATA_DLY_SHIFT                        _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_DATA_DLY_FIELD                        _MK_FIELD_CONST(0xff, SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_DATA_DLY_SHIFT)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_DATA_DLY_RANGE                        15:8
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_DATA_DLY_WOFFSET                      0x0
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_DATA_DLY_DEFAULT                      _MK_MASK_CONST(0xe)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_DATA_DLY_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_DATA_DLY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_DATA_DLY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_DATA_DLY_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_DATA_DLY_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_BIT_PERIOD_SHIFT                      _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_BIT_PERIOD_FIELD                      _MK_FIELD_CONST(0xff, SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_BIT_PERIOD_SHIFT)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_BIT_PERIOD_RANGE                      7:0
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_BIT_PERIOD_WOFFSET                    0x0
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_BIT_PERIOD_DEFAULT                    _MK_MASK_CONST(0x13)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_BIT_PERIOD_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_BIT_PERIOD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_BIT_PERIOD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_BIT_PERIOD_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0_BIT_PERIOD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_REFCLK_0
#define SOR_NV_PDISP_SOR_REFCLK_0                       _MK_ADDR_CONST(0xe6)
#define SOR_NV_PDISP_SOR_REFCLK_0_SECURE                        0x0
#define SOR_NV_PDISP_SOR_REFCLK_0_DUAL                  0x0
#define SOR_NV_PDISP_SOR_REFCLK_0_SCR                   0
#define SOR_NV_PDISP_SOR_REFCLK_0_WORD_COUNT                    0x1
#define SOR_NV_PDISP_SOR_REFCLK_0_RESET_VAL                     _MK_MASK_CONST(0x1900)
#define SOR_NV_PDISP_SOR_REFCLK_0_RESET_MASK                    _MK_MASK_CONST(0xffc0)
#define SOR_NV_PDISP_SOR_REFCLK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_REFCLK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_REFCLK_0_READ_MASK                     _MK_MASK_CONST(0xffc0)
#define SOR_NV_PDISP_SOR_REFCLK_0_WRITE_MASK                    _MK_MASK_CONST(0xffc0)
#define SOR_NV_PDISP_SOR_REFCLK_0_DIV_INT_SHIFT                 _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_REFCLK_0_DIV_INT_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_REFCLK_0_DIV_INT_SHIFT)
#define SOR_NV_PDISP_SOR_REFCLK_0_DIV_INT_RANGE                 15:8
#define SOR_NV_PDISP_SOR_REFCLK_0_DIV_INT_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_REFCLK_0_DIV_INT_DEFAULT                       _MK_MASK_CONST(0x19)
#define SOR_NV_PDISP_SOR_REFCLK_0_DIV_INT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_REFCLK_0_DIV_INT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_REFCLK_0_DIV_INT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_REFCLK_0_DIV_INT_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_REFCLK_0_DIV_INT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_REFCLK_0_DIV_FRAC_SHIFT                        _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_SOR_REFCLK_0_DIV_FRAC_FIELD                        _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_REFCLK_0_DIV_FRAC_SHIFT)
#define SOR_NV_PDISP_SOR_REFCLK_0_DIV_FRAC_RANGE                        7:6
#define SOR_NV_PDISP_SOR_REFCLK_0_DIV_FRAC_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_REFCLK_0_DIV_FRAC_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_REFCLK_0_DIV_FRAC_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_REFCLK_0_DIV_FRAC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_REFCLK_0_DIV_FRAC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_REFCLK_0_DIV_FRAC_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_REFCLK_0_DIV_FRAC_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_CRC_CONTROL_0
#define SOR_NV_PDISP_CRC_CONTROL_0                      _MK_ADDR_CONST(0xe7)
#define SOR_NV_PDISP_CRC_CONTROL_0_SECURE                       0x0
#define SOR_NV_PDISP_CRC_CONTROL_0_DUAL                         0x0
#define SOR_NV_PDISP_CRC_CONTROL_0_SCR                  0
#define SOR_NV_PDISP_CRC_CONTROL_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_CRC_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_CRC_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_CRC_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_CRC_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_CRC_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_CRC_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_CRC_CONTROL_0_ARM_CRC_ENABLE_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_CRC_CONTROL_0_ARM_CRC_ENABLE_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_CRC_CONTROL_0_ARM_CRC_ENABLE_SHIFT)
#define SOR_NV_PDISP_CRC_CONTROL_0_ARM_CRC_ENABLE_RANGE                 0:0
#define SOR_NV_PDISP_CRC_CONTROL_0_ARM_CRC_ENABLE_WOFFSET                       0x0
#define SOR_NV_PDISP_CRC_CONTROL_0_ARM_CRC_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_CRC_CONTROL_0_ARM_CRC_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_CRC_CONTROL_0_ARM_CRC_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_CRC_CONTROL_0_ARM_CRC_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_CRC_CONTROL_0_ARM_CRC_ENABLE_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_CRC_CONTROL_0_ARM_CRC_ENABLE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_CRC_CONTROL_0_ARM_CRC_ENABLE_INIT_ENUM                     NO
#define SOR_NV_PDISP_CRC_CONTROL_0_ARM_CRC_ENABLE_NO                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_CRC_CONTROL_0_ARM_CRC_ENABLE_YES                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_CRC_CONTROL_0_ARM_CRC_ENABLE_DIS                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_CRC_CONTROL_0_ARM_CRC_ENABLE_EN                    _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_INPUT_CONTROL_0
#define SOR_NV_PDISP_INPUT_CONTROL_0                    _MK_ADDR_CONST(0xe8)
#define SOR_NV_PDISP_INPUT_CONTROL_0_SECURE                     0x0
#define SOR_NV_PDISP_INPUT_CONTROL_0_DUAL                       0x0
#define SOR_NV_PDISP_INPUT_CONTROL_0_SCR                        0
#define SOR_NV_PDISP_INPUT_CONTROL_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_INPUT_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INPUT_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_INPUT_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INPUT_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INPUT_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_INPUT_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_INPUT_CONTROL_0_HDMI_SRC_SELECT_SHIFT                      _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_INPUT_CONTROL_0_HDMI_SRC_SELECT_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INPUT_CONTROL_0_HDMI_SRC_SELECT_SHIFT)
#define SOR_NV_PDISP_INPUT_CONTROL_0_HDMI_SRC_SELECT_RANGE                      0:0
#define SOR_NV_PDISP_INPUT_CONTROL_0_HDMI_SRC_SELECT_WOFFSET                    0x0
#define SOR_NV_PDISP_INPUT_CONTROL_0_HDMI_SRC_SELECT_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INPUT_CONTROL_0_HDMI_SRC_SELECT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INPUT_CONTROL_0_HDMI_SRC_SELECT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INPUT_CONTROL_0_HDMI_SRC_SELECT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INPUT_CONTROL_0_HDMI_SRC_SELECT_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INPUT_CONTROL_0_HDMI_SRC_SELECT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INPUT_CONTROL_0_HDMI_SRC_SELECT_INIT_ENUM                  DISPLAY
#define SOR_NV_PDISP_INPUT_CONTROL_0_HDMI_SRC_SELECT_DISPLAY                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INPUT_CONTROL_0_HDMI_SRC_SELECT_DISPLAYB                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INPUT_CONTROL_0_ARM_VIDEO_RANGE_SHIFT                      _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_INPUT_CONTROL_0_ARM_VIDEO_RANGE_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INPUT_CONTROL_0_ARM_VIDEO_RANGE_SHIFT)
#define SOR_NV_PDISP_INPUT_CONTROL_0_ARM_VIDEO_RANGE_RANGE                      1:1
#define SOR_NV_PDISP_INPUT_CONTROL_0_ARM_VIDEO_RANGE_WOFFSET                    0x0
#define SOR_NV_PDISP_INPUT_CONTROL_0_ARM_VIDEO_RANGE_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INPUT_CONTROL_0_ARM_VIDEO_RANGE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INPUT_CONTROL_0_ARM_VIDEO_RANGE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INPUT_CONTROL_0_ARM_VIDEO_RANGE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INPUT_CONTROL_0_ARM_VIDEO_RANGE_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INPUT_CONTROL_0_ARM_VIDEO_RANGE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INPUT_CONTROL_0_ARM_VIDEO_RANGE_INIT_ENUM                  FULL
#define SOR_NV_PDISP_INPUT_CONTROL_0_ARM_VIDEO_RANGE_FULL                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INPUT_CONTROL_0_ARM_VIDEO_RANGE_LIMITED                    _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SCRATCH_0
#define SOR_NV_PDISP_SCRATCH_0                  _MK_ADDR_CONST(0xe9)
#define SOR_NV_PDISP_SCRATCH_0_SECURE                   0x0
#define SOR_NV_PDISP_SCRATCH_0_DUAL                     0x0
#define SOR_NV_PDISP_SCRATCH_0_SCR                      0
#define SOR_NV_PDISP_SCRATCH_0_WORD_COUNT                       0x1
#define SOR_NV_PDISP_SCRATCH_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SCRATCH_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SCRATCH_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SCRATCH_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SCRATCH_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SCRATCH_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SCRATCH_0_DATA_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SCRATCH_0_DATA_FIELD                       _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SCRATCH_0_DATA_SHIFT)
#define SOR_NV_PDISP_SCRATCH_0_DATA_RANGE                       31:0
#define SOR_NV_PDISP_SCRATCH_0_DATA_WOFFSET                     0x0
#define SOR_NV_PDISP_SCRATCH_0_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SCRATCH_0_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SCRATCH_0_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SCRATCH_0_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SCRATCH_0_DATA_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_KEY_CTRL_0
#define SOR_NV_PDISP_KEY_CTRL_0                 _MK_ADDR_CONST(0xea)
#define SOR_NV_PDISP_KEY_CTRL_0_SECURE                  0x0
#define SOR_NV_PDISP_KEY_CTRL_0_DUAL                    0x0
#define SOR_NV_PDISP_KEY_CTRL_0_SCR                     0
#define SOR_NV_PDISP_KEY_CTRL_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_KEY_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0x3ff033)
#define SOR_NV_PDISP_KEY_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_READ_MASK                       _MK_MASK_CONST(0xfffff073)
#define SOR_NV_PDISP_KEY_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0x3ff033)
#define SOR_NV_PDISP_KEY_CTRL_0_LOCAL_KEYS_SHIFT                        _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_KEY_CTRL_0_LOCAL_KEYS_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_KEY_CTRL_0_LOCAL_KEYS_SHIFT)
#define SOR_NV_PDISP_KEY_CTRL_0_LOCAL_KEYS_RANGE                        0:0
#define SOR_NV_PDISP_KEY_CTRL_0_LOCAL_KEYS_WOFFSET                      0x0
#define SOR_NV_PDISP_KEY_CTRL_0_LOCAL_KEYS_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_LOCAL_KEYS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_CTRL_0_LOCAL_KEYS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_LOCAL_KEYS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_LOCAL_KEYS_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_CTRL_0_LOCAL_KEYS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_CTRL_0_LOCAL_KEYS_INIT_ENUM                    DISABLED
#define SOR_NV_PDISP_KEY_CTRL_0_LOCAL_KEYS_DISABLED                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_KEY_CTRL_0_LOCAL_KEYS_ENABLED                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_KEY_CTRL_0_AUTOINC_SHIFT                   _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_KEY_CTRL_0_AUTOINC_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_KEY_CTRL_0_AUTOINC_SHIFT)
#define SOR_NV_PDISP_KEY_CTRL_0_AUTOINC_RANGE                   1:1
#define SOR_NV_PDISP_KEY_CTRL_0_AUTOINC_WOFFSET                 0x0
#define SOR_NV_PDISP_KEY_CTRL_0_AUTOINC_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_AUTOINC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_CTRL_0_AUTOINC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_AUTOINC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_AUTOINC_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_CTRL_0_AUTOINC_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_CTRL_0_AUTOINC_INIT_ENUM                       DISABLED
#define SOR_NV_PDISP_KEY_CTRL_0_AUTOINC_DISABLED                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_KEY_CTRL_0_AUTOINC_ENABLED                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_KEY_CTRL_0_WRITE16_SHIFT                   _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_KEY_CTRL_0_WRITE16_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_KEY_CTRL_0_WRITE16_SHIFT)
#define SOR_NV_PDISP_KEY_CTRL_0_WRITE16_RANGE                   4:4
#define SOR_NV_PDISP_KEY_CTRL_0_WRITE16_WOFFSET                 0x0
#define SOR_NV_PDISP_KEY_CTRL_0_WRITE16_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_WRITE16_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_CTRL_0_WRITE16_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_WRITE16_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_WRITE16_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_CTRL_0_WRITE16_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_CTRL_0_WRITE16_INIT_ENUM                       DONE
#define SOR_NV_PDISP_KEY_CTRL_0_WRITE16_DONE                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_KEY_CTRL_0_WRITE16_TRIGGER                 _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_KEY_CTRL_0_WRITE16_PENDING                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_KEY_CTRL_0_PKEY_REQUEST_RELOAD_SHIFT                       _MK_SHIFT_CONST(5)
#define SOR_NV_PDISP_KEY_CTRL_0_PKEY_REQUEST_RELOAD_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_KEY_CTRL_0_PKEY_REQUEST_RELOAD_SHIFT)
#define SOR_NV_PDISP_KEY_CTRL_0_PKEY_REQUEST_RELOAD_RANGE                       5:5
#define SOR_NV_PDISP_KEY_CTRL_0_PKEY_REQUEST_RELOAD_WOFFSET                     0x0
#define SOR_NV_PDISP_KEY_CTRL_0_PKEY_REQUEST_RELOAD_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_PKEY_REQUEST_RELOAD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_CTRL_0_PKEY_REQUEST_RELOAD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_PKEY_REQUEST_RELOAD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_PKEY_REQUEST_RELOAD_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_CTRL_0_PKEY_REQUEST_RELOAD_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_CTRL_0_PKEY_REQUEST_RELOAD_INIT_ENUM                   IDLE
#define SOR_NV_PDISP_KEY_CTRL_0_PKEY_REQUEST_RELOAD_IDLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_KEY_CTRL_0_PKEY_REQUEST_RELOAD_TRIGGER                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_KEY_CTRL_0_PKEY_LOADED_SHIFT                       _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_KEY_CTRL_0_PKEY_LOADED_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_KEY_CTRL_0_PKEY_LOADED_SHIFT)
#define SOR_NV_PDISP_KEY_CTRL_0_PKEY_LOADED_RANGE                       6:6
#define SOR_NV_PDISP_KEY_CTRL_0_PKEY_LOADED_WOFFSET                     0x0
#define SOR_NV_PDISP_KEY_CTRL_0_PKEY_LOADED_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_PKEY_LOADED_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_PKEY_LOADED_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_PKEY_LOADED_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_PKEY_LOADED_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_PKEY_LOADED_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_CTRL_0_PKEY_LOADED_FALSE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_KEY_CTRL_0_PKEY_LOADED_TRUE                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_KEY_CTRL_0_LOAD_ADDRESS_SHIFT                      _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_KEY_CTRL_0_LOAD_ADDRESS_FIELD                      _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_KEY_CTRL_0_LOAD_ADDRESS_SHIFT)
#define SOR_NV_PDISP_KEY_CTRL_0_LOAD_ADDRESS_RANGE                      21:12
#define SOR_NV_PDISP_KEY_CTRL_0_LOAD_ADDRESS_WOFFSET                    0x0
#define SOR_NV_PDISP_KEY_CTRL_0_LOAD_ADDRESS_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_LOAD_ADDRESS_DEFAULT_MASK                       _MK_MASK_CONST(0x3ff)
#define SOR_NV_PDISP_KEY_CTRL_0_LOAD_ADDRESS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_LOAD_ADDRESS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_LOAD_ADDRESS_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_CTRL_0_LOAD_ADDRESS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_KEY_CTRL_0_ADDRESS_SHIFT                   _MK_SHIFT_CONST(22)
#define SOR_NV_PDISP_KEY_CTRL_0_ADDRESS_FIELD                   _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_KEY_CTRL_0_ADDRESS_SHIFT)
#define SOR_NV_PDISP_KEY_CTRL_0_ADDRESS_RANGE                   31:22
#define SOR_NV_PDISP_KEY_CTRL_0_ADDRESS_WOFFSET                 0x0
#define SOR_NV_PDISP_KEY_CTRL_0_ADDRESS_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_ADDRESS_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_ADDRESS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_ADDRESS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_ADDRESS_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_CTRL_0_ADDRESS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_KEY_DEBUG0_0
#define SOR_NV_PDISP_KEY_DEBUG0_0                       _MK_ADDR_CONST(0xeb)
#define SOR_NV_PDISP_KEY_DEBUG0_0_SECURE                        0x0
#define SOR_NV_PDISP_KEY_DEBUG0_0_DUAL                  0x0
#define SOR_NV_PDISP_KEY_DEBUG0_0_SCR                   0
#define SOR_NV_PDISP_KEY_DEBUG0_0_WORD_COUNT                    0x1
#define SOR_NV_PDISP_KEY_DEBUG0_0_RESET_VAL                     _MK_MASK_CONST(0x60)
#define SOR_NV_PDISP_KEY_DEBUG0_0_RESET_MASK                    _MK_MASK_CONST(0x71)
#define SOR_NV_PDISP_KEY_DEBUG0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG0_0_READ_MASK                     _MK_MASK_CONST(0x71)
#define SOR_NV_PDISP_KEY_DEBUG0_0_WRITE_MASK                    _MK_MASK_CONST(0x11)
#define SOR_NV_PDISP_KEY_DEBUG0_0_SRAMCLEAR_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_KEY_DEBUG0_0_SRAMCLEAR_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_KEY_DEBUG0_0_SRAMCLEAR_SHIFT)
#define SOR_NV_PDISP_KEY_DEBUG0_0_SRAMCLEAR_RANGE                       0:0
#define SOR_NV_PDISP_KEY_DEBUG0_0_SRAMCLEAR_WOFFSET                     0x0
#define SOR_NV_PDISP_KEY_DEBUG0_0_SRAMCLEAR_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG0_0_SRAMCLEAR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_DEBUG0_0_SRAMCLEAR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG0_0_SRAMCLEAR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG0_0_SRAMCLEAR_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_DEBUG0_0_SRAMCLEAR_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_DEBUG0_0_SRAMCLEAR_INIT_ENUM                   DONE
#define SOR_NV_PDISP_KEY_DEBUG0_0_SRAMCLEAR_DONE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_KEY_DEBUG0_0_SRAMCLEAR_TRIGGER                     _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_KEY_DEBUG0_0_SRAMCLEAR_PENDING                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUM_SHIFT                        _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUM_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUM_SHIFT)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUM_RANGE                        4:4
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUM_WOFFSET                      0x0
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUM_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUM_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUM_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUM_INIT_ENUM                    DONE
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUM_DONE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUM_TRIGGER                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUM_PENDING                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_LOW_SHIFT                 _MK_SHIFT_CONST(5)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_LOW_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_LOW_SHIFT)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_LOW_RANGE                 5:5
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_LOW_WOFFSET                       0x0
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_LOW_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_LOW_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_LOW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_LOW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_LOW_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_LOW_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_LOW_INIT_ENUM                     MATCH
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_LOW_MISMATCH                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_LOW_MATCH                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_HIGH_SHIFT                        _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_HIGH_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_HIGH_SHIFT)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_HIGH_RANGE                        6:6
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_HIGH_WOFFSET                      0x0
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_HIGH_DEFAULT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_HIGH_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_HIGH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_HIGH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_HIGH_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_HIGH_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_HIGH_INIT_ENUM                    MATCH
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_HIGH_MISMATCH                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_KEY_DEBUG0_0_CHECKSUMCMP_HIGH_MATCH                        _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_KEY_DEBUG1_0
#define SOR_NV_PDISP_KEY_DEBUG1_0                       _MK_ADDR_CONST(0xec)
#define SOR_NV_PDISP_KEY_DEBUG1_0_SECURE                        0x0
#define SOR_NV_PDISP_KEY_DEBUG1_0_DUAL                  0x0
#define SOR_NV_PDISP_KEY_DEBUG1_0_SCR                   0
#define SOR_NV_PDISP_KEY_DEBUG1_0_WORD_COUNT                    0x1
#define SOR_NV_PDISP_KEY_DEBUG1_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG1_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_KEY_DEBUG1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG1_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_KEY_DEBUG1_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_KEY_DEBUG1_0_CHECKSUMVAL_LOW_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_KEY_DEBUG1_0_CHECKSUMVAL_LOW_FIELD                 _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_KEY_DEBUG1_0_CHECKSUMVAL_LOW_SHIFT)
#define SOR_NV_PDISP_KEY_DEBUG1_0_CHECKSUMVAL_LOW_RANGE                 15:0
#define SOR_NV_PDISP_KEY_DEBUG1_0_CHECKSUMVAL_LOW_WOFFSET                       0x0
#define SOR_NV_PDISP_KEY_DEBUG1_0_CHECKSUMVAL_LOW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG1_0_CHECKSUMVAL_LOW_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_KEY_DEBUG1_0_CHECKSUMVAL_LOW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG1_0_CHECKSUMVAL_LOW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG1_0_CHECKSUMVAL_LOW_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_DEBUG1_0_CHECKSUMVAL_LOW_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_KEY_DEBUG1_0_CHECKSUMVAL_HIGH_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_KEY_DEBUG1_0_CHECKSUMVAL_HIGH_FIELD                        _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_KEY_DEBUG1_0_CHECKSUMVAL_HIGH_SHIFT)
#define SOR_NV_PDISP_KEY_DEBUG1_0_CHECKSUMVAL_HIGH_RANGE                        31:16
#define SOR_NV_PDISP_KEY_DEBUG1_0_CHECKSUMVAL_HIGH_WOFFSET                      0x0
#define SOR_NV_PDISP_KEY_DEBUG1_0_CHECKSUMVAL_HIGH_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG1_0_CHECKSUMVAL_HIGH_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_KEY_DEBUG1_0_CHECKSUMVAL_HIGH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG1_0_CHECKSUMVAL_HIGH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG1_0_CHECKSUMVAL_HIGH_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_DEBUG1_0_CHECKSUMVAL_HIGH_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_KEY_DEBUG2_0
#define SOR_NV_PDISP_KEY_DEBUG2_0                       _MK_ADDR_CONST(0xed)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SECURE                        0x0
#define SOR_NV_PDISP_KEY_DEBUG2_0_DUAL                  0x0
#define SOR_NV_PDISP_KEY_DEBUG2_0_SCR                   0
#define SOR_NV_PDISP_KEY_DEBUG2_0_WORD_COUNT                    0x1
#define SOR_NV_PDISP_KEY_DEBUG2_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG2_0_RESET_MASK                    _MK_MASK_CONST(0xff3ff012)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG2_0_READ_MASK                     _MK_MASK_CONST(0xff3ff012)
#define SOR_NV_PDISP_KEY_DEBUG2_0_WRITE_MASK                    _MK_MASK_CONST(0xff3ff012)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMAUTOINC_SHIFT                     _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMAUTOINC_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_KEY_DEBUG2_0_SRAMAUTOINC_SHIFT)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMAUTOINC_RANGE                     1:1
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMAUTOINC_WOFFSET                   0x0
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMAUTOINC_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMAUTOINC_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMAUTOINC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMAUTOINC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMAUTOINC_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMAUTOINC_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMAUTOINC_INIT_ENUM                 DISABLED
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMAUTOINC_DISABLED                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMAUTOINC_ENABLED                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMWRITE1_SHIFT                      _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMWRITE1_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_KEY_DEBUG2_0_SRAMWRITE1_SHIFT)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMWRITE1_RANGE                      4:4
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMWRITE1_WOFFSET                    0x0
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMWRITE1_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMWRITE1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMWRITE1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMWRITE1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMWRITE1_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMWRITE1_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMWRITE1_INIT_ENUM                  DONE
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMWRITE1_DONE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMWRITE1_TRIGGER                    _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMWRITE1_PENDING                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMADDR_SHIFT                        _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMADDR_FIELD                        _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_KEY_DEBUG2_0_SRAMADDR_SHIFT)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMADDR_RANGE                        21:12
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMADDR_WOFFSET                      0x0
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMADDR_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMADDR_DEFAULT_MASK                 _MK_MASK_CONST(0x3ff)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMADDR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMADDR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMADDR_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMADDR_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMDATA_SHIFT                        _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMDATA_FIELD                        _MK_FIELD_CONST(0xff, SOR_NV_PDISP_KEY_DEBUG2_0_SRAMDATA_SHIFT)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMDATA_RANGE                        31:24
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMDATA_WOFFSET                      0x0
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMDATA_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMDATA_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMDATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMDATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMDATA_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_DEBUG2_0_SRAMDATA_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_KEY_HDCP_KEY_0_0
#define SOR_NV_PDISP_KEY_HDCP_KEY_0_0                   _MK_ADDR_CONST(0xee)
#define SOR_NV_PDISP_KEY_HDCP_KEY_0_0_SECURE                    0x0
#define SOR_NV_PDISP_KEY_HDCP_KEY_0_0_DUAL                      0x0
#define SOR_NV_PDISP_KEY_HDCP_KEY_0_0_SCR                       0
#define SOR_NV_PDISP_KEY_HDCP_KEY_0_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_KEY_HDCP_KEY_0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_0_0_RESET_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_0_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_KEY_HDCP_KEY_0_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_KEY_HDCP_KEY_0_0_KEY_REG_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_0_0_KEY_REG_FIELD                     _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_KEY_HDCP_KEY_0_0_KEY_REG_SHIFT)
#define SOR_NV_PDISP_KEY_HDCP_KEY_0_0_KEY_REG_RANGE                     31:0
#define SOR_NV_PDISP_KEY_HDCP_KEY_0_0_KEY_REG_WOFFSET                   0x0
#define SOR_NV_PDISP_KEY_HDCP_KEY_0_0_KEY_REG_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_0_0_KEY_REG_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_0_0_KEY_REG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_0_0_KEY_REG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_0_0_KEY_REG_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_0_0_KEY_REG_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_KEY_HDCP_KEY_1_0
#define SOR_NV_PDISP_KEY_HDCP_KEY_1_0                   _MK_ADDR_CONST(0xef)
#define SOR_NV_PDISP_KEY_HDCP_KEY_1_0_SECURE                    0x0
#define SOR_NV_PDISP_KEY_HDCP_KEY_1_0_DUAL                      0x0
#define SOR_NV_PDISP_KEY_HDCP_KEY_1_0_SCR                       0
#define SOR_NV_PDISP_KEY_HDCP_KEY_1_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_KEY_HDCP_KEY_1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_1_0_RESET_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_KEY_HDCP_KEY_1_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_KEY_HDCP_KEY_1_0_KEY_REG_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_1_0_KEY_REG_FIELD                     _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_KEY_HDCP_KEY_1_0_KEY_REG_SHIFT)
#define SOR_NV_PDISP_KEY_HDCP_KEY_1_0_KEY_REG_RANGE                     31:0
#define SOR_NV_PDISP_KEY_HDCP_KEY_1_0_KEY_REG_WOFFSET                   0x0
#define SOR_NV_PDISP_KEY_HDCP_KEY_1_0_KEY_REG_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_1_0_KEY_REG_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_1_0_KEY_REG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_1_0_KEY_REG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_1_0_KEY_REG_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_1_0_KEY_REG_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_KEY_HDCP_KEY_2_0
#define SOR_NV_PDISP_KEY_HDCP_KEY_2_0                   _MK_ADDR_CONST(0xf0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_2_0_SECURE                    0x0
#define SOR_NV_PDISP_KEY_HDCP_KEY_2_0_DUAL                      0x0
#define SOR_NV_PDISP_KEY_HDCP_KEY_2_0_SCR                       0
#define SOR_NV_PDISP_KEY_HDCP_KEY_2_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_KEY_HDCP_KEY_2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_2_0_RESET_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_2_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_KEY_HDCP_KEY_2_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_KEY_HDCP_KEY_2_0_KEY_REG_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_2_0_KEY_REG_FIELD                     _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_KEY_HDCP_KEY_2_0_KEY_REG_SHIFT)
#define SOR_NV_PDISP_KEY_HDCP_KEY_2_0_KEY_REG_RANGE                     31:0
#define SOR_NV_PDISP_KEY_HDCP_KEY_2_0_KEY_REG_WOFFSET                   0x0
#define SOR_NV_PDISP_KEY_HDCP_KEY_2_0_KEY_REG_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_2_0_KEY_REG_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_2_0_KEY_REG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_2_0_KEY_REG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_2_0_KEY_REG_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_2_0_KEY_REG_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_KEY_HDCP_KEY_3_0
#define SOR_NV_PDISP_KEY_HDCP_KEY_3_0                   _MK_ADDR_CONST(0xf1)
#define SOR_NV_PDISP_KEY_HDCP_KEY_3_0_SECURE                    0x0
#define SOR_NV_PDISP_KEY_HDCP_KEY_3_0_DUAL                      0x0
#define SOR_NV_PDISP_KEY_HDCP_KEY_3_0_SCR                       0
#define SOR_NV_PDISP_KEY_HDCP_KEY_3_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_KEY_HDCP_KEY_3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_3_0_RESET_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_3_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_KEY_HDCP_KEY_3_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_KEY_HDCP_KEY_3_0_KEY_REG_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_3_0_KEY_REG_FIELD                     _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_KEY_HDCP_KEY_3_0_KEY_REG_SHIFT)
#define SOR_NV_PDISP_KEY_HDCP_KEY_3_0_KEY_REG_RANGE                     31:0
#define SOR_NV_PDISP_KEY_HDCP_KEY_3_0_KEY_REG_WOFFSET                   0x0
#define SOR_NV_PDISP_KEY_HDCP_KEY_3_0_KEY_REG_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_3_0_KEY_REG_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_3_0_KEY_REG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_3_0_KEY_REG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_3_0_KEY_REG_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_3_0_KEY_REG_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_KEY_HDCP_KEY_TRIG_0
#define SOR_NV_PDISP_KEY_HDCP_KEY_TRIG_0                        _MK_ADDR_CONST(0xf2)
#define SOR_NV_PDISP_KEY_HDCP_KEY_TRIG_0_SECURE                         0x0
#define SOR_NV_PDISP_KEY_HDCP_KEY_TRIG_0_DUAL                   0x0
#define SOR_NV_PDISP_KEY_HDCP_KEY_TRIG_0_SCR                    0
#define SOR_NV_PDISP_KEY_HDCP_KEY_TRIG_0_WORD_COUNT                     0x1
#define SOR_NV_PDISP_KEY_HDCP_KEY_TRIG_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_TRIG_0_RESET_MASK                     _MK_MASK_CONST(0x100)
#define SOR_NV_PDISP_KEY_HDCP_KEY_TRIG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_TRIG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_TRIG_0_READ_MASK                      _MK_MASK_CONST(0x100)
#define SOR_NV_PDISP_KEY_HDCP_KEY_TRIG_0_WRITE_MASK                     _MK_MASK_CONST(0x100)
#define SOR_NV_PDISP_KEY_HDCP_KEY_TRIG_0_LOAD_HDCP_KEY_SHIFT                    _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_KEY_HDCP_KEY_TRIG_0_LOAD_HDCP_KEY_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_KEY_HDCP_KEY_TRIG_0_LOAD_HDCP_KEY_SHIFT)
#define SOR_NV_PDISP_KEY_HDCP_KEY_TRIG_0_LOAD_HDCP_KEY_RANGE                    8:8
#define SOR_NV_PDISP_KEY_HDCP_KEY_TRIG_0_LOAD_HDCP_KEY_WOFFSET                  0x0
#define SOR_NV_PDISP_KEY_HDCP_KEY_TRIG_0_LOAD_HDCP_KEY_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_TRIG_0_LOAD_HDCP_KEY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_HDCP_KEY_TRIG_0_LOAD_HDCP_KEY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_TRIG_0_LOAD_HDCP_KEY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_TRIG_0_LOAD_HDCP_KEY_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_HDCP_KEY_TRIG_0_LOAD_HDCP_KEY_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_HDCP_KEY_TRIG_0_LOAD_HDCP_KEY_INIT_ENUM                        IDLE
#define SOR_NV_PDISP_KEY_HDCP_KEY_TRIG_0_LOAD_HDCP_KEY_IDLE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_KEY_HDCP_KEY_TRIG_0_LOAD_HDCP_KEY_TRIGGER                  _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_KEY_SKEY_INDEX_0
#define SOR_NV_PDISP_KEY_SKEY_INDEX_0                   _MK_ADDR_CONST(0xf3)
#define SOR_NV_PDISP_KEY_SKEY_INDEX_0_SECURE                    0x0
#define SOR_NV_PDISP_KEY_SKEY_INDEX_0_DUAL                      0x0
#define SOR_NV_PDISP_KEY_SKEY_INDEX_0_SCR                       0
#define SOR_NV_PDISP_KEY_SKEY_INDEX_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_KEY_SKEY_INDEX_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_SKEY_INDEX_0_RESET_MASK                        _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_KEY_SKEY_INDEX_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_SKEY_INDEX_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_SKEY_INDEX_0_READ_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_SKEY_INDEX_0_WRITE_MASK                        _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_KEY_SKEY_INDEX_0_IDX_VALUE_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_KEY_SKEY_INDEX_0_IDX_VALUE_FIELD                   _MK_FIELD_CONST(0xf, SOR_NV_PDISP_KEY_SKEY_INDEX_0_IDX_VALUE_SHIFT)
#define SOR_NV_PDISP_KEY_SKEY_INDEX_0_IDX_VALUE_RANGE                   3:0
#define SOR_NV_PDISP_KEY_SKEY_INDEX_0_IDX_VALUE_WOFFSET                 0x0
#define SOR_NV_PDISP_KEY_SKEY_INDEX_0_IDX_VALUE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_SKEY_INDEX_0_IDX_VALUE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_KEY_SKEY_INDEX_0_IDX_VALUE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_SKEY_INDEX_0_IDX_VALUE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_KEY_SKEY_INDEX_0_IDX_VALUE_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_SKEY_INDEX_0_IDX_VALUE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_KEY_SKEY_INDEX_0_IDX_VALUE_TEST                    _MK_ENUM_CONST(15)

// Reserved address 0xf4

// Reserved address 0xf5

// Reserved address 0xf6

// Reserved address 0xf7

// Reserved address 0xf8

// Reserved address 0xf9

// Reserved address 0xfa

// Reserved address 0xfb

// Register SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0                 _MK_ADDR_CONST(0xfc)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SCR                     0
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_RESET_VAL                       _MK_MASK_CONST(0x101000)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_RESET_MASK                      _MK_MASK_CONST(0x20301001)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_READ_MASK                       _MK_MASK_CONST(0xa03f1001)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_WRITE_MASK                      _MK_MASK_CONST(0x20301001)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_PORT_CONNECTIVITY_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_PORT_CONNECTIVITY_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_PORT_CONNECTIVITY_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_PORT_CONNECTIVITY_RANGE                 0:0
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_PORT_CONNECTIVITY_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_PORT_CONNECTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_PORT_CONNECTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_PORT_CONNECTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_PORT_CONNECTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_PORT_CONNECTIVITY_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_PORT_CONNECTIVITY_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_PORT_CONNECTIVITY_INIT_ENUM                     ENABLE
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_PORT_CONNECTIVITY_ENABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_PORT_CONNECTIVITY_DISABLE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_AFIFO_FLUSH_SHIFT                       _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_AFIFO_FLUSH_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_AFIFO_FLUSH_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_AFIFO_FLUSH_RANGE                       12:12
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_AFIFO_FLUSH_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_AFIFO_FLUSH_DEFAULT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_AFIFO_FLUSH_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_AFIFO_FLUSH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_AFIFO_FLUSH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_AFIFO_FLUSH_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_AFIFO_FLUSH_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_AFIFO_FLUSH_INIT_ENUM                   ENABLED
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_AFIFO_FLUSH_DISABLED                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_AFIFO_FLUSH_ENABLED                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SAMPLING_FREQ_SHIFT                     _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SAMPLING_FREQ_FIELD                     _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SAMPLING_FREQ_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SAMPLING_FREQ_RANGE                     19:16
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SAMPLING_FREQ_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SAMPLING_FREQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SAMPLING_FREQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SAMPLING_FREQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SAMPLING_FREQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SAMPLING_FREQ_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SAMPLING_FREQ_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SAMPLING_FREQ_FREQ_32_0KHZ                      _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SAMPLING_FREQ_FREQ_44_1KHZ                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SAMPLING_FREQ_FREQ_88_2KHZ                      _MK_ENUM_CONST(8)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SAMPLING_FREQ_FREQ_176_4KHZ                     _MK_ENUM_CONST(12)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SAMPLING_FREQ_FREQ_48_0KHZ                      _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SAMPLING_FREQ_FREQ_96_0KHZ                      _MK_ENUM_CONST(10)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SAMPLING_FREQ_FREQ_192_0KHZ                     _MK_ENUM_CONST(14)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SAMPLING_FREQ_FREQ_UNKNOWN                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SOURCE_SELECT_SHIFT                     _MK_SHIFT_CONST(20)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SOURCE_SELECT_FIELD                     _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SOURCE_SELECT_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SOURCE_SELECT_RANGE                     21:20
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SOURCE_SELECT_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SOURCE_SELECT_DEFAULT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SOURCE_SELECT_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SOURCE_SELECT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SOURCE_SELECT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SOURCE_SELECT_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SOURCE_SELECT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SOURCE_SELECT_INIT_ENUM                 SPDIF
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SOURCE_SELECT_AUTO                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SOURCE_SELECT_SPDIF                     _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_SOURCE_SELECT_HDAL                      _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_INJECT_NULLSMPL_SHIFT                   _MK_SHIFT_CONST(29)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_INJECT_NULLSMPL_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_INJECT_NULLSMPL_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_INJECT_NULLSMPL_RANGE                   29:29
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_INJECT_NULLSMPL_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_INJECT_NULLSMPL_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_INJECT_NULLSMPL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_INJECT_NULLSMPL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_INJECT_NULLSMPL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_INJECT_NULLSMPL_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_INJECT_NULLSMPL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_INJECT_NULLSMPL_INIT_ENUM                       DISABLE
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_INJECT_NULLSMPL_DISABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_INJECT_NULLSMPL_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_INPUT_MODE_SHIFT                        _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_INPUT_MODE_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_INPUT_MODE_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_INPUT_MODE_RANGE                        31:31
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_INPUT_MODE_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_INPUT_MODE_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_INPUT_MODE_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_INPUT_MODE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_INPUT_MODE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_INPUT_MODE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_INPUT_MODE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_INPUT_MODE_HDA                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0_INPUT_MODE_SPDIF                        _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_AUDIO_DEBUG_0
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0                  _MK_ADDR_CONST(0xfd)
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_SECURE                   0x0
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_DUAL                     0x0
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_SCR                      0
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_WORD_COUNT                       0x1
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_RESET_MASK                       _MK_MASK_CONST(0x9)
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_READ_MASK                        _MK_MASK_CONST(0x9)
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_WRITE_MASK                       _MK_MASK_CONST(0x9)
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_BLANK_COUNT_ERROR_SHIFT                  _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_BLANK_COUNT_ERROR_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_BLANK_COUNT_ERROR_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_BLANK_COUNT_ERROR_RANGE                  3:3
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_BLANK_COUNT_ERROR_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_BLANK_COUNT_ERROR_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_BLANK_COUNT_ERROR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_BLANK_COUNT_ERROR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_BLANK_COUNT_ERROR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_BLANK_COUNT_ERROR_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_BLANK_COUNT_ERROR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_BLANK_COUNT_ERROR_INIT_ENUM                      NO
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_BLANK_COUNT_ERROR_NO                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_BLANK_COUNT_ERROR_YES                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_FIFO_ERROR_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_FIFO_ERROR_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_FIFO_ERROR_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_FIFO_ERROR_RANGE                 0:0
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_FIFO_ERROR_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_FIFO_ERROR_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_FIFO_ERROR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_FIFO_ERROR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_FIFO_ERROR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_FIFO_ERROR_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_FIFO_ERROR_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_FIFO_ERROR_INIT_ENUM                     NO
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_FIFO_ERROR_NO                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_DEBUG_0_FIFO_ERROR_YES                   _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_AUDIO_SPARE0_0
#define SOR_NV_PDISP_SOR_AUDIO_SPARE0_0                 _MK_ADDR_CONST(0xfe)
#define SOR_NV_PDISP_SOR_AUDIO_SPARE0_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_AUDIO_SPARE0_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_AUDIO_SPARE0_0_SCR                     0
#define SOR_NV_PDISP_SOR_AUDIO_SPARE0_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_AUDIO_SPARE0_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_SPARE0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_AUDIO_SPARE0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_SPARE0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_SPARE0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_AUDIO_SPARE0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_AUDIO_SPARE0_0_ECO_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_SPARE0_0_ECO_FIELD                       _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_AUDIO_SPARE0_0_ECO_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_SPARE0_0_ECO_RANGE                       31:0
#define SOR_NV_PDISP_SOR_AUDIO_SPARE0_0_ECO_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_AUDIO_SPARE0_0_ECO_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_SPARE0_0_ECO_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_AUDIO_SPARE0_0_ECO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_SPARE0_0_ECO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_SPARE0_0_ECO_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_SPARE0_0_ECO_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_AUDIO_NVAL_0320_0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0320_0                      _MK_ADDR_CONST(0xff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0320_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0320_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0320_0_SCR                  0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0320_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0320_0_RESET_VAL                    _MK_MASK_CONST(0x1000)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0320_0_RESET_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0320_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0320_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0320_0_READ_MASK                    _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0320_0_WRITE_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0320_0_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0320_0_VALUE_FIELD                  _MK_FIELD_CONST(0xfffff, SOR_NV_PDISP_SOR_AUDIO_NVAL_0320_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0320_0_VALUE_RANGE                  19:0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0320_0_VALUE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0320_0_VALUE_DEFAULT                        _MK_MASK_CONST(0x1000)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0320_0_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0320_0_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0320_0_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0320_0_VALUE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0320_0_VALUE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_AUDIO_NVAL_0441_0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0441_0                      _MK_ADDR_CONST(0x100)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0441_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0441_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0441_0_SCR                  0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0441_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0441_0_RESET_VAL                    _MK_MASK_CONST(0x1880)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0441_0_RESET_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0441_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0441_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0441_0_READ_MASK                    _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0441_0_WRITE_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0441_0_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0441_0_VALUE_FIELD                  _MK_FIELD_CONST(0xfffff, SOR_NV_PDISP_SOR_AUDIO_NVAL_0441_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0441_0_VALUE_RANGE                  19:0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0441_0_VALUE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0441_0_VALUE_DEFAULT                        _MK_MASK_CONST(0x1880)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0441_0_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0441_0_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0441_0_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0441_0_VALUE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0441_0_VALUE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_AUDIO_NVAL_0882_0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0882_0                      _MK_ADDR_CONST(0x101)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0882_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0882_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0882_0_SCR                  0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0882_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0882_0_RESET_VAL                    _MK_MASK_CONST(0x3100)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0882_0_RESET_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0882_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0882_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0882_0_READ_MASK                    _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0882_0_WRITE_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0882_0_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0882_0_VALUE_FIELD                  _MK_FIELD_CONST(0xfffff, SOR_NV_PDISP_SOR_AUDIO_NVAL_0882_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0882_0_VALUE_RANGE                  19:0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0882_0_VALUE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0882_0_VALUE_DEFAULT                        _MK_MASK_CONST(0x3100)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0882_0_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0882_0_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0882_0_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0882_0_VALUE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0882_0_VALUE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_AUDIO_NVAL_1764_0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1764_0                      _MK_ADDR_CONST(0x102)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1764_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1764_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1764_0_SCR                  0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1764_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1764_0_RESET_VAL                    _MK_MASK_CONST(0x6200)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1764_0_RESET_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1764_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1764_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1764_0_READ_MASK                    _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1764_0_WRITE_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1764_0_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1764_0_VALUE_FIELD                  _MK_FIELD_CONST(0xfffff, SOR_NV_PDISP_SOR_AUDIO_NVAL_1764_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1764_0_VALUE_RANGE                  19:0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1764_0_VALUE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1764_0_VALUE_DEFAULT                        _MK_MASK_CONST(0x6200)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1764_0_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1764_0_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1764_0_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1764_0_VALUE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1764_0_VALUE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_AUDIO_NVAL_0480_0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0480_0                      _MK_ADDR_CONST(0x103)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0480_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0480_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0480_0_SCR                  0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0480_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0480_0_RESET_VAL                    _MK_MASK_CONST(0x1800)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0480_0_RESET_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0480_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0480_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0480_0_READ_MASK                    _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0480_0_WRITE_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0480_0_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0480_0_VALUE_FIELD                  _MK_FIELD_CONST(0xfffff, SOR_NV_PDISP_SOR_AUDIO_NVAL_0480_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0480_0_VALUE_RANGE                  19:0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0480_0_VALUE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0480_0_VALUE_DEFAULT                        _MK_MASK_CONST(0x1800)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0480_0_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0480_0_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0480_0_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0480_0_VALUE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0480_0_VALUE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_AUDIO_NVAL_0960_0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0960_0                      _MK_ADDR_CONST(0x104)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0960_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0960_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0960_0_SCR                  0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0960_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0960_0_RESET_VAL                    _MK_MASK_CONST(0x3000)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0960_0_RESET_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0960_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0960_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0960_0_READ_MASK                    _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0960_0_WRITE_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0960_0_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0960_0_VALUE_FIELD                  _MK_FIELD_CONST(0xfffff, SOR_NV_PDISP_SOR_AUDIO_NVAL_0960_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0960_0_VALUE_RANGE                  19:0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0960_0_VALUE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0960_0_VALUE_DEFAULT                        _MK_MASK_CONST(0x3000)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0960_0_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0960_0_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0960_0_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0960_0_VALUE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_0960_0_VALUE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_AUDIO_NVAL_1920_0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1920_0                      _MK_ADDR_CONST(0x105)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1920_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1920_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1920_0_SCR                  0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1920_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1920_0_RESET_VAL                    _MK_MASK_CONST(0x6000)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1920_0_RESET_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1920_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1920_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1920_0_READ_MASK                    _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1920_0_WRITE_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1920_0_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1920_0_VALUE_FIELD                  _MK_FIELD_CONST(0xfffff, SOR_NV_PDISP_SOR_AUDIO_NVAL_1920_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1920_0_VALUE_RANGE                  19:0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1920_0_VALUE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1920_0_VALUE_DEFAULT                        _MK_MASK_CONST(0x6000)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1920_0_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1920_0_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1920_0_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1920_0_VALUE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_NVAL_1920_0_VALUE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_0                   _MK_ADDR_CONST(0x106)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_0_SCR                       0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_0_RESERVED_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_0_RESERVED_FIELD                    _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_0_RESERVED_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_0_RESERVED_RANGE                    31:0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_0_RESERVED_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_0_RESERVED_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_0_RESERVED_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_0_RESERVED_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_0_RESERVED_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_0_RESERVED_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_0_RESERVED_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_0                   _MK_ADDR_CONST(0x107)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_0_SCR                       0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_0_RESERVED_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_0_RESERVED_FIELD                    _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_0_RESERVED_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_0_RESERVED_RANGE                    31:0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_0_RESERVED_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_0_RESERVED_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_0_RESERVED_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_0_RESERVED_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_0_RESERVED_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_0_RESERVED_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_0_RESERVED_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_0                   _MK_ADDR_CONST(0x108)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_0_SCR                       0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_0_RESERVED_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_0_RESERVED_FIELD                    _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_0_RESERVED_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_0_RESERVED_RANGE                    31:0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_0_RESERVED_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_0_RESERVED_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_0_RESERVED_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_0_RESERVED_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_0_RESERVED_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_0_RESERVED_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_0_RESERVED_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_0                   _MK_ADDR_CONST(0x109)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_0_SCR                       0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_0_RESERVED_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_0_RESERVED_FIELD                    _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_0_RESERVED_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_0_RESERVED_RANGE                    31:0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_0_RESERVED_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_0_RESERVED_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_0_RESERVED_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_0_RESERVED_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_0_RESERVED_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_0_RESERVED_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_0_RESERVED_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0_0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0_0                     _MK_ADDR_CONST(0x10a)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0_0_SECURE                      0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0_0_DUAL                        0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0_0_SCR                         0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0_0_WORD_COUNT                  0x1
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0_0_DATA_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0_0_DATA_FIELD                  _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0_0_DATA_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0_0_DATA_RANGE                  31:0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0_0_DATA_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0_0_DATA_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0_0_DATA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0_0_DATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0_0_DATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0_0_DATA_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0_0_DATA_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1_0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1_0                     _MK_ADDR_CONST(0x10b)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1_0_SECURE                      0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1_0_DUAL                        0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1_0_SCR                         0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1_0_WORD_COUNT                  0x1
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1_0_DATA_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1_0_DATA_FIELD                  _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1_0_DATA_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1_0_DATA_RANGE                  31:0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1_0_DATA_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1_0_DATA_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1_0_DATA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1_0_DATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1_0_DATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1_0_DATA_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1_0_DATA_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0                  _MK_ADDR_CONST(0x10c)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_SECURE                   0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_DUAL                     0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_SCR                      0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_WORD_COUNT                       0x1
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_INDEX_SHIFT                      _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_INDEX_FIELD                      _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_INDEX_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_INDEX_RANGE                      15:8
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_INDEX_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_INDEX_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_INDEX_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_INDEX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_INDEX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_INDEX_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_INDEX_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_DATABYTE_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_DATABYTE_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_DATABYTE_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_DATABYTE_RANGE                   7:0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_DATABYTE_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_DATABYTE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_DATABYTE_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_DATABYTE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_DATABYTE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_DATABYTE_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0_DATABYTE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0                   _MK_ADDR_CONST(0x10d)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_SCR                       0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_ELDV_SHIFT                        _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_ELDV_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_ELDV_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_ELDV_RANGE                        1:1
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_ELDV_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_ELDV_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_ELDV_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_ELDV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_ELDV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_ELDV_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_ELDV_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_ELDV_INIT_ENUM                    INVALID
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_ELDV_INVALID                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_ELDV_VALID                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_PD_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_PD_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_PD_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_PD_RANGE                  0:0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_PD_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_PD_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_PD_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_PD_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_PD_INIT_ENUM                      NOT_PRESENT
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_PD_NOT_PRESENT                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0_PD_PRESENT                        _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0                 _MK_ADDR_CONST(0x10e)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_SCR                     0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_RESET_MASK                      _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_READ_MASK                       _MK_MASK_CONST(0x7)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_REQUEST_STATE_VALID_SHIFT                       _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_REQUEST_STATE_VALID_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_REQUEST_STATE_VALID_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_REQUEST_STATE_VALID_RANGE                       2:2
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_REQUEST_STATE_VALID_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_REQUEST_STATE_VALID_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_REQUEST_STATE_VALID_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_REQUEST_STATE_VALID_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_REQUEST_STATE_VALID_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_REQUEST_STATE_VALID_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_REQUEST_STATE_VALID_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_REQUEST_STATE_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_REQUEST_STATE_FIELD                     _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_REQUEST_STATE_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_REQUEST_STATE_RANGE                     1:0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_REQUEST_STATE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_REQUEST_STATE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_REQUEST_STATE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_REQUEST_STATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_REQUEST_STATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_REQUEST_STATE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_REQUEST_STATE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_REQUEST_STATE_INIT_ENUM                 DONT_CARE
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_REQUEST_STATE_DONT_CARE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_REQUEST_STATE_PROTECTION_OFF                    _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0_REQUEST_STATE_PTOTECTION_ON                     _MK_ENUM_CONST(3)

// Register SOR_NV_PDISP_SOR_AUDIO_AVAL_0320_0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0320_0                      _MK_ADDR_CONST(0x10f)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0320_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0320_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0320_0_SCR                  0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0320_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0320_0_RESET_VAL                    _MK_MASK_CONST(0x5dc0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0320_0_RESET_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0320_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0320_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0320_0_READ_MASK                    _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0320_0_WRITE_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0320_0_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0320_0_VALUE_FIELD                  _MK_FIELD_CONST(0xfffff, SOR_NV_PDISP_SOR_AUDIO_AVAL_0320_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0320_0_VALUE_RANGE                  19:0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0320_0_VALUE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0320_0_VALUE_DEFAULT                        _MK_MASK_CONST(0x5dc0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0320_0_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0320_0_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0320_0_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0320_0_VALUE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0320_0_VALUE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_AUDIO_AVAL_0441_0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0441_0                      _MK_ADDR_CONST(0x110)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0441_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0441_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0441_0_SCR                  0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0441_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0441_0_RESET_VAL                    _MK_MASK_CONST(0x4e20)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0441_0_RESET_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0441_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0441_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0441_0_READ_MASK                    _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0441_0_WRITE_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0441_0_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0441_0_VALUE_FIELD                  _MK_FIELD_CONST(0xfffff, SOR_NV_PDISP_SOR_AUDIO_AVAL_0441_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0441_0_VALUE_RANGE                  19:0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0441_0_VALUE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0441_0_VALUE_DEFAULT                        _MK_MASK_CONST(0x4e20)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0441_0_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0441_0_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0441_0_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0441_0_VALUE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0441_0_VALUE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_AUDIO_AVAL_0882_0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0882_0                      _MK_ADDR_CONST(0x111)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0882_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0882_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0882_0_SCR                  0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0882_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0882_0_RESET_VAL                    _MK_MASK_CONST(0x4e20)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0882_0_RESET_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0882_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0882_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0882_0_READ_MASK                    _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0882_0_WRITE_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0882_0_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0882_0_VALUE_FIELD                  _MK_FIELD_CONST(0xfffff, SOR_NV_PDISP_SOR_AUDIO_AVAL_0882_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0882_0_VALUE_RANGE                  19:0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0882_0_VALUE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0882_0_VALUE_DEFAULT                        _MK_MASK_CONST(0x4e20)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0882_0_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0882_0_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0882_0_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0882_0_VALUE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0882_0_VALUE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_AUDIO_AVAL_1764_0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1764_0                      _MK_ADDR_CONST(0x112)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1764_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1764_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1764_0_SCR                  0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1764_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1764_0_RESET_VAL                    _MK_MASK_CONST(0x4e20)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1764_0_RESET_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1764_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1764_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1764_0_READ_MASK                    _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1764_0_WRITE_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1764_0_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1764_0_VALUE_FIELD                  _MK_FIELD_CONST(0xfffff, SOR_NV_PDISP_SOR_AUDIO_AVAL_1764_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1764_0_VALUE_RANGE                  19:0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1764_0_VALUE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1764_0_VALUE_DEFAULT                        _MK_MASK_CONST(0x4e20)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1764_0_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1764_0_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1764_0_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1764_0_VALUE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1764_0_VALUE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_AUDIO_AVAL_0480_0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0480_0                      _MK_ADDR_CONST(0x113)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0480_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0480_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0480_0_SCR                  0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0480_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0480_0_RESET_VAL                    _MK_MASK_CONST(0x5dc0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0480_0_RESET_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0480_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0480_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0480_0_READ_MASK                    _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0480_0_WRITE_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0480_0_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0480_0_VALUE_FIELD                  _MK_FIELD_CONST(0xfffff, SOR_NV_PDISP_SOR_AUDIO_AVAL_0480_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0480_0_VALUE_RANGE                  19:0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0480_0_VALUE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0480_0_VALUE_DEFAULT                        _MK_MASK_CONST(0x5dc0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0480_0_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0480_0_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0480_0_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0480_0_VALUE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0480_0_VALUE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_AUDIO_AVAL_0960_0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0960_0                      _MK_ADDR_CONST(0x114)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0960_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0960_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0960_0_SCR                  0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0960_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0960_0_RESET_VAL                    _MK_MASK_CONST(0x5dc0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0960_0_RESET_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0960_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0960_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0960_0_READ_MASK                    _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0960_0_WRITE_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0960_0_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0960_0_VALUE_FIELD                  _MK_FIELD_CONST(0xfffff, SOR_NV_PDISP_SOR_AUDIO_AVAL_0960_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0960_0_VALUE_RANGE                  19:0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0960_0_VALUE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0960_0_VALUE_DEFAULT                        _MK_MASK_CONST(0x5dc0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0960_0_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0960_0_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0960_0_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0960_0_VALUE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_0960_0_VALUE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_AUDIO_AVAL_1920_0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1920_0                      _MK_ADDR_CONST(0x115)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1920_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1920_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1920_0_SCR                  0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1920_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1920_0_RESET_VAL                    _MK_MASK_CONST(0x5dc0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1920_0_RESET_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1920_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1920_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1920_0_READ_MASK                    _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1920_0_WRITE_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1920_0_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1920_0_VALUE_FIELD                  _MK_FIELD_CONST(0xfffff, SOR_NV_PDISP_SOR_AUDIO_AVAL_1920_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1920_0_VALUE_RANGE                  19:0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1920_0_VALUE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1920_0_VALUE_DEFAULT                        _MK_MASK_CONST(0x5dc0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1920_0_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1920_0_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1920_0_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1920_0_VALUE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_1920_0_VALUE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_0                   _MK_ADDR_CONST(0x116)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_0_SCR                       0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_0_RESET_VAL                         _MK_MASK_CONST(0x5dc0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_0_RESET_MASK                        _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_0_READ_MASK                         _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_0_WRITE_MASK                        _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_0_VALUE_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_0_VALUE_FIELD                       _MK_FIELD_CONST(0xfffff, SOR_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_0_VALUE_RANGE                       19:0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_0_VALUE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_0_VALUE_DEFAULT                     _MK_MASK_CONST(0x5dc0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_0_VALUE_DEFAULT_MASK                        _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_0_VALUE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_0_VALUE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_0_VALUE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_0_VALUE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0                       _MK_ADDR_CONST(0x117)
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_SECURE                        0x0
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_DUAL                  0x0
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_SCR                   0
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_WORD_COUNT                    0x1
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_READ_MASK                     _MK_MASK_CONST(0xffff00ff)
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_WRITE_MASK                    _MK_MASK_CONST(0xffff00ff)
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_DEV_ID_SHIFT                  _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_DEV_ID_FIELD                  _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_DEV_ID_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_DEV_ID_RANGE                  31:16
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_DEV_ID_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_DEV_ID_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_DEV_ID_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_DEV_ID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_DEV_ID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_DEV_ID_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_DEV_ID_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_REV_ID_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_REV_ID_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_REV_ID_SHIFT)
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_REV_ID_RANGE                  7:0
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_REV_ID_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_REV_ID_DEFAULT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_REV_ID_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_REV_ID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_REV_ID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_REV_ID_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0_REV_ID_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Reserved address 0x118

// Reserved address 0x119

// Reserved address 0x11a

// Reserved address 0x11b

// Register SOR_NV_PDISP_INT_STATUS_0
#define SOR_NV_PDISP_INT_STATUS_0                       _MK_ADDR_CONST(0x11c)
#define SOR_NV_PDISP_INT_STATUS_0_SECURE                        0x0
#define SOR_NV_PDISP_INT_STATUS_0_DUAL                  0x0
#define SOR_NV_PDISP_INT_STATUS_0_SCR                   0
#define SOR_NV_PDISP_INT_STATUS_0_WORD_COUNT                    0x1
#define SOR_NV_PDISP_INT_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_READ_MASK                     _MK_MASK_CONST(0xfffffff)
#define SOR_NV_PDISP_INT_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0xfffffff)
#define SOR_NV_PDISP_INT_STATUS_0_CODEC_SCRATCH0_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_INT_STATUS_0_CODEC_SCRATCH0_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_CODEC_SCRATCH0_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_CODEC_SCRATCH0_RANGE                  0:0
#define SOR_NV_PDISP_INT_STATUS_0_CODEC_SCRATCH0_WOFFSET                        0x0
#define SOR_NV_PDISP_INT_STATUS_0_CODEC_SCRATCH0_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_CODEC_SCRATCH0_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_CODEC_SCRATCH0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_CODEC_SCRATCH0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_CODEC_SCRATCH0_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_CODEC_SCRATCH0_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_INT_STATUS_0_CODEC_SCRATCH1_SHIFT                  _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_INT_STATUS_0_CODEC_SCRATCH1_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_CODEC_SCRATCH1_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_CODEC_SCRATCH1_RANGE                  1:1
#define SOR_NV_PDISP_INT_STATUS_0_CODEC_SCRATCH1_WOFFSET                        0x0
#define SOR_NV_PDISP_INT_STATUS_0_CODEC_SCRATCH1_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_CODEC_SCRATCH1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_CODEC_SCRATCH1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_CODEC_SCRATCH1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_CODEC_SCRATCH1_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_CODEC_SCRATCH1_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_INT_STATUS_0_CP_REQUEST_SHIFT                      _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_INT_STATUS_0_CP_REQUEST_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_CP_REQUEST_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_CP_REQUEST_RANGE                      2:2
#define SOR_NV_PDISP_INT_STATUS_0_CP_REQUEST_WOFFSET                    0x0
#define SOR_NV_PDISP_INT_STATUS_0_CP_REQUEST_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_CP_REQUEST_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_CP_REQUEST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_CP_REQUEST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_CP_REQUEST_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_CP_REQUEST_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_INT_STATUS_0_SCRATCH_SHIFT                 _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_INT_STATUS_0_SCRATCH_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_SCRATCH_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_SCRATCH_RANGE                 3:3
#define SOR_NV_PDISP_INT_STATUS_0_SCRATCH_WOFFSET                       0x0
#define SOR_NV_PDISP_INT_STATUS_0_SCRATCH_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_SCRATCH_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_SCRATCH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_SCRATCH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_SCRATCH_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_SCRATCH_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_INT_STATUS_0_REG_SECURE_ACCESS_ERR_SHIFT                   _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_INT_STATUS_0_REG_SECURE_ACCESS_ERR_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_REG_SECURE_ACCESS_ERR_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_REG_SECURE_ACCESS_ERR_RANGE                   4:4
#define SOR_NV_PDISP_INT_STATUS_0_REG_SECURE_ACCESS_ERR_WOFFSET                 0x0
#define SOR_NV_PDISP_INT_STATUS_0_REG_SECURE_ACCESS_ERR_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_REG_SECURE_ACCESS_ERR_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_REG_SECURE_ACCESS_ERR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_REG_SECURE_ACCESS_ERR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_REG_SECURE_ACCESS_ERR_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_REG_SECURE_ACCESS_ERR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_INT_STATUS_0_LANE0_FIFO_UNDERFLOW_SHIFT                    _MK_SHIFT_CONST(5)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_FIFO_UNDERFLOW_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_LANE0_FIFO_UNDERFLOW_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_FIFO_UNDERFLOW_RANGE                    5:5
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_FIFO_UNDERFLOW_WOFFSET                  0x0
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_FIFO_UNDERFLOW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_FIFO_UNDERFLOW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_FIFO_UNDERFLOW_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_FIFO_UNDERFLOW_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_FIFO_UNDERFLOW_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_FIFO_UNDERFLOW_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_INT_STATUS_0_LANE1_FIFO_UNDERFLOW_SHIFT                    _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_FIFO_UNDERFLOW_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_LANE1_FIFO_UNDERFLOW_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_FIFO_UNDERFLOW_RANGE                    6:6
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_FIFO_UNDERFLOW_WOFFSET                  0x0
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_FIFO_UNDERFLOW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_FIFO_UNDERFLOW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_FIFO_UNDERFLOW_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_FIFO_UNDERFLOW_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_FIFO_UNDERFLOW_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_FIFO_UNDERFLOW_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_INT_STATUS_0_LANE2_FIFO_UNDERFLOW_SHIFT                    _MK_SHIFT_CONST(7)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_FIFO_UNDERFLOW_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_LANE2_FIFO_UNDERFLOW_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_FIFO_UNDERFLOW_RANGE                    7:7
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_FIFO_UNDERFLOW_WOFFSET                  0x0
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_FIFO_UNDERFLOW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_FIFO_UNDERFLOW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_FIFO_UNDERFLOW_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_FIFO_UNDERFLOW_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_FIFO_UNDERFLOW_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_FIFO_UNDERFLOW_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_INT_STATUS_0_LANE3_FIFO_UNDERFLOW_SHIFT                    _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_FIFO_UNDERFLOW_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_LANE3_FIFO_UNDERFLOW_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_FIFO_UNDERFLOW_RANGE                    8:8
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_FIFO_UNDERFLOW_WOFFSET                  0x0
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_FIFO_UNDERFLOW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_FIFO_UNDERFLOW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_FIFO_UNDERFLOW_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_FIFO_UNDERFLOW_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_FIFO_UNDERFLOW_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_FIFO_UNDERFLOW_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_INT_STATUS_0_LANE0_PIXPACK_OVERFLOW_SHIFT                  _MK_SHIFT_CONST(9)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_PIXPACK_OVERFLOW_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_LANE0_PIXPACK_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_PIXPACK_OVERFLOW_RANGE                  9:9
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_PIXPACK_OVERFLOW_WOFFSET                        0x0
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_PIXPACK_OVERFLOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_PIXPACK_OVERFLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_PIXPACK_OVERFLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_PIXPACK_OVERFLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_PIXPACK_OVERFLOW_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_PIXPACK_OVERFLOW_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_INT_STATUS_0_LANE1_PIXPACK_OVERFLOW_SHIFT                  _MK_SHIFT_CONST(10)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_PIXPACK_OVERFLOW_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_LANE1_PIXPACK_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_PIXPACK_OVERFLOW_RANGE                  10:10
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_PIXPACK_OVERFLOW_WOFFSET                        0x0
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_PIXPACK_OVERFLOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_PIXPACK_OVERFLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_PIXPACK_OVERFLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_PIXPACK_OVERFLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_PIXPACK_OVERFLOW_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_PIXPACK_OVERFLOW_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_INT_STATUS_0_LANE2_PIXPACK_OVERFLOW_SHIFT                  _MK_SHIFT_CONST(11)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_PIXPACK_OVERFLOW_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_LANE2_PIXPACK_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_PIXPACK_OVERFLOW_RANGE                  11:11
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_PIXPACK_OVERFLOW_WOFFSET                        0x0
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_PIXPACK_OVERFLOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_PIXPACK_OVERFLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_PIXPACK_OVERFLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_PIXPACK_OVERFLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_PIXPACK_OVERFLOW_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_PIXPACK_OVERFLOW_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_INT_STATUS_0_LANE3_PIXPACK_OVERFLOW_SHIFT                  _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_PIXPACK_OVERFLOW_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_LANE3_PIXPACK_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_PIXPACK_OVERFLOW_RANGE                  12:12
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_PIXPACK_OVERFLOW_WOFFSET                        0x0
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_PIXPACK_OVERFLOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_PIXPACK_OVERFLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_PIXPACK_OVERFLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_PIXPACK_OVERFLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_PIXPACK_OVERFLOW_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_PIXPACK_OVERFLOW_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_INT_STATUS_0_LANE0_STEER_ERROR_SHIFT                       _MK_SHIFT_CONST(13)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_STEER_ERROR_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_LANE0_STEER_ERROR_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_STEER_ERROR_RANGE                       13:13
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_STEER_ERROR_WOFFSET                     0x0
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_STEER_ERROR_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_STEER_ERROR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_STEER_ERROR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_STEER_ERROR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_STEER_ERROR_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_STEER_ERROR_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_INT_STATUS_0_LANE1_STEER_ERROR_SHIFT                       _MK_SHIFT_CONST(14)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_STEER_ERROR_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_LANE1_STEER_ERROR_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_STEER_ERROR_RANGE                       14:14
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_STEER_ERROR_WOFFSET                     0x0
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_STEER_ERROR_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_STEER_ERROR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_STEER_ERROR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_STEER_ERROR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_STEER_ERROR_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_STEER_ERROR_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_INT_STATUS_0_LANE2_STEER_ERROR_SHIFT                       _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_STEER_ERROR_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_LANE2_STEER_ERROR_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_STEER_ERROR_RANGE                       15:15
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_STEER_ERROR_WOFFSET                     0x0
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_STEER_ERROR_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_STEER_ERROR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_STEER_ERROR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_STEER_ERROR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_STEER_ERROR_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_STEER_ERROR_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_INT_STATUS_0_LANE3_STEER_ERROR_SHIFT                       _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_STEER_ERROR_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_LANE3_STEER_ERROR_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_STEER_ERROR_RANGE                       16:16
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_STEER_ERROR_WOFFSET                     0x0
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_STEER_ERROR_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_STEER_ERROR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_STEER_ERROR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_STEER_ERROR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_STEER_ERROR_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_STEER_ERROR_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_INT_STATUS_0_SPKT_OVERRUN_SHIFT                    _MK_SHIFT_CONST(17)
#define SOR_NV_PDISP_INT_STATUS_0_SPKT_OVERRUN_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_SPKT_OVERRUN_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_SPKT_OVERRUN_RANGE                    17:17
#define SOR_NV_PDISP_INT_STATUS_0_SPKT_OVERRUN_WOFFSET                  0x0
#define SOR_NV_PDISP_INT_STATUS_0_SPKT_OVERRUN_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_SPKT_OVERRUN_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_SPKT_OVERRUN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_SPKT_OVERRUN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_SPKT_OVERRUN_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_SPKT_OVERRUN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_INT_STATUS_0_LANE0_FIFO_OVERFLOW_SHIFT                     _MK_SHIFT_CONST(18)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_FIFO_OVERFLOW_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_LANE0_FIFO_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_FIFO_OVERFLOW_RANGE                     18:18
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_FIFO_OVERFLOW_WOFFSET                   0x0
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_FIFO_OVERFLOW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_FIFO_OVERFLOW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_FIFO_OVERFLOW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_FIFO_OVERFLOW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_FIFO_OVERFLOW_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_LANE0_FIFO_OVERFLOW_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_INT_STATUS_0_LANE1_FIFO_OVERFLOW_SHIFT                     _MK_SHIFT_CONST(19)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_FIFO_OVERFLOW_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_LANE1_FIFO_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_FIFO_OVERFLOW_RANGE                     19:19
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_FIFO_OVERFLOW_WOFFSET                   0x0
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_FIFO_OVERFLOW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_FIFO_OVERFLOW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_FIFO_OVERFLOW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_FIFO_OVERFLOW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_FIFO_OVERFLOW_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_LANE1_FIFO_OVERFLOW_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_INT_STATUS_0_LANE2_FIFO_OVERFLOW_SHIFT                     _MK_SHIFT_CONST(20)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_FIFO_OVERFLOW_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_LANE2_FIFO_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_FIFO_OVERFLOW_RANGE                     20:20
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_FIFO_OVERFLOW_WOFFSET                   0x0
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_FIFO_OVERFLOW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_FIFO_OVERFLOW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_FIFO_OVERFLOW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_FIFO_OVERFLOW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_FIFO_OVERFLOW_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_LANE2_FIFO_OVERFLOW_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_INT_STATUS_0_LANE3_FIFO_OVERFLOW_SHIFT                     _MK_SHIFT_CONST(21)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_FIFO_OVERFLOW_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_LANE3_FIFO_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_FIFO_OVERFLOW_RANGE                     21:21
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_FIFO_OVERFLOW_WOFFSET                   0x0
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_FIFO_OVERFLOW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_FIFO_OVERFLOW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_FIFO_OVERFLOW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_FIFO_OVERFLOW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_FIFO_OVERFLOW_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_LANE3_FIFO_OVERFLOW_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_INT_STATUS_0_LB_UNDERFLOW_SHIFT                    _MK_SHIFT_CONST(22)
#define SOR_NV_PDISP_INT_STATUS_0_LB_UNDERFLOW_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_LB_UNDERFLOW_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_LB_UNDERFLOW_RANGE                    22:22
#define SOR_NV_PDISP_INT_STATUS_0_LB_UNDERFLOW_WOFFSET                  0x0
#define SOR_NV_PDISP_INT_STATUS_0_LB_UNDERFLOW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LB_UNDERFLOW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LB_UNDERFLOW_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LB_UNDERFLOW_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LB_UNDERFLOW_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_LB_UNDERFLOW_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_INT_STATUS_0_LB_OVERFLOW_SHIFT                     _MK_SHIFT_CONST(23)
#define SOR_NV_PDISP_INT_STATUS_0_LB_OVERFLOW_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_LB_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_LB_OVERFLOW_RANGE                     23:23
#define SOR_NV_PDISP_INT_STATUS_0_LB_OVERFLOW_WOFFSET                   0x0
#define SOR_NV_PDISP_INT_STATUS_0_LB_OVERFLOW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LB_OVERFLOW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LB_OVERFLOW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LB_OVERFLOW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LB_OVERFLOW_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_LB_OVERFLOW_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_INT_STATUS_0_AFIFO_UNDERFLOW_SHIFT                 _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_INT_STATUS_0_AFIFO_UNDERFLOW_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_AFIFO_UNDERFLOW_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_AFIFO_UNDERFLOW_RANGE                 24:24
#define SOR_NV_PDISP_INT_STATUS_0_AFIFO_UNDERFLOW_WOFFSET                       0x0
#define SOR_NV_PDISP_INT_STATUS_0_AFIFO_UNDERFLOW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_AFIFO_UNDERFLOW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_AFIFO_UNDERFLOW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_AFIFO_UNDERFLOW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_AFIFO_UNDERFLOW_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_AFIFO_UNDERFLOW_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_INT_STATUS_0_AFIFO_OVERFLOW_SHIFT                  _MK_SHIFT_CONST(25)
#define SOR_NV_PDISP_INT_STATUS_0_AFIFO_OVERFLOW_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_AFIFO_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_AFIFO_OVERFLOW_RANGE                  25:25
#define SOR_NV_PDISP_INT_STATUS_0_AFIFO_OVERFLOW_WOFFSET                        0x0
#define SOR_NV_PDISP_INT_STATUS_0_AFIFO_OVERFLOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_AFIFO_OVERFLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_AFIFO_OVERFLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_AFIFO_OVERFLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_AFIFO_OVERFLOW_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_AFIFO_OVERFLOW_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_INT_STATUS_0_LB_AFIFO_UNDERFLOW_SHIFT                      _MK_SHIFT_CONST(26)
#define SOR_NV_PDISP_INT_STATUS_0_LB_AFIFO_UNDERFLOW_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_LB_AFIFO_UNDERFLOW_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_LB_AFIFO_UNDERFLOW_RANGE                      26:26
#define SOR_NV_PDISP_INT_STATUS_0_LB_AFIFO_UNDERFLOW_WOFFSET                    0x0
#define SOR_NV_PDISP_INT_STATUS_0_LB_AFIFO_UNDERFLOW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LB_AFIFO_UNDERFLOW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LB_AFIFO_UNDERFLOW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LB_AFIFO_UNDERFLOW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LB_AFIFO_UNDERFLOW_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_LB_AFIFO_UNDERFLOW_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_INT_STATUS_0_LB_AFIFO_OVERFLOW_SHIFT                       _MK_SHIFT_CONST(27)
#define SOR_NV_PDISP_INT_STATUS_0_LB_AFIFO_OVERFLOW_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_STATUS_0_LB_AFIFO_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_INT_STATUS_0_LB_AFIFO_OVERFLOW_RANGE                       27:27
#define SOR_NV_PDISP_INT_STATUS_0_LB_AFIFO_OVERFLOW_WOFFSET                     0x0
#define SOR_NV_PDISP_INT_STATUS_0_LB_AFIFO_OVERFLOW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LB_AFIFO_OVERFLOW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LB_AFIFO_OVERFLOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LB_AFIFO_OVERFLOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_STATUS_0_LB_AFIFO_OVERFLOW_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_STATUS_0_LB_AFIFO_OVERFLOW_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_INT_MASK_0
#define SOR_NV_PDISP_INT_MASK_0                 _MK_ADDR_CONST(0x11d)
#define SOR_NV_PDISP_INT_MASK_0_SECURE                  0x0
#define SOR_NV_PDISP_INT_MASK_0_DUAL                    0x0
#define SOR_NV_PDISP_INT_MASK_0_SCR                     0
#define SOR_NV_PDISP_INT_MASK_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_INT_MASK_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_RESET_MASK                      _MK_MASK_CONST(0xfffffff)
#define SOR_NV_PDISP_INT_MASK_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_READ_MASK                       _MK_MASK_CONST(0xfffffff)
#define SOR_NV_PDISP_INT_MASK_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffff)
#define SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH0_MASK_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH0_MASK_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH0_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH0_MASK_RANGE                       0:0
#define SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH0_MASK_WOFFSET                     0x0
#define SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH0_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH0_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH0_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH0_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH0_MASK_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH0_MASK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH0_MASK_INIT_ENUM                   MASKED
#define SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH0_MASK_MASKED                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH0_MASK_NOTMASKED                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH1_MASK_SHIFT                       _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH1_MASK_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH1_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH1_MASK_RANGE                       1:1
#define SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH1_MASK_WOFFSET                     0x0
#define SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH1_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH1_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH1_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH1_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH1_MASK_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH1_MASK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH1_MASK_INIT_ENUM                   MASKED
#define SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH1_MASK_MASKED                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_CODEC_SCRATCH1_MASK_NOTMASKED                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_MASK_0_CP_REQUEST_MASK_SHIFT                   _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_INT_MASK_0_CP_REQUEST_MASK_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_CP_REQUEST_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_CP_REQUEST_MASK_RANGE                   2:2
#define SOR_NV_PDISP_INT_MASK_0_CP_REQUEST_MASK_WOFFSET                 0x0
#define SOR_NV_PDISP_INT_MASK_0_CP_REQUEST_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_CP_REQUEST_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_CP_REQUEST_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_CP_REQUEST_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_CP_REQUEST_MASK_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_CP_REQUEST_MASK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_CP_REQUEST_MASK_INIT_ENUM                       MASKED
#define SOR_NV_PDISP_INT_MASK_0_CP_REQUEST_MASK_MASKED                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_CP_REQUEST_MASK_NOTMASKED                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_MASK_0_SCRATCH_MASK_SHIFT                      _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_INT_MASK_0_SCRATCH_MASK_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_SCRATCH_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_SCRATCH_MASK_RANGE                      3:3
#define SOR_NV_PDISP_INT_MASK_0_SCRATCH_MASK_WOFFSET                    0x0
#define SOR_NV_PDISP_INT_MASK_0_SCRATCH_MASK_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_SCRATCH_MASK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_SCRATCH_MASK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_SCRATCH_MASK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_SCRATCH_MASK_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_SCRATCH_MASK_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_SCRATCH_MASK_INIT_ENUM                  MASKED
#define SOR_NV_PDISP_INT_MASK_0_SCRATCH_MASK_MASKED                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_SCRATCH_MASK_NOTMASKED                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_MASK_0_REG_SECURE_ACCESS_ERR_MASK_SHIFT                        _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_INT_MASK_0_REG_SECURE_ACCESS_ERR_MASK_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_REG_SECURE_ACCESS_ERR_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_REG_SECURE_ACCESS_ERR_MASK_RANGE                        4:4
#define SOR_NV_PDISP_INT_MASK_0_REG_SECURE_ACCESS_ERR_MASK_WOFFSET                      0x0
#define SOR_NV_PDISP_INT_MASK_0_REG_SECURE_ACCESS_ERR_MASK_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_REG_SECURE_ACCESS_ERR_MASK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_REG_SECURE_ACCESS_ERR_MASK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_REG_SECURE_ACCESS_ERR_MASK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_REG_SECURE_ACCESS_ERR_MASK_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_REG_SECURE_ACCESS_ERR_MASK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_REG_SECURE_ACCESS_ERR_MASK_INIT_ENUM                    MASKED
#define SOR_NV_PDISP_INT_MASK_0_REG_SECURE_ACCESS_ERR_MASK_MASKED                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_REG_SECURE_ACCESS_ERR_MASK_NOTMASKED                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_SHIFT                 _MK_SHIFT_CONST(5)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_RANGE                 5:5
#define SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_WOFFSET                       0x0
#define SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_INIT_ENUM                     MASKED
#define SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_MASKED                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_NOTMASKED                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_SHIFT                 _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_RANGE                 6:6
#define SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_WOFFSET                       0x0
#define SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_INIT_ENUM                     MASKED
#define SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_MASKED                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_NOTMASKED                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_SHIFT                 _MK_SHIFT_CONST(7)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_RANGE                 7:7
#define SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_WOFFSET                       0x0
#define SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_INIT_ENUM                     MASKED
#define SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_MASKED                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_NOTMASKED                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_SHIFT                 _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_RANGE                 8:8
#define SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_WOFFSET                       0x0
#define SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_INIT_ENUM                     MASKED
#define SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_MASKED                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_NOTMASKED                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_SHIFT                       _MK_SHIFT_CONST(9)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_RANGE                       9:9
#define SOR_NV_PDISP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_WOFFSET                     0x0
#define SOR_NV_PDISP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_INIT_ENUM                   MASKED
#define SOR_NV_PDISP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_MASKED                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_NOTMASKED                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_SHIFT                       _MK_SHIFT_CONST(10)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_RANGE                       10:10
#define SOR_NV_PDISP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_WOFFSET                     0x0
#define SOR_NV_PDISP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_INIT_ENUM                   MASKED
#define SOR_NV_PDISP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_MASKED                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_NOTMASKED                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_SHIFT                       _MK_SHIFT_CONST(11)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_RANGE                       11:11
#define SOR_NV_PDISP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_WOFFSET                     0x0
#define SOR_NV_PDISP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_INIT_ENUM                   MASKED
#define SOR_NV_PDISP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_MASKED                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_NOTMASKED                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_SHIFT                       _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_RANGE                       12:12
#define SOR_NV_PDISP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_WOFFSET                     0x0
#define SOR_NV_PDISP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_INIT_ENUM                   MASKED
#define SOR_NV_PDISP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_MASKED                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_NOTMASKED                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_MASK_0_LANE0_STEER_ERROR_MASK_SHIFT                    _MK_SHIFT_CONST(13)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_STEER_ERROR_MASK_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_LANE0_STEER_ERROR_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_STEER_ERROR_MASK_RANGE                    13:13
#define SOR_NV_PDISP_INT_MASK_0_LANE0_STEER_ERROR_MASK_WOFFSET                  0x0
#define SOR_NV_PDISP_INT_MASK_0_LANE0_STEER_ERROR_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_STEER_ERROR_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_STEER_ERROR_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_STEER_ERROR_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_STEER_ERROR_MASK_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_STEER_ERROR_MASK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_STEER_ERROR_MASK_INIT_ENUM                        MASKED
#define SOR_NV_PDISP_INT_MASK_0_LANE0_STEER_ERROR_MASK_MASKED                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_STEER_ERROR_MASK_NOTMASKED                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_MASK_0_LANE1_STEER_ERROR_MASK_SHIFT                    _MK_SHIFT_CONST(14)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_STEER_ERROR_MASK_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_LANE1_STEER_ERROR_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_STEER_ERROR_MASK_RANGE                    14:14
#define SOR_NV_PDISP_INT_MASK_0_LANE1_STEER_ERROR_MASK_WOFFSET                  0x0
#define SOR_NV_PDISP_INT_MASK_0_LANE1_STEER_ERROR_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_STEER_ERROR_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_STEER_ERROR_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_STEER_ERROR_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_STEER_ERROR_MASK_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_STEER_ERROR_MASK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_STEER_ERROR_MASK_INIT_ENUM                        MASKED
#define SOR_NV_PDISP_INT_MASK_0_LANE1_STEER_ERROR_MASK_MASKED                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_STEER_ERROR_MASK_NOTMASKED                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_MASK_0_LANE2_STEER_ERROR_MASK_SHIFT                    _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_STEER_ERROR_MASK_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_LANE2_STEER_ERROR_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_STEER_ERROR_MASK_RANGE                    15:15
#define SOR_NV_PDISP_INT_MASK_0_LANE2_STEER_ERROR_MASK_WOFFSET                  0x0
#define SOR_NV_PDISP_INT_MASK_0_LANE2_STEER_ERROR_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_STEER_ERROR_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_STEER_ERROR_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_STEER_ERROR_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_STEER_ERROR_MASK_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_STEER_ERROR_MASK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_STEER_ERROR_MASK_INIT_ENUM                        MASKED
#define SOR_NV_PDISP_INT_MASK_0_LANE2_STEER_ERROR_MASK_MASKED                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_STEER_ERROR_MASK_NOTMASKED                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_MASK_0_LANE3_STEER_ERROR_MASK_SHIFT                    _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_STEER_ERROR_MASK_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_LANE3_STEER_ERROR_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_STEER_ERROR_MASK_RANGE                    16:16
#define SOR_NV_PDISP_INT_MASK_0_LANE3_STEER_ERROR_MASK_WOFFSET                  0x0
#define SOR_NV_PDISP_INT_MASK_0_LANE3_STEER_ERROR_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_STEER_ERROR_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_STEER_ERROR_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_STEER_ERROR_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_STEER_ERROR_MASK_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_STEER_ERROR_MASK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_STEER_ERROR_MASK_INIT_ENUM                        MASKED
#define SOR_NV_PDISP_INT_MASK_0_LANE3_STEER_ERROR_MASK_MASKED                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_STEER_ERROR_MASK_NOTMASKED                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_MASK_0_SPKT_OVERRUN_MASK_SHIFT                 _MK_SHIFT_CONST(17)
#define SOR_NV_PDISP_INT_MASK_0_SPKT_OVERRUN_MASK_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_SPKT_OVERRUN_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_SPKT_OVERRUN_MASK_RANGE                 17:17
#define SOR_NV_PDISP_INT_MASK_0_SPKT_OVERRUN_MASK_WOFFSET                       0x0
#define SOR_NV_PDISP_INT_MASK_0_SPKT_OVERRUN_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_SPKT_OVERRUN_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_SPKT_OVERRUN_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_SPKT_OVERRUN_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_SPKT_OVERRUN_MASK_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_SPKT_OVERRUN_MASK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_SPKT_OVERRUN_MASK_INIT_ENUM                     MASKED
#define SOR_NV_PDISP_INT_MASK_0_SPKT_OVERRUN_MASK_MASKED                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_SPKT_OVERRUN_MASK_NOTMASKED                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_SHIFT                  _MK_SHIFT_CONST(18)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_RANGE                  18:18
#define SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_WOFFSET                        0x0
#define SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_INIT_ENUM                      MASKED
#define SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_MASKED                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_NOTMASKED                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_SHIFT                  _MK_SHIFT_CONST(19)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_RANGE                  19:19
#define SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_WOFFSET                        0x0
#define SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_INIT_ENUM                      MASKED
#define SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_MASKED                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_NOTMASKED                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_SHIFT                  _MK_SHIFT_CONST(20)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_RANGE                  20:20
#define SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_WOFFSET                        0x0
#define SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_INIT_ENUM                      MASKED
#define SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_MASKED                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_NOTMASKED                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_SHIFT                  _MK_SHIFT_CONST(21)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_RANGE                  21:21
#define SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_WOFFSET                        0x0
#define SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_INIT_ENUM                      MASKED
#define SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_MASKED                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_NOTMASKED                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_MASK_0_LB_UNDERFLOW_MASK_SHIFT                 _MK_SHIFT_CONST(22)
#define SOR_NV_PDISP_INT_MASK_0_LB_UNDERFLOW_MASK_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_LB_UNDERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_LB_UNDERFLOW_MASK_RANGE                 22:22
#define SOR_NV_PDISP_INT_MASK_0_LB_UNDERFLOW_MASK_WOFFSET                       0x0
#define SOR_NV_PDISP_INT_MASK_0_LB_UNDERFLOW_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LB_UNDERFLOW_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LB_UNDERFLOW_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LB_UNDERFLOW_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LB_UNDERFLOW_MASK_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LB_UNDERFLOW_MASK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LB_UNDERFLOW_MASK_INIT_ENUM                     MASKED
#define SOR_NV_PDISP_INT_MASK_0_LB_UNDERFLOW_MASK_MASKED                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_LB_UNDERFLOW_MASK_NOTMASKED                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_MASK_0_LB_OVERFLOW_MASK_SHIFT                  _MK_SHIFT_CONST(23)
#define SOR_NV_PDISP_INT_MASK_0_LB_OVERFLOW_MASK_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_LB_OVERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_LB_OVERFLOW_MASK_RANGE                  23:23
#define SOR_NV_PDISP_INT_MASK_0_LB_OVERFLOW_MASK_WOFFSET                        0x0
#define SOR_NV_PDISP_INT_MASK_0_LB_OVERFLOW_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LB_OVERFLOW_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LB_OVERFLOW_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LB_OVERFLOW_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LB_OVERFLOW_MASK_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LB_OVERFLOW_MASK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LB_OVERFLOW_MASK_INIT_ENUM                      MASKED
#define SOR_NV_PDISP_INT_MASK_0_LB_OVERFLOW_MASK_MASKED                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_LB_OVERFLOW_MASK_NOTMASKED                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_MASK_0_AFIFO_UNDERFLOW_MASK_SHIFT                      _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_INT_MASK_0_AFIFO_UNDERFLOW_MASK_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_AFIFO_UNDERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_AFIFO_UNDERFLOW_MASK_RANGE                      24:24
#define SOR_NV_PDISP_INT_MASK_0_AFIFO_UNDERFLOW_MASK_WOFFSET                    0x0
#define SOR_NV_PDISP_INT_MASK_0_AFIFO_UNDERFLOW_MASK_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_AFIFO_UNDERFLOW_MASK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_AFIFO_UNDERFLOW_MASK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_AFIFO_UNDERFLOW_MASK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_AFIFO_UNDERFLOW_MASK_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_AFIFO_UNDERFLOW_MASK_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_AFIFO_UNDERFLOW_MASK_INIT_ENUM                  MASKED
#define SOR_NV_PDISP_INT_MASK_0_AFIFO_UNDERFLOW_MASK_MASKED                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_AFIFO_UNDERFLOW_MASK_NOTMASKED                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_MASK_0_AFIFO_OVERFLOW_MASK_SHIFT                       _MK_SHIFT_CONST(25)
#define SOR_NV_PDISP_INT_MASK_0_AFIFO_OVERFLOW_MASK_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_AFIFO_OVERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_AFIFO_OVERFLOW_MASK_RANGE                       25:25
#define SOR_NV_PDISP_INT_MASK_0_AFIFO_OVERFLOW_MASK_WOFFSET                     0x0
#define SOR_NV_PDISP_INT_MASK_0_AFIFO_OVERFLOW_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_AFIFO_OVERFLOW_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_AFIFO_OVERFLOW_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_AFIFO_OVERFLOW_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_AFIFO_OVERFLOW_MASK_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_AFIFO_OVERFLOW_MASK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_AFIFO_OVERFLOW_MASK_INIT_ENUM                   MASKED
#define SOR_NV_PDISP_INT_MASK_0_AFIFO_OVERFLOW_MASK_MASKED                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_AFIFO_OVERFLOW_MASK_NOTMASKED                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_UNDERFLOW_MASK_SHIFT                   _MK_SHIFT_CONST(26)
#define SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_UNDERFLOW_MASK_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_UNDERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_UNDERFLOW_MASK_RANGE                   26:26
#define SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_UNDERFLOW_MASK_WOFFSET                 0x0
#define SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_UNDERFLOW_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_UNDERFLOW_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_UNDERFLOW_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_UNDERFLOW_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_UNDERFLOW_MASK_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_UNDERFLOW_MASK_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_UNDERFLOW_MASK_INIT_ENUM                       MASKED
#define SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_UNDERFLOW_MASK_MASKED                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_UNDERFLOW_MASK_NOTMASKED                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_OVERFLOW_MASK_SHIFT                    _MK_SHIFT_CONST(27)
#define SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_OVERFLOW_MASK_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_OVERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_OVERFLOW_MASK_RANGE                    27:27
#define SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_OVERFLOW_MASK_WOFFSET                  0x0
#define SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_OVERFLOW_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_OVERFLOW_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_OVERFLOW_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_OVERFLOW_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_OVERFLOW_MASK_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_OVERFLOW_MASK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_OVERFLOW_MASK_INIT_ENUM                        MASKED
#define SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_OVERFLOW_MASK_MASKED                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_MASK_0_LB_AFIFO_OVERFLOW_MASK_NOTMASKED                        _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_INT_ENABLE_0
#define SOR_NV_PDISP_INT_ENABLE_0                       _MK_ADDR_CONST(0x11e)
#define SOR_NV_PDISP_INT_ENABLE_0_SECURE                        0x0
#define SOR_NV_PDISP_INT_ENABLE_0_DUAL                  0x0
#define SOR_NV_PDISP_INT_ENABLE_0_SCR                   0
#define SOR_NV_PDISP_INT_ENABLE_0_WORD_COUNT                    0x1
#define SOR_NV_PDISP_INT_ENABLE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_RESET_MASK                    _MK_MASK_CONST(0xfffffff)
#define SOR_NV_PDISP_INT_ENABLE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_READ_MASK                     _MK_MASK_CONST(0xfffffff)
#define SOR_NV_PDISP_INT_ENABLE_0_WRITE_MASK                    _MK_MASK_CONST(0xfffffff)
#define SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH0_ENABLE_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH0_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH0_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH0_ENABLE_RANGE                   0:0
#define SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH0_ENABLE_WOFFSET                 0x0
#define SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH0_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH0_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH0_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH0_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH0_ENABLE_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH0_ENABLE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH0_ENABLE_INIT_ENUM                       DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH0_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH0_ENABLE_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH1_ENABLE_SHIFT                   _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH1_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH1_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH1_ENABLE_RANGE                   1:1
#define SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH1_ENABLE_WOFFSET                 0x0
#define SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH1_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH1_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH1_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH1_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH1_ENABLE_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH1_ENABLE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH1_ENABLE_INIT_ENUM                       DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH1_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_CODEC_SCRATCH1_ENABLE_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_ENABLE_0_CP_REQUEST_ENABLE_SHIFT                       _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_INT_ENABLE_0_CP_REQUEST_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_CP_REQUEST_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_CP_REQUEST_ENABLE_RANGE                       2:2
#define SOR_NV_PDISP_INT_ENABLE_0_CP_REQUEST_ENABLE_WOFFSET                     0x0
#define SOR_NV_PDISP_INT_ENABLE_0_CP_REQUEST_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_CP_REQUEST_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_CP_REQUEST_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_CP_REQUEST_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_CP_REQUEST_ENABLE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_CP_REQUEST_ENABLE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_CP_REQUEST_ENABLE_INIT_ENUM                   DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_CP_REQUEST_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_CP_REQUEST_ENABLE_ENABLE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_ENABLE_0_SCRATCH_ENABLE_SHIFT                  _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_INT_ENABLE_0_SCRATCH_ENABLE_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_SCRATCH_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_SCRATCH_ENABLE_RANGE                  3:3
#define SOR_NV_PDISP_INT_ENABLE_0_SCRATCH_ENABLE_WOFFSET                        0x0
#define SOR_NV_PDISP_INT_ENABLE_0_SCRATCH_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_SCRATCH_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_SCRATCH_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_SCRATCH_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_SCRATCH_ENABLE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_SCRATCH_ENABLE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_SCRATCH_ENABLE_INIT_ENUM                      DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_SCRATCH_ENABLE_DISABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_SCRATCH_ENABLE_ENABLE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_ENABLE_0_REG_SECURE_ACCESS_ERR_ENABLE_SHIFT                    _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_INT_ENABLE_0_REG_SECURE_ACCESS_ERR_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_REG_SECURE_ACCESS_ERR_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_REG_SECURE_ACCESS_ERR_ENABLE_RANGE                    4:4
#define SOR_NV_PDISP_INT_ENABLE_0_REG_SECURE_ACCESS_ERR_ENABLE_WOFFSET                  0x0
#define SOR_NV_PDISP_INT_ENABLE_0_REG_SECURE_ACCESS_ERR_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_REG_SECURE_ACCESS_ERR_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_REG_SECURE_ACCESS_ERR_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_REG_SECURE_ACCESS_ERR_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_REG_SECURE_ACCESS_ERR_ENABLE_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_REG_SECURE_ACCESS_ERR_ENABLE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_REG_SECURE_ACCESS_ERR_ENABLE_INIT_ENUM                        DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_REG_SECURE_ACCESS_ERR_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_REG_SECURE_ACCESS_ERR_ENABLE_ENABLE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_SHIFT                     _MK_SHIFT_CONST(5)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_RANGE                     5:5
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_WOFFSET                   0x0
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_INIT_ENUM                 DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_SHIFT                     _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_RANGE                     6:6
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_WOFFSET                   0x0
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_INIT_ENUM                 DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_SHIFT                     _MK_SHIFT_CONST(7)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_RANGE                     7:7
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_WOFFSET                   0x0
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_INIT_ENUM                 DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_SHIFT                     _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_RANGE                     8:8
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_WOFFSET                   0x0
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_INIT_ENUM                 DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_SHIFT                   _MK_SHIFT_CONST(9)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_RANGE                   9:9
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_WOFFSET                 0x0
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_INIT_ENUM                       DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_SHIFT                   _MK_SHIFT_CONST(10)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_RANGE                   10:10
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_WOFFSET                 0x0
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_INIT_ENUM                       DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_SHIFT                   _MK_SHIFT_CONST(11)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_RANGE                   11:11
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_WOFFSET                 0x0
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_INIT_ENUM                       DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_SHIFT                   _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_RANGE                   12:12
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_WOFFSET                 0x0
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_INIT_ENUM                       DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_SHIFT                        _MK_SHIFT_CONST(13)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_RANGE                        13:13
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_WOFFSET                      0x0
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_INIT_ENUM                    DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_ENABLE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_SHIFT                        _MK_SHIFT_CONST(14)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_RANGE                        14:14
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_WOFFSET                      0x0
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_INIT_ENUM                    DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_ENABLE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_SHIFT                        _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_RANGE                        15:15
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_WOFFSET                      0x0
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_INIT_ENUM                    DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_ENABLE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_RANGE                        16:16
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_WOFFSET                      0x0
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_INIT_ENUM                    DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_ENABLE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_SHIFT                     _MK_SHIFT_CONST(17)
#define SOR_NV_PDISP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_RANGE                     17:17
#define SOR_NV_PDISP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_WOFFSET                   0x0
#define SOR_NV_PDISP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_INIT_ENUM                 DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_SHIFT                      _MK_SHIFT_CONST(18)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_RANGE                      18:18
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_WOFFSET                    0x0
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_INIT_ENUM                  DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_ENABLE                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_SHIFT                      _MK_SHIFT_CONST(19)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_RANGE                      19:19
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_WOFFSET                    0x0
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_INIT_ENUM                  DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_ENABLE                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_SHIFT                      _MK_SHIFT_CONST(20)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_RANGE                      20:20
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_WOFFSET                    0x0
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_INIT_ENUM                  DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_ENABLE                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_SHIFT                      _MK_SHIFT_CONST(21)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_RANGE                      21:21
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_WOFFSET                    0x0
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_INIT_ENUM                  DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_ENABLE                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_ENABLE_0_LB_UNDERFLOW_ENABLE_SHIFT                     _MK_SHIFT_CONST(22)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_UNDERFLOW_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_LB_UNDERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_UNDERFLOW_ENABLE_RANGE                     22:22
#define SOR_NV_PDISP_INT_ENABLE_0_LB_UNDERFLOW_ENABLE_WOFFSET                   0x0
#define SOR_NV_PDISP_INT_ENABLE_0_LB_UNDERFLOW_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_UNDERFLOW_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_UNDERFLOW_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_UNDERFLOW_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_UNDERFLOW_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_UNDERFLOW_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_UNDERFLOW_ENABLE_INIT_ENUM                 DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_LB_UNDERFLOW_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_UNDERFLOW_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_ENABLE_0_LB_OVERFLOW_ENABLE_SHIFT                      _MK_SHIFT_CONST(23)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_OVERFLOW_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_LB_OVERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_OVERFLOW_ENABLE_RANGE                      23:23
#define SOR_NV_PDISP_INT_ENABLE_0_LB_OVERFLOW_ENABLE_WOFFSET                    0x0
#define SOR_NV_PDISP_INT_ENABLE_0_LB_OVERFLOW_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_OVERFLOW_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_OVERFLOW_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_OVERFLOW_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_OVERFLOW_ENABLE_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_OVERFLOW_ENABLE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_OVERFLOW_ENABLE_INIT_ENUM                  DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_LB_OVERFLOW_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_OVERFLOW_ENABLE_ENABLE                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_ENABLE_0_AFIFO_UNDERFLOW_ENABLE_SHIFT                  _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_INT_ENABLE_0_AFIFO_UNDERFLOW_ENABLE_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_AFIFO_UNDERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_AFIFO_UNDERFLOW_ENABLE_RANGE                  24:24
#define SOR_NV_PDISP_INT_ENABLE_0_AFIFO_UNDERFLOW_ENABLE_WOFFSET                        0x0
#define SOR_NV_PDISP_INT_ENABLE_0_AFIFO_UNDERFLOW_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_AFIFO_UNDERFLOW_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_AFIFO_UNDERFLOW_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_AFIFO_UNDERFLOW_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_AFIFO_UNDERFLOW_ENABLE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_AFIFO_UNDERFLOW_ENABLE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_AFIFO_UNDERFLOW_ENABLE_INIT_ENUM                      DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_AFIFO_UNDERFLOW_ENABLE_DISABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_AFIFO_UNDERFLOW_ENABLE_ENABLE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_ENABLE_0_AFIFO_OVERFLOW_ENABLE_SHIFT                   _MK_SHIFT_CONST(25)
#define SOR_NV_PDISP_INT_ENABLE_0_AFIFO_OVERFLOW_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_AFIFO_OVERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_AFIFO_OVERFLOW_ENABLE_RANGE                   25:25
#define SOR_NV_PDISP_INT_ENABLE_0_AFIFO_OVERFLOW_ENABLE_WOFFSET                 0x0
#define SOR_NV_PDISP_INT_ENABLE_0_AFIFO_OVERFLOW_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_AFIFO_OVERFLOW_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_AFIFO_OVERFLOW_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_AFIFO_OVERFLOW_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_AFIFO_OVERFLOW_ENABLE_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_AFIFO_OVERFLOW_ENABLE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_AFIFO_OVERFLOW_ENABLE_INIT_ENUM                       DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_AFIFO_OVERFLOW_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_AFIFO_OVERFLOW_ENABLE_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_UNDERFLOW_ENABLE_SHIFT                       _MK_SHIFT_CONST(26)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_UNDERFLOW_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_UNDERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_UNDERFLOW_ENABLE_RANGE                       26:26
#define SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_UNDERFLOW_ENABLE_WOFFSET                     0x0
#define SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_UNDERFLOW_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_UNDERFLOW_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_UNDERFLOW_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_UNDERFLOW_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_UNDERFLOW_ENABLE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_UNDERFLOW_ENABLE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_UNDERFLOW_ENABLE_INIT_ENUM                   DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_UNDERFLOW_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_UNDERFLOW_ENABLE_ENABLE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_OVERFLOW_ENABLE_SHIFT                        _MK_SHIFT_CONST(27)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_OVERFLOW_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_OVERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_OVERFLOW_ENABLE_RANGE                        27:27
#define SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_OVERFLOW_ENABLE_WOFFSET                      0x0
#define SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_OVERFLOW_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_OVERFLOW_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_OVERFLOW_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_OVERFLOW_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_OVERFLOW_ENABLE_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_OVERFLOW_ENABLE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_OVERFLOW_ENABLE_INIT_ENUM                    DISABLE
#define SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_OVERFLOW_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_INT_ENABLE_0_LB_AFIFO_OVERFLOW_ENABLE_ENABLE                       _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_TMDS_HDCP_M0_LO_0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_LO_0                      _MK_ADDR_CONST(0x11f)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_LO_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_LO_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_LO_0_SCR                  0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_LO_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_LO_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_LO_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_LO_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_LO_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_LO_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_LO_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_LO_0_value_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_LO_0_value_FIELD                  _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_TMDS_HDCP_M0_LO_0_value_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_LO_0_value_RANGE                  31:0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_LO_0_value_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_LO_0_value_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_LO_0_value_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_LO_0_value_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_LO_0_value_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_LO_0_value_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_LO_0_value_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_TMDS_HDCP_M0_HI_0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_HI_0                      _MK_ADDR_CONST(0x120)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_HI_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_HI_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_HI_0_SCR                  0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_HI_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_HI_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_HI_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_HI_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_HI_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_HI_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_HI_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_HI_0_value_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_HI_0_value_FIELD                  _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_TMDS_HDCP_M0_HI_0_value_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_HI_0_value_RANGE                  31:0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_HI_0_value_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_HI_0_value_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_HI_0_value_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_HI_0_value_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_HI_0_value_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_HI_0_value_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_M0_HI_0_value_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0                     _MK_ADDR_CONST(0x121)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_SECURE                      0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_DUAL                        0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_SCR                         0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_WORD_COUNT                  0x1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0x107)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_READ_MASK                   _MK_MASK_CONST(0x107)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x107)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_RPTR_OVERRIDE_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_RPTR_OVERRIDE_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_RPTR_OVERRIDE_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_RPTR_OVERRIDE_RANGE                 0:0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_RPTR_OVERRIDE_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_RPTR_OVERRIDE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_RPTR_OVERRIDE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_RPTR_OVERRIDE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_RPTR_OVERRIDE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_RPTR_OVERRIDE_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_RPTR_OVERRIDE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_UNPROTECTED_OVERRIDE_SHIFT                  _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_UNPROTECTED_OVERRIDE_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_UNPROTECTED_OVERRIDE_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_UNPROTECTED_OVERRIDE_RANGE                  1:1
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_UNPROTECTED_OVERRIDE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_UNPROTECTED_OVERRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_UNPROTECTED_OVERRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_UNPROTECTED_OVERRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_UNPROTECTED_OVERRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_UNPROTECTED_OVERRIDE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_UNPROTECTED_OVERRIDE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_SCOPE_OVERRIDE_SHIFT                        _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_SCOPE_OVERRIDE_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_SCOPE_OVERRIDE_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_SCOPE_OVERRIDE_RANGE                        2:2
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_SCOPE_OVERRIDE_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_SCOPE_OVERRIDE_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_SCOPE_OVERRIDE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_SCOPE_OVERRIDE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_SCOPE_OVERRIDE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_SCOPE_OVERRIDE_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_SCOPE_OVERRIDE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_OVERRIDE_ENABLE_SHIFT                       _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_OVERRIDE_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_OVERRIDE_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_OVERRIDE_ENABLE_RANGE                       8:8
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_OVERRIDE_ENABLE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_OVERRIDE_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_OVERRIDE_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_OVERRIDE_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_OVERRIDE_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_OVERRIDE_ENABLE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0_OVERRIDE_ENABLE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

// Register SOR_NV_HDACODEC_AUDIO_GEN_CTL_0
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0                 _MK_ADDR_CONST(0x122)
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_SECURE                  0x0
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_DUAL                    0x0
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_SCR                     0
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_WORD_COUNT                      0x1
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_RESET_VAL                       _MK_MASK_CONST(0xf)
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_RESET_MASK                      _MK_MASK_CONST(0x1f)
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_READ_MASK                       _MK_MASK_CONST(0x1f)
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_WRITE_MASK                      _MK_MASK_CONST(0x1f)
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_CHSTS_FS_3840_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_CHSTS_FS_3840_FIELD                     _MK_FIELD_CONST(0xf, SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_CHSTS_FS_3840_SHIFT)
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_CHSTS_FS_3840_RANGE                     3:0
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_CHSTS_FS_3840_WOFFSET                   0x0
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_CHSTS_FS_3840_DEFAULT                   _MK_MASK_CONST(0xf)
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_CHSTS_FS_3840_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_CHSTS_FS_3840_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_CHSTS_FS_3840_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_CHSTS_FS_3840_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_CHSTS_FS_3840_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_COPY_POLARITY_SHIFT                     _MK_SHIFT_CONST(4)
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_COPY_POLARITY_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_COPY_POLARITY_SHIFT)
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_COPY_POLARITY_RANGE                     4:4
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_COPY_POLARITY_WOFFSET                   0x0
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_COPY_POLARITY_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_COPY_POLARITY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_COPY_POLARITY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_COPY_POLARITY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_COPY_POLARITY_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_COPY_POLARITY_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_COPY_POLARITY_INIT_ENUM                 OLD
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_COPY_POLARITY_OLD                       _MK_ENUM_CONST(0)
#define SOR_NV_HDACODEC_AUDIO_GEN_CTL_0_COPY_POLARITY_NEW                       _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0                      _MK_ADDR_CONST(0x123)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_SCR                  0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_RESET_VAL                    _MK_MASK_CONST(0x10200)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_RESET_MASK                   _MK_MASK_CONST(0x10311)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_READ_MASK                    _MK_MASK_CONST(0x10311)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_WRITE_MASK                   _MK_MASK_CONST(0x10311)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_ENABLE_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_ENABLE_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_ENABLE_RANGE                 0:0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_ENABLE_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_ENABLE_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_ENABLE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_ENABLE_INIT_ENUM                     NO
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_ENABLE_NO                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_ENABLE_YES                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_ENABLE_DIS                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_ENABLE_EN                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_OTHER_SHIFT                  _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_OTHER_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_OTHER_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_OTHER_RANGE                  4:4
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_OTHER_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_OTHER_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_OTHER_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_OTHER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_OTHER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_OTHER_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_OTHER_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_OTHER_INIT_ENUM                      DIS
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_OTHER_DIS                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_OTHER_EN                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_SINGLE_SHIFT                 _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_SINGLE_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_SINGLE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_SINGLE_RANGE                 8:8
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_SINGLE_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_SINGLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_SINGLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_SINGLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_SINGLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_SINGLE_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_SINGLE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_SINGLE_INIT_ENUM                     DIS
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_SINGLE_DIS                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_SINGLE_EN                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_CHKSUM_HW_SHIFT                      _MK_SHIFT_CONST(9)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_CHKSUM_HW_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_CHKSUM_HW_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_CHKSUM_HW_RANGE                      9:9
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_CHKSUM_HW_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_CHKSUM_HW_DEFAULT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_CHKSUM_HW_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_CHKSUM_HW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_CHKSUM_HW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_CHKSUM_HW_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_CHKSUM_HW_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_CHKSUM_HW_INIT_ENUM                  ENABLE
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_CHKSUM_HW_DISABLE                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_CHKSUM_HW_ENABLE                     _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_CHKSUM_HW_DIS                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_CHKSUM_HW_EN                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_VIDEO_FMT_SHIFT                      _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_VIDEO_FMT_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_VIDEO_FMT_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_VIDEO_FMT_RANGE                      16:16
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_VIDEO_FMT_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_VIDEO_FMT_DEFAULT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_VIDEO_FMT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_VIDEO_FMT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_VIDEO_FMT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_VIDEO_FMT_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_VIDEO_FMT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_VIDEO_FMT_INIT_ENUM                  HW_CONTROLLED
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_VIDEO_FMT_SW_CONTROLLED                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0_VIDEO_FMT_HW_CONTROLLED                      _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_STATUS_0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_STATUS_0                    _MK_ADDR_CONST(0x124)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_STATUS_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_STATUS_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_STATUS_0_SCR                        0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_STATUS_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_STATUS_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_STATUS_0_SENT_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_STATUS_0_SENT_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_STATUS_0_SENT_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_STATUS_0_SENT_RANGE                 0:0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_STATUS_0_SENT_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_STATUS_0_SENT_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_STATUS_0_SENT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_STATUS_0_SENT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_STATUS_0_SENT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_STATUS_0_SENT_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_STATUS_0_SENT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_STATUS_0_SENT_INIT_ENUM                     WAITING
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_STATUS_0_SENT_WAITING                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_STATUS_0_SENT_DONE                  _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0                    _MK_ADDR_CONST(0x125)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_SCR                        0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_RESET_MASK                         _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_READ_MASK                  _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_WRITE_MASK                         _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB0_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB0_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB0_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB0_RANGE                  7:0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB0_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB0_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB0_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB0_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB0_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB1_SHIFT                  _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB1_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB1_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB1_RANGE                  15:8
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB1_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB1_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB1_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB1_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB1_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB2_SHIFT                  _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB2_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB2_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB2_RANGE                  23:16
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB2_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB2_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB2_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB2_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0_HB2_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0                      _MK_ADDR_CONST(0x126)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_SCR                  0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB0_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB0_FIELD                    _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB0_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB0_RANGE                    7:0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB0_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB0_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB0_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB0_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB1_SHIFT                    _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB1_FIELD                    _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB1_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB1_RANGE                    15:8
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB1_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB1_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB1_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB1_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB2_SHIFT                    _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB2_FIELD                    _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB2_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB2_RANGE                    23:16
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB2_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB2_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB2_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB2_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB2_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB3_SHIFT                    _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB3_FIELD                    _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB3_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB3_RANGE                    31:24
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB3_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB3_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB3_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB3_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0_PB3_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0                     _MK_ADDR_CONST(0x127)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_SECURE                      0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_DUAL                        0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_SCR                         0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_WORD_COUNT                  0x1
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_RESET_MASK                  _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_READ_MASK                   _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB4_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB4_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB4_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB4_RANGE                   7:0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB4_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB4_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB4_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB4_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB4_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB5_SHIFT                   _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB5_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB5_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB5_RANGE                   15:8
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB5_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB5_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB5_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB5_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB5_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB6_SHIFT                   _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB6_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB6_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB6_RANGE                   23:16
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB6_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB6_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB6_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB6_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0_PB6_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0                      _MK_ADDR_CONST(0x128)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_SCR                  0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB7_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB7_FIELD                    _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB7_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB7_RANGE                    7:0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB7_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB7_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB7_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB7_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB7_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB8_SHIFT                    _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB8_FIELD                    _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB8_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB8_RANGE                    15:8
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB8_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB8_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB8_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB8_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB8_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB8_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB8_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB9_SHIFT                    _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB9_FIELD                    _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB9_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB9_RANGE                    23:16
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB9_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB9_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB9_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB9_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB9_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB9_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB9_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB10_SHIFT                   _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB10_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB10_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB10_RANGE                   31:24
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB10_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB10_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB10_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB10_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB10_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB10_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0_PB10_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0                     _MK_ADDR_CONST(0x129)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_SECURE                      0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_DUAL                        0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_SCR                         0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_WORD_COUNT                  0x1
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_RESET_MASK                  _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_READ_MASK                   _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB11_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB11_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB11_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB11_RANGE                  7:0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB11_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB11_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB11_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB11_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB11_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB11_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB11_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB12_SHIFT                  _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB12_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB12_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB12_RANGE                  15:8
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB12_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB12_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB12_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB12_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB12_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB12_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB12_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB13_SHIFT                  _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB13_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB13_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB13_RANGE                  23:16
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB13_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB13_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB13_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB13_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB13_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB13_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0_PB13_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0                      _MK_ADDR_CONST(0x12a)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_SCR                  0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB14_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB14_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB14_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB14_RANGE                   7:0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB14_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB14_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB14_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB14_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB14_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB14_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB14_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB15_SHIFT                   _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB15_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB15_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB15_RANGE                   15:8
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB15_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB15_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB15_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB15_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB15_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB15_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB15_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB16_SHIFT                   _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB16_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB16_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB16_RANGE                   23:16
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB16_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB16_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB16_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB16_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB16_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB16_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB16_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB17_SHIFT                   _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB17_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB17_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB17_RANGE                   31:24
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB17_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB17_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB17_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB17_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB17_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB17_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0_PB17_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0                     _MK_ADDR_CONST(0x12b)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_SECURE                      0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_DUAL                        0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_SCR                         0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_WORD_COUNT                  0x1
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_RESET_MASK                  _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_READ_MASK                   _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB18_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB18_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB18_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB18_RANGE                  7:0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB18_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB18_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB18_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB18_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB18_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB18_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB18_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB19_SHIFT                  _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB19_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB19_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB19_RANGE                  15:8
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB19_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB19_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB19_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB19_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB19_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB19_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB19_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB20_SHIFT                  _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB20_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB20_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB20_RANGE                  23:16
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB20_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB20_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB20_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB20_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB20_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB20_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0_PB20_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0                      _MK_ADDR_CONST(0x12c)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_SCR                  0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB21_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB21_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB21_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB21_RANGE                   7:0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB21_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB21_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB21_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB21_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB21_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB21_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB21_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB22_SHIFT                   _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB22_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB22_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB22_RANGE                   15:8
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB22_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB22_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB22_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB22_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB22_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB22_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB22_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB23_SHIFT                   _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB23_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB23_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB23_RANGE                   23:16
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB23_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB23_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB23_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB23_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB23_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB23_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB23_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB24_SHIFT                   _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB24_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB24_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB24_RANGE                   31:24
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB24_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB24_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB24_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB24_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB24_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB24_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0_PB24_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0                     _MK_ADDR_CONST(0x12d)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_SECURE                      0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_DUAL                        0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_SCR                         0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_WORD_COUNT                  0x1
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_RESET_MASK                  _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_READ_MASK                   _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB25_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB25_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB25_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB25_RANGE                  7:0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB25_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB25_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB25_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB25_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB25_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB25_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB25_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB26_SHIFT                  _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB26_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB26_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB26_RANGE                  15:8
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB26_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB26_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB26_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB26_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB26_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB26_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB26_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB27_SHIFT                  _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB27_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB27_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB27_RANGE                  23:16
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB27_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB27_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB27_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB27_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB27_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB27_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0_PB27_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_AUDIO_CRC_0
#define SOR_NV_PDISP_SOR_DP_AUDIO_CRC_0                 _MK_ADDR_CONST(0x12e)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CRC_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_CRC_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_CRC_0_SCR                     0
#define SOR_NV_PDISP_SOR_DP_AUDIO_CRC_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_DP_AUDIO_CRC_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CRC_0_RESET_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CRC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CRC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CRC_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CRC_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CRC_0_VALUE_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CRC_0_VALUE_FIELD                     _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_DP_AUDIO_CRC_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CRC_0_VALUE_RANGE                     31:0
#define SOR_NV_PDISP_SOR_DP_AUDIO_CRC_0_VALUE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_CRC_0_VALUE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CRC_0_VALUE_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CRC_0_VALUE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CRC_0_VALUE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CRC_0_VALUE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_CRC_0_VALUE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_AUDIO_MN_0
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0                  _MK_ADDR_CONST(0x12f)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_SECURE                   0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_DUAL                     0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_SCR                      0
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_WORD_COUNT                       0x1
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_RESET_VAL                        _MK_MASK_CONST(0x8000)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_RESET_MASK                       _MK_MASK_CONST(0xcfffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_READ_MASK                        _MK_MASK_CONST(0xcfffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_WRITE_MASK                       _MK_MASK_CONST(0xcfffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_VAL_SHIFT                        _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_VAL_FIELD                        _MK_FIELD_CONST(0xffffff, SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_VAL_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_VAL_RANGE                        23:0
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_VAL_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_VAL_DEFAULT                      _MK_MASK_CONST(0x8000)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0xffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_VAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_VAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_DELTA_SHIFT                      _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_DELTA_FIELD                      _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_DELTA_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_DELTA_RANGE                      27:24
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_DELTA_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_DELTA_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_DELTA_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_DELTA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_DELTA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_DELTA_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_DELTA_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_MOD_SHIFT                        _MK_SHIFT_CONST(30)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_MOD_FIELD                        _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_MOD_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_MOD_RANGE                        31:30
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_MOD_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_MOD_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_MOD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_MOD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_MOD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_MOD_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_MOD_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_MOD_NONE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_MOD_INC                  _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_MN_0_MOD_DEC                  _MK_ENUM_CONST(2)

// Register SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0                    _MK_ADDR_CONST(0x130)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_SCR                        0
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB0_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB0_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB0_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB0_RANGE                  7:0
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB0_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB0_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB0_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB0_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB0_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB1_SHIFT                  _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB1_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB1_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB1_RANGE                  15:8
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB1_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB1_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB1_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB1_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB1_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB2_SHIFT                  _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB2_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB2_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB2_RANGE                  23:16
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB2_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB2_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB2_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB2_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB2_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB3_SHIFT                  _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB3_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB3_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB3_RANGE                  31:24
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB3_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB3_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB3_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB3_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0_HB3_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0                      _MK_ADDR_CONST(0x131)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_SCR                  0
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB0_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB0_FIELD                    _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB0_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB0_RANGE                    7:0
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB0_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB0_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB0_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB0_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB1_SHIFT                    _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB1_FIELD                    _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB1_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB1_RANGE                    15:8
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB1_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB1_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB1_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB1_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB2_SHIFT                    _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB2_FIELD                    _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB2_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB2_RANGE                    23:16
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB2_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB2_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB2_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB2_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB2_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB3_SHIFT                    _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB3_FIELD                    _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB3_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB3_RANGE                    31:24
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB3_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB3_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB3_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB3_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0_PB3_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0                     _MK_ADDR_CONST(0x132)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_SECURE                      0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_DUAL                        0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_SCR                         0
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_WORD_COUNT                  0x1
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_RESET_MASK                  _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_READ_MASK                   _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_WRITE_MASK                  _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB4_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB4_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB4_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB4_RANGE                   7:0
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB4_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB4_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB4_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB4_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB4_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB5_SHIFT                   _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB5_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB5_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB5_RANGE                   15:8
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB5_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB5_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB5_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB5_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0_PB5_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0                      _MK_ADDR_CONST(0x133)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_SCR                  0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_RESET_VAL                    _MK_MASK_CONST(0x40014e7)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_D_N_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_D_N_FIELD                    _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_D_N_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_D_N_RANGE                    15:0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_D_N_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_D_N_DEFAULT                  _MK_MASK_CONST(0x14e7)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_D_N_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_D_N_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_D_N_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_D_N_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_D_N_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_N_SHIFT                      _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_N_FIELD                      _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_N_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_N_RANGE                      31:16
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_N_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_N_DEFAULT                    _MK_MASK_CONST(0x400)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_N_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_N_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_N_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_N_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0_N_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0                      _MK_ADDR_CONST(0x134)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_SCR                  0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_RESET_VAL                    _MK_MASK_CONST(0x9302051)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_D_N_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_D_N_FIELD                    _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_D_N_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_D_N_RANGE                    15:0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_D_N_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_D_N_DEFAULT                  _MK_MASK_CONST(0x2051)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_D_N_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_D_N_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_D_N_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_D_N_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_D_N_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_N_SHIFT                      _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_N_FIELD                      _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_N_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_N_RANGE                      31:16
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_N_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_N_DEFAULT                    _MK_MASK_CONST(0x930)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_N_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_N_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_N_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_N_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0_N_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0                      _MK_ADDR_CONST(0x135)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_SCR                  0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_RESET_VAL                    _MK_MASK_CONST(0x12601721)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_D_N_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_D_N_FIELD                    _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_D_N_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_D_N_RANGE                    15:0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_D_N_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_D_N_DEFAULT                  _MK_MASK_CONST(0x1721)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_D_N_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_D_N_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_D_N_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_D_N_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_D_N_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_N_SHIFT                      _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_N_FIELD                      _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_N_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_N_RANGE                      31:16
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_N_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_N_DEFAULT                    _MK_MASK_CONST(0x1260)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_N_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_N_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_N_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_N_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0_N_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0                      _MK_ADDR_CONST(0x136)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_SCR                  0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_RESET_VAL                    _MK_MASK_CONST(0x24c004c1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_D_N_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_D_N_FIELD                    _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_D_N_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_D_N_RANGE                    15:0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_D_N_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_D_N_DEFAULT                  _MK_MASK_CONST(0x4c1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_D_N_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_D_N_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_D_N_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_D_N_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_D_N_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_N_SHIFT                      _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_N_FIELD                      _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_N_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_N_RANGE                      31:16
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_N_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_N_DEFAULT                    _MK_MASK_CONST(0x24c0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_N_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_N_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_N_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_N_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0_N_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0                      _MK_ADDR_CONST(0x137)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_SCR                  0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_RESET_VAL                    _MK_MASK_CONST(0x200064d)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_D_N_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_D_N_FIELD                    _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_D_N_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_D_N_RANGE                    15:0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_D_N_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_D_N_DEFAULT                  _MK_MASK_CONST(0x64d)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_D_N_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_D_N_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_D_N_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_D_N_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_D_N_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_N_SHIFT                      _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_N_FIELD                      _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_N_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_N_RANGE                      31:16
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_N_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_N_DEFAULT                    _MK_MASK_CONST(0x200)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_N_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_N_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_N_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_N_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0_N_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0                      _MK_ADDR_CONST(0x138)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_SCR                  0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_RESET_VAL                    _MK_MASK_CONST(0x400044d)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_D_N_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_D_N_FIELD                    _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_D_N_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_D_N_RANGE                    15:0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_D_N_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_D_N_DEFAULT                  _MK_MASK_CONST(0x44d)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_D_N_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_D_N_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_D_N_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_D_N_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_D_N_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_N_SHIFT                      _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_N_FIELD                      _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_N_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_N_RANGE                      31:16
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_N_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_N_DEFAULT                    _MK_MASK_CONST(0x400)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_N_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_N_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_N_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_N_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0_N_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0                      _MK_ADDR_CONST(0x139)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_SCR                  0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_RESET_VAL                    _MK_MASK_CONST(0x800004d)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_D_N_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_D_N_FIELD                    _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_D_N_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_D_N_RANGE                    15:0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_D_N_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_D_N_DEFAULT                  _MK_MASK_CONST(0x4d)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_D_N_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_D_N_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_D_N_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_D_N_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_D_N_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_N_SHIFT                      _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_N_FIELD                      _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_N_SHIFT)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_N_RANGE                      31:16
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_N_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_N_DEFAULT                    _MK_MASK_CONST(0x800)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_N_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_N_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_N_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_N_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0_N_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0                    _MK_ADDR_CONST(0x13a)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SCR                        0
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_RESET_VAL                  _MK_MASK_CONST(0xf21fffff)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_ABCDM_SHIFT                        _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_ABCDM_FIELD                        _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_ABCDM_SHIFT)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_ABCDM_RANGE                        7:0
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_ABCDM_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_ABCDM_DEFAULT                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_ABCDM_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_ABCDM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_ABCDM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_ABCDM_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_ABCDM_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_CODE_SHIFT                 _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_CODE_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_CODE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_CODE_RANGE                 15:8
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_CODE_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_CODE_DEFAULT                       _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_CODE_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_CODE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_CODE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_CODE_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_CODE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SOURCE_SHIFT                       _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SOURCE_FIELD                       _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SOURCE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SOURCE_RANGE                       19:16
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SOURCE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SOURCE_DEFAULT                     _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SOURCE_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SOURCE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SOURCE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SOURCE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SOURCE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_CHANNEL_SHIFT                      _MK_SHIFT_CONST(20)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_CHANNEL_FIELD                      _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_CHANNEL_SHIFT)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_CHANNEL_RANGE                      23:20
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_CHANNEL_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_CHANNEL_DEFAULT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_CHANNEL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_CHANNEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_CHANNEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_CHANNEL_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_CHANNEL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SFREQ_SHIFT                        _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SFREQ_FIELD                        _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SFREQ_SHIFT)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SFREQ_RANGE                        27:24
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SFREQ_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SFREQ_DEFAULT                      _MK_MASK_CONST(0x2)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SFREQ_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SFREQ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SFREQ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SFREQ_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SFREQ_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SFREQ_FREQ_22_05KHZ                        _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SFREQ_FREQ_44_1KHZ                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SFREQ_FREQ_88_2KHZ                 _MK_ENUM_CONST(8)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SFREQ_FREQ_176_4KHZ                        _MK_ENUM_CONST(12)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SFREQ_FREQ_24KHZ                   _MK_ENUM_CONST(6)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SFREQ_FREQ_48KHZ                   _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SFREQ_FREQ_96KHZ                   _MK_ENUM_CONST(10)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SFREQ_FREQ_192KHZ                  _MK_ENUM_CONST(14)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SFREQ_FREQ_32KHZ                   _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_SFREQ_FREQ_UNDEFINED                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_ACCURACY_SHIFT                     _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_ACCURACY_FIELD                     _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_ACCURACY_SHIFT)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_ACCURACY_RANGE                     31:28
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_ACCURACY_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_ACCURACY_DEFAULT                   _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_ACCURACY_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_ACCURACY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_ACCURACY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_ACCURACY_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_ACCURACY_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_ACCURACY_LVL1                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_ACCURACY_LVL2                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_ACCURACY_LVL3                      _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0_ACCURACY_OTHER                     _MK_ENUM_CONST(3)

// Register SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0                    _MK_ADDR_CONST(0x13b)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_SCR                        0
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_RESET_VAL                  _MK_MASK_CONST(0xf1)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_RESET_MASK                         _MK_MASK_CONST(0x800000ff)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_READ_MASK                  _MK_MASK_CONST(0x800000ff)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_WRITE_MASK                         _MK_MASK_CONST(0x800000ff)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_MAX_LENGTH_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_MAX_LENGTH_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_MAX_LENGTH_SHIFT)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_MAX_LENGTH_RANGE                   0:0
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_MAX_LENGTH_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_MAX_LENGTH_DEFAULT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_MAX_LENGTH_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_MAX_LENGTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_MAX_LENGTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_MAX_LENGTH_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_MAX_LENGTH_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_MAX_LENGTH_MAX20                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_MAX_LENGTH_MAX24                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_LENGTH_SHIFT                       _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_LENGTH_FIELD                       _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_LENGTH_SHIFT)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_LENGTH_RANGE                       3:1
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_LENGTH_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_LENGTH_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_LENGTH_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_LENGTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_LENGTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_LENGTH_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_LENGTH_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_LENGTH_MAX20_UNDEF                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_LENGTH_MAX20_16BITS                        _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_LENGTH_MAX20_18BITS                        _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_LENGTH_MAX20_19BITS                        _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_LENGTH_MAX20_20BITS                        _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_LENGTH_MAX20_17BITS                        _MK_ENUM_CONST(6)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_LENGTH_MAX24_UNDEF                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_LENGTH_MAX24_20BITS                        _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_LENGTH_MAX24_22BITS                        _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_LENGTH_MAX24_23BITS                        _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_LENGTH_MAX24_24BITS                        _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_LENGTH_MAX24_21BITS                        _MK_ENUM_CONST(6)

#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ORIGINAL_SHIFT                     _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ORIGINAL_FIELD                     _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ORIGINAL_SHIFT)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ORIGINAL_RANGE                     7:4
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ORIGINAL_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ORIGINAL_DEFAULT                   _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ORIGINAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ORIGINAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ORIGINAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ORIGINAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ORIGINAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ORIGINAL_FREQ_8KHZ                 _MK_ENUM_CONST(6)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ORIGINAL_FREQ_11_025KHZ                    _MK_ENUM_CONST(10)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ORIGINAL_FREQ_12KHZ                        _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ORIGINAL_FREQ_16KHZ                        _MK_ENUM_CONST(8)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ORIGINAL_FREQ_22_05KHZ                     _MK_ENUM_CONST(11)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ORIGINAL_FREQ_24KHZ                        _MK_ENUM_CONST(9)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ORIGINAL_FREQ_44_1KHZ                      _MK_ENUM_CONST(15)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ORIGINAL_FREQ_48KHZ                        _MK_ENUM_CONST(13)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ORIGINAL_FREQ_88_2KHZ                      _MK_ENUM_CONST(7)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ORIGINAL_FREQ_96KHZ                        _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ORIGINAL_FREQ_176_4KHZ                     _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ORIGINAL_FREQ_192KHZ                       _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ORIGINAL_FREQ_UNDEFINED                    _MK_ENUM_CONST(0)

#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ENABLE_SHIFT                       _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ENABLE_RANGE                       31:31
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ENABLE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ENABLE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ENABLE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ENABLE_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ENABLE_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0_ENABLE_YES                 _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_HDMI_AUDIO_N_0
#define SOR_NV_PDISP_HDMI_AUDIO_N_0                     _MK_ADDR_CONST(0x13c)
#define SOR_NV_PDISP_HDMI_AUDIO_N_0_SECURE                      0x0
#define SOR_NV_PDISP_HDMI_AUDIO_N_0_DUAL                        0x0
#define SOR_NV_PDISP_HDMI_AUDIO_N_0_SCR                         0
#define SOR_NV_PDISP_HDMI_AUDIO_N_0_WORD_COUNT                  0x1
#define SOR_NV_PDISP_HDMI_AUDIO_N_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_AUDIO_N_0_RESET_MASK                  _MK_MASK_CONST(0x10000000)
#define SOR_NV_PDISP_HDMI_AUDIO_N_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_AUDIO_N_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_AUDIO_N_0_READ_MASK                   _MK_MASK_CONST(0x10000000)
#define SOR_NV_PDISP_HDMI_AUDIO_N_0_WRITE_MASK                  _MK_MASK_CONST(0x10000000)
#define SOR_NV_PDISP_HDMI_AUDIO_N_0_LOOKUP_SHIFT                        _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_HDMI_AUDIO_N_0_LOOKUP_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_HDMI_AUDIO_N_0_LOOKUP_SHIFT)
#define SOR_NV_PDISP_HDMI_AUDIO_N_0_LOOKUP_RANGE                        28:28
#define SOR_NV_PDISP_HDMI_AUDIO_N_0_LOOKUP_WOFFSET                      0x0
#define SOR_NV_PDISP_HDMI_AUDIO_N_0_LOOKUP_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_AUDIO_N_0_LOOKUP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HDMI_AUDIO_N_0_LOOKUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_AUDIO_N_0_LOOKUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_AUDIO_N_0_LOOKUP_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HDMI_AUDIO_N_0_LOOKUP_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HDMI_AUDIO_N_0_LOOKUP_ENABLE                       _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_HDMI_AUDIO_N_0_LOOKUP_DISABLE                      _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0                     _MK_ADDR_CONST(0x13d)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_SECURE                      0x0
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_DUAL                        0x0
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_SCR                         0
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_WORD_COUNT                  0x1
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE3_CALIB_SHIFT                   _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE3_CALIB_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE3_CALIB_SHIFT)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE3_CALIB_RANGE                   31:24
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE3_CALIB_WOFFSET                 0x0
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE3_CALIB_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE3_CALIB_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE3_CALIB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE3_CALIB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE3_CALIB_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE3_CALIB_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE2_CALIB_SHIFT                   _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE2_CALIB_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE2_CALIB_SHIFT)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE2_CALIB_RANGE                   23:16
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE2_CALIB_WOFFSET                 0x0
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE2_CALIB_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE2_CALIB_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE2_CALIB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE2_CALIB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE2_CALIB_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE2_CALIB_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE1_CALIB_SHIFT                   _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE1_CALIB_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE1_CALIB_SHIFT)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE1_CALIB_RANGE                   15:8
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE1_CALIB_WOFFSET                 0x0
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE1_CALIB_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE1_CALIB_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE1_CALIB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE1_CALIB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE1_CALIB_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE1_CALIB_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE0_CALIB_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE0_CALIB_FIELD                   _MK_FIELD_CONST(0xff, SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE0_CALIB_SHIFT)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE0_CALIB_RANGE                   7:0
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE0_CALIB_WOFFSET                 0x0
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE0_CALIB_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE0_CALIB_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE0_CALIB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE0_CALIB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE0_CALIB_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0_LANE0_CALIB_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI2_CTRL_0
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0                   _MK_ADDR_CONST(0x13e)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SCR                       0
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_RESET_VAL                         _MK_MASK_CONST(0x2000080)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_RESET_MASK                        _MK_MASK_CONST(0xffff00f7)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_READ_MASK                         _MK_MASK_CONST(0xffff00f7)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xffff00f7)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SCRAMBLE_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SCRAMBLE_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SCRAMBLE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SCRAMBLE_RANGE                    0:0
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SCRAMBLE_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SCRAMBLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SCRAMBLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SCRAMBLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SCRAMBLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SCRAMBLE_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SCRAMBLE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SCRAMBLE_ENABLE                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SCRAMBLE_DISABLE                  _MK_ENUM_CONST(0)

#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_CLOCK_MODE_SHIFT                  _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_CLOCK_MODE_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI2_CTRL_0_CLOCK_MODE_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_CLOCK_MODE_RANGE                  1:1
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_CLOCK_MODE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_CLOCK_MODE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_CLOCK_MODE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_CLOCK_MODE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_CLOCK_MODE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_CLOCK_MODE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_CLOCK_MODE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_CLOCK_MODE_NORMAL                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_CLOCK_MODE_MODE_DIV_BY_4                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SCRAMBLE_AT_LOADV_SHIFT                   _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SCRAMBLE_AT_LOADV_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SCRAMBLE_AT_LOADV_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SCRAMBLE_AT_LOADV_RANGE                   2:2
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SCRAMBLE_AT_LOADV_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SCRAMBLE_AT_LOADV_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SCRAMBLE_AT_LOADV_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SCRAMBLE_AT_LOADV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SCRAMBLE_AT_LOADV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SCRAMBLE_AT_LOADV_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SCRAMBLE_AT_LOADV_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SCRAMBLE_AT_LOADV_DISABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SCRAMBLE_AT_LOADV_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SSCP_LENGTH_SHIFT                 _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SSCP_LENGTH_FIELD                 _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SSCP_LENGTH_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SSCP_LENGTH_RANGE                 7:4
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SSCP_LENGTH_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SSCP_LENGTH_DEFAULT                       _MK_MASK_CONST(0x8)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SSCP_LENGTH_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SSCP_LENGTH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SSCP_LENGTH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SSCP_LENGTH_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SSCP_LENGTH_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SSCP_START_SHIFT                  _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SSCP_START_FIELD                  _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SSCP_START_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SSCP_START_RANGE                  31:16
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SSCP_START_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SSCP_START_DEFAULT                        _MK_MASK_CONST(0x200)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SSCP_START_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SSCP_START_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SSCP_START_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SSCP_START_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI2_CTRL_0_SSCP_START_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI2_LFSR0_0
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0                  _MK_ADDR_CONST(0x13f)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_SECURE                   0x0
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_DUAL                     0x0
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_SCR                      0
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_WORD_COUNT                       0x1
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_RESET_VAL                        _MK_MASK_CONST(0xfffeffff)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_LANE0_SEED_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_LANE0_SEED_FIELD                 _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_LANE0_SEED_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_LANE0_SEED_RANGE                 15:0
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_LANE0_SEED_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_LANE0_SEED_DEFAULT                       _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_LANE0_SEED_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_LANE0_SEED_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_LANE0_SEED_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_LANE0_SEED_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_LANE0_SEED_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_LANE1_SEED_SHIFT                 _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_LANE1_SEED_FIELD                 _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_LANE1_SEED_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_LANE1_SEED_RANGE                 31:16
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_LANE1_SEED_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_LANE1_SEED_DEFAULT                       _MK_MASK_CONST(0xfffe)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_LANE1_SEED_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_LANE1_SEED_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_LANE1_SEED_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_LANE1_SEED_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR0_0_LANE1_SEED_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDMI2_LFSR1_0
#define SOR_NV_PDISP_SOR_HDMI2_LFSR1_0                  _MK_ADDR_CONST(0x140)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR1_0_SECURE                   0x0
#define SOR_NV_PDISP_SOR_HDMI2_LFSR1_0_DUAL                     0x0
#define SOR_NV_PDISP_SOR_HDMI2_LFSR1_0_SCR                      0
#define SOR_NV_PDISP_SOR_HDMI2_LFSR1_0_WORD_COUNT                       0x1
#define SOR_NV_PDISP_SOR_HDMI2_LFSR1_0_RESET_VAL                        _MK_MASK_CONST(0xfffd)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR1_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR1_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR1_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR1_0_LANE2_SEED_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR1_0_LANE2_SEED_FIELD                 _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_HDMI2_LFSR1_0_LANE2_SEED_SHIFT)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR1_0_LANE2_SEED_RANGE                 15:0
#define SOR_NV_PDISP_SOR_HDMI2_LFSR1_0_LANE2_SEED_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDMI2_LFSR1_0_LANE2_SEED_DEFAULT                       _MK_MASK_CONST(0xfffd)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR1_0_LANE2_SEED_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR1_0_LANE2_SEED_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR1_0_LANE2_SEED_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR1_0_LANE2_SEED_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDMI2_LFSR1_0_LANE2_SEED_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDCP22_CTRL_0
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0                  _MK_ADDR_CONST(0x141)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_SECURE                   0x0
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_DUAL                     0x0
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_SCR                      0
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_WORD_COUNT                       0x1
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_RESET_VAL                        _MK_MASK_CONST(0x64)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_RESET_MASK                       _MK_MASK_CONST(0x77)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_READ_MASK                        _MK_MASK_CONST(0x77)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_WRITE_MASK                       _MK_MASK_CONST(0x77)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_CRYPT_SHIFT                      _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_CRYPT_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDCP22_CTRL_0_CRYPT_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_CRYPT_RANGE                      0:0
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_CRYPT_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_CRYPT_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_CRYPT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_CRYPT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_CRYPT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_CRYPT_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_CRYPT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_CRYPT_DISABLE                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_CRYPT_ENABLE                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_INIT_SHIFT                       _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_INIT_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDCP22_CTRL_0_INIT_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_INIT_RANGE                       1:1
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_INIT_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_INIT_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_INIT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_INIT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_INIT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_INIT_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_INIT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_INIT_DONE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_INIT_TRIGGER                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_LOCK_TYPE_SHIFT                  _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_LOCK_TYPE_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDCP22_CTRL_0_LOCK_TYPE_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_LOCK_TYPE_RANGE                  2:2
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_LOCK_TYPE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_LOCK_TYPE_DEFAULT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_LOCK_TYPE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_LOCK_TYPE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_LOCK_TYPE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_LOCK_TYPE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_LOCK_TYPE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_LOCK_TYPE_UNLOCKED                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_LOCK_TYPE_LOCKED                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_REPEATER_SHIFT                   _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_REPEATER_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDCP22_CTRL_0_REPEATER_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_REPEATER_RANGE                   4:4
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_REPEATER_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_REPEATER_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_REPEATER_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_REPEATER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_REPEATER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_REPEATER_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_REPEATER_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_REPEATER_YES                     _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_REPEATER_NO                      _MK_ENUM_CONST(0)

#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_DISABLE_DETACH_SHIFT                     _MK_SHIFT_CONST(5)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_DISABLE_DETACH_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDCP22_CTRL_0_DISABLE_DETACH_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_DISABLE_DETACH_RANGE                     5:5
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_DISABLE_DETACH_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_DISABLE_DETACH_DEFAULT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_DISABLE_DETACH_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_DISABLE_DETACH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_DISABLE_DETACH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_DISABLE_DETACH_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_DISABLE_DETACH_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_DISABLE_DETACH_YES                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_DISABLE_DETACH_NO                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_DISABLE_LANE_CNT0_SHIFT                  _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_DISABLE_LANE_CNT0_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDCP22_CTRL_0_DISABLE_LANE_CNT0_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_DISABLE_LANE_CNT0_RANGE                  6:6
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_DISABLE_LANE_CNT0_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_DISABLE_LANE_CNT0_DEFAULT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_DISABLE_LANE_CNT0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_DISABLE_LANE_CNT0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_DISABLE_LANE_CNT0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_DISABLE_LANE_CNT0_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_DISABLE_LANE_CNT0_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_DISABLE_LANE_CNT0_YES                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_CTRL_0_DISABLE_LANE_CNT0_NO                     _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_HDCP22_STATUS_0
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0                        _MK_ADDR_CONST(0x142)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_SECURE                         0x0
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_DUAL                   0x0
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_SCR                    0
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_WORD_COUNT                     0x1
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0xfff)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_READ_MASK                      _MK_MASK_CONST(0xfff)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_CRYPT_STATUS_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_CRYPT_STATUS_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDCP22_STATUS_0_CRYPT_STATUS_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_CRYPT_STATUS_RANGE                     0:0
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_CRYPT_STATUS_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_CRYPT_STATUS_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_CRYPT_STATUS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_CRYPT_STATUS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_CRYPT_STATUS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_CRYPT_STATUS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_CRYPT_STATUS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_CRYPT_STATUS_INACTIVE                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_CRYPT_STATUS_ACTIVE                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_BFM_SHIFT                      _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_BFM_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDCP22_STATUS_0_BFM_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_BFM_RANGE                      1:1
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_BFM_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_BFM_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_BFM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_BFM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_BFM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_BFM_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_BFM_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_BFM_INACTIVE                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_BFM_ACTIVE                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_FRAME_CNT_OVERFLOW_SHIFT                       _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_FRAME_CNT_OVERFLOW_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDCP22_STATUS_0_FRAME_CNT_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_FRAME_CNT_OVERFLOW_RANGE                       2:2
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_FRAME_CNT_OVERFLOW_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_FRAME_CNT_OVERFLOW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_FRAME_CNT_OVERFLOW_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_FRAME_CNT_OVERFLOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_FRAME_CNT_OVERFLOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_FRAME_CNT_OVERFLOW_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_FRAME_CNT_OVERFLOW_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_FRAME_CNT_OVERFLOW_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_FRAME_CNT_OVERFLOW_YES                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_DATA_CNT_OVERFLOW_SHIFT                        _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_DATA_CNT_OVERFLOW_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDCP22_STATUS_0_DATA_CNT_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_DATA_CNT_OVERFLOW_RANGE                        3:3
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_DATA_CNT_OVERFLOW_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_DATA_CNT_OVERFLOW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_DATA_CNT_OVERFLOW_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_DATA_CNT_OVERFLOW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_DATA_CNT_OVERFLOW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_DATA_CNT_OVERFLOW_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_DATA_CNT_OVERFLOW_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_DATA_CNT_OVERFLOW_NO                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_DATA_CNT_OVERFLOW_YES                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_DETACHED_DISABLE_SHIFT                 _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_DETACHED_DISABLE_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDCP22_STATUS_0_DETACHED_DISABLE_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_DETACHED_DISABLE_RANGE                 4:4
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_DETACHED_DISABLE_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_DETACHED_DISABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_DETACHED_DISABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_DETACHED_DISABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_DETACHED_DISABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_DETACHED_DISABLE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_DETACHED_DISABLE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_DETACHED_DISABLE_NO                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_DETACHED_DISABLE_YES                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_LANE_CNT0_DISABLE_SHIFT                        _MK_SHIFT_CONST(5)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_LANE_CNT0_DISABLE_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDCP22_STATUS_0_LANE_CNT0_DISABLE_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_LANE_CNT0_DISABLE_RANGE                        5:5
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_LANE_CNT0_DISABLE_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_LANE_CNT0_DISABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_LANE_CNT0_DISABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_LANE_CNT0_DISABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_LANE_CNT0_DISABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_LANE_CNT0_DISABLE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_LANE_CNT0_DISABLE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_LANE_CNT0_DISABLE_NO                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_LANE_CNT0_DISABLE_YES                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_LC128_ERROR_SHIFT                      _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_LC128_ERROR_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_HDCP22_STATUS_0_LC128_ERROR_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_LC128_ERROR_RANGE                      6:6
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_LC128_ERROR_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_LC128_ERROR_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_LC128_ERROR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_LC128_ERROR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_LC128_ERROR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_LC128_ERROR_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_LC128_ERROR_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_LC128_ERROR_NO                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_LC128_ERROR_YES                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_AUTODIS_STATE_SHIFT                    _MK_SHIFT_CONST(7)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_AUTODIS_STATE_FIELD                    _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_HDCP22_STATUS_0_AUTODIS_STATE_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_AUTODIS_STATE_RANGE                    8:7
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_AUTODIS_STATE_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_AUTODIS_STATE_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_AUTODIS_STATE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_AUTODIS_STATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_AUTODIS_STATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_AUTODIS_STATE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_AUTODIS_STATE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_AUTODIS_STATE_IDLE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_AUTODIS_STATE_ENCRYPTING                       _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_AUTODIS_STATE_DISABLE_LC_0                     _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_AUTODIS_STATE_DISABLE_DETACH                   _MK_ENUM_CONST(3)

#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_HDCP_STATE_SHIFT                       _MK_SHIFT_CONST(9)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_HDCP_STATE_FIELD                       _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_HDCP22_STATUS_0_HDCP_STATE_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_HDCP_STATE_RANGE                       11:9
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_HDCP_STATE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_HDCP_STATE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_HDCP_STATE_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_HDCP_STATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_HDCP_STATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_HDCP_STATE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_HDCP_STATE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_HDCP_STATE_IDLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_HDCP_STATE_WAIT_LC128                  _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_HDCP_STATE_WAIT_AES_READY                      _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_HDCP_STATE_HDCP22_ENABLE                       _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_HDCP_STATE_HDMI_ENCRYPT_ON                     _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_HDCP22_STATUS_0_HDCP_STATE_DP_ENCRYPT_ON                       _MK_ENUM_CONST(5)

// Register SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0                        _MK_ADDR_CONST(0x143)
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_SECURE                         0x0
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_DUAL                   0x0
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_SCR                    0
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_WORD_COUNT                     0x1
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_DATA_CNTR_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_DATA_CNTR_VALUE_FIELD                  _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_DATA_CNTR_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_DATA_CNTR_VALUE_RANGE                  15:0
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_DATA_CNTR_VALUE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_DATA_CNTR_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_DATA_CNTR_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_DATA_CNTR_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_DATA_CNTR_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_DATA_CNTR_VALUE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_DATA_CNTR_VALUE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_FRAME_CNTR_VALUE_SHIFT                 _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_FRAME_CNTR_VALUE_FIELD                 _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_FRAME_CNTR_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_FRAME_CNTR_VALUE_RANGE                 31:16
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_FRAME_CNTR_VALUE_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_FRAME_CNTR_VALUE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_FRAME_CNTR_VALUE_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_FRAME_CNTR_VALUE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_FRAME_CNTR_VALUE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_FRAME_CNTR_VALUE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0_FRAME_CNTR_VALUE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_MSB_0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_MSB_0                       _MK_ADDR_CONST(0x144)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_MSB_0_SECURE                        0x0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_MSB_0_DUAL                  0x0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_MSB_0_SCR                   0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_MSB_0_WORD_COUNT                    0x1
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_MSB_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_MSB_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_MSB_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_MSB_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_MSB_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_MSB_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_MSB_0_VALUE_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_MSB_0_VALUE_FIELD                   _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_MSB_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_MSB_0_VALUE_RANGE                   31:0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_MSB_0_VALUE_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_MSB_0_VALUE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_MSB_0_VALUE_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_MSB_0_VALUE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_MSB_0_VALUE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_MSB_0_VALUE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_MSB_0_VALUE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB1_0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB1_0                      _MK_ADDR_CONST(0x145)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB1_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB1_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB1_0_SCR                  0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB1_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB1_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB1_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB1_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB1_0_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB1_0_VALUE_FIELD                  _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB1_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB1_0_VALUE_RANGE                  31:0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB1_0_VALUE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB1_0_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB1_0_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB1_0_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB1_0_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB1_0_VALUE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB1_0_VALUE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB2_0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB2_0                      _MK_ADDR_CONST(0x146)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB2_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB2_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB2_0_SCR                  0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB2_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB2_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB2_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB2_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB2_0_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB2_0_VALUE_FIELD                  _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB2_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB2_0_VALUE_RANGE                  31:0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB2_0_VALUE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB2_0_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB2_0_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB2_0_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB2_0_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB2_0_VALUE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB2_0_VALUE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB3_0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB3_0                      _MK_ADDR_CONST(0x147)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB3_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB3_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB3_0_SCR                  0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB3_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB3_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB3_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB3_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB3_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB3_0_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB3_0_VALUE_FIELD                  _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB3_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB3_0_VALUE_RANGE                  31:0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB3_0_VALUE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB3_0_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB3_0_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB3_0_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB3_0_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB3_0_VALUE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB3_0_VALUE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_MSB_0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_MSB_0                      _MK_ADDR_CONST(0x148)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_MSB_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_MSB_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_MSB_0_SCR                  0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_MSB_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_MSB_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_MSB_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_MSB_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_MSB_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_MSB_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_MSB_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_MSB_0_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_MSB_0_VALUE_FIELD                  _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_MSB_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_MSB_0_VALUE_RANGE                  31:0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_MSB_0_VALUE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_MSB_0_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_MSB_0_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_MSB_0_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_MSB_0_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_MSB_0_VALUE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_MSB_0_VALUE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_LSB_0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_LSB_0                      _MK_ADDR_CONST(0x149)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_LSB_0_SECURE                       0x0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_LSB_0_DUAL                         0x0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_LSB_0_SCR                  0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_LSB_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_LSB_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_LSB_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_LSB_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_LSB_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_LSB_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_LSB_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_LSB_0_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_LSB_0_VALUE_FIELD                  _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_LSB_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_LSB_0_VALUE_RANGE                  31:0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_LSB_0_VALUE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_LSB_0_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_LSB_0_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_LSB_0_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_LSB_0_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_LSB_0_VALUE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_LSB_0_VALUE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDCP22_SST_DP_TYPE_0
#define SOR_NV_PDISP_SOR_HDCP22_SST_DP_TYPE_0                   _MK_ADDR_CONST(0x14a)
#define SOR_NV_PDISP_SOR_HDCP22_SST_DP_TYPE_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_HDCP22_SST_DP_TYPE_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_HDCP22_SST_DP_TYPE_0_SCR                       0
#define SOR_NV_PDISP_SOR_HDCP22_SST_DP_TYPE_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_HDCP22_SST_DP_TYPE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_SST_DP_TYPE_0_RESET_MASK                        _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDCP22_SST_DP_TYPE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_SST_DP_TYPE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_SST_DP_TYPE_0_READ_MASK                         _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDCP22_SST_DP_TYPE_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDCP22_SST_DP_TYPE_0_VALUE_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_SST_DP_TYPE_0_VALUE_FIELD                       _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_HDCP22_SST_DP_TYPE_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_SST_DP_TYPE_0_VALUE_RANGE                       7:0
#define SOR_NV_PDISP_SOR_HDCP22_SST_DP_TYPE_0_VALUE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_HDCP22_SST_DP_TYPE_0_VALUE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_SST_DP_TYPE_0_VALUE_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_HDCP22_SST_DP_TYPE_0_VALUE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_SST_DP_TYPE_0_VALUE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_SST_DP_TYPE_0_VALUE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_HDCP22_SST_DP_TYPE_0_VALUE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDCP22_LC128_MSB_0
#define SOR_NV_PDISP_SOR_HDCP22_LC128_MSB_0                     _MK_ADDR_CONST(0x14b)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_MSB_0_SECURE                      0x0
#define SOR_NV_PDISP_SOR_HDCP22_LC128_MSB_0_DUAL                        0x0
#define SOR_NV_PDISP_SOR_HDCP22_LC128_MSB_0_SCR                         0
#define SOR_NV_PDISP_SOR_HDCP22_LC128_MSB_0_WORD_COUNT                  0x1
#define SOR_NV_PDISP_SOR_HDCP22_LC128_MSB_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_MSB_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_MSB_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_MSB_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_MSB_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_MSB_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_MSB_0_VALUE_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_MSB_0_VALUE_FIELD                 _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_HDCP22_LC128_MSB_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_MSB_0_VALUE_RANGE                 31:0
#define SOR_NV_PDISP_SOR_HDCP22_LC128_MSB_0_VALUE_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_HDCP22_LC128_MSB_0_VALUE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_MSB_0_VALUE_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_MSB_0_VALUE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_MSB_0_VALUE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_MSB_0_VALUE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_MSB_0_VALUE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDCP22_LC128_LSB1_0
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB1_0                    _MK_ADDR_CONST(0x14c)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB1_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB1_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB1_0_SCR                        0
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB1_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB1_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB1_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB1_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB1_0_VALUE_SHIFT                        _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB1_0_VALUE_FIELD                        _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_HDCP22_LC128_LSB1_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB1_0_VALUE_RANGE                        31:0
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB1_0_VALUE_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB1_0_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB1_0_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB1_0_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB1_0_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB1_0_VALUE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB1_0_VALUE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDCP22_LC128_LSB2_0
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB2_0                    _MK_ADDR_CONST(0x14d)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB2_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB2_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB2_0_SCR                        0
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB2_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB2_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB2_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB2_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB2_0_VALUE_SHIFT                        _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB2_0_VALUE_FIELD                        _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_HDCP22_LC128_LSB2_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB2_0_VALUE_RANGE                        31:0
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB2_0_VALUE_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB2_0_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB2_0_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB2_0_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB2_0_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB2_0_VALUE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB2_0_VALUE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_HDCP22_LC128_LSB3_0
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB3_0                    _MK_ADDR_CONST(0x14e)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB3_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB3_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB3_0_SCR                        0
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB3_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB3_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB3_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB3_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB3_0_VALUE_SHIFT                        _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB3_0_VALUE_FIELD                        _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_HDCP22_LC128_LSB3_0_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB3_0_VALUE_RANGE                        31:0
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB3_0_VALUE_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB3_0_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB3_0_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB3_0_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB3_0_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB3_0_VALUE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_HDCP22_LC128_LSB3_0_VALUE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register SOR_CTXSW_NEXT_0
#define SOR_CTXSW_NEXT_0                        _MK_ADDR_CONST(0x14f)
#define SOR_CTXSW_NEXT_0_SECURE                         0x0
#define SOR_CTXSW_NEXT_0_DUAL                   0x0
#define SOR_CTXSW_NEXT_0_SCR                    0
#define SOR_CTXSW_NEXT_0_WORD_COUNT                     0x1
#define SOR_CTXSW_NEXT_0_RESET_VAL                      _MK_MASK_CONST(0xfc00)
#define SOR_CTXSW_NEXT_0_RESET_MASK                     _MK_MASK_CONST(0xfffff)
#define SOR_CTXSW_NEXT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_CTXSW_NEXT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_CTXSW_NEXT_0_READ_MASK                      _MK_MASK_CONST(0xfffff)
#define SOR_CTXSW_NEXT_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define SOR_CTXSW_NEXT_0_NEXT_CLASS_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_CTXSW_NEXT_0_NEXT_CLASS_FIELD                       _MK_FIELD_CONST(0x3ff, SOR_CTXSW_NEXT_0_NEXT_CLASS_SHIFT)
#define SOR_CTXSW_NEXT_0_NEXT_CLASS_RANGE                       9:0
#define SOR_CTXSW_NEXT_0_NEXT_CLASS_WOFFSET                     0x0
#define SOR_CTXSW_NEXT_0_NEXT_CLASS_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_CTXSW_NEXT_0_NEXT_CLASS_DEFAULT_MASK                        _MK_MASK_CONST(0x3ff)
#define SOR_CTXSW_NEXT_0_NEXT_CLASS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_CTXSW_NEXT_0_NEXT_CLASS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_CTXSW_NEXT_0_NEXT_CLASS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_CTXSW_NEXT_0_NEXT_CLASS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SOR_CTXSW_NEXT_0_NEXT_CHANNEL_SHIFT                     _MK_SHIFT_CONST(10)
#define SOR_CTXSW_NEXT_0_NEXT_CHANNEL_FIELD                     _MK_FIELD_CONST(0x3ff, SOR_CTXSW_NEXT_0_NEXT_CHANNEL_SHIFT)
#define SOR_CTXSW_NEXT_0_NEXT_CHANNEL_RANGE                     19:10
#define SOR_CTXSW_NEXT_0_NEXT_CHANNEL_WOFFSET                   0x0
#define SOR_CTXSW_NEXT_0_NEXT_CHANNEL_DEFAULT                   _MK_MASK_CONST(0x3f)
#define SOR_CTXSW_NEXT_0_NEXT_CHANNEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3ff)
#define SOR_CTXSW_NEXT_0_NEXT_CHANNEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_CTXSW_NEXT_0_NEXT_CHANNEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_CTXSW_NEXT_0_NEXT_CHANNEL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SOR_CTXSW_NEXT_0_NEXT_CHANNEL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register SOR_CTXSW_0
#define SOR_CTXSW_0                     _MK_ADDR_CONST(0x150)
#define SOR_CTXSW_0_SECURE                      0x0
#define SOR_CTXSW_0_DUAL                        0x0
#define SOR_CTXSW_0_SCR                         0
#define SOR_CTXSW_0_WORD_COUNT                  0x1
#define SOR_CTXSW_0_RESET_VAL                   _MK_MASK_CONST(0x1fc00)
#define SOR_CTXSW_0_RESET_MASK                  _MK_MASK_CONST(0x1fffff)
#define SOR_CTXSW_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SOR_CTXSW_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_CTXSW_0_READ_MASK                   _MK_MASK_CONST(0x1fffff)
#define SOR_CTXSW_0_WRITE_MASK                  _MK_MASK_CONST(0x1fffff)
#define SOR_CTXSW_0_CURR_CLASS_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_CTXSW_0_CURR_CLASS_FIELD                    _MK_FIELD_CONST(0x3ff, SOR_CTXSW_0_CURR_CLASS_SHIFT)
#define SOR_CTXSW_0_CURR_CLASS_RANGE                    9:0
#define SOR_CTXSW_0_CURR_CLASS_WOFFSET                  0x0
#define SOR_CTXSW_0_CURR_CLASS_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_CTXSW_0_CURR_CLASS_DEFAULT_MASK                     _MK_MASK_CONST(0x3ff)
#define SOR_CTXSW_0_CURR_CLASS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_CTXSW_0_CURR_CLASS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_CTXSW_0_CURR_CLASS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SOR_CTXSW_0_CURR_CLASS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_CTXSW_0_AUTO_ACK_SHIFT                      _MK_SHIFT_CONST(10)
#define SOR_CTXSW_0_AUTO_ACK_FIELD                      _MK_FIELD_CONST(0x1, SOR_CTXSW_0_AUTO_ACK_SHIFT)
#define SOR_CTXSW_0_AUTO_ACK_RANGE                      10:10
#define SOR_CTXSW_0_AUTO_ACK_WOFFSET                    0x0
#define SOR_CTXSW_0_AUTO_ACK_DEFAULT                    _MK_MASK_CONST(0x1)
#define SOR_CTXSW_0_AUTO_ACK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_CTXSW_0_AUTO_ACK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_CTXSW_0_AUTO_ACK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_CTXSW_0_AUTO_ACK_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SOR_CTXSW_0_AUTO_ACK_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_CTXSW_0_AUTO_ACK_MANUAL                     _MK_ENUM_CONST(0)
#define SOR_CTXSW_0_AUTO_ACK_AUTOACK                    _MK_ENUM_CONST(1)

#define SOR_CTXSW_0_CURR_CHANNEL_SHIFT                  _MK_SHIFT_CONST(11)
#define SOR_CTXSW_0_CURR_CHANNEL_FIELD                  _MK_FIELD_CONST(0x3ff, SOR_CTXSW_0_CURR_CHANNEL_SHIFT)
#define SOR_CTXSW_0_CURR_CHANNEL_RANGE                  20:11
#define SOR_CTXSW_0_CURR_CHANNEL_WOFFSET                        0x0
#define SOR_CTXSW_0_CURR_CHANNEL_DEFAULT                        _MK_MASK_CONST(0x3f)
#define SOR_CTXSW_0_CURR_CHANNEL_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
#define SOR_CTXSW_0_CURR_CHANNEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_CTXSW_0_CURR_CHANNEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_CTXSW_0_CURR_CHANNEL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SOR_CTXSW_0_CURR_CHANNEL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_HEAD_STATE0_0
#define SOR_NV_PDISP_HEAD_STATE0_0                      _MK_ADDR_CONST(0x151)
#define SOR_NV_PDISP_HEAD_STATE0_0_SECURE                       0x0
#define SOR_NV_PDISP_HEAD_STATE0_0_DUAL                         0x0
#define SOR_NV_PDISP_HEAD_STATE0_0_SCR                  0
#define SOR_NV_PDISP_HEAD_STATE0_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_HEAD_STATE0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_0_RESET_MASK                   _MK_MASK_CONST(0x3f)
#define SOR_NV_PDISP_HEAD_STATE0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_0_READ_MASK                    _MK_MASK_CONST(0x3f)
#define SOR_NV_PDISP_HEAD_STATE0_0_WRITE_MASK                   _MK_MASK_CONST(0x3f)
#define SOR_NV_PDISP_HEAD_STATE0_0_INTERLACED_SHIFT                     _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_HEAD_STATE0_0_INTERLACED_FIELD                     _MK_FIELD_CONST(0x3, SOR_NV_PDISP_HEAD_STATE0_0_INTERLACED_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE0_0_INTERLACED_RANGE                     5:4
#define SOR_NV_PDISP_HEAD_STATE0_0_INTERLACED_WOFFSET                   0x0
#define SOR_NV_PDISP_HEAD_STATE0_0_INTERLACED_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_0_INTERLACED_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_HEAD_STATE0_0_INTERLACED_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_0_INTERLACED_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_0_INTERLACED_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_0_INTERLACED_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_0_INTERLACED_INIT_ENUM                 PROGRESSIVE
#define SOR_NV_PDISP_HEAD_STATE0_0_INTERLACED_PROGRESSIVE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE0_0_INTERLACED_INTERLACED                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_HEAD_STATE0_0_RANGECOMPRESS_SHIFT                  _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_HEAD_STATE0_0_RANGECOMPRESS_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_HEAD_STATE0_0_RANGECOMPRESS_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE0_0_RANGECOMPRESS_RANGE                  3:3
#define SOR_NV_PDISP_HEAD_STATE0_0_RANGECOMPRESS_WOFFSET                        0x0
#define SOR_NV_PDISP_HEAD_STATE0_0_RANGECOMPRESS_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_0_RANGECOMPRESS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_0_RANGECOMPRESS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_0_RANGECOMPRESS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_0_RANGECOMPRESS_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_0_RANGECOMPRESS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_0_RANGECOMPRESS_INIT_ENUM                      DISABLE
#define SOR_NV_PDISP_HEAD_STATE0_0_RANGECOMPRESS_DISABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE0_0_RANGECOMPRESS_ENABLE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_HEAD_STATE0_0_DYNRANGE_SHIFT                       _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_HEAD_STATE0_0_DYNRANGE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_HEAD_STATE0_0_DYNRANGE_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE0_0_DYNRANGE_RANGE                       2:2
#define SOR_NV_PDISP_HEAD_STATE0_0_DYNRANGE_WOFFSET                     0x0
#define SOR_NV_PDISP_HEAD_STATE0_0_DYNRANGE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_0_DYNRANGE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_0_DYNRANGE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_0_DYNRANGE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_0_DYNRANGE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_0_DYNRANGE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_0_DYNRANGE_INIT_ENUM                   VESA
#define SOR_NV_PDISP_HEAD_STATE0_0_DYNRANGE_VESA                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE0_0_DYNRANGE_CEA                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_FIELD                     _MK_FIELD_CONST(0x3, SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_RANGE                     1:0
#define SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_WOFFSET                   0x0
#define SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_INIT_ENUM                 RGB
#define SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_RGB                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_YUV_601                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_YUV_709                   _MK_ENUM_CONST(2)

// Register SOR_NV_PDISP_HEAD_STATE0
#define SOR_NV_PDISP_HEAD_STATE0                        _MK_ADDR_CONST(0x151)
#define SOR_NV_PDISP_HEAD_STATE0_SECURE                         0x0
#define SOR_NV_PDISP_HEAD_STATE0_DUAL                   0x0
#define SOR_NV_PDISP_HEAD_STATE0_SCR                    0
#define SOR_NV_PDISP_HEAD_STATE0_WORD_COUNT                     0x1
#define SOR_NV_PDISP_HEAD_STATE0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_RESET_MASK                     _MK_MASK_CONST(0x3f)
#define SOR_NV_PDISP_HEAD_STATE0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_READ_MASK                      _MK_MASK_CONST(0x3f)
#define SOR_NV_PDISP_HEAD_STATE0_WRITE_MASK                     _MK_MASK_CONST(0x3f)
#define SOR_NV_PDISP_HEAD_STATE0_INTERLACED_SHIFT                       _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_HEAD_STATE0_INTERLACED_FIELD                       _MK_FIELD_CONST(0x3, SOR_NV_PDISP_HEAD_STATE0_INTERLACED_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE0_INTERLACED_RANGE                       5:4
#define SOR_NV_PDISP_HEAD_STATE0_INTERLACED_WOFFSET                     0x0
#define SOR_NV_PDISP_HEAD_STATE0_INTERLACED_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_INTERLACED_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_HEAD_STATE0_INTERLACED_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_INTERLACED_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_INTERLACED_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_INTERLACED_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_INTERLACED_INIT_ENUM                   PROGRESSIVE
#define SOR_NV_PDISP_HEAD_STATE0_INTERLACED_PROGRESSIVE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE0_INTERLACED_INTERLACED                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_HEAD_STATE0_RANGECOMPRESS_SHIFT                    _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_HEAD_STATE0_RANGECOMPRESS_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_HEAD_STATE0_RANGECOMPRESS_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE0_RANGECOMPRESS_RANGE                    3:3
#define SOR_NV_PDISP_HEAD_STATE0_RANGECOMPRESS_WOFFSET                  0x0
#define SOR_NV_PDISP_HEAD_STATE0_RANGECOMPRESS_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_RANGECOMPRESS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_RANGECOMPRESS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_RANGECOMPRESS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_RANGECOMPRESS_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_RANGECOMPRESS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_RANGECOMPRESS_INIT_ENUM                        DISABLE
#define SOR_NV_PDISP_HEAD_STATE0_RANGECOMPRESS_DISABLE                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE0_RANGECOMPRESS_ENABLE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_HEAD_STATE0_DYNRANGE_SHIFT                 _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_HEAD_STATE0_DYNRANGE_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_HEAD_STATE0_DYNRANGE_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE0_DYNRANGE_RANGE                 2:2
#define SOR_NV_PDISP_HEAD_STATE0_DYNRANGE_WOFFSET                       0x0
#define SOR_NV_PDISP_HEAD_STATE0_DYNRANGE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_DYNRANGE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_DYNRANGE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_DYNRANGE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_DYNRANGE_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_DYNRANGE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_DYNRANGE_INIT_ENUM                     VESA
#define SOR_NV_PDISP_HEAD_STATE0_DYNRANGE_VESA                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE0_DYNRANGE_CEA                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_FIELD                       _MK_FIELD_CONST(0x3, SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_RANGE                       1:0
#define SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_WOFFSET                     0x0
#define SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_INIT_ENUM                   RGB
#define SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_RGB                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_YUV_601                     _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_YUV_709                     _MK_ENUM_CONST(2)

// Register SOR_NV_PDISP_HEAD_STATE0_1
#define SOR_NV_PDISP_HEAD_STATE0_1                      _MK_ADDR_CONST(0x152)
#define SOR_NV_PDISP_HEAD_STATE0_1_SECURE                       0x0
#define SOR_NV_PDISP_HEAD_STATE0_1_DUAL                         0x0
#define SOR_NV_PDISP_HEAD_STATE0_1_SCR                  0
#define SOR_NV_PDISP_HEAD_STATE0_1_WORD_COUNT                   0x1
#define SOR_NV_PDISP_HEAD_STATE0_1_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_1_RESET_MASK                   _MK_MASK_CONST(0x3f)
#define SOR_NV_PDISP_HEAD_STATE0_1_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_1_READ_MASK                    _MK_MASK_CONST(0x3f)
#define SOR_NV_PDISP_HEAD_STATE0_1_WRITE_MASK                   _MK_MASK_CONST(0x3f)
#define SOR_NV_PDISP_HEAD_STATE0_1_INTERLACED_SHIFT                     _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_HEAD_STATE0_1_INTERLACED_FIELD                     _MK_FIELD_CONST(0x3, SOR_NV_PDISP_HEAD_STATE0_1_INTERLACED_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE0_1_INTERLACED_RANGE                     5:4
#define SOR_NV_PDISP_HEAD_STATE0_1_INTERLACED_WOFFSET                   0x0
#define SOR_NV_PDISP_HEAD_STATE0_1_INTERLACED_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_1_INTERLACED_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_HEAD_STATE0_1_INTERLACED_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_1_INTERLACED_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_1_INTERLACED_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_1_INTERLACED_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_1_INTERLACED_INIT_ENUM                 PROGRESSIVE
#define SOR_NV_PDISP_HEAD_STATE0_1_INTERLACED_PROGRESSIVE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE0_1_INTERLACED_INTERLACED                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_HEAD_STATE0_1_RANGECOMPRESS_SHIFT                  _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_HEAD_STATE0_1_RANGECOMPRESS_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_HEAD_STATE0_1_RANGECOMPRESS_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE0_1_RANGECOMPRESS_RANGE                  3:3
#define SOR_NV_PDISP_HEAD_STATE0_1_RANGECOMPRESS_WOFFSET                        0x0
#define SOR_NV_PDISP_HEAD_STATE0_1_RANGECOMPRESS_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_1_RANGECOMPRESS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_1_RANGECOMPRESS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_1_RANGECOMPRESS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_1_RANGECOMPRESS_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_1_RANGECOMPRESS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_1_RANGECOMPRESS_INIT_ENUM                      DISABLE
#define SOR_NV_PDISP_HEAD_STATE0_1_RANGECOMPRESS_DISABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE0_1_RANGECOMPRESS_ENABLE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_HEAD_STATE0_1_DYNRANGE_SHIFT                       _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_HEAD_STATE0_1_DYNRANGE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_HEAD_STATE0_1_DYNRANGE_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE0_1_DYNRANGE_RANGE                       2:2
#define SOR_NV_PDISP_HEAD_STATE0_1_DYNRANGE_WOFFSET                     0x0
#define SOR_NV_PDISP_HEAD_STATE0_1_DYNRANGE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_1_DYNRANGE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_1_DYNRANGE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_1_DYNRANGE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_1_DYNRANGE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_1_DYNRANGE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_1_DYNRANGE_INIT_ENUM                   VESA
#define SOR_NV_PDISP_HEAD_STATE0_1_DYNRANGE_VESA                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE0_1_DYNRANGE_CEA                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_FIELD                     _MK_FIELD_CONST(0x3, SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_RANGE                     1:0
#define SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_WOFFSET                   0x0
#define SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_INIT_ENUM                 RGB
#define SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_RGB                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_YUV_601                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_YUV_709                   _MK_ENUM_CONST(2)

// Register SOR_NV_PDISP_HEAD_STATE0_2
#define SOR_NV_PDISP_HEAD_STATE0_2                      _MK_ADDR_CONST(0x153)
#define SOR_NV_PDISP_HEAD_STATE0_2_SECURE                       0x0
#define SOR_NV_PDISP_HEAD_STATE0_2_DUAL                         0x0
#define SOR_NV_PDISP_HEAD_STATE0_2_SCR                  0
#define SOR_NV_PDISP_HEAD_STATE0_2_WORD_COUNT                   0x1
#define SOR_NV_PDISP_HEAD_STATE0_2_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_2_RESET_MASK                   _MK_MASK_CONST(0x3f)
#define SOR_NV_PDISP_HEAD_STATE0_2_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_2_READ_MASK                    _MK_MASK_CONST(0x3f)
#define SOR_NV_PDISP_HEAD_STATE0_2_WRITE_MASK                   _MK_MASK_CONST(0x3f)
#define SOR_NV_PDISP_HEAD_STATE0_2_INTERLACED_SHIFT                     _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_HEAD_STATE0_2_INTERLACED_FIELD                     _MK_FIELD_CONST(0x3, SOR_NV_PDISP_HEAD_STATE0_2_INTERLACED_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE0_2_INTERLACED_RANGE                     5:4
#define SOR_NV_PDISP_HEAD_STATE0_2_INTERLACED_WOFFSET                   0x0
#define SOR_NV_PDISP_HEAD_STATE0_2_INTERLACED_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_2_INTERLACED_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_HEAD_STATE0_2_INTERLACED_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_2_INTERLACED_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_2_INTERLACED_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_2_INTERLACED_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_2_INTERLACED_INIT_ENUM                 PROGRESSIVE
#define SOR_NV_PDISP_HEAD_STATE0_2_INTERLACED_PROGRESSIVE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE0_2_INTERLACED_INTERLACED                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_HEAD_STATE0_2_RANGECOMPRESS_SHIFT                  _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_HEAD_STATE0_2_RANGECOMPRESS_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_HEAD_STATE0_2_RANGECOMPRESS_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE0_2_RANGECOMPRESS_RANGE                  3:3
#define SOR_NV_PDISP_HEAD_STATE0_2_RANGECOMPRESS_WOFFSET                        0x0
#define SOR_NV_PDISP_HEAD_STATE0_2_RANGECOMPRESS_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_2_RANGECOMPRESS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_2_RANGECOMPRESS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_2_RANGECOMPRESS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_2_RANGECOMPRESS_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_2_RANGECOMPRESS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_2_RANGECOMPRESS_INIT_ENUM                      DISABLE
#define SOR_NV_PDISP_HEAD_STATE0_2_RANGECOMPRESS_DISABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE0_2_RANGECOMPRESS_ENABLE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_HEAD_STATE0_2_DYNRANGE_SHIFT                       _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_HEAD_STATE0_2_DYNRANGE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_HEAD_STATE0_2_DYNRANGE_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE0_2_DYNRANGE_RANGE                       2:2
#define SOR_NV_PDISP_HEAD_STATE0_2_DYNRANGE_WOFFSET                     0x0
#define SOR_NV_PDISP_HEAD_STATE0_2_DYNRANGE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_2_DYNRANGE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_2_DYNRANGE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_2_DYNRANGE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_2_DYNRANGE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_2_DYNRANGE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_2_DYNRANGE_INIT_ENUM                   VESA
#define SOR_NV_PDISP_HEAD_STATE0_2_DYNRANGE_VESA                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE0_2_DYNRANGE_CEA                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_HEAD_STATE0_2_COLORSPACE_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE0_2_COLORSPACE_FIELD                     _MK_FIELD_CONST(0x3, SOR_NV_PDISP_HEAD_STATE0_2_COLORSPACE_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE0_2_COLORSPACE_RANGE                     1:0
#define SOR_NV_PDISP_HEAD_STATE0_2_COLORSPACE_WOFFSET                   0x0
#define SOR_NV_PDISP_HEAD_STATE0_2_COLORSPACE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_2_COLORSPACE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_HEAD_STATE0_2_COLORSPACE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_2_COLORSPACE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_2_COLORSPACE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_2_COLORSPACE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_2_COLORSPACE_INIT_ENUM                 RGB
#define SOR_NV_PDISP_HEAD_STATE0_2_COLORSPACE_RGB                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE0_2_COLORSPACE_YUV_601                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_HEAD_STATE0_2_COLORSPACE_YUV_709                   _MK_ENUM_CONST(2)

// Register SOR_NV_PDISP_HEAD_STATE0_3
#define SOR_NV_PDISP_HEAD_STATE0_3                      _MK_ADDR_CONST(0x154)
#define SOR_NV_PDISP_HEAD_STATE0_3_SECURE                       0x0
#define SOR_NV_PDISP_HEAD_STATE0_3_DUAL                         0x0
#define SOR_NV_PDISP_HEAD_STATE0_3_SCR                  0
#define SOR_NV_PDISP_HEAD_STATE0_3_WORD_COUNT                   0x1
#define SOR_NV_PDISP_HEAD_STATE0_3_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_3_RESET_MASK                   _MK_MASK_CONST(0x3f)
#define SOR_NV_PDISP_HEAD_STATE0_3_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_3_READ_MASK                    _MK_MASK_CONST(0x3f)
#define SOR_NV_PDISP_HEAD_STATE0_3_WRITE_MASK                   _MK_MASK_CONST(0x3f)
#define SOR_NV_PDISP_HEAD_STATE0_3_INTERLACED_SHIFT                     _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_HEAD_STATE0_3_INTERLACED_FIELD                     _MK_FIELD_CONST(0x3, SOR_NV_PDISP_HEAD_STATE0_3_INTERLACED_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE0_3_INTERLACED_RANGE                     5:4
#define SOR_NV_PDISP_HEAD_STATE0_3_INTERLACED_WOFFSET                   0x0
#define SOR_NV_PDISP_HEAD_STATE0_3_INTERLACED_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_3_INTERLACED_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_HEAD_STATE0_3_INTERLACED_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_3_INTERLACED_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_3_INTERLACED_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_3_INTERLACED_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_3_INTERLACED_INIT_ENUM                 PROGRESSIVE
#define SOR_NV_PDISP_HEAD_STATE0_3_INTERLACED_PROGRESSIVE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE0_3_INTERLACED_INTERLACED                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_HEAD_STATE0_3_RANGECOMPRESS_SHIFT                  _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_HEAD_STATE0_3_RANGECOMPRESS_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_HEAD_STATE0_3_RANGECOMPRESS_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE0_3_RANGECOMPRESS_RANGE                  3:3
#define SOR_NV_PDISP_HEAD_STATE0_3_RANGECOMPRESS_WOFFSET                        0x0
#define SOR_NV_PDISP_HEAD_STATE0_3_RANGECOMPRESS_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_3_RANGECOMPRESS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_3_RANGECOMPRESS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_3_RANGECOMPRESS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_3_RANGECOMPRESS_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_3_RANGECOMPRESS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_3_RANGECOMPRESS_INIT_ENUM                      DISABLE
#define SOR_NV_PDISP_HEAD_STATE0_3_RANGECOMPRESS_DISABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE0_3_RANGECOMPRESS_ENABLE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_HEAD_STATE0_3_DYNRANGE_SHIFT                       _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_HEAD_STATE0_3_DYNRANGE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_HEAD_STATE0_3_DYNRANGE_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE0_3_DYNRANGE_RANGE                       2:2
#define SOR_NV_PDISP_HEAD_STATE0_3_DYNRANGE_WOFFSET                     0x0
#define SOR_NV_PDISP_HEAD_STATE0_3_DYNRANGE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_3_DYNRANGE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_3_DYNRANGE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_3_DYNRANGE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_3_DYNRANGE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_3_DYNRANGE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_3_DYNRANGE_INIT_ENUM                   VESA
#define SOR_NV_PDISP_HEAD_STATE0_3_DYNRANGE_VESA                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE0_3_DYNRANGE_CEA                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_HEAD_STATE0_3_COLORSPACE_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE0_3_COLORSPACE_FIELD                     _MK_FIELD_CONST(0x3, SOR_NV_PDISP_HEAD_STATE0_3_COLORSPACE_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE0_3_COLORSPACE_RANGE                     1:0
#define SOR_NV_PDISP_HEAD_STATE0_3_COLORSPACE_WOFFSET                   0x0
#define SOR_NV_PDISP_HEAD_STATE0_3_COLORSPACE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_3_COLORSPACE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_HEAD_STATE0_3_COLORSPACE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_3_COLORSPACE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE0_3_COLORSPACE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_3_COLORSPACE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE0_3_COLORSPACE_INIT_ENUM                 RGB
#define SOR_NV_PDISP_HEAD_STATE0_3_COLORSPACE_RGB                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE0_3_COLORSPACE_YUV_601                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_HEAD_STATE0_3_COLORSPACE_YUV_709                   _MK_ENUM_CONST(2)

// Register SOR_NV_PDISP_HEAD_STATE1_0
#define SOR_NV_PDISP_HEAD_STATE1_0                      _MK_ADDR_CONST(0x155)
#define SOR_NV_PDISP_HEAD_STATE1_0_SECURE                       0x0
#define SOR_NV_PDISP_HEAD_STATE1_0_DUAL                         0x0
#define SOR_NV_PDISP_HEAD_STATE1_0_SCR                  0
#define SOR_NV_PDISP_HEAD_STATE1_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_HEAD_STATE1_0_RESET_VAL                    _MK_MASK_CONST(0x1011000)
#define SOR_NV_PDISP_HEAD_STATE1_0_RESET_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_0_READ_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE1_0_WRITE_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE1_0_VTOTAL_SHIFT                 _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_HEAD_STATE1_0_VTOTAL_FIELD                 _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE1_0_VTOTAL_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE1_0_VTOTAL_RANGE                 30:16
#define SOR_NV_PDISP_HEAD_STATE1_0_VTOTAL_WOFFSET                       0x0
#define SOR_NV_PDISP_HEAD_STATE1_0_VTOTAL_DEFAULT                       _MK_MASK_CONST(0x101)
#define SOR_NV_PDISP_HEAD_STATE1_0_VTOTAL_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE1_0_VTOTAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_0_VTOTAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_0_VTOTAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE1_0_VTOTAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HEAD_STATE1_0_HTOTAL_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE1_0_HTOTAL_FIELD                 _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE1_0_HTOTAL_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE1_0_HTOTAL_RANGE                 14:0
#define SOR_NV_PDISP_HEAD_STATE1_0_HTOTAL_WOFFSET                       0x0
#define SOR_NV_PDISP_HEAD_STATE1_0_HTOTAL_DEFAULT                       _MK_MASK_CONST(0x1000)
#define SOR_NV_PDISP_HEAD_STATE1_0_HTOTAL_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE1_0_HTOTAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_0_HTOTAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_0_HTOTAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE1_0_HTOTAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_HEAD_STATE1
#define SOR_NV_PDISP_HEAD_STATE1                        _MK_ADDR_CONST(0x155)
#define SOR_NV_PDISP_HEAD_STATE1_SECURE                         0x0
#define SOR_NV_PDISP_HEAD_STATE1_DUAL                   0x0
#define SOR_NV_PDISP_HEAD_STATE1_SCR                    0
#define SOR_NV_PDISP_HEAD_STATE1_WORD_COUNT                     0x1
#define SOR_NV_PDISP_HEAD_STATE1_RESET_VAL                      _MK_MASK_CONST(0x1011000)
#define SOR_NV_PDISP_HEAD_STATE1_RESET_MASK                     _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE1_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_READ_MASK                      _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE1_WRITE_MASK                     _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE1_VTOTAL_SHIFT                   _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_HEAD_STATE1_VTOTAL_FIELD                   _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE1_VTOTAL_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE1_VTOTAL_RANGE                   30:16
#define SOR_NV_PDISP_HEAD_STATE1_VTOTAL_WOFFSET                 0x0
#define SOR_NV_PDISP_HEAD_STATE1_VTOTAL_DEFAULT                 _MK_MASK_CONST(0x101)
#define SOR_NV_PDISP_HEAD_STATE1_VTOTAL_DEFAULT_MASK                    _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE1_VTOTAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_VTOTAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_VTOTAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE1_VTOTAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HEAD_STATE1_HTOTAL_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE1_HTOTAL_FIELD                   _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE1_HTOTAL_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE1_HTOTAL_RANGE                   14:0
#define SOR_NV_PDISP_HEAD_STATE1_HTOTAL_WOFFSET                 0x0
#define SOR_NV_PDISP_HEAD_STATE1_HTOTAL_DEFAULT                 _MK_MASK_CONST(0x1000)
#define SOR_NV_PDISP_HEAD_STATE1_HTOTAL_DEFAULT_MASK                    _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE1_HTOTAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_HTOTAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_HTOTAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE1_HTOTAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_HEAD_STATE1_1
#define SOR_NV_PDISP_HEAD_STATE1_1                      _MK_ADDR_CONST(0x156)
#define SOR_NV_PDISP_HEAD_STATE1_1_SECURE                       0x0
#define SOR_NV_PDISP_HEAD_STATE1_1_DUAL                         0x0
#define SOR_NV_PDISP_HEAD_STATE1_1_SCR                  0
#define SOR_NV_PDISP_HEAD_STATE1_1_WORD_COUNT                   0x1
#define SOR_NV_PDISP_HEAD_STATE1_1_RESET_VAL                    _MK_MASK_CONST(0x1011000)
#define SOR_NV_PDISP_HEAD_STATE1_1_RESET_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE1_1_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_1_READ_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE1_1_WRITE_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE1_1_VTOTAL_SHIFT                 _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_HEAD_STATE1_1_VTOTAL_FIELD                 _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE1_1_VTOTAL_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE1_1_VTOTAL_RANGE                 30:16
#define SOR_NV_PDISP_HEAD_STATE1_1_VTOTAL_WOFFSET                       0x0
#define SOR_NV_PDISP_HEAD_STATE1_1_VTOTAL_DEFAULT                       _MK_MASK_CONST(0x101)
#define SOR_NV_PDISP_HEAD_STATE1_1_VTOTAL_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE1_1_VTOTAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_1_VTOTAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_1_VTOTAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE1_1_VTOTAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HEAD_STATE1_1_HTOTAL_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE1_1_HTOTAL_FIELD                 _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE1_1_HTOTAL_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE1_1_HTOTAL_RANGE                 14:0
#define SOR_NV_PDISP_HEAD_STATE1_1_HTOTAL_WOFFSET                       0x0
#define SOR_NV_PDISP_HEAD_STATE1_1_HTOTAL_DEFAULT                       _MK_MASK_CONST(0x1000)
#define SOR_NV_PDISP_HEAD_STATE1_1_HTOTAL_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE1_1_HTOTAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_1_HTOTAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_1_HTOTAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE1_1_HTOTAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_HEAD_STATE1_2
#define SOR_NV_PDISP_HEAD_STATE1_2                      _MK_ADDR_CONST(0x157)
#define SOR_NV_PDISP_HEAD_STATE1_2_SECURE                       0x0
#define SOR_NV_PDISP_HEAD_STATE1_2_DUAL                         0x0
#define SOR_NV_PDISP_HEAD_STATE1_2_SCR                  0
#define SOR_NV_PDISP_HEAD_STATE1_2_WORD_COUNT                   0x1
#define SOR_NV_PDISP_HEAD_STATE1_2_RESET_VAL                    _MK_MASK_CONST(0x1011000)
#define SOR_NV_PDISP_HEAD_STATE1_2_RESET_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE1_2_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_2_READ_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE1_2_WRITE_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE1_2_VTOTAL_SHIFT                 _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_HEAD_STATE1_2_VTOTAL_FIELD                 _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE1_2_VTOTAL_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE1_2_VTOTAL_RANGE                 30:16
#define SOR_NV_PDISP_HEAD_STATE1_2_VTOTAL_WOFFSET                       0x0
#define SOR_NV_PDISP_HEAD_STATE1_2_VTOTAL_DEFAULT                       _MK_MASK_CONST(0x101)
#define SOR_NV_PDISP_HEAD_STATE1_2_VTOTAL_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE1_2_VTOTAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_2_VTOTAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_2_VTOTAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE1_2_VTOTAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HEAD_STATE1_2_HTOTAL_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE1_2_HTOTAL_FIELD                 _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE1_2_HTOTAL_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE1_2_HTOTAL_RANGE                 14:0
#define SOR_NV_PDISP_HEAD_STATE1_2_HTOTAL_WOFFSET                       0x0
#define SOR_NV_PDISP_HEAD_STATE1_2_HTOTAL_DEFAULT                       _MK_MASK_CONST(0x1000)
#define SOR_NV_PDISP_HEAD_STATE1_2_HTOTAL_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE1_2_HTOTAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_2_HTOTAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_2_HTOTAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE1_2_HTOTAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_HEAD_STATE1_3
#define SOR_NV_PDISP_HEAD_STATE1_3                      _MK_ADDR_CONST(0x158)
#define SOR_NV_PDISP_HEAD_STATE1_3_SECURE                       0x0
#define SOR_NV_PDISP_HEAD_STATE1_3_DUAL                         0x0
#define SOR_NV_PDISP_HEAD_STATE1_3_SCR                  0
#define SOR_NV_PDISP_HEAD_STATE1_3_WORD_COUNT                   0x1
#define SOR_NV_PDISP_HEAD_STATE1_3_RESET_VAL                    _MK_MASK_CONST(0x1011000)
#define SOR_NV_PDISP_HEAD_STATE1_3_RESET_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE1_3_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_3_READ_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE1_3_WRITE_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE1_3_VTOTAL_SHIFT                 _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_HEAD_STATE1_3_VTOTAL_FIELD                 _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE1_3_VTOTAL_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE1_3_VTOTAL_RANGE                 30:16
#define SOR_NV_PDISP_HEAD_STATE1_3_VTOTAL_WOFFSET                       0x0
#define SOR_NV_PDISP_HEAD_STATE1_3_VTOTAL_DEFAULT                       _MK_MASK_CONST(0x101)
#define SOR_NV_PDISP_HEAD_STATE1_3_VTOTAL_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE1_3_VTOTAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_3_VTOTAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_3_VTOTAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE1_3_VTOTAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HEAD_STATE1_3_HTOTAL_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE1_3_HTOTAL_FIELD                 _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE1_3_HTOTAL_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE1_3_HTOTAL_RANGE                 14:0
#define SOR_NV_PDISP_HEAD_STATE1_3_HTOTAL_WOFFSET                       0x0
#define SOR_NV_PDISP_HEAD_STATE1_3_HTOTAL_DEFAULT                       _MK_MASK_CONST(0x1000)
#define SOR_NV_PDISP_HEAD_STATE1_3_HTOTAL_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE1_3_HTOTAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_3_HTOTAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE1_3_HTOTAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE1_3_HTOTAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_HEAD_STATE2_0
#define SOR_NV_PDISP_HEAD_STATE2_0                      _MK_ADDR_CONST(0x159)
#define SOR_NV_PDISP_HEAD_STATE2_0_SECURE                       0x0
#define SOR_NV_PDISP_HEAD_STATE2_0_DUAL                         0x0
#define SOR_NV_PDISP_HEAD_STATE2_0_SCR                  0
#define SOR_NV_PDISP_HEAD_STATE2_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_HEAD_STATE2_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE2_0_RESET_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_0_READ_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE2_0_WRITE_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE2_0_VSYNC_END_SHIFT                      _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_HEAD_STATE2_0_VSYNC_END_FIELD                      _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE2_0_VSYNC_END_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE2_0_VSYNC_END_RANGE                      30:16
#define SOR_NV_PDISP_HEAD_STATE2_0_VSYNC_END_WOFFSET                    0x0
#define SOR_NV_PDISP_HEAD_STATE2_0_VSYNC_END_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_0_VSYNC_END_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE2_0_VSYNC_END_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_0_VSYNC_END_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_0_VSYNC_END_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE2_0_VSYNC_END_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HEAD_STATE2_0_HSYNC_END_SHIFT                      _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE2_0_HSYNC_END_FIELD                      _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE2_0_HSYNC_END_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE2_0_HSYNC_END_RANGE                      14:0
#define SOR_NV_PDISP_HEAD_STATE2_0_HSYNC_END_WOFFSET                    0x0
#define SOR_NV_PDISP_HEAD_STATE2_0_HSYNC_END_DEFAULT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE2_0_HSYNC_END_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE2_0_HSYNC_END_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_0_HSYNC_END_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_0_HSYNC_END_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE2_0_HSYNC_END_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_HEAD_STATE2
#define SOR_NV_PDISP_HEAD_STATE2                        _MK_ADDR_CONST(0x159)
#define SOR_NV_PDISP_HEAD_STATE2_SECURE                         0x0
#define SOR_NV_PDISP_HEAD_STATE2_DUAL                   0x0
#define SOR_NV_PDISP_HEAD_STATE2_SCR                    0
#define SOR_NV_PDISP_HEAD_STATE2_WORD_COUNT                     0x1
#define SOR_NV_PDISP_HEAD_STATE2_RESET_VAL                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE2_RESET_MASK                     _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE2_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_READ_MASK                      _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE2_WRITE_MASK                     _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE2_VSYNC_END_SHIFT                        _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_HEAD_STATE2_VSYNC_END_FIELD                        _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE2_VSYNC_END_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE2_VSYNC_END_RANGE                        30:16
#define SOR_NV_PDISP_HEAD_STATE2_VSYNC_END_WOFFSET                      0x0
#define SOR_NV_PDISP_HEAD_STATE2_VSYNC_END_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_VSYNC_END_DEFAULT_MASK                 _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE2_VSYNC_END_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_VSYNC_END_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_VSYNC_END_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE2_VSYNC_END_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HEAD_STATE2_HSYNC_END_SHIFT                        _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE2_HSYNC_END_FIELD                        _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE2_HSYNC_END_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE2_HSYNC_END_RANGE                        14:0
#define SOR_NV_PDISP_HEAD_STATE2_HSYNC_END_WOFFSET                      0x0
#define SOR_NV_PDISP_HEAD_STATE2_HSYNC_END_DEFAULT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE2_HSYNC_END_DEFAULT_MASK                 _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE2_HSYNC_END_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_HSYNC_END_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_HSYNC_END_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE2_HSYNC_END_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_HEAD_STATE2_1
#define SOR_NV_PDISP_HEAD_STATE2_1                      _MK_ADDR_CONST(0x15a)
#define SOR_NV_PDISP_HEAD_STATE2_1_SECURE                       0x0
#define SOR_NV_PDISP_HEAD_STATE2_1_DUAL                         0x0
#define SOR_NV_PDISP_HEAD_STATE2_1_SCR                  0
#define SOR_NV_PDISP_HEAD_STATE2_1_WORD_COUNT                   0x1
#define SOR_NV_PDISP_HEAD_STATE2_1_RESET_VAL                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE2_1_RESET_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE2_1_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_1_READ_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE2_1_WRITE_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE2_1_VSYNC_END_SHIFT                      _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_HEAD_STATE2_1_VSYNC_END_FIELD                      _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE2_1_VSYNC_END_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE2_1_VSYNC_END_RANGE                      30:16
#define SOR_NV_PDISP_HEAD_STATE2_1_VSYNC_END_WOFFSET                    0x0
#define SOR_NV_PDISP_HEAD_STATE2_1_VSYNC_END_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_1_VSYNC_END_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE2_1_VSYNC_END_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_1_VSYNC_END_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_1_VSYNC_END_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE2_1_VSYNC_END_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HEAD_STATE2_1_HSYNC_END_SHIFT                      _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE2_1_HSYNC_END_FIELD                      _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE2_1_HSYNC_END_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE2_1_HSYNC_END_RANGE                      14:0
#define SOR_NV_PDISP_HEAD_STATE2_1_HSYNC_END_WOFFSET                    0x0
#define SOR_NV_PDISP_HEAD_STATE2_1_HSYNC_END_DEFAULT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE2_1_HSYNC_END_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE2_1_HSYNC_END_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_1_HSYNC_END_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_1_HSYNC_END_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE2_1_HSYNC_END_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_HEAD_STATE2_2
#define SOR_NV_PDISP_HEAD_STATE2_2                      _MK_ADDR_CONST(0x15b)
#define SOR_NV_PDISP_HEAD_STATE2_2_SECURE                       0x0
#define SOR_NV_PDISP_HEAD_STATE2_2_DUAL                         0x0
#define SOR_NV_PDISP_HEAD_STATE2_2_SCR                  0
#define SOR_NV_PDISP_HEAD_STATE2_2_WORD_COUNT                   0x1
#define SOR_NV_PDISP_HEAD_STATE2_2_RESET_VAL                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE2_2_RESET_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE2_2_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_2_READ_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE2_2_WRITE_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE2_2_VSYNC_END_SHIFT                      _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_HEAD_STATE2_2_VSYNC_END_FIELD                      _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE2_2_VSYNC_END_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE2_2_VSYNC_END_RANGE                      30:16
#define SOR_NV_PDISP_HEAD_STATE2_2_VSYNC_END_WOFFSET                    0x0
#define SOR_NV_PDISP_HEAD_STATE2_2_VSYNC_END_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_2_VSYNC_END_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE2_2_VSYNC_END_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_2_VSYNC_END_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_2_VSYNC_END_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE2_2_VSYNC_END_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HEAD_STATE2_2_HSYNC_END_SHIFT                      _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE2_2_HSYNC_END_FIELD                      _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE2_2_HSYNC_END_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE2_2_HSYNC_END_RANGE                      14:0
#define SOR_NV_PDISP_HEAD_STATE2_2_HSYNC_END_WOFFSET                    0x0
#define SOR_NV_PDISP_HEAD_STATE2_2_HSYNC_END_DEFAULT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE2_2_HSYNC_END_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE2_2_HSYNC_END_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_2_HSYNC_END_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_2_HSYNC_END_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE2_2_HSYNC_END_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_HEAD_STATE2_3
#define SOR_NV_PDISP_HEAD_STATE2_3                      _MK_ADDR_CONST(0x15c)
#define SOR_NV_PDISP_HEAD_STATE2_3_SECURE                       0x0
#define SOR_NV_PDISP_HEAD_STATE2_3_DUAL                         0x0
#define SOR_NV_PDISP_HEAD_STATE2_3_SCR                  0
#define SOR_NV_PDISP_HEAD_STATE2_3_WORD_COUNT                   0x1
#define SOR_NV_PDISP_HEAD_STATE2_3_RESET_VAL                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE2_3_RESET_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE2_3_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_3_READ_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE2_3_WRITE_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE2_3_VSYNC_END_SHIFT                      _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_HEAD_STATE2_3_VSYNC_END_FIELD                      _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE2_3_VSYNC_END_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE2_3_VSYNC_END_RANGE                      30:16
#define SOR_NV_PDISP_HEAD_STATE2_3_VSYNC_END_WOFFSET                    0x0
#define SOR_NV_PDISP_HEAD_STATE2_3_VSYNC_END_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_3_VSYNC_END_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE2_3_VSYNC_END_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_3_VSYNC_END_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_3_VSYNC_END_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE2_3_VSYNC_END_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HEAD_STATE2_3_HSYNC_END_SHIFT                      _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE2_3_HSYNC_END_FIELD                      _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE2_3_HSYNC_END_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE2_3_HSYNC_END_RANGE                      14:0
#define SOR_NV_PDISP_HEAD_STATE2_3_HSYNC_END_WOFFSET                    0x0
#define SOR_NV_PDISP_HEAD_STATE2_3_HSYNC_END_DEFAULT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE2_3_HSYNC_END_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE2_3_HSYNC_END_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_3_HSYNC_END_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE2_3_HSYNC_END_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE2_3_HSYNC_END_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_HEAD_STATE3_0
#define SOR_NV_PDISP_HEAD_STATE3_0                      _MK_ADDR_CONST(0x15d)
#define SOR_NV_PDISP_HEAD_STATE3_0_SECURE                       0x0
#define SOR_NV_PDISP_HEAD_STATE3_0_DUAL                         0x0
#define SOR_NV_PDISP_HEAD_STATE3_0_SCR                  0
#define SOR_NV_PDISP_HEAD_STATE3_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_HEAD_STATE3_0_RESET_VAL                    _MK_MASK_CONST(0x10011)
#define SOR_NV_PDISP_HEAD_STATE3_0_RESET_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_0_READ_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE3_0_WRITE_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE3_0_VBLANK_END_SHIFT                     _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_HEAD_STATE3_0_VBLANK_END_FIELD                     _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE3_0_VBLANK_END_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE3_0_VBLANK_END_RANGE                     30:16
#define SOR_NV_PDISP_HEAD_STATE3_0_VBLANK_END_WOFFSET                   0x0
#define SOR_NV_PDISP_HEAD_STATE3_0_VBLANK_END_DEFAULT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE3_0_VBLANK_END_DEFAULT_MASK                      _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE3_0_VBLANK_END_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_0_VBLANK_END_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_0_VBLANK_END_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE3_0_VBLANK_END_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HEAD_STATE3_0_HBLANK_END_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE3_0_HBLANK_END_FIELD                     _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE3_0_HBLANK_END_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE3_0_HBLANK_END_RANGE                     14:0
#define SOR_NV_PDISP_HEAD_STATE3_0_HBLANK_END_WOFFSET                   0x0
#define SOR_NV_PDISP_HEAD_STATE3_0_HBLANK_END_DEFAULT                   _MK_MASK_CONST(0x11)
#define SOR_NV_PDISP_HEAD_STATE3_0_HBLANK_END_DEFAULT_MASK                      _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE3_0_HBLANK_END_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_0_HBLANK_END_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_0_HBLANK_END_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE3_0_HBLANK_END_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_HEAD_STATE3
#define SOR_NV_PDISP_HEAD_STATE3                        _MK_ADDR_CONST(0x15d)
#define SOR_NV_PDISP_HEAD_STATE3_SECURE                         0x0
#define SOR_NV_PDISP_HEAD_STATE3_DUAL                   0x0
#define SOR_NV_PDISP_HEAD_STATE3_SCR                    0
#define SOR_NV_PDISP_HEAD_STATE3_WORD_COUNT                     0x1
#define SOR_NV_PDISP_HEAD_STATE3_RESET_VAL                      _MK_MASK_CONST(0x10011)
#define SOR_NV_PDISP_HEAD_STATE3_RESET_MASK                     _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE3_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_READ_MASK                      _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE3_WRITE_MASK                     _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE3_VBLANK_END_SHIFT                       _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_HEAD_STATE3_VBLANK_END_FIELD                       _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE3_VBLANK_END_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE3_VBLANK_END_RANGE                       30:16
#define SOR_NV_PDISP_HEAD_STATE3_VBLANK_END_WOFFSET                     0x0
#define SOR_NV_PDISP_HEAD_STATE3_VBLANK_END_DEFAULT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE3_VBLANK_END_DEFAULT_MASK                        _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE3_VBLANK_END_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_VBLANK_END_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_VBLANK_END_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE3_VBLANK_END_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HEAD_STATE3_HBLANK_END_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE3_HBLANK_END_FIELD                       _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE3_HBLANK_END_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE3_HBLANK_END_RANGE                       14:0
#define SOR_NV_PDISP_HEAD_STATE3_HBLANK_END_WOFFSET                     0x0
#define SOR_NV_PDISP_HEAD_STATE3_HBLANK_END_DEFAULT                     _MK_MASK_CONST(0x11)
#define SOR_NV_PDISP_HEAD_STATE3_HBLANK_END_DEFAULT_MASK                        _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE3_HBLANK_END_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_HBLANK_END_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_HBLANK_END_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE3_HBLANK_END_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_HEAD_STATE3_1
#define SOR_NV_PDISP_HEAD_STATE3_1                      _MK_ADDR_CONST(0x15e)
#define SOR_NV_PDISP_HEAD_STATE3_1_SECURE                       0x0
#define SOR_NV_PDISP_HEAD_STATE3_1_DUAL                         0x0
#define SOR_NV_PDISP_HEAD_STATE3_1_SCR                  0
#define SOR_NV_PDISP_HEAD_STATE3_1_WORD_COUNT                   0x1
#define SOR_NV_PDISP_HEAD_STATE3_1_RESET_VAL                    _MK_MASK_CONST(0x10011)
#define SOR_NV_PDISP_HEAD_STATE3_1_RESET_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE3_1_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_1_READ_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE3_1_WRITE_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE3_1_VBLANK_END_SHIFT                     _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_HEAD_STATE3_1_VBLANK_END_FIELD                     _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE3_1_VBLANK_END_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE3_1_VBLANK_END_RANGE                     30:16
#define SOR_NV_PDISP_HEAD_STATE3_1_VBLANK_END_WOFFSET                   0x0
#define SOR_NV_PDISP_HEAD_STATE3_1_VBLANK_END_DEFAULT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE3_1_VBLANK_END_DEFAULT_MASK                      _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE3_1_VBLANK_END_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_1_VBLANK_END_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_1_VBLANK_END_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE3_1_VBLANK_END_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HEAD_STATE3_1_HBLANK_END_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE3_1_HBLANK_END_FIELD                     _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE3_1_HBLANK_END_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE3_1_HBLANK_END_RANGE                     14:0
#define SOR_NV_PDISP_HEAD_STATE3_1_HBLANK_END_WOFFSET                   0x0
#define SOR_NV_PDISP_HEAD_STATE3_1_HBLANK_END_DEFAULT                   _MK_MASK_CONST(0x11)
#define SOR_NV_PDISP_HEAD_STATE3_1_HBLANK_END_DEFAULT_MASK                      _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE3_1_HBLANK_END_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_1_HBLANK_END_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_1_HBLANK_END_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE3_1_HBLANK_END_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_HEAD_STATE3_2
#define SOR_NV_PDISP_HEAD_STATE3_2                      _MK_ADDR_CONST(0x15f)
#define SOR_NV_PDISP_HEAD_STATE3_2_SECURE                       0x0
#define SOR_NV_PDISP_HEAD_STATE3_2_DUAL                         0x0
#define SOR_NV_PDISP_HEAD_STATE3_2_SCR                  0
#define SOR_NV_PDISP_HEAD_STATE3_2_WORD_COUNT                   0x1
#define SOR_NV_PDISP_HEAD_STATE3_2_RESET_VAL                    _MK_MASK_CONST(0x10011)
#define SOR_NV_PDISP_HEAD_STATE3_2_RESET_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE3_2_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_2_READ_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE3_2_WRITE_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE3_2_VBLANK_END_SHIFT                     _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_HEAD_STATE3_2_VBLANK_END_FIELD                     _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE3_2_VBLANK_END_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE3_2_VBLANK_END_RANGE                     30:16
#define SOR_NV_PDISP_HEAD_STATE3_2_VBLANK_END_WOFFSET                   0x0
#define SOR_NV_PDISP_HEAD_STATE3_2_VBLANK_END_DEFAULT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE3_2_VBLANK_END_DEFAULT_MASK                      _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE3_2_VBLANK_END_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_2_VBLANK_END_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_2_VBLANK_END_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE3_2_VBLANK_END_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HEAD_STATE3_2_HBLANK_END_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE3_2_HBLANK_END_FIELD                     _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE3_2_HBLANK_END_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE3_2_HBLANK_END_RANGE                     14:0
#define SOR_NV_PDISP_HEAD_STATE3_2_HBLANK_END_WOFFSET                   0x0
#define SOR_NV_PDISP_HEAD_STATE3_2_HBLANK_END_DEFAULT                   _MK_MASK_CONST(0x11)
#define SOR_NV_PDISP_HEAD_STATE3_2_HBLANK_END_DEFAULT_MASK                      _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE3_2_HBLANK_END_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_2_HBLANK_END_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_2_HBLANK_END_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE3_2_HBLANK_END_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_HEAD_STATE3_3
#define SOR_NV_PDISP_HEAD_STATE3_3                      _MK_ADDR_CONST(0x160)
#define SOR_NV_PDISP_HEAD_STATE3_3_SECURE                       0x0
#define SOR_NV_PDISP_HEAD_STATE3_3_DUAL                         0x0
#define SOR_NV_PDISP_HEAD_STATE3_3_SCR                  0
#define SOR_NV_PDISP_HEAD_STATE3_3_WORD_COUNT                   0x1
#define SOR_NV_PDISP_HEAD_STATE3_3_RESET_VAL                    _MK_MASK_CONST(0x10011)
#define SOR_NV_PDISP_HEAD_STATE3_3_RESET_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE3_3_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_3_READ_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE3_3_WRITE_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE3_3_VBLANK_END_SHIFT                     _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_HEAD_STATE3_3_VBLANK_END_FIELD                     _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE3_3_VBLANK_END_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE3_3_VBLANK_END_RANGE                     30:16
#define SOR_NV_PDISP_HEAD_STATE3_3_VBLANK_END_WOFFSET                   0x0
#define SOR_NV_PDISP_HEAD_STATE3_3_VBLANK_END_DEFAULT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE3_3_VBLANK_END_DEFAULT_MASK                      _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE3_3_VBLANK_END_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_3_VBLANK_END_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_3_VBLANK_END_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE3_3_VBLANK_END_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HEAD_STATE3_3_HBLANK_END_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE3_3_HBLANK_END_FIELD                     _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE3_3_HBLANK_END_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE3_3_HBLANK_END_RANGE                     14:0
#define SOR_NV_PDISP_HEAD_STATE3_3_HBLANK_END_WOFFSET                   0x0
#define SOR_NV_PDISP_HEAD_STATE3_3_HBLANK_END_DEFAULT                   _MK_MASK_CONST(0x11)
#define SOR_NV_PDISP_HEAD_STATE3_3_HBLANK_END_DEFAULT_MASK                      _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE3_3_HBLANK_END_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_3_HBLANK_END_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE3_3_HBLANK_END_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE3_3_HBLANK_END_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_HEAD_STATE4_0
#define SOR_NV_PDISP_HEAD_STATE4_0                      _MK_ADDR_CONST(0x161)
#define SOR_NV_PDISP_HEAD_STATE4_0_SECURE                       0x0
#define SOR_NV_PDISP_HEAD_STATE4_0_DUAL                         0x0
#define SOR_NV_PDISP_HEAD_STATE4_0_SCR                  0
#define SOR_NV_PDISP_HEAD_STATE4_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_HEAD_STATE4_0_RESET_VAL                    _MK_MASK_CONST(0x110100)
#define SOR_NV_PDISP_HEAD_STATE4_0_RESET_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE4_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_0_READ_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE4_0_WRITE_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE4_0_VBLANK_START_SHIFT                   _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_HEAD_STATE4_0_VBLANK_START_FIELD                   _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE4_0_VBLANK_START_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE4_0_VBLANK_START_RANGE                   30:16
#define SOR_NV_PDISP_HEAD_STATE4_0_VBLANK_START_WOFFSET                 0x0
#define SOR_NV_PDISP_HEAD_STATE4_0_VBLANK_START_DEFAULT                 _MK_MASK_CONST(0x11)
#define SOR_NV_PDISP_HEAD_STATE4_0_VBLANK_START_DEFAULT_MASK                    _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE4_0_VBLANK_START_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_0_VBLANK_START_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_0_VBLANK_START_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE4_0_VBLANK_START_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HEAD_STATE4_0_HBLANK_START_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE4_0_HBLANK_START_FIELD                   _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE4_0_HBLANK_START_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE4_0_HBLANK_START_RANGE                   14:0
#define SOR_NV_PDISP_HEAD_STATE4_0_HBLANK_START_WOFFSET                 0x0
#define SOR_NV_PDISP_HEAD_STATE4_0_HBLANK_START_DEFAULT                 _MK_MASK_CONST(0x100)
#define SOR_NV_PDISP_HEAD_STATE4_0_HBLANK_START_DEFAULT_MASK                    _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE4_0_HBLANK_START_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_0_HBLANK_START_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_0_HBLANK_START_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE4_0_HBLANK_START_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_HEAD_STATE4
#define SOR_NV_PDISP_HEAD_STATE4                        _MK_ADDR_CONST(0x161)
#define SOR_NV_PDISP_HEAD_STATE4_SECURE                         0x0
#define SOR_NV_PDISP_HEAD_STATE4_DUAL                   0x0
#define SOR_NV_PDISP_HEAD_STATE4_SCR                    0
#define SOR_NV_PDISP_HEAD_STATE4_WORD_COUNT                     0x1
#define SOR_NV_PDISP_HEAD_STATE4_RESET_VAL                      _MK_MASK_CONST(0x110100)
#define SOR_NV_PDISP_HEAD_STATE4_RESET_MASK                     _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE4_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_READ_MASK                      _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE4_WRITE_MASK                     _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE4_VBLANK_START_SHIFT                     _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_HEAD_STATE4_VBLANK_START_FIELD                     _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE4_VBLANK_START_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE4_VBLANK_START_RANGE                     30:16
#define SOR_NV_PDISP_HEAD_STATE4_VBLANK_START_WOFFSET                   0x0
#define SOR_NV_PDISP_HEAD_STATE4_VBLANK_START_DEFAULT                   _MK_MASK_CONST(0x11)
#define SOR_NV_PDISP_HEAD_STATE4_VBLANK_START_DEFAULT_MASK                      _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE4_VBLANK_START_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_VBLANK_START_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_VBLANK_START_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE4_VBLANK_START_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HEAD_STATE4_HBLANK_START_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE4_HBLANK_START_FIELD                     _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE4_HBLANK_START_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE4_HBLANK_START_RANGE                     14:0
#define SOR_NV_PDISP_HEAD_STATE4_HBLANK_START_WOFFSET                   0x0
#define SOR_NV_PDISP_HEAD_STATE4_HBLANK_START_DEFAULT                   _MK_MASK_CONST(0x100)
#define SOR_NV_PDISP_HEAD_STATE4_HBLANK_START_DEFAULT_MASK                      _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE4_HBLANK_START_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_HBLANK_START_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_HBLANK_START_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE4_HBLANK_START_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_HEAD_STATE4_1
#define SOR_NV_PDISP_HEAD_STATE4_1                      _MK_ADDR_CONST(0x162)
#define SOR_NV_PDISP_HEAD_STATE4_1_SECURE                       0x0
#define SOR_NV_PDISP_HEAD_STATE4_1_DUAL                         0x0
#define SOR_NV_PDISP_HEAD_STATE4_1_SCR                  0
#define SOR_NV_PDISP_HEAD_STATE4_1_WORD_COUNT                   0x1
#define SOR_NV_PDISP_HEAD_STATE4_1_RESET_VAL                    _MK_MASK_CONST(0x110100)
#define SOR_NV_PDISP_HEAD_STATE4_1_RESET_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE4_1_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_1_READ_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE4_1_WRITE_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE4_1_VBLANK_START_SHIFT                   _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_HEAD_STATE4_1_VBLANK_START_FIELD                   _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE4_1_VBLANK_START_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE4_1_VBLANK_START_RANGE                   30:16
#define SOR_NV_PDISP_HEAD_STATE4_1_VBLANK_START_WOFFSET                 0x0
#define SOR_NV_PDISP_HEAD_STATE4_1_VBLANK_START_DEFAULT                 _MK_MASK_CONST(0x11)
#define SOR_NV_PDISP_HEAD_STATE4_1_VBLANK_START_DEFAULT_MASK                    _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE4_1_VBLANK_START_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_1_VBLANK_START_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_1_VBLANK_START_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE4_1_VBLANK_START_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HEAD_STATE4_1_HBLANK_START_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE4_1_HBLANK_START_FIELD                   _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE4_1_HBLANK_START_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE4_1_HBLANK_START_RANGE                   14:0
#define SOR_NV_PDISP_HEAD_STATE4_1_HBLANK_START_WOFFSET                 0x0
#define SOR_NV_PDISP_HEAD_STATE4_1_HBLANK_START_DEFAULT                 _MK_MASK_CONST(0x100)
#define SOR_NV_PDISP_HEAD_STATE4_1_HBLANK_START_DEFAULT_MASK                    _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE4_1_HBLANK_START_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_1_HBLANK_START_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_1_HBLANK_START_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE4_1_HBLANK_START_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_HEAD_STATE4_2
#define SOR_NV_PDISP_HEAD_STATE4_2                      _MK_ADDR_CONST(0x163)
#define SOR_NV_PDISP_HEAD_STATE4_2_SECURE                       0x0
#define SOR_NV_PDISP_HEAD_STATE4_2_DUAL                         0x0
#define SOR_NV_PDISP_HEAD_STATE4_2_SCR                  0
#define SOR_NV_PDISP_HEAD_STATE4_2_WORD_COUNT                   0x1
#define SOR_NV_PDISP_HEAD_STATE4_2_RESET_VAL                    _MK_MASK_CONST(0x110100)
#define SOR_NV_PDISP_HEAD_STATE4_2_RESET_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE4_2_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_2_READ_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE4_2_WRITE_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE4_2_VBLANK_START_SHIFT                   _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_HEAD_STATE4_2_VBLANK_START_FIELD                   _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE4_2_VBLANK_START_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE4_2_VBLANK_START_RANGE                   30:16
#define SOR_NV_PDISP_HEAD_STATE4_2_VBLANK_START_WOFFSET                 0x0
#define SOR_NV_PDISP_HEAD_STATE4_2_VBLANK_START_DEFAULT                 _MK_MASK_CONST(0x11)
#define SOR_NV_PDISP_HEAD_STATE4_2_VBLANK_START_DEFAULT_MASK                    _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE4_2_VBLANK_START_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_2_VBLANK_START_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_2_VBLANK_START_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE4_2_VBLANK_START_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HEAD_STATE4_2_HBLANK_START_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE4_2_HBLANK_START_FIELD                   _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE4_2_HBLANK_START_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE4_2_HBLANK_START_RANGE                   14:0
#define SOR_NV_PDISP_HEAD_STATE4_2_HBLANK_START_WOFFSET                 0x0
#define SOR_NV_PDISP_HEAD_STATE4_2_HBLANK_START_DEFAULT                 _MK_MASK_CONST(0x100)
#define SOR_NV_PDISP_HEAD_STATE4_2_HBLANK_START_DEFAULT_MASK                    _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE4_2_HBLANK_START_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_2_HBLANK_START_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_2_HBLANK_START_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE4_2_HBLANK_START_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_HEAD_STATE4_3
#define SOR_NV_PDISP_HEAD_STATE4_3                      _MK_ADDR_CONST(0x164)
#define SOR_NV_PDISP_HEAD_STATE4_3_SECURE                       0x0
#define SOR_NV_PDISP_HEAD_STATE4_3_DUAL                         0x0
#define SOR_NV_PDISP_HEAD_STATE4_3_SCR                  0
#define SOR_NV_PDISP_HEAD_STATE4_3_WORD_COUNT                   0x1
#define SOR_NV_PDISP_HEAD_STATE4_3_RESET_VAL                    _MK_MASK_CONST(0x110100)
#define SOR_NV_PDISP_HEAD_STATE4_3_RESET_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE4_3_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_3_READ_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE4_3_WRITE_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE4_3_VBLANK_START_SHIFT                   _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_HEAD_STATE4_3_VBLANK_START_FIELD                   _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE4_3_VBLANK_START_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE4_3_VBLANK_START_RANGE                   30:16
#define SOR_NV_PDISP_HEAD_STATE4_3_VBLANK_START_WOFFSET                 0x0
#define SOR_NV_PDISP_HEAD_STATE4_3_VBLANK_START_DEFAULT                 _MK_MASK_CONST(0x11)
#define SOR_NV_PDISP_HEAD_STATE4_3_VBLANK_START_DEFAULT_MASK                    _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE4_3_VBLANK_START_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_3_VBLANK_START_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_3_VBLANK_START_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE4_3_VBLANK_START_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HEAD_STATE4_3_HBLANK_START_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE4_3_HBLANK_START_FIELD                   _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE4_3_HBLANK_START_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE4_3_HBLANK_START_RANGE                   14:0
#define SOR_NV_PDISP_HEAD_STATE4_3_HBLANK_START_WOFFSET                 0x0
#define SOR_NV_PDISP_HEAD_STATE4_3_HBLANK_START_DEFAULT                 _MK_MASK_CONST(0x100)
#define SOR_NV_PDISP_HEAD_STATE4_3_HBLANK_START_DEFAULT_MASK                    _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE4_3_HBLANK_START_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_3_HBLANK_START_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE4_3_HBLANK_START_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE4_3_HBLANK_START_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_HEAD_STATE5_0
#define SOR_NV_PDISP_HEAD_STATE5_0                      _MK_ADDR_CONST(0x165)
#define SOR_NV_PDISP_HEAD_STATE5_0_SECURE                       0x0
#define SOR_NV_PDISP_HEAD_STATE5_0_DUAL                         0x0
#define SOR_NV_PDISP_HEAD_STATE5_0_SCR                  0
#define SOR_NV_PDISP_HEAD_STATE5_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_HEAD_STATE5_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE5_0_RESET_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE5_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_0_READ_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE5_0_WRITE_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_END_2_SHIFT                   _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_END_2_FIELD                   _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_END_2_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_END_2_RANGE                   30:16
#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_END_2_WOFFSET                 0x0
#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_END_2_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_END_2_DEFAULT_MASK                    _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_END_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_END_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_END_2_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_END_2_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_START_2_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_START_2_FIELD                 _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_START_2_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_START_2_RANGE                 14:0
#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_START_2_WOFFSET                       0x0
#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_START_2_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_START_2_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_START_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_START_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_START_2_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_START_2_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_HEAD_STATE5
#define SOR_NV_PDISP_HEAD_STATE5                        _MK_ADDR_CONST(0x165)
#define SOR_NV_PDISP_HEAD_STATE5_SECURE                         0x0
#define SOR_NV_PDISP_HEAD_STATE5_DUAL                   0x0
#define SOR_NV_PDISP_HEAD_STATE5_SCR                    0
#define SOR_NV_PDISP_HEAD_STATE5_WORD_COUNT                     0x1
#define SOR_NV_PDISP_HEAD_STATE5_RESET_VAL                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE5_RESET_MASK                     _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE5_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_READ_MASK                      _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE5_WRITE_MASK                     _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_END_2_SHIFT                     _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_END_2_FIELD                     _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE5_VBLANK_END_2_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_END_2_RANGE                     30:16
#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_END_2_WOFFSET                   0x0
#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_END_2_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_END_2_DEFAULT_MASK                      _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_END_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_END_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_END_2_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_END_2_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_START_2_SHIFT                   _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_START_2_FIELD                   _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE5_VBLANK_START_2_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_START_2_RANGE                   14:0
#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_START_2_WOFFSET                 0x0
#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_START_2_DEFAULT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_START_2_DEFAULT_MASK                    _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_START_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_START_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_START_2_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_START_2_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_HEAD_STATE5_1
#define SOR_NV_PDISP_HEAD_STATE5_1                      _MK_ADDR_CONST(0x166)
#define SOR_NV_PDISP_HEAD_STATE5_1_SECURE                       0x0
#define SOR_NV_PDISP_HEAD_STATE5_1_DUAL                         0x0
#define SOR_NV_PDISP_HEAD_STATE5_1_SCR                  0
#define SOR_NV_PDISP_HEAD_STATE5_1_WORD_COUNT                   0x1
#define SOR_NV_PDISP_HEAD_STATE5_1_RESET_VAL                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE5_1_RESET_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE5_1_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_1_READ_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE5_1_WRITE_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_END_2_SHIFT                   _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_END_2_FIELD                   _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_END_2_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_END_2_RANGE                   30:16
#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_END_2_WOFFSET                 0x0
#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_END_2_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_END_2_DEFAULT_MASK                    _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_END_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_END_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_END_2_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_END_2_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_START_2_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_START_2_FIELD                 _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_START_2_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_START_2_RANGE                 14:0
#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_START_2_WOFFSET                       0x0
#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_START_2_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_START_2_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_START_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_START_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_START_2_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_START_2_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_HEAD_STATE5_2
#define SOR_NV_PDISP_HEAD_STATE5_2                      _MK_ADDR_CONST(0x167)
#define SOR_NV_PDISP_HEAD_STATE5_2_SECURE                       0x0
#define SOR_NV_PDISP_HEAD_STATE5_2_DUAL                         0x0
#define SOR_NV_PDISP_HEAD_STATE5_2_SCR                  0
#define SOR_NV_PDISP_HEAD_STATE5_2_WORD_COUNT                   0x1
#define SOR_NV_PDISP_HEAD_STATE5_2_RESET_VAL                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE5_2_RESET_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE5_2_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_2_READ_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE5_2_WRITE_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE5_2_VBLANK_END_2_SHIFT                   _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_HEAD_STATE5_2_VBLANK_END_2_FIELD                   _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE5_2_VBLANK_END_2_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE5_2_VBLANK_END_2_RANGE                   30:16
#define SOR_NV_PDISP_HEAD_STATE5_2_VBLANK_END_2_WOFFSET                 0x0
#define SOR_NV_PDISP_HEAD_STATE5_2_VBLANK_END_2_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_2_VBLANK_END_2_DEFAULT_MASK                    _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE5_2_VBLANK_END_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_2_VBLANK_END_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_2_VBLANK_END_2_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE5_2_VBLANK_END_2_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HEAD_STATE5_2_VBLANK_START_2_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE5_2_VBLANK_START_2_FIELD                 _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE5_2_VBLANK_START_2_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE5_2_VBLANK_START_2_RANGE                 14:0
#define SOR_NV_PDISP_HEAD_STATE5_2_VBLANK_START_2_WOFFSET                       0x0
#define SOR_NV_PDISP_HEAD_STATE5_2_VBLANK_START_2_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE5_2_VBLANK_START_2_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE5_2_VBLANK_START_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_2_VBLANK_START_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_2_VBLANK_START_2_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE5_2_VBLANK_START_2_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_HEAD_STATE5_3
#define SOR_NV_PDISP_HEAD_STATE5_3                      _MK_ADDR_CONST(0x168)
#define SOR_NV_PDISP_HEAD_STATE5_3_SECURE                       0x0
#define SOR_NV_PDISP_HEAD_STATE5_3_DUAL                         0x0
#define SOR_NV_PDISP_HEAD_STATE5_3_SCR                  0
#define SOR_NV_PDISP_HEAD_STATE5_3_WORD_COUNT                   0x1
#define SOR_NV_PDISP_HEAD_STATE5_3_RESET_VAL                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE5_3_RESET_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE5_3_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_3_READ_MASK                    _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE5_3_WRITE_MASK                   _MK_MASK_CONST(0x7fff7fff)
#define SOR_NV_PDISP_HEAD_STATE5_3_VBLANK_END_2_SHIFT                   _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_HEAD_STATE5_3_VBLANK_END_2_FIELD                   _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE5_3_VBLANK_END_2_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE5_3_VBLANK_END_2_RANGE                   30:16
#define SOR_NV_PDISP_HEAD_STATE5_3_VBLANK_END_2_WOFFSET                 0x0
#define SOR_NV_PDISP_HEAD_STATE5_3_VBLANK_END_2_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_3_VBLANK_END_2_DEFAULT_MASK                    _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE5_3_VBLANK_END_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_3_VBLANK_END_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_3_VBLANK_END_2_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE5_3_VBLANK_END_2_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_HEAD_STATE5_3_VBLANK_START_2_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_HEAD_STATE5_3_VBLANK_START_2_FIELD                 _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE5_3_VBLANK_START_2_SHIFT)
#define SOR_NV_PDISP_HEAD_STATE5_3_VBLANK_START_2_RANGE                 14:0
#define SOR_NV_PDISP_HEAD_STATE5_3_VBLANK_START_2_WOFFSET                       0x0
#define SOR_NV_PDISP_HEAD_STATE5_3_VBLANK_START_2_DEFAULT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE5_3_VBLANK_START_2_DEFAULT_MASK                  _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_HEAD_STATE5_3_VBLANK_START_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_3_VBLANK_START_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_HEAD_STATE5_3_VBLANK_START_2_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_HEAD_STATE5_3_VBLANK_START_2_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_PLL0_0
#define SOR_NV_PDISP_SOR_PLL0_0                 _MK_ADDR_CONST(0x169)
#define SOR_NV_PDISP_SOR_PLL0_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_PLL0_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_PLL0_0_SCR                     0
#define SOR_NV_PDISP_SOR_PLL0_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_PLL0_0_RESET_VAL                       _MK_MASK_CONST(0x50503c5)
#define SOR_NV_PDISP_SOR_PLL0_0_RESET_MASK                      _MK_MASK_CONST(0xf0f3fe5)
#define SOR_NV_PDISP_SOR_PLL0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL0_0_READ_MASK                       _MK_MASK_CONST(0xf0f3fe5)
#define SOR_NV_PDISP_SOR_PLL0_0_WRITE_MASK                      _MK_MASK_CONST(0xf0f3fe5)
#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP_SHIFT                    _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP_FIELD                    _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_PLL0_0_ICHPMP_SHIFT)
#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP_RANGE                    27:24
#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP_DEFAULT                  _MK_MASK_CONST(0x5)
#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP_INIT_ENUM                        RST
#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP_RST                      _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP__PROD_C_RBR                      _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP__PROD_C_HBR                      _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP__PROD_C_HBR2                     _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP__PROD_C_HBR3                     _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP__PROD_C_R_HDMI_0M_54M                    _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP__PROD_C_R_HDMI_54M_111M                  _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP__PROD_C_R_HDMI_111M_223M                 _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP__PROD_C_R_HDMI_223M_300M                 _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP__PROD_C_R_HDMI_300M_600M                 _MK_ENUM_CONST(5)

#define SOR_NV_PDISP_SOR_PLL0_0_FILTER_SHIFT                    _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_PLL0_0_FILTER_FIELD                    _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_PLL0_0_FILTER_SHIFT)
#define SOR_NV_PDISP_SOR_PLL0_0_FILTER_RANGE                    19:16
#define SOR_NV_PDISP_SOR_PLL0_0_FILTER_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_PLL0_0_FILTER_DEFAULT                  _MK_MASK_CONST(0x5)
#define SOR_NV_PDISP_SOR_PLL0_0_FILTER_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_PLL0_0_FILTER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL0_0_FILTER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL0_0_FILTER_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL0_0_FILTER_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL0_0_FILTER__PROD_C_R_HDMI_0M_54M                    _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_PLL0_0_FILTER__PROD_C_R_HDMI_54M_111M                  _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_PLL0_0_FILTER__PROD_C_R_HDMI_111M_223M                 _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_PLL0_0_FILTER__PROD_C_R_HDMI_223M_300M                 _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_PLL0_0_FILTER__PROD_C_R_HDMI_300M_600M                 _MK_ENUM_CONST(5)

#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_SHIFT                       _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_FIELD                       _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_SHIFT)
#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_RANGE                       13:12
#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_INIT_ENUM                   V25
#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_V25                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_V15                 _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_V35                 _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_V45                 _MK_ENUM_CONST(3)

#define SOR_NV_PDISP_SOR_PLL0_0_VCOCAP_SHIFT                    _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_PLL0_0_VCOCAP_FIELD                    _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_PLL0_0_VCOCAP_SHIFT)
#define SOR_NV_PDISP_SOR_PLL0_0_VCOCAP_RANGE                    11:8
#define SOR_NV_PDISP_SOR_PLL0_0_VCOCAP_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_PLL0_0_VCOCAP_DEFAULT                  _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_PLL0_0_VCOCAP_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_PLL0_0_VCOCAP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL0_0_VCOCAP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL0_0_VCOCAP_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL0_0_VCOCAP_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL0_0_VCOCAP_INIT_ENUM                        RST
#define SOR_NV_PDISP_SOR_PLL0_0_VCOCAP_RST                      _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_PLL0_0_VCOCAP__PROD_C_R_HDMI_0M_54M                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL0_0_VCOCAP__PROD_C_R_HDMI_54M_111M                  _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PLL0_0_VCOCAP__PROD_C_R_HDMI_111M_223M                 _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_PLL0_0_VCOCAP__PROD_C_R_HDMI_223M_300M                 _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_PLL0_0_VCOCAP__PROD_C_R_HDMI_300M_600M                 _MK_ENUM_CONST(3)

#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_SHIFT                      _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_FIELD                      _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_SHIFT)
#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_RANGE                      7:6
#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_DEFAULT                    _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_INIT_ENUM                  V45
#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_V25                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_V15                        _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_V35                        _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_V45                        _MK_ENUM_CONST(3)

#define SOR_NV_PDISP_SOR_PLL0_0_PULLDOWN_SHIFT                  _MK_SHIFT_CONST(5)
#define SOR_NV_PDISP_SOR_PLL0_0_PULLDOWN_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL0_0_PULLDOWN_SHIFT)
#define SOR_NV_PDISP_SOR_PLL0_0_PULLDOWN_RANGE                  5:5
#define SOR_NV_PDISP_SOR_PLL0_0_PULLDOWN_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_PLL0_0_PULLDOWN_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL0_0_PULLDOWN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL0_0_PULLDOWN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL0_0_PULLDOWN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL0_0_PULLDOWN_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL0_0_PULLDOWN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL0_0_PULLDOWN_INIT_ENUM                      DISABLE
#define SOR_NV_PDISP_SOR_PLL0_0_PULLDOWN_DISABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL0_0_PULLDOWN_ENABLE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_SHIFT                     _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL0_0_VCOPD_SHIFT)
#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_RANGE                     2:2
#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_DEFAULT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_INIT_ENUM                 ASSERT
#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_RESCIND                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_ASSERT                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PLL0_0_PWR_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_PLL0_0_PWR_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL0_0_PWR_SHIFT)
#define SOR_NV_PDISP_SOR_PLL0_0_PWR_RANGE                       0:0
#define SOR_NV_PDISP_SOR_PLL0_0_PWR_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_PLL0_0_PWR_DEFAULT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL0_0_PWR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL0_0_PWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL0_0_PWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL0_0_PWR_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL0_0_PWR_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL0_0_PWR_INIT_ENUM                   OFF
#define SOR_NV_PDISP_SOR_PLL0_0_PWR_ON                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL0_0_PWR_OFF                 _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_PLL1_0
#define SOR_NV_PDISP_SOR_PLL1_0                 _MK_ADDR_CONST(0x16a)
#define SOR_NV_PDISP_SOR_PLL1_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_PLL1_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_PLL1_0_SCR                     0
#define SOR_NV_PDISP_SOR_PLL1_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_PLL1_0_RESET_VAL                       _MK_MASK_CONST(0x1000)
#define SOR_NV_PDISP_SOR_PLL1_0_RESET_MASK                      _MK_MASK_CONST(0x23f01f3f)
#define SOR_NV_PDISP_SOR_PLL1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL1_0_READ_MASK                       _MK_MASK_CONST(0x23f09f3f)
#define SOR_NV_PDISP_SOR_PLL1_0_WRITE_MASK                      _MK_MASK_CONST(0x23f01f3f)
#define SOR_NV_PDISP_SOR_PLL1_0_COHERENTMODE_SHIFT                      _MK_SHIFT_CONST(29)
#define SOR_NV_PDISP_SOR_PLL1_0_COHERENTMODE_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL1_0_COHERENTMODE_SHIFT)
#define SOR_NV_PDISP_SOR_PLL1_0_COHERENTMODE_RANGE                      29:29
#define SOR_NV_PDISP_SOR_PLL1_0_COHERENTMODE_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_PLL1_0_COHERENTMODE_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL1_0_COHERENTMODE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL1_0_COHERENTMODE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL1_0_COHERENTMODE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL1_0_COHERENTMODE_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL1_0_COHERENTMODE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL1_0_COHERENTMODE_INIT_ENUM                  DISABLE
#define SOR_NV_PDISP_SOR_PLL1_0_COHERENTMODE_DISABLE                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL1_0_COHERENTMODE_ENABLE                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PLL1_0_LVDSCM_SHIFT                    _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_PLL1_0_LVDSCM_FIELD                    _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_PLL1_0_LVDSCM_SHIFT)
#define SOR_NV_PDISP_SOR_PLL1_0_LVDSCM_RANGE                    25:24
#define SOR_NV_PDISP_SOR_PLL1_0_LVDSCM_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_PLL1_0_LVDSCM_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL1_0_LVDSCM_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_PLL1_0_LVDSCM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL1_0_LVDSCM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL1_0_LVDSCM_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL1_0_LVDSCM_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL1_0_LVDSCM__PROD_C_RBR                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL1_0_LVDSCM__PROD_C_HBR                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL1_0_LVDSCM__PROD_C_HBR2                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL1_0_LVDSCM__PROD_C_HBR3                     _MK_ENUM_CONST(0)

#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ_SHIFT                   _MK_SHIFT_CONST(20)
#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ_FIELD                   _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_PLL1_0_LOADADJ_SHIFT)
#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ_RANGE                   23:20
#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ_INIT_ENUM                       CENTER
#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ_CENTER                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ__PROD_C_R_HDMI_0M_54M                   _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ__PROD_C_R_HDMI_54M_111M                 _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ__PROD_C_R_HDMI_111M_223M                        _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ__PROD_C_R_HDMI_223M_300M                        _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ__PROD_C_R_HDMI_300M_600M                        _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ__PROD_C_RBR                     _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ__PROD_C_HBR                     _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ__PROD_C_HBR2                    _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ__PROD_C_HBR3                    _MK_ENUM_CONST(4)

#define SOR_NV_PDISP_SOR_PLL1_0_TERM_COMPOUT_SHIFT                      _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_SOR_PLL1_0_TERM_COMPOUT_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL1_0_TERM_COMPOUT_SHIFT)
#define SOR_NV_PDISP_SOR_PLL1_0_TERM_COMPOUT_RANGE                      15:15
#define SOR_NV_PDISP_SOR_PLL1_0_TERM_COMPOUT_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_PLL1_0_TERM_COMPOUT_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL1_0_TERM_COMPOUT_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL1_0_TERM_COMPOUT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL1_0_TERM_COMPOUT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL1_0_TERM_COMPOUT_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL1_0_TERM_COMPOUT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL1_0_TERM_COMPOUT_LOW                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL1_0_TERM_COMPOUT_HIGH                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ_SHIFT                      _MK_SHIFT_CONST(9)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ_FIELD                      _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ_SHIFT)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ_RANGE                      12:9
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ_DEFAULT                    _MK_MASK_CONST(0x8)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ_INIT_ENUM                  OHM500
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ_OHM500                     _MK_ENUM_CONST(8)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ__PROD_C_R_HDMI_0M_54M                      _MK_ENUM_CONST(8)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ__PROD_C_R_HDMI_54M_111M                    _MK_ENUM_CONST(8)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ__PROD_C_R_HDMI_111M_223M                   _MK_ENUM_CONST(8)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ__PROD_C_R_HDMI_223M_300M                   _MK_ENUM_CONST(8)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ__PROD_C_R_HDMI_300M_600M                   _MK_ENUM_CONST(12)

#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM_SHIFT                 _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM_SHIFT)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM_RANGE                 8:8
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM_INIT_ENUM                     DISABLE
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM_DISABLE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM_ENABLE                        _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM__PROD_C_RBR                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM__PROD_C_HBR                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM__PROD_C_HBR2                  _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM__PROD_C_HBR3                  _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM__PROD_C_R_HDMI_0M_54M                 _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM__PROD_C_R_HDMI_54M_111M                       _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM__PROD_C_R_HDMI_111M_223M                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM__PROD_C_R_HDMI_223M_300M                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM__PROD_C_R_HDMI_300M_600M                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PLL1_0_IOCURRENT_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_PLL1_0_IOCURRENT_FIELD                 _MK_FIELD_CONST(0x3f, SOR_NV_PDISP_SOR_PLL1_0_IOCURRENT_SHIFT)
#define SOR_NV_PDISP_SOR_PLL1_0_IOCURRENT_RANGE                 5:0
#define SOR_NV_PDISP_SOR_PLL1_0_IOCURRENT_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_PLL1_0_IOCURRENT_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL1_0_IOCURRENT_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
#define SOR_NV_PDISP_SOR_PLL1_0_IOCURRENT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL1_0_IOCURRENT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL1_0_IOCURRENT_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL1_0_IOCURRENT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL1_0_IOCURRENT_INIT_ENUM                     RST
#define SOR_NV_PDISP_SOR_PLL1_0_IOCURRENT_RST                   _MK_ENUM_CONST(0)

// Register SOR_NV_PDISP_SOR_PLL2_0
#define SOR_NV_PDISP_SOR_PLL2_0                 _MK_ADDR_CONST(0x16b)
#define SOR_NV_PDISP_SOR_PLL2_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_PLL2_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_PLL2_0_SCR                     0
#define SOR_NV_PDISP_SOR_PLL2_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_PLL2_0_RESET_VAL                       _MK_MASK_CONST(0x5c00014)
#define SOR_NV_PDISP_SOR_PLL2_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_PLL2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_PLL2_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_MDIV_SHIFT                  _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_MDIV_FIELD                  _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_PLL2_0_PLL_MDIV_SHIFT)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_MDIV_RANGE                  31:28
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_MDIV_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_MDIV_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_MDIV_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_MDIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_MDIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_MDIV_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_MDIV_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_PLL2_0_CLKGEN_MODE_SHIFT                       _MK_SHIFT_CONST(26)
#define SOR_NV_PDISP_SOR_PLL2_0_CLKGEN_MODE_FIELD                       _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_PLL2_0_CLKGEN_MODE_SHIFT)
#define SOR_NV_PDISP_SOR_PLL2_0_CLKGEN_MODE_RANGE                       27:26
#define SOR_NV_PDISP_SOR_PLL2_0_CLKGEN_MODE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_PLL2_0_CLKGEN_MODE_DEFAULT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_CLKGEN_MODE_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_PLL2_0_CLKGEN_MODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_CLKGEN_MODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_CLKGEN_MODE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_CLKGEN_MODE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_CLKGEN_MODE_INIT_ENUM                   DP_TMDS
#define SOR_NV_PDISP_SOR_PLL2_0_CLKGEN_MODE_LVDS                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL2_0_CLKGEN_MODE_DP_TMDS                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_SHIFT                      _MK_SHIFT_CONST(25)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL2_0_AUX9_SHIFT)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_RANGE                      25:25
#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_INIT_ENUM                  LVDSEN_ALLOW
#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_LVDSEN_ALLOW                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_LVDSEN_OVERRIDE                    _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX9__PROD_C_RBR                        _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX9__PROD_C_HBR                        _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX9__PROD_C_HBR2                       _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX9__PROD_C_HBR3                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_SHIFT                      _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL2_0_AUX8_SHIFT)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_RANGE                      24:24
#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_DEFAULT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_INIT_ENUM                  SEQ_PLLCAPPD_ENFORCE_ENABLE
#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_SHIFT                      _MK_SHIFT_CONST(23)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL2_0_AUX7_SHIFT)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_RANGE                      23:23
#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_DEFAULT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_INIT_ENUM                  PORT_POWERDOWN_ENABLE
#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_PORT_POWERDOWN_DISABLE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_PORT_POWERDOWN_ENABLE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_SHIFT                      _MK_SHIFT_CONST(22)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL2_0_AUX6_SHIFT)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_RANGE                      22:22
#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_DEFAULT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_INIT_ENUM                  BANDGAP_POWERDOWN_ENABLE
#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_BANDGAP_POWERDOWN_DISABLE                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_BANDGAP_POWERDOWN_ENABLE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PLL2_0_AUX5_SHIFT                      _MK_SHIFT_CONST(21)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX5_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL2_0_AUX5_SHIFT)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX5_RANGE                      21:21
#define SOR_NV_PDISP_SOR_PLL2_0_AUX5_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_PLL2_0_AUX5_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX5_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX5_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX5_INIT_ENUM                  SINGLE_LINK_LVDS
#define SOR_NV_PDISP_SOR_PLL2_0_AUX5_SINGLE_LINK_LVDS                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX5_DUAL_LINK_LVDS                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PLL2_0_AUX4_SHIFT                      _MK_SHIFT_CONST(20)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX4_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL2_0_AUX4_SHIFT)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX4_RANGE                      20:20
#define SOR_NV_PDISP_SOR_PLL2_0_AUX4_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_PLL2_0_AUX4_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX4_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX4_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX4_INIT_ENUM                  DUPLICATE_CTRL_DISABLE
#define SOR_NV_PDISP_SOR_PLL2_0_AUX4_DUPLICATE_CTRL_DISABLE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX4_DUPLICATE_CTRL_ENABLE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PLL2_0_AUX3_SHIFT                      _MK_SHIFT_CONST(19)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX3_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL2_0_AUX3_SHIFT)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX3_RANGE                      19:19
#define SOR_NV_PDISP_SOR_PLL2_0_AUX3_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_PLL2_0_AUX3_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX3_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX3_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX3_INIT_ENUM                  ROTATE_DISABLE
#define SOR_NV_PDISP_SOR_PLL2_0_AUX3_ROTATE_DISABLE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX3_ROTATE_ENABLE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PLL2_0_AUX2_SHIFT                      _MK_SHIFT_CONST(18)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX2_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL2_0_AUX2_SHIFT)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX2_RANGE                      18:18
#define SOR_NV_PDISP_SOR_PLL2_0_AUX2_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_PLL2_0_AUX2_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX2_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX2_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX2_INIT_ENUM                  OVERRIDE_POWERDOWN
#define SOR_NV_PDISP_SOR_PLL2_0_AUX2_OVERRIDE_POWERDOWN                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX2_ALLOW_POWERDOWN                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PLL2_0_AUX1_SHIFT                      _MK_SHIFT_CONST(17)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX1_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL2_0_AUX1_SHIFT)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX1_RANGE                      17:17
#define SOR_NV_PDISP_SOR_PLL2_0_AUX1_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_PLL2_0_AUX1_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX1_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX1_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX1_INIT_ENUM                  SEQ_PLLCAPPD_ALLOW
#define SOR_NV_PDISP_SOR_PLL2_0_AUX1_SEQ_PLLCAPPD_ALLOW                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX1_SEQ_PLLCAPPD_OVERRIDE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PLL2_0_AUX0_SHIFT                      _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX0_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL2_0_AUX0_SHIFT)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX0_RANGE                      16:16
#define SOR_NV_PDISP_SOR_PLL2_0_AUX0_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_PLL2_0_AUX0_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX0_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX0_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX0_INIT_ENUM                  SEQ_PLL_PULLDOWN_ALLOW
#define SOR_NV_PDISP_SOR_PLL2_0_AUX0_SEQ_PLL_PULLDOWN_ALLOW                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL2_0_AUX0_SEQ_PLL_PULLDOWN_OVERRIDE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_SHIFT                  _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_FIELD                  _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_SHIFT)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_RANGE                  15:8
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_INIT_ENUM                      BY_1
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_BY_1                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_BY_1_1                 _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_BY_2                   _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_BY_3                   _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_BY_4                   _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_BY_5                   _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_BY_6                   _MK_ENUM_CONST(6)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_BY_7                   _MK_ENUM_CONST(7)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_BY_8                   _MK_ENUM_CONST(8)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_BY_9                   _MK_ENUM_CONST(9)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_BY_10                  _MK_ENUM_CONST(10)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_BY_11                  _MK_ENUM_CONST(11)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_BY_12                  _MK_ENUM_CONST(12)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_BY_13                  _MK_ENUM_CONST(13)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_BY_14                  _MK_ENUM_CONST(14)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_BY_15                  _MK_ENUM_CONST(15)

#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_SHIFT                  _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_FIELD                  _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_SHIFT)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_RANGE                  7:4
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_DEFAULT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_INIT_ENUM                      BY_2
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_BY_1                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_BY_2                   _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_BY_4                   _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_BY_8                   _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_BY_16                  _MK_ENUM_CONST(4)

#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_MODE_SHIFT                     _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_MODE_FIELD                     _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_MODE_SHIFT)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_MODE_RANGE                     3:2
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_MODE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_MODE_DEFAULT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_MODE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_MODE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_MODE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_MODE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_MODE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_MODE_INIT_ENUM                 TMDS_DP_MODE
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_MODE_LVDS_MODE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_MODE_TMDS_DP_MODE                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_MODE_EDP_RATE3_MODE                    _MK_ENUM_CONST(2)

#define SOR_NV_PDISP_SOR_PLL2_0_DIV_RATIO_OVERRIDE_SHIFT                        _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_PLL2_0_DIV_RATIO_OVERRIDE_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL2_0_DIV_RATIO_OVERRIDE_SHIFT)
#define SOR_NV_PDISP_SOR_PLL2_0_DIV_RATIO_OVERRIDE_RANGE                        1:1
#define SOR_NV_PDISP_SOR_PLL2_0_DIV_RATIO_OVERRIDE_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_PLL2_0_DIV_RATIO_OVERRIDE_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_DIV_RATIO_OVERRIDE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_DIV_RATIO_OVERRIDE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_DIV_RATIO_OVERRIDE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_DIV_RATIO_OVERRIDE_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_DIV_RATIO_OVERRIDE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_DIV_RATIO_OVERRIDE_INIT_ENUM                    DISABLE
#define SOR_NV_PDISP_SOR_PLL2_0_DIV_RATIO_OVERRIDE_DISABLE                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL2_0_DIV_RATIO_OVERRIDE_ENABLE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PLL2_0_DCIR_PLL_RESET_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_PLL2_0_DCIR_PLL_RESET_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL2_0_DCIR_PLL_RESET_SHIFT)
#define SOR_NV_PDISP_SOR_PLL2_0_DCIR_PLL_RESET_RANGE                    0:0
#define SOR_NV_PDISP_SOR_PLL2_0_DCIR_PLL_RESET_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_PLL2_0_DCIR_PLL_RESET_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_DCIR_PLL_RESET_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_DCIR_PLL_RESET_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_DCIR_PLL_RESET_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL2_0_DCIR_PLL_RESET_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_DCIR_PLL_RESET_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL2_0_DCIR_PLL_RESET_INIT_ENUM                        OVERRIDE
#define SOR_NV_PDISP_SOR_PLL2_0_DCIR_PLL_RESET_OVERRIDE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL2_0_DCIR_PLL_RESET_ALLOW                    _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_PLL3_0
#define SOR_NV_PDISP_SOR_PLL3_0                 _MK_ADDR_CONST(0x16c)
#define SOR_NV_PDISP_SOR_PLL3_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_PLL3_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_PLL3_0_SCR                     0
#define SOR_NV_PDISP_SOR_PLL3_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_PLL3_0_RESET_VAL                       _MK_MASK_CONST(0x38000440)
#define SOR_NV_PDISP_SOR_PLL3_0_RESET_MASK                      _MK_MASK_CONST(0xffff7ff3)
#define SOR_NV_PDISP_SOR_PLL3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL3_0_READ_MASK                       _MK_MASK_CONST(0xffff7ff3)
#define SOR_NV_PDISP_SOR_PLL3_0_WRITE_MASK                      _MK_MASK_CONST(0xffff7ff3)
#define SOR_NV_PDISP_SOR_PLL3_0_BG_TEMP_COEFF_SHIFT                     _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_PLL3_0_BG_TEMP_COEFF_FIELD                     _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_PLL3_0_BG_TEMP_COEFF_SHIFT)
#define SOR_NV_PDISP_SOR_PLL3_0_BG_TEMP_COEFF_RANGE                     31:28
#define SOR_NV_PDISP_SOR_PLL3_0_BG_TEMP_COEFF_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_PLL3_0_BG_TEMP_COEFF_DEFAULT                   _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_PLL3_0_BG_TEMP_COEFF_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_PLL3_0_BG_TEMP_COEFF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL3_0_BG_TEMP_COEFF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL3_0_BG_TEMP_COEFF_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL3_0_BG_TEMP_COEFF_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL3_0_BG_TEMP_COEFF__PROD_C_R_HDMI_0M_54M                     _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_PLL3_0_BG_TEMP_COEFF__PROD_C_R_HDMI_54M_111M                   _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_PLL3_0_BG_TEMP_COEFF__PROD_C_R_HDMI_111M_223M                  _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_PLL3_0_BG_TEMP_COEFF__PROD_C_R_HDMI_223M_300M                  _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_PLL3_0_BG_TEMP_COEFF__PROD_C_R_HDMI_300M_600M                  _MK_ENUM_CONST(3)

#define SOR_NV_PDISP_SOR_PLL3_0_BG_VREF_LEVEL_SHIFT                     _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_PLL3_0_BG_VREF_LEVEL_FIELD                     _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_PLL3_0_BG_VREF_LEVEL_SHIFT)
#define SOR_NV_PDISP_SOR_PLL3_0_BG_VREF_LEVEL_RANGE                     27:24
#define SOR_NV_PDISP_SOR_PLL3_0_BG_VREF_LEVEL_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_PLL3_0_BG_VREF_LEVEL_DEFAULT                   _MK_MASK_CONST(0x8)
#define SOR_NV_PDISP_SOR_PLL3_0_BG_VREF_LEVEL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_PLL3_0_BG_VREF_LEVEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL3_0_BG_VREF_LEVEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL3_0_BG_VREF_LEVEL_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL3_0_BG_VREF_LEVEL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL3_0_BG_VREF_LEVEL__PROD_C_R_HDMI_0M_54M                     _MK_ENUM_CONST(8)
#define SOR_NV_PDISP_SOR_PLL3_0_BG_VREF_LEVEL__PROD_C_R_HDMI_54M_111M                   _MK_ENUM_CONST(8)
#define SOR_NV_PDISP_SOR_PLL3_0_BG_VREF_LEVEL__PROD_C_R_HDMI_111M_223M                  _MK_ENUM_CONST(8)
#define SOR_NV_PDISP_SOR_PLL3_0_BG_VREF_LEVEL__PROD_C_R_HDMI_223M_300M                  _MK_ENUM_CONST(8)
#define SOR_NV_PDISP_SOR_PLL3_0_BG_VREF_LEVEL__PROD_C_R_HDMI_300M_600M                  _MK_ENUM_CONST(8)

#define SOR_NV_PDISP_SOR_PLL3_0_SHALLOW_LOOPBACK_CVDD_SHIFT                     _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_PLL3_0_SHALLOW_LOOPBACK_CVDD_FIELD                     _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_PLL3_0_SHALLOW_LOOPBACK_CVDD_SHIFT)
#define SOR_NV_PDISP_SOR_PLL3_0_SHALLOW_LOOPBACK_CVDD_RANGE                     23:16
#define SOR_NV_PDISP_SOR_PLL3_0_SHALLOW_LOOPBACK_CVDD_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_PLL3_0_SHALLOW_LOOPBACK_CVDD_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL3_0_SHALLOW_LOOPBACK_CVDD_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_PLL3_0_SHALLOW_LOOPBACK_CVDD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL3_0_SHALLOW_LOOPBACK_CVDD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL3_0_SHALLOW_LOOPBACK_CVDD_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL3_0_SHALLOW_LOOPBACK_CVDD_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_PLL3_0_PLL_BYPASS_SHIFT                        _MK_SHIFT_CONST(14)
#define SOR_NV_PDISP_SOR_PLL3_0_PLL_BYPASS_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL3_0_PLL_BYPASS_SHIFT)
#define SOR_NV_PDISP_SOR_PLL3_0_PLL_BYPASS_RANGE                        14:14
#define SOR_NV_PDISP_SOR_PLL3_0_PLL_BYPASS_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_PLL3_0_PLL_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL3_0_PLL_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL3_0_PLL_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL3_0_PLL_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL3_0_PLL_BYPASS_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL3_0_PLL_BYPASS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL3_0_PLL_BYPASS_INIT_ENUM                    DISABLE
#define SOR_NV_PDISP_SOR_PLL3_0_PLL_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL3_0_PLL_BYPASS_ENABLE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PLL3_0_PLLVDD_MODE_SHIFT                       _MK_SHIFT_CONST(13)
#define SOR_NV_PDISP_SOR_PLL3_0_PLLVDD_MODE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL3_0_PLLVDD_MODE_SHIFT)
#define SOR_NV_PDISP_SOR_PLL3_0_PLLVDD_MODE_RANGE                       13:13
#define SOR_NV_PDISP_SOR_PLL3_0_PLLVDD_MODE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_PLL3_0_PLLVDD_MODE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL3_0_PLLVDD_MODE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL3_0_PLLVDD_MODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL3_0_PLLVDD_MODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL3_0_PLLVDD_MODE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL3_0_PLLVDD_MODE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL3_0_PLLVDD_MODE_INIT_ENUM                   V1_8
#define SOR_NV_PDISP_SOR_PLL3_0_PLLVDD_MODE_V1_8                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL3_0_PLLVDD_MODE_V3_3                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PLL3_0_KVCO_2NDVCO_SHIFT                       _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_PLL3_0_KVCO_2NDVCO_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL3_0_KVCO_2NDVCO_SHIFT)
#define SOR_NV_PDISP_SOR_PLL3_0_KVCO_2NDVCO_RANGE                       12:12
#define SOR_NV_PDISP_SOR_PLL3_0_KVCO_2NDVCO_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_PLL3_0_KVCO_2NDVCO_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL3_0_KVCO_2NDVCO_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL3_0_KVCO_2NDVCO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL3_0_KVCO_2NDVCO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL3_0_KVCO_2NDVCO_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL3_0_KVCO_2NDVCO_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL3_0_KVCO_2NDVCO_INIT_ENUM                   DISABLE
#define SOR_NV_PDISP_SOR_PLL3_0_KVCO_2NDVCO_DISABLE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL3_0_KVCO_2NDVCO_ENABLE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_SHIFT                      _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_FIELD                      _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_SHIFT)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_RANGE                      11:8
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_DEFAULT                    _MK_MASK_CONST(0x4)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_INIT_ENUM                  V1_00
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_V0_80                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_V0_85                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_V0_90                      _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_V0_95                      _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_V1_00                      _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_V1_05                      _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_V1_10                      _MK_ENUM_CONST(6)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_V1_15                      _MK_ENUM_CONST(7)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL__PROD_C_R_HDMI_0M_54M                      _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL__PROD_C_R_HDMI_54M_111M                    _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL__PROD_C_R_HDMI_111M_223M                   _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL__PROD_C_R_HDMI_223M_300M                   _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL__PROD_C_R_HDMI_300M_600M                   _MK_ENUM_CONST(4)

#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_SHIFT                      _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_FIELD                      _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_SHIFT)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_RANGE                      7:4
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_DEFAULT                    _MK_MASK_CONST(0x4)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_INIT_ENUM                  V1_40
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_V1_12                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_V1_19                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_V1_26                      _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_V1_33                      _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_V1_40                      _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_V1_47                      _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_V1_54                      _MK_ENUM_CONST(6)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_V1_61                      _MK_ENUM_CONST(7)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL__PROD_C_R_HDMI_0M_54M                      _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL__PROD_C_R_HDMI_54M_111M                    _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL__PROD_C_R_HDMI_111M_223M                   _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL__PROD_C_R_HDMI_223M_300M                   _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL__PROD_C_R_HDMI_300M_600M                   _MK_ENUM_CONST(4)

#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_FIELD                 _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_SHIFT)
#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_RANGE                 1:0
#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_INIT_ENUM                     DISABLE
#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_DISABLE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_LOOP_75                       _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_LOOP_67                       _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_LOOP_54_4                     _MK_ENUM_CONST(3)

// Register SOR_NV_PDISP_SOR_PLL4_0
#define SOR_NV_PDISP_SOR_PLL4_0                 _MK_ADDR_CONST(0x16d)
#define SOR_NV_PDISP_SOR_PLL4_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_PLL4_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_PLL4_0_SCR                     0
#define SOR_NV_PDISP_SOR_PLL4_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_PLL4_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_RESET_MASK                      _MK_MASK_CONST(0x3fc1fff1)
#define SOR_NV_PDISP_SOR_PLL4_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_READ_MASK                       _MK_MASK_CONST(0x3fe1fff1)
#define SOR_NV_PDISP_SOR_PLL4_0_WRITE_MASK                      _MK_MASK_CONST(0x3fc01ff0)
#define SOR_NV_PDISP_SOR_PLL4_0_SETUP_LCKDET_SHIFT                      _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_PLL4_0_SETUP_LCKDET_FIELD                      _MK_FIELD_CONST(0x3f, SOR_NV_PDISP_SOR_PLL4_0_SETUP_LCKDET_SHIFT)
#define SOR_NV_PDISP_SOR_PLL4_0_SETUP_LCKDET_RANGE                      29:24
#define SOR_NV_PDISP_SOR_PLL4_0_SETUP_LCKDET_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_PLL4_0_SETUP_LCKDET_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_SETUP_LCKDET_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
#define SOR_NV_PDISP_SOR_PLL4_0_SETUP_LCKDET_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_SETUP_LCKDET_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_SETUP_LCKDET_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL4_0_SETUP_LCKDET_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_PLL4_0_LOCK_OVERRIDE_SHIFT                     _MK_SHIFT_CONST(23)
#define SOR_NV_PDISP_SOR_PLL4_0_LOCK_OVERRIDE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL4_0_LOCK_OVERRIDE_SHIFT)
#define SOR_NV_PDISP_SOR_PLL4_0_LOCK_OVERRIDE_RANGE                     23:23
#define SOR_NV_PDISP_SOR_PLL4_0_LOCK_OVERRIDE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_PLL4_0_LOCK_OVERRIDE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_LOCK_OVERRIDE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL4_0_LOCK_OVERRIDE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_LOCK_OVERRIDE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_LOCK_OVERRIDE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL4_0_LOCK_OVERRIDE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL4_0_LOCK_OVERRIDE_INIT_ENUM                 DISABLE
#define SOR_NV_PDISP_SOR_PLL4_0_LOCK_OVERRIDE_DISABLE                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL4_0_LOCK_OVERRIDE_ENABLE                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PLL4_0_ENB_LCKDET_SHIFT                        _MK_SHIFT_CONST(22)
#define SOR_NV_PDISP_SOR_PLL4_0_ENB_LCKDET_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL4_0_ENB_LCKDET_SHIFT)
#define SOR_NV_PDISP_SOR_PLL4_0_ENB_LCKDET_RANGE                        22:22
#define SOR_NV_PDISP_SOR_PLL4_0_ENB_LCKDET_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_PLL4_0_ENB_LCKDET_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_ENB_LCKDET_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL4_0_ENB_LCKDET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_ENB_LCKDET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_ENB_LCKDET_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL4_0_ENB_LCKDET_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL4_0_ENB_LCKDET_INIT_ENUM                    ENABLE
#define SOR_NV_PDISP_SOR_PLL4_0_ENB_LCKDET_ENABLE                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL4_0_ENB_LCKDET_DISABLE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PLL4_0_LOCKDET_SHIFT                   _MK_SHIFT_CONST(21)
#define SOR_NV_PDISP_SOR_PLL4_0_LOCKDET_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL4_0_LOCKDET_SHIFT)
#define SOR_NV_PDISP_SOR_PLL4_0_LOCKDET_RANGE                   21:21
#define SOR_NV_PDISP_SOR_PLL4_0_LOCKDET_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_PLL4_0_LOCKDET_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_LOCKDET_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_LOCKDET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_LOCKDET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_LOCKDET_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_LOCKDET_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_PLL4_0_SLOWCLK_OUT_SHIFT                       _MK_SHIFT_CONST(13)
#define SOR_NV_PDISP_SOR_PLL4_0_SLOWCLK_OUT_FIELD                       _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_PLL4_0_SLOWCLK_OUT_SHIFT)
#define SOR_NV_PDISP_SOR_PLL4_0_SLOWCLK_OUT_RANGE                       16:13
#define SOR_NV_PDISP_SOR_PLL4_0_SLOWCLK_OUT_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_PLL4_0_SLOWCLK_OUT_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_SLOWCLK_OUT_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_PLL4_0_SLOWCLK_OUT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_SLOWCLK_OUT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_SLOWCLK_OUT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_SLOWCLK_OUT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_PLL4_0_PLL_MODE_SHIFT                  _MK_SHIFT_CONST(11)
#define SOR_NV_PDISP_SOR_PLL4_0_PLL_MODE_FIELD                  _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_PLL4_0_PLL_MODE_SHIFT)
#define SOR_NV_PDISP_SOR_PLL4_0_PLL_MODE_RANGE                  12:11
#define SOR_NV_PDISP_SOR_PLL4_0_PLL_MODE_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_PLL4_0_PLL_MODE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_PLL_MODE_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_PLL4_0_PLL_MODE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_PLL_MODE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_PLL_MODE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL4_0_PLL_MODE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_PLL4_0_TX_BIAS_SHIFT                   _MK_SHIFT_CONST(9)
#define SOR_NV_PDISP_SOR_PLL4_0_TX_BIAS_FIELD                   _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_PLL4_0_TX_BIAS_SHIFT)
#define SOR_NV_PDISP_SOR_PLL4_0_TX_BIAS_RANGE                   10:9
#define SOR_NV_PDISP_SOR_PLL4_0_TX_BIAS_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_PLL4_0_TX_BIAS_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_TX_BIAS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_PLL4_0_TX_BIAS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_TX_BIAS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_TX_BIAS_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL4_0_TX_BIAS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_PLL4_0_SLOWCLK_OUT_SEL_SHIFT                   _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_PLL4_0_SLOWCLK_OUT_SEL_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL4_0_SLOWCLK_OUT_SEL_SHIFT)
#define SOR_NV_PDISP_SOR_PLL4_0_SLOWCLK_OUT_SEL_RANGE                   8:8
#define SOR_NV_PDISP_SOR_PLL4_0_SLOWCLK_OUT_SEL_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_PLL4_0_SLOWCLK_OUT_SEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_SLOWCLK_OUT_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL4_0_SLOWCLK_OUT_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_SLOWCLK_OUT_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_SLOWCLK_OUT_SEL_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL4_0_SLOWCLK_OUT_SEL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_PLL4_0_AVDD10_LOAD_SHIFT                       _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_SOR_PLL4_0_AVDD10_LOAD_FIELD                       _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_PLL4_0_AVDD10_LOAD_SHIFT)
#define SOR_NV_PDISP_SOR_PLL4_0_AVDD10_LOAD_RANGE                       7:6
#define SOR_NV_PDISP_SOR_PLL4_0_AVDD10_LOAD_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_PLL4_0_AVDD10_LOAD_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_AVDD10_LOAD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_PLL4_0_AVDD10_LOAD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_AVDD10_LOAD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_AVDD10_LOAD_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL4_0_AVDD10_LOAD_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL4_0_AVDD10_LOAD_MA_0                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL4_0_AVDD10_LOAD_MA_1                        _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PLL4_0_AVDD10_LOAD_MA_2                        _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_PLL4_0_AVDD10_LOAD_MA_3                        _MK_ENUM_CONST(3)

#define SOR_NV_PDISP_SOR_PLL4_0_AVDD14_LOAD_SHIFT                       _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_PLL4_0_AVDD14_LOAD_FIELD                       _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_PLL4_0_AVDD14_LOAD_SHIFT)
#define SOR_NV_PDISP_SOR_PLL4_0_AVDD14_LOAD_RANGE                       5:4
#define SOR_NV_PDISP_SOR_PLL4_0_AVDD14_LOAD_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_PLL4_0_AVDD14_LOAD_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_AVDD14_LOAD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_PLL4_0_AVDD14_LOAD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_AVDD14_LOAD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_AVDD14_LOAD_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL4_0_AVDD14_LOAD_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL4_0_AVDD14_LOAD_UA_0                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL4_0_AVDD14_LOAD_UA_175                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PLL4_0_AVDD14_LOAD_UA_350                      _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_PLL4_0_AVDD14_LOAD_UA_525                      _MK_ENUM_CONST(3)

#define SOR_NV_PDISP_SOR_PLL4_0_MACROPLL_LOCK_READY_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_PLL4_0_MACROPLL_LOCK_READY_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL4_0_MACROPLL_LOCK_READY_SHIFT)
#define SOR_NV_PDISP_SOR_PLL4_0_MACROPLL_LOCK_READY_RANGE                       0:0
#define SOR_NV_PDISP_SOR_PLL4_0_MACROPLL_LOCK_READY_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_PLL4_0_MACROPLL_LOCK_READY_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_MACROPLL_LOCK_READY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL4_0_MACROPLL_LOCK_READY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_MACROPLL_LOCK_READY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_MACROPLL_LOCK_READY_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL4_0_MACROPLL_LOCK_READY_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL4_0_MACROPLL_LOCK_READY_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_PLL4_0_MACROPLL_LOCK_READY_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL4_0_MACROPLL_LOCK_READY_YES                 _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_DP_PADCTL0_0
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0                   _MK_ADDR_CONST(0x16e)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SCR                       0
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_RESET_VAL                         _MK_MASK_CONST(0x800000)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOLIMIT_DISABLE_SHIFT                    _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOLIMIT_DISABLE_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOLIMIT_DISABLE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOLIMIT_DISABLE_RANGE                    31:31
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOLIMIT_DISABLE_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOLIMIT_DISABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOLIMIT_DISABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOLIMIT_DISABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOLIMIT_DISABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOLIMIT_DISABLE_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOLIMIT_DISABLE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOLIMIT_DISABLE_INIT_ENUM                        DISABLE
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOLIMIT_DISABLE_DISABLE                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOLIMIT_DISABLE_ENABLE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_TS0_SHIFT                        _MK_SHIFT_CONST(30)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_TS0_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_TS0_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_TS0_RANGE                        30:30
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_TS0_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_TS0_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_TS0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_TS0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_TS0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_TS0_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_TS0_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_OVERWRB_SHIFT                    _MK_SHIFT_CONST(29)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_OVERWRB_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_OVERWRB_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_OVERWRB_RANGE                    29:29
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_OVERWRB_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_OVERWRB_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_OVERWRB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_OVERWRB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_OVERWRB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_OVERWRB_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_OVERWRB_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_OVERWRB_INIT_ENUM                        DISABLE
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_OVERWRB_DISABLE                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_OVERWRB_ENABLE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_EN_SHIFT                 _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_EN_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_EN_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_EN_RANGE                 28:28
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_EN_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOCALIB_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_LOADADJ_BYPN_SHIFT                        _MK_SHIFT_CONST(27)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_LOADADJ_BYPN_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_LOADADJ_BYPN_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_LOADADJ_BYPN_RANGE                        27:27
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_LOADADJ_BYPN_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_LOADADJ_BYPN_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_LOADADJ_BYPN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_LOADADJ_BYPN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_LOADADJ_BYPN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_LOADADJ_BYPN_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_LOADADJ_BYPN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_LOADADJ_BYPN_INIT_ENUM                    DISABLE
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_LOADADJ_BYPN_DISABLE                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_LOADADJ_BYPN_ENABLE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_LOADADJ_SYNC_EN_SHIFT                     _MK_SHIFT_CONST(26)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_LOADADJ_SYNC_EN_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_LOADADJ_SYNC_EN_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_LOADADJ_SYNC_EN_RANGE                     26:26
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_LOADADJ_SYNC_EN_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_LOADADJ_SYNC_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_LOADADJ_SYNC_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_LOADADJ_SYNC_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_LOADADJ_SYNC_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_LOADADJ_SYNC_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_LOADADJ_SYNC_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOLIMIT_SEL_SHIFT                        _MK_SHIFT_CONST(25)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOLIMIT_SEL_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOLIMIT_SEL_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOLIMIT_SEL_RANGE                        25:25
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOLIMIT_SEL_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOLIMIT_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOLIMIT_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOLIMIT_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOLIMIT_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOLIMIT_SEL_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCOLIMIT_SEL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SELVCO_SHIFT                      _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SELVCO_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_SELVCO_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SELVCO_RANGE                      24:24
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SELVCO_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SELVCO_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SELVCO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SELVCO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SELVCO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SELVCO_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SELVCO_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SELVCO_INIT_ENUM                  DISABLE
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SELVCO_DISABLE                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SELVCO_ENABLE                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PAD_CAL_PD_SHIFT                  _MK_SHIFT_CONST(23)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PAD_CAL_PD_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_PAD_CAL_PD_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PAD_CAL_PD_RANGE                  23:23
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PAD_CAL_PD_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PAD_CAL_PD_DEFAULT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PAD_CAL_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PAD_CAL_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PAD_CAL_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PAD_CAL_PD_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PAD_CAL_PD_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PAD_CAL_PD_INIT_ENUM                      POWERDOWN
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PAD_CAL_PD_POWERUP                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PAD_CAL_PD_POWERDOWN                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_SHIFT                       _MK_SHIFT_CONST(22)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_RANGE                       22:22
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_INIT_ENUM                   DISABLE
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_DISABLE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_ENABLE                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU__PROD_C_R_HDMI_0M_54M                       _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU__PROD_C_R_HDMI_54M_111M                     _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU__PROD_C_R_HDMI_111M_223M                    _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU__PROD_C_R_HDMI_223M_300M                    _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU__PROD_C_R_HDMI_300M_600M                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_REG_CTRL_SHIFT                    _MK_SHIFT_CONST(20)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_REG_CTRL_FIELD                    _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_DP_PADCTL0_0_REG_CTRL_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_REG_CTRL_RANGE                    21:20
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_REG_CTRL_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_REG_CTRL_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_REG_CTRL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_REG_CTRL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_REG_CTRL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_REG_CTRL_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_REG_CTRL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_SHIFT                     _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_FIELD                     _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_RANGE                     19:16
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_INIT_ENUM                 TRISTATE
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_TRISTATE                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_TEST_MUX                  _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_WEAK_PULLDOWN                     _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_STRONG_PULLDOWN                   _MK_ENUM_CONST(4)

#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_SHIFT                 _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_RANGE                 15:8
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE__PROD_C_R_HDMI_0M_54M                 _MK_ENUM_CONST(16)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE__PROD_C_R_HDMI_54M_111M                       _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE__PROD_C_R_HDMI_111M_223M                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE__PROD_C_R_HDMI_223M_300M                      _MK_ENUM_CONST(64)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE__PROD_C_R_HDMI_300M_600M                      _MK_ENUM_CONST(96)

#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_3_DP_TXD_3_SHIFT                   _MK_SHIFT_CONST(7)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_3_DP_TXD_3_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_3_DP_TXD_3_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_3_DP_TXD_3_RANGE                   7:7
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_3_DP_TXD_3_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_3_DP_TXD_3_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_3_DP_TXD_3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_3_DP_TXD_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_3_DP_TXD_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_3_DP_TXD_3_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_3_DP_TXD_3_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_3_DP_TXD_3_INIT_ENUM                       DISABLE
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_3_DP_TXD_3_DISABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_3_DP_TXD_3_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_2_DP_TXD_0_SHIFT                   _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_2_DP_TXD_0_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_2_DP_TXD_0_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_2_DP_TXD_0_RANGE                   6:6
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_2_DP_TXD_0_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_2_DP_TXD_0_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_2_DP_TXD_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_2_DP_TXD_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_2_DP_TXD_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_2_DP_TXD_0_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_2_DP_TXD_0_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_2_DP_TXD_0_INIT_ENUM                       DISABLE
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_2_DP_TXD_0_DISABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_2_DP_TXD_0_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_1_DP_TXD_1_SHIFT                   _MK_SHIFT_CONST(5)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_1_DP_TXD_1_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_1_DP_TXD_1_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_1_DP_TXD_1_RANGE                   5:5
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_1_DP_TXD_1_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_1_DP_TXD_1_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_1_DP_TXD_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_1_DP_TXD_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_1_DP_TXD_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_1_DP_TXD_1_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_1_DP_TXD_1_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_1_DP_TXD_1_INIT_ENUM                       DISABLE
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_1_DP_TXD_1_DISABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_1_DP_TXD_1_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_0_DP_TXD_2_SHIFT                   _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_0_DP_TXD_2_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_0_DP_TXD_2_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_0_DP_TXD_2_RANGE                   4:4
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_0_DP_TXD_2_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_0_DP_TXD_2_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_0_DP_TXD_2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_0_DP_TXD_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_0_DP_TXD_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_0_DP_TXD_2_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_0_DP_TXD_2_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_0_DP_TXD_2_INIT_ENUM                       DISABLE
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_0_DP_TXD_2_DISABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_0_DP_TXD_2_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_3_SHIFT                    _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_3_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_3_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_3_RANGE                    3:3
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_3_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_3_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_3_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_3_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_3_INIT_ENUM                        YES
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_3_YES                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_3_NO                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_0_SHIFT                    _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_0_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_0_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_0_RANGE                    2:2
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_0_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_0_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_0_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_0_INIT_ENUM                        YES
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_0_YES                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_0_NO                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_1_SHIFT                    _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_1_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_1_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_1_RANGE                    1:1
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_1_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_1_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_1_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_1_INIT_ENUM                        YES
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_1_YES                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_1_NO                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_2_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_2_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_2_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_2_RANGE                    0:0
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_2_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_2_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_2_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_2_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_2_INIT_ENUM                        YES
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_2_YES                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_2_NO                       _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_DP_PADCTL1_0
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0                   _MK_ADDR_CONST(0x16f)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SCR                       0
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOLIMIT_DISABLE_SHIFT                    _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOLIMIT_DISABLE_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOLIMIT_DISABLE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOLIMIT_DISABLE_RANGE                    31:31
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOLIMIT_DISABLE_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOLIMIT_DISABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOLIMIT_DISABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOLIMIT_DISABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOLIMIT_DISABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOLIMIT_DISABLE_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOLIMIT_DISABLE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOLIMIT_DISABLE_INIT_ENUM                        DISABLE
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOLIMIT_DISABLE_DISABLE                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOLIMIT_DISABLE_ENABLE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_TS0_SHIFT                        _MK_SHIFT_CONST(30)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_TS0_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_TS0_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_TS0_RANGE                        30:30
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_TS0_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_TS0_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_TS0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_TS0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_TS0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_TS0_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_TS0_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_OVERWRB_SHIFT                    _MK_SHIFT_CONST(29)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_OVERWRB_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_OVERWRB_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_OVERWRB_RANGE                    29:29
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_OVERWRB_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_OVERWRB_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_OVERWRB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_OVERWRB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_OVERWRB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_OVERWRB_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_OVERWRB_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_OVERWRB_INIT_ENUM                        DISABLE
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_OVERWRB_DISABLE                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_OVERWRB_ENABLE                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_EN_SHIFT                 _MK_SHIFT_CONST(28)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_EN_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_EN_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_EN_RANGE                 28:28
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_EN_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOCALIB_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_LOADADJ_BYPN_SHIFT                        _MK_SHIFT_CONST(27)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_LOADADJ_BYPN_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_LOADADJ_BYPN_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_LOADADJ_BYPN_RANGE                        27:27
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_LOADADJ_BYPN_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_LOADADJ_BYPN_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_LOADADJ_BYPN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_LOADADJ_BYPN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_LOADADJ_BYPN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_LOADADJ_BYPN_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_LOADADJ_BYPN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_LOADADJ_BYPN_INIT_ENUM                    DISABLE
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_LOADADJ_BYPN_DISABLE                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_LOADADJ_BYPN_ENABLE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_LOADADJ_SYNC_EN_SHIFT                     _MK_SHIFT_CONST(26)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_LOADADJ_SYNC_EN_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_LOADADJ_SYNC_EN_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_LOADADJ_SYNC_EN_RANGE                     26:26
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_LOADADJ_SYNC_EN_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_LOADADJ_SYNC_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_LOADADJ_SYNC_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_LOADADJ_SYNC_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_LOADADJ_SYNC_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_LOADADJ_SYNC_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_LOADADJ_SYNC_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOLIMIT_SEL_SHIFT                        _MK_SHIFT_CONST(25)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOLIMIT_SEL_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOLIMIT_SEL_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOLIMIT_SEL_RANGE                        25:25
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOLIMIT_SEL_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOLIMIT_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOLIMIT_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOLIMIT_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOLIMIT_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOLIMIT_SEL_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCOLIMIT_SEL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SELVCO_SHIFT                      _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SELVCO_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_SELVCO_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SELVCO_RANGE                      24:24
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SELVCO_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SELVCO_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SELVCO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SELVCO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SELVCO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SELVCO_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SELVCO_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SELVCO_INIT_ENUM                  DISABLE
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SELVCO_DISABLE                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SELVCO_ENABLE                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PAD_CAL_PD_SHIFT                  _MK_SHIFT_CONST(23)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PAD_CAL_PD_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_PAD_CAL_PD_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PAD_CAL_PD_RANGE                  23:23
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PAD_CAL_PD_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PAD_CAL_PD_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PAD_CAL_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PAD_CAL_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PAD_CAL_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PAD_CAL_PD_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PAD_CAL_PD_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PAD_CAL_PD_INIT_ENUM                      POWERUP
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PAD_CAL_PD_POWERUP                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PAD_CAL_PD_POWERDOWN                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_SHIFT                       _MK_SHIFT_CONST(22)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_RANGE                       22:22
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_INIT_ENUM                   DISABLE
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_DISABLE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_ENABLE                      _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_REG_CTRL_SHIFT                    _MK_SHIFT_CONST(20)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_REG_CTRL_FIELD                    _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_DP_PADCTL1_0_REG_CTRL_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_REG_CTRL_RANGE                    21:20
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_REG_CTRL_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_REG_CTRL_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_REG_CTRL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_REG_CTRL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_REG_CTRL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_REG_CTRL_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_REG_CTRL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_SHIFT                     _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_FIELD                     _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_RANGE                     19:16
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_INIT_ENUM                 TRISTATE
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_TRISTATE                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_TEST_MUX                  _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_WEAK_PULLDOWN                     _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_STRONG_PULLDOWN                   _MK_ENUM_CONST(4)

#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_VALUE_SHIFT                 _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_VALUE_FIELD                 _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_VALUE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_VALUE_RANGE                 15:8
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_VALUE_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_VALUE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_VALUE_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_VALUE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_VALUE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_VALUE_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_VALUE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_3_DP_TXD_3_SHIFT                   _MK_SHIFT_CONST(7)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_3_DP_TXD_3_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_3_DP_TXD_3_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_3_DP_TXD_3_RANGE                   7:7
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_3_DP_TXD_3_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_3_DP_TXD_3_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_3_DP_TXD_3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_3_DP_TXD_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_3_DP_TXD_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_3_DP_TXD_3_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_3_DP_TXD_3_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_3_DP_TXD_3_INIT_ENUM                       DISABLE
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_3_DP_TXD_3_DISABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_3_DP_TXD_3_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_2_DP_TXD_0_SHIFT                   _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_2_DP_TXD_0_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_2_DP_TXD_0_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_2_DP_TXD_0_RANGE                   6:6
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_2_DP_TXD_0_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_2_DP_TXD_0_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_2_DP_TXD_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_2_DP_TXD_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_2_DP_TXD_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_2_DP_TXD_0_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_2_DP_TXD_0_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_2_DP_TXD_0_INIT_ENUM                       DISABLE
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_2_DP_TXD_0_DISABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_2_DP_TXD_0_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_1_DP_TXD_1_SHIFT                   _MK_SHIFT_CONST(5)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_1_DP_TXD_1_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_1_DP_TXD_1_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_1_DP_TXD_1_RANGE                   5:5
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_1_DP_TXD_1_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_1_DP_TXD_1_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_1_DP_TXD_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_1_DP_TXD_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_1_DP_TXD_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_1_DP_TXD_1_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_1_DP_TXD_1_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_1_DP_TXD_1_INIT_ENUM                       DISABLE
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_1_DP_TXD_1_DISABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_1_DP_TXD_1_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_0_DP_TXD_2_SHIFT                   _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_0_DP_TXD_2_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_0_DP_TXD_2_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_0_DP_TXD_2_RANGE                   4:4
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_0_DP_TXD_2_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_0_DP_TXD_2_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_0_DP_TXD_2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_0_DP_TXD_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_0_DP_TXD_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_0_DP_TXD_2_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_0_DP_TXD_2_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_0_DP_TXD_2_INIT_ENUM                       DISABLE
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_0_DP_TXD_2_DISABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_0_DP_TXD_2_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_3_SHIFT                    _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_3_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_3_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_3_RANGE                    3:3
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_3_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_3_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_3_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_3_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_3_INIT_ENUM                        YES
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_3_YES                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_3_NO                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_0_SHIFT                    _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_0_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_0_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_0_RANGE                    2:2
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_0_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_0_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_0_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_0_INIT_ENUM                        YES
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_0_YES                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_0_NO                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_1_SHIFT                    _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_1_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_1_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_1_RANGE                    1:1
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_1_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_1_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_1_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_1_INIT_ENUM                        YES
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_1_YES                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_1_NO                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_2_SHIFT                    _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_2_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_2_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_2_RANGE                    0:0
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_2_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_2_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_2_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_2_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_2_INIT_ENUM                        YES
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_2_YES                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_2_NO                       _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_DP_PADCTL2_0
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0                   _MK_ADDR_CONST(0x170)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SCR                       0
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_RESET_MASK                        _MK_MASK_CONST(0xfffffff1)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_READ_MASK                         _MK_MASK_CONST(0xfffffff1)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_WRITE_MASK                        _MK_MASK_CONST(0xfffffff1)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPAREPLL_SHIFT                    _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPAREPLL_FIELD                    _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPAREPLL_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPAREPLL_RANGE                    31:24
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPAREPLL_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPAREPLL_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPAREPLL_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPAREPLL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPAREPLL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPAREPLL_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPAREPLL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPAREPLL__PROD_C_R_HDMI_0M_54M                    _MK_ENUM_CONST(84)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPAREPLL__PROD_C_R_HDMI_54M_111M                  _MK_ENUM_CONST(68)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPAREPLL__PROD_C_R_HDMI_111M_223M                 _MK_ENUM_CONST(52)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPAREPLL__PROD_C_R_HDMI_223M_300M                 _MK_ENUM_CONST(52)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPAREPLL__PROD_C_R_HDMI_300M_600M                 _MK_ENUM_CONST(52)

#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE4_SHIFT                      _MK_SHIFT_CONST(20)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE4_FIELD                      _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE4_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE4_RANGE                      23:20
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE4_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE4_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE4_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE4_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE4_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE3_SHIFT                      _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE3_FIELD                      _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE3_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE3_RANGE                      19:16
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE3_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE3_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE3_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE3_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE3_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE0_SHIFT                      _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE0_FIELD                      _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE0_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE0_RANGE                      15:12
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE0_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE0_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE0_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE0_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE0_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE1_SHIFT                      _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE1_FIELD                      _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE1_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE1_RANGE                      11:8
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE1_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE1_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE1_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE1_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE1_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE2_SHIFT                      _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE2_FIELD                      _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE2_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE2_RANGE                      7:4
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE2_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE2_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE2_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE2_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_SPARE2_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_REG_BYPASS_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_REG_BYPASS_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL2_0_REG_BYPASS_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_REG_BYPASS_RANGE                  0:0
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_REG_BYPASS_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_REG_BYPASS_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_REG_BYPASS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_REG_BYPASS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_REG_BYPASS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_REG_BYPASS_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL2_0_REG_BYPASS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_PADCTL3_0
#define SOR_NV_PDISP_SOR_DP_PADCTL3_0                   _MK_ADDR_CONST(0x171)
#define SOR_NV_PDISP_SOR_DP_PADCTL3_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL3_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL3_0_SCR                       0
#define SOR_NV_PDISP_SOR_DP_PADCTL3_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_DP_PADCTL3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL3_0_RESET_MASK                        _MK_MASK_CONST(0xff000000)
#define SOR_NV_PDISP_SOR_DP_PADCTL3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL3_0_READ_MASK                         _MK_MASK_CONST(0xff000000)
#define SOR_NV_PDISP_SOR_DP_PADCTL3_0_WRITE_MASK                        _MK_MASK_CONST(0xff000000)
#define SOR_NV_PDISP_SOR_DP_PADCTL3_0_TX_PATTERN_GEN_SHIFT                      _MK_SHIFT_CONST(24)
#define SOR_NV_PDISP_SOR_DP_PADCTL3_0_TX_PATTERN_GEN_FIELD                      _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_PADCTL3_0_TX_PATTERN_GEN_SHIFT)
#define SOR_NV_PDISP_SOR_DP_PADCTL3_0_TX_PATTERN_GEN_RANGE                      31:24
#define SOR_NV_PDISP_SOR_DP_PADCTL3_0_TX_PATTERN_GEN_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_PADCTL3_0_TX_PATTERN_GEN_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL3_0_TX_PATTERN_GEN_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define SOR_NV_PDISP_SOR_DP_PADCTL3_0_TX_PATTERN_GEN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL3_0_TX_PATTERN_GEN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_PADCTL3_0_TX_PATTERN_GEN_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_PADCTL3_0_TX_PATTERN_GEN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_BS_0
#define SOR_NV_PDISP_SOR_DP_BS_0                        _MK_ADDR_CONST(0x172)
#define SOR_NV_PDISP_SOR_DP_BS_0_SECURE                         0x0
#define SOR_NV_PDISP_SOR_DP_BS_0_DUAL                   0x0
#define SOR_NV_PDISP_SOR_DP_BS_0_SCR                    0
#define SOR_NV_PDISP_SOR_DP_BS_0_WORD_COUNT                     0x1
#define SOR_NV_PDISP_SOR_DP_BS_0_RESET_VAL                      _MK_MASK_CONST(0x4)
#define SOR_NV_PDISP_SOR_DP_BS_0_RESET_MASK                     _MK_MASK_CONST(0x803ff)
#define SOR_NV_PDISP_SOR_DP_BS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_BS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_BS_0_READ_MASK                      _MK_MASK_CONST(0xfffff)
#define SOR_NV_PDISP_SOR_DP_BS_0_WRITE_MASK                     _MK_MASK_CONST(0x801ff)
#define SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_SHIFT                 _MK_SHIFT_CONST(19)
#define SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_RANGE                 19:19
#define SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_INIT_ENUM                     DONE
#define SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_DONE                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_TRIGGER                       _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_PENDING                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_BS_0_CNT_STATUS_SHIFT                       _MK_SHIFT_CONST(10)
#define SOR_NV_PDISP_SOR_DP_BS_0_CNT_STATUS_FIELD                       _MK_FIELD_CONST(0x1ff, SOR_NV_PDISP_SOR_DP_BS_0_CNT_STATUS_SHIFT)
#define SOR_NV_PDISP_SOR_DP_BS_0_CNT_STATUS_RANGE                       18:10
#define SOR_NV_PDISP_SOR_DP_BS_0_CNT_STATUS_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_DP_BS_0_CNT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_BS_0_CNT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_BS_0_CNT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_BS_0_CNT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_BS_0_CNT_STATUS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_BS_0_CNT_STATUS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_DEBUG_SHIFT                   _MK_SHIFT_CONST(9)
#define SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_DEBUG_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_DEBUG_SHIFT)
#define SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_DEBUG_RANGE                   9:9
#define SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_DEBUG_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_DEBUG_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_DEBUG_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_DEBUG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_DEBUG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_DEBUG_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_DEBUG_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_DEBUG_INIT_ENUM                       DONE
#define SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_DEBUG_DONE                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_BS_0_OVERRIDE_DEBUG_PENDING                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_BS_0_CNT_SHIFT                      _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_BS_0_CNT_FIELD                      _MK_FIELD_CONST(0x1ff, SOR_NV_PDISP_SOR_DP_BS_0_CNT_SHIFT)
#define SOR_NV_PDISP_SOR_DP_BS_0_CNT_RANGE                      8:0
#define SOR_NV_PDISP_SOR_DP_BS_0_CNT_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_BS_0_CNT_DEFAULT                    _MK_MASK_CONST(0x4)
#define SOR_NV_PDISP_SOR_DP_BS_0_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0x1ff)
#define SOR_NV_PDISP_SOR_DP_BS_0_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_BS_0_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_BS_0_CNT_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_BS_0_CNT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0                    _MK_ADDR_CONST(0x173)
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_SECURE                     0x0
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_DUAL                       0x0
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_SCR                        0
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_RESET_MASK                         _MK_MASK_CONST(0x80000001)
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_READ_MASK                  _MK_MASK_CONST(0x80000001)
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_WRITE_MASK                         _MK_MASK_CONST(0x80000001)
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_ENABLE_SHIFT)
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_ENABLE_RANGE                       0:0
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_ENABLE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_ENABLE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_ENABLE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_ENABLE_INIT_ENUM                   NO
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_ENABLE_NO                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_ENABLE_YES                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_CNTL_SHIFT                 _MK_SHIFT_CONST(31)
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_CNTL_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_CNTL_SHIFT)
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_CNTL_RANGE                 31:31
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_CNTL_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_CNTL_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_CNTL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_CNTL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_CNTL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_CNTL_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_CNTL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_CNTL_INIT_ENUM                     DONE
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_CNTL_DONE                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_CNTL_TRIGGER                       _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0_CNTL_PENDING                       _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_DP_MISC1_BIT6_0
#define SOR_NV_PDISP_SOR_DP_MISC1_BIT6_0                        _MK_ADDR_CONST(0x174)
#define SOR_NV_PDISP_SOR_DP_MISC1_BIT6_0_SECURE                         0x0
#define SOR_NV_PDISP_SOR_DP_MISC1_BIT6_0_DUAL                   0x0
#define SOR_NV_PDISP_SOR_DP_MISC1_BIT6_0_SCR                    0
#define SOR_NV_PDISP_SOR_DP_MISC1_BIT6_0_WORD_COUNT                     0x1
#define SOR_NV_PDISP_SOR_DP_MISC1_BIT6_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MISC1_BIT6_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_MISC1_BIT6_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MISC1_BIT6_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MISC1_BIT6_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_MISC1_BIT6_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_MISC1_BIT6_0_VAL_SHIFT                      _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_DP_MISC1_BIT6_0_VAL_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_MISC1_BIT6_0_VAL_SHIFT)
#define SOR_NV_PDISP_SOR_DP_MISC1_BIT6_0_VAL_RANGE                      0:0
#define SOR_NV_PDISP_SOR_DP_MISC1_BIT6_0_VAL_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_DP_MISC1_BIT6_0_VAL_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MISC1_BIT6_0_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_MISC1_BIT6_0_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MISC1_BIT6_0_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_DP_MISC1_BIT6_0_VAL_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_DP_MISC1_BIT6_0_VAL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_DP_INT_STATUS_0
#define SOR_NV_PDISP_DP_INT_STATUS_0                    _MK_ADDR_CONST(0x175)
#define SOR_NV_PDISP_DP_INT_STATUS_0_SECURE                     0x0
#define SOR_NV_PDISP_DP_INT_STATUS_0_DUAL                       0x0
#define SOR_NV_PDISP_DP_INT_STATUS_0_SCR                        0
#define SOR_NV_PDISP_DP_INT_STATUS_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_DP_INT_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_READ_MASK                  _MK_MASK_CONST(0x1ffff)
#define SOR_NV_PDISP_DP_INT_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x1ffff)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_FIFO_OVERFLOW_SHIFT                  _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_FIFO_OVERFLOW_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_FIFO_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_FIFO_OVERFLOW_RANGE                  16:16
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_FIFO_OVERFLOW_WOFFSET                        0x0
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_FIFO_OVERFLOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_FIFO_OVERFLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_FIFO_OVERFLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_FIFO_OVERFLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_FIFO_OVERFLOW_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_FIFO_OVERFLOW_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_FIFO_OVERFLOW_SHIFT                  _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_FIFO_OVERFLOW_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_FIFO_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_FIFO_OVERFLOW_RANGE                  15:15
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_FIFO_OVERFLOW_WOFFSET                        0x0
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_FIFO_OVERFLOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_FIFO_OVERFLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_FIFO_OVERFLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_FIFO_OVERFLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_FIFO_OVERFLOW_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_FIFO_OVERFLOW_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_FIFO_OVERFLOW_SHIFT                  _MK_SHIFT_CONST(14)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_FIFO_OVERFLOW_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_FIFO_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_FIFO_OVERFLOW_RANGE                  14:14
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_FIFO_OVERFLOW_WOFFSET                        0x0
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_FIFO_OVERFLOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_FIFO_OVERFLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_FIFO_OVERFLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_FIFO_OVERFLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_FIFO_OVERFLOW_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_FIFO_OVERFLOW_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_FIFO_OVERFLOW_SHIFT                  _MK_SHIFT_CONST(13)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_FIFO_OVERFLOW_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_FIFO_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_FIFO_OVERFLOW_RANGE                  13:13
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_FIFO_OVERFLOW_WOFFSET                        0x0
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_FIFO_OVERFLOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_FIFO_OVERFLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_FIFO_OVERFLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_FIFO_OVERFLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_FIFO_OVERFLOW_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_FIFO_OVERFLOW_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_DP_INT_STATUS_0_SPKT_OVERRUN_SHIFT                 _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_DP_INT_STATUS_0_SPKT_OVERRUN_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_STATUS_0_SPKT_OVERRUN_SHIFT)
#define SOR_NV_PDISP_DP_INT_STATUS_0_SPKT_OVERRUN_RANGE                 12:12
#define SOR_NV_PDISP_DP_INT_STATUS_0_SPKT_OVERRUN_WOFFSET                       0x0
#define SOR_NV_PDISP_DP_INT_STATUS_0_SPKT_OVERRUN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_SPKT_OVERRUN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_SPKT_OVERRUN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_SPKT_OVERRUN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_SPKT_OVERRUN_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_STATUS_0_SPKT_OVERRUN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_STEER_ERROR_SHIFT                    _MK_SHIFT_CONST(11)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_STEER_ERROR_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_STEER_ERROR_SHIFT)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_STEER_ERROR_RANGE                    11:11
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_STEER_ERROR_WOFFSET                  0x0
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_STEER_ERROR_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_STEER_ERROR_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_STEER_ERROR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_STEER_ERROR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_STEER_ERROR_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_STEER_ERROR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_STEER_ERROR_SHIFT                    _MK_SHIFT_CONST(10)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_STEER_ERROR_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_STEER_ERROR_SHIFT)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_STEER_ERROR_RANGE                    10:10
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_STEER_ERROR_WOFFSET                  0x0
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_STEER_ERROR_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_STEER_ERROR_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_STEER_ERROR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_STEER_ERROR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_STEER_ERROR_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_STEER_ERROR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_STEER_ERROR_SHIFT                    _MK_SHIFT_CONST(9)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_STEER_ERROR_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_STEER_ERROR_SHIFT)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_STEER_ERROR_RANGE                    9:9
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_STEER_ERROR_WOFFSET                  0x0
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_STEER_ERROR_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_STEER_ERROR_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_STEER_ERROR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_STEER_ERROR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_STEER_ERROR_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_STEER_ERROR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_STEER_ERROR_SHIFT                    _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_STEER_ERROR_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_STEER_ERROR_SHIFT)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_STEER_ERROR_RANGE                    8:8
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_STEER_ERROR_WOFFSET                  0x0
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_STEER_ERROR_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_STEER_ERROR_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_STEER_ERROR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_STEER_ERROR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_STEER_ERROR_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_STEER_ERROR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_PIXPACK_OVERFLOW_SHIFT                       _MK_SHIFT_CONST(7)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_PIXPACK_OVERFLOW_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_PIXPACK_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_PIXPACK_OVERFLOW_RANGE                       7:7
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_PIXPACK_OVERFLOW_WOFFSET                     0x0
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_PIXPACK_OVERFLOW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_PIXPACK_OVERFLOW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_PIXPACK_OVERFLOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_PIXPACK_OVERFLOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_PIXPACK_OVERFLOW_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_PIXPACK_OVERFLOW_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_PIXPACK_OVERFLOW_SHIFT                       _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_PIXPACK_OVERFLOW_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_PIXPACK_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_PIXPACK_OVERFLOW_RANGE                       6:6
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_PIXPACK_OVERFLOW_WOFFSET                     0x0
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_PIXPACK_OVERFLOW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_PIXPACK_OVERFLOW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_PIXPACK_OVERFLOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_PIXPACK_OVERFLOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_PIXPACK_OVERFLOW_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_PIXPACK_OVERFLOW_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_PIXPACK_OVERFLOW_SHIFT                       _MK_SHIFT_CONST(5)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_PIXPACK_OVERFLOW_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_PIXPACK_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_PIXPACK_OVERFLOW_RANGE                       5:5
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_PIXPACK_OVERFLOW_WOFFSET                     0x0
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_PIXPACK_OVERFLOW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_PIXPACK_OVERFLOW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_PIXPACK_OVERFLOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_PIXPACK_OVERFLOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_PIXPACK_OVERFLOW_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_PIXPACK_OVERFLOW_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_PIXPACK_OVERFLOW_SHIFT                       _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_PIXPACK_OVERFLOW_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_PIXPACK_OVERFLOW_SHIFT)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_PIXPACK_OVERFLOW_RANGE                       4:4
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_PIXPACK_OVERFLOW_WOFFSET                     0x0
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_PIXPACK_OVERFLOW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_PIXPACK_OVERFLOW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_PIXPACK_OVERFLOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_PIXPACK_OVERFLOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_PIXPACK_OVERFLOW_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_PIXPACK_OVERFLOW_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_FIFO_UNDERFLOW_SHIFT                 _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_FIFO_UNDERFLOW_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_FIFO_UNDERFLOW_SHIFT)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_FIFO_UNDERFLOW_RANGE                 3:3
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_FIFO_UNDERFLOW_WOFFSET                       0x0
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_FIFO_UNDERFLOW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_FIFO_UNDERFLOW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_FIFO_UNDERFLOW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_FIFO_UNDERFLOW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_FIFO_UNDERFLOW_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE3_FIFO_UNDERFLOW_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_FIFO_UNDERFLOW_SHIFT                 _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_FIFO_UNDERFLOW_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_FIFO_UNDERFLOW_SHIFT)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_FIFO_UNDERFLOW_RANGE                 2:2
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_FIFO_UNDERFLOW_WOFFSET                       0x0
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_FIFO_UNDERFLOW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_FIFO_UNDERFLOW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_FIFO_UNDERFLOW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_FIFO_UNDERFLOW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_FIFO_UNDERFLOW_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE2_FIFO_UNDERFLOW_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_FIFO_UNDERFLOW_SHIFT                 _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_FIFO_UNDERFLOW_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_FIFO_UNDERFLOW_SHIFT)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_FIFO_UNDERFLOW_RANGE                 1:1
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_FIFO_UNDERFLOW_WOFFSET                       0x0
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_FIFO_UNDERFLOW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_FIFO_UNDERFLOW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_FIFO_UNDERFLOW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_FIFO_UNDERFLOW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_FIFO_UNDERFLOW_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE1_FIFO_UNDERFLOW_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_FIFO_UNDERFLOW_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_FIFO_UNDERFLOW_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_FIFO_UNDERFLOW_SHIFT)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_FIFO_UNDERFLOW_RANGE                 0:0
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_FIFO_UNDERFLOW_WOFFSET                       0x0
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_FIFO_UNDERFLOW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_FIFO_UNDERFLOW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_FIFO_UNDERFLOW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_FIFO_UNDERFLOW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_FIFO_UNDERFLOW_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_STATUS_0_LANE0_FIFO_UNDERFLOW_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

// Register SOR_NV_PDISP_DP_INT_MASK_0
#define SOR_NV_PDISP_DP_INT_MASK_0                      _MK_ADDR_CONST(0x176)
#define SOR_NV_PDISP_DP_INT_MASK_0_SECURE                       0x0
#define SOR_NV_PDISP_DP_INT_MASK_0_DUAL                         0x0
#define SOR_NV_PDISP_DP_INT_MASK_0_SCR                  0
#define SOR_NV_PDISP_DP_INT_MASK_0_WORD_COUNT                   0x1
#define SOR_NV_PDISP_DP_INT_MASK_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_RESET_MASK                   _MK_MASK_CONST(0x1ffff)
#define SOR_NV_PDISP_DP_INT_MASK_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_READ_MASK                    _MK_MASK_CONST(0x1ffff)
#define SOR_NV_PDISP_DP_INT_MASK_0_WRITE_MASK                   _MK_MASK_CONST(0x1ffff)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_SHIFT                       _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_RANGE                       16:16
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_WOFFSET                     0x0
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_INIT_ENUM                   MASKED
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_MASKED                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_OVERFLOW_MASK_NOTMASKED                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_SHIFT                       _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_RANGE                       15:15
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_WOFFSET                     0x0
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_INIT_ENUM                   MASKED
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_MASKED                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_OVERFLOW_MASK_NOTMASKED                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_SHIFT                       _MK_SHIFT_CONST(14)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_RANGE                       14:14
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_WOFFSET                     0x0
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_INIT_ENUM                   MASKED
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_MASKED                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_OVERFLOW_MASK_NOTMASKED                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_SHIFT                       _MK_SHIFT_CONST(13)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_RANGE                       13:13
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_WOFFSET                     0x0
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_INIT_ENUM                   MASKED
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_MASKED                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_OVERFLOW_MASK_NOTMASKED                   _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_MASK_0_SPKT_OVERRUN_MASK_SHIFT                      _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_DP_INT_MASK_0_SPKT_OVERRUN_MASK_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_MASK_0_SPKT_OVERRUN_MASK_SHIFT)
#define SOR_NV_PDISP_DP_INT_MASK_0_SPKT_OVERRUN_MASK_RANGE                      12:12
#define SOR_NV_PDISP_DP_INT_MASK_0_SPKT_OVERRUN_MASK_WOFFSET                    0x0
#define SOR_NV_PDISP_DP_INT_MASK_0_SPKT_OVERRUN_MASK_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_SPKT_OVERRUN_MASK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_SPKT_OVERRUN_MASK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_SPKT_OVERRUN_MASK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_SPKT_OVERRUN_MASK_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_SPKT_OVERRUN_MASK_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_SPKT_OVERRUN_MASK_INIT_ENUM                  MASKED
#define SOR_NV_PDISP_DP_INT_MASK_0_SPKT_OVERRUN_MASK_MASKED                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_MASK_0_SPKT_OVERRUN_MASK_NOTMASKED                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_STEER_ERROR_MASK_SHIFT                 _MK_SHIFT_CONST(11)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_STEER_ERROR_MASK_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_MASK_0_LANE3_STEER_ERROR_MASK_SHIFT)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_STEER_ERROR_MASK_RANGE                 11:11
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_STEER_ERROR_MASK_WOFFSET                       0x0
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_STEER_ERROR_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_STEER_ERROR_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_STEER_ERROR_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_STEER_ERROR_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_STEER_ERROR_MASK_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_STEER_ERROR_MASK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_STEER_ERROR_MASK_INIT_ENUM                     MASKED
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_STEER_ERROR_MASK_MASKED                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_STEER_ERROR_MASK_NOTMASKED                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_STEER_ERROR_MASK_SHIFT                 _MK_SHIFT_CONST(10)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_STEER_ERROR_MASK_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_MASK_0_LANE2_STEER_ERROR_MASK_SHIFT)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_STEER_ERROR_MASK_RANGE                 10:10
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_STEER_ERROR_MASK_WOFFSET                       0x0
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_STEER_ERROR_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_STEER_ERROR_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_STEER_ERROR_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_STEER_ERROR_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_STEER_ERROR_MASK_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_STEER_ERROR_MASK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_STEER_ERROR_MASK_INIT_ENUM                     MASKED
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_STEER_ERROR_MASK_MASKED                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_STEER_ERROR_MASK_NOTMASKED                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_STEER_ERROR_MASK_SHIFT                 _MK_SHIFT_CONST(9)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_STEER_ERROR_MASK_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_MASK_0_LANE1_STEER_ERROR_MASK_SHIFT)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_STEER_ERROR_MASK_RANGE                 9:9
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_STEER_ERROR_MASK_WOFFSET                       0x0
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_STEER_ERROR_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_STEER_ERROR_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_STEER_ERROR_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_STEER_ERROR_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_STEER_ERROR_MASK_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_STEER_ERROR_MASK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_STEER_ERROR_MASK_INIT_ENUM                     MASKED
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_STEER_ERROR_MASK_MASKED                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_STEER_ERROR_MASK_NOTMASKED                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_STEER_ERROR_MASK_SHIFT                 _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_STEER_ERROR_MASK_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_MASK_0_LANE0_STEER_ERROR_MASK_SHIFT)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_STEER_ERROR_MASK_RANGE                 8:8
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_STEER_ERROR_MASK_WOFFSET                       0x0
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_STEER_ERROR_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_STEER_ERROR_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_STEER_ERROR_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_STEER_ERROR_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_STEER_ERROR_MASK_PARITY_PROTECTION                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_STEER_ERROR_MASK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_STEER_ERROR_MASK_INIT_ENUM                     MASKED
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_STEER_ERROR_MASK_MASKED                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_STEER_ERROR_MASK_NOTMASKED                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_SHIFT                    _MK_SHIFT_CONST(7)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_RANGE                    7:7
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_WOFFSET                  0x0
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_INIT_ENUM                        MASKED
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_MASKED                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_PIXPACK_OVERFLOW_MASK_NOTMASKED                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_SHIFT                    _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_RANGE                    6:6
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_WOFFSET                  0x0
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_INIT_ENUM                        MASKED
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_MASKED                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_PIXPACK_OVERFLOW_MASK_NOTMASKED                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_SHIFT                    _MK_SHIFT_CONST(5)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_RANGE                    5:5
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_WOFFSET                  0x0
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_INIT_ENUM                        MASKED
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_MASKED                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_PIXPACK_OVERFLOW_MASK_NOTMASKED                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_SHIFT                    _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_FIELD                    _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_RANGE                    4:4
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_WOFFSET                  0x0
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_INIT_ENUM                        MASKED
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_MASKED                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_PIXPACK_OVERFLOW_MASK_NOTMASKED                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_SHIFT                      _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_RANGE                      3:3
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_WOFFSET                    0x0
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_INIT_ENUM                  MASKED
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_MASKED                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE3_FIFO_UNDERFLOW_MASK_NOTMASKED                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_SHIFT                      _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_RANGE                      2:2
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_WOFFSET                    0x0
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_INIT_ENUM                  MASKED
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_MASKED                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE2_FIFO_UNDERFLOW_MASK_NOTMASKED                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_SHIFT                      _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_RANGE                      1:1
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_WOFFSET                    0x0
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_INIT_ENUM                  MASKED
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_MASKED                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE1_FIFO_UNDERFLOW_MASK_NOTMASKED                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_SHIFT                      _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_SHIFT)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_RANGE                      0:0
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_WOFFSET                    0x0
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_INIT_ENUM                  MASKED
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_MASKED                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_MASK_0_LANE0_FIFO_UNDERFLOW_MASK_NOTMASKED                  _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_DP_INT_ENABLE_0
#define SOR_NV_PDISP_DP_INT_ENABLE_0                    _MK_ADDR_CONST(0x177)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_SECURE                     0x0
#define SOR_NV_PDISP_DP_INT_ENABLE_0_DUAL                       0x0
#define SOR_NV_PDISP_DP_INT_ENABLE_0_SCR                        0
#define SOR_NV_PDISP_DP_INT_ENABLE_0_WORD_COUNT                         0x1
#define SOR_NV_PDISP_DP_INT_ENABLE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_RESET_MASK                         _MK_MASK_CONST(0x1ffff)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_READ_MASK                  _MK_MASK_CONST(0x1ffff)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_WRITE_MASK                         _MK_MASK_CONST(0x1ffff)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_SHIFT                   _MK_SHIFT_CONST(16)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_RANGE                   16:16
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_WOFFSET                 0x0
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_INIT_ENUM                       DISABLE
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_OVERFLOW_ENABLE_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_SHIFT                   _MK_SHIFT_CONST(15)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_RANGE                   15:15
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_WOFFSET                 0x0
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_INIT_ENUM                       DISABLE
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_OVERFLOW_ENABLE_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_SHIFT                   _MK_SHIFT_CONST(14)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_RANGE                   14:14
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_WOFFSET                 0x0
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_INIT_ENUM                       DISABLE
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_OVERFLOW_ENABLE_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_SHIFT                   _MK_SHIFT_CONST(13)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_RANGE                   13:13
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_WOFFSET                 0x0
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_INIT_ENUM                       DISABLE
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_OVERFLOW_ENABLE_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_SHIFT                  _MK_SHIFT_CONST(12)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_SHIFT)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_RANGE                  12:12
#define SOR_NV_PDISP_DP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_WOFFSET                        0x0
#define SOR_NV_PDISP_DP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_INIT_ENUM                      DISABLE
#define SOR_NV_PDISP_DP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_DISABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_SPKT_OVERRUN_ENABLE_ENABLE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_SHIFT                     _MK_SHIFT_CONST(11)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_SHIFT)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_RANGE                     11:11
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_WOFFSET                   0x0
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_INIT_ENUM                 DISABLE
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_STEER_ERROR_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_SHIFT                     _MK_SHIFT_CONST(10)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_SHIFT)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_RANGE                     10:10
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_WOFFSET                   0x0
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_INIT_ENUM                 DISABLE
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_STEER_ERROR_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_SHIFT                     _MK_SHIFT_CONST(9)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_SHIFT)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_RANGE                     9:9
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_WOFFSET                   0x0
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_INIT_ENUM                 DISABLE
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_STEER_ERROR_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_SHIFT                     _MK_SHIFT_CONST(8)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_SHIFT)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_RANGE                     8:8
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_WOFFSET                   0x0
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_INIT_ENUM                 DISABLE
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_DISABLE                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_STEER_ERROR_ENABLE_ENABLE                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_SHIFT                        _MK_SHIFT_CONST(7)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_RANGE                        7:7
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_WOFFSET                      0x0
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_INIT_ENUM                    DISABLE
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_PIXPACK_OVERFLOW_ENABLE_ENABLE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_SHIFT                        _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_RANGE                        6:6
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_WOFFSET                      0x0
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_INIT_ENUM                    DISABLE
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_PIXPACK_OVERFLOW_ENABLE_ENABLE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_SHIFT                        _MK_SHIFT_CONST(5)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_RANGE                        5:5
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_WOFFSET                      0x0
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_INIT_ENUM                    DISABLE
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_PIXPACK_OVERFLOW_ENABLE_ENABLE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_SHIFT                        _MK_SHIFT_CONST(4)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_RANGE                        4:4
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_WOFFSET                      0x0
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_INIT_ENUM                    DISABLE
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_PIXPACK_OVERFLOW_ENABLE_ENABLE                       _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_SHIFT                  _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_RANGE                  3:3
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_WOFFSET                        0x0
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_INIT_ENUM                      DISABLE
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_DISABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE3_FIFO_UNDERFLOW_ENABLE_ENABLE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_SHIFT                  _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_RANGE                  2:2
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_WOFFSET                        0x0
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_INIT_ENUM                      DISABLE
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_DISABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE2_FIFO_UNDERFLOW_ENABLE_ENABLE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_SHIFT                  _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_RANGE                  1:1
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_WOFFSET                        0x0
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_INIT_ENUM                      DISABLE
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_DISABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE1_FIFO_UNDERFLOW_ENABLE_ENABLE                 _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_SHIFT                  _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_SHIFT)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_RANGE                  0:0
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_WOFFSET                        0x0
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_INIT_ENUM                      DISABLE
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_DISABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_DP_INT_ENABLE_0_LANE0_FIFO_UNDERFLOW_ENABLE_ENABLE                 _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_VPR_POLICY_0
#define SOR_NV_PDISP_SOR_VPR_POLICY_0                   _MK_ADDR_CONST(0x178)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_SCR                       0
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_RESET_MASK                        _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_READ_MASK                         _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_WRITE_MASK                        _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_DIGITAL_OUT_SHIFT                   _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_DIGITAL_OUT_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_DIGITAL_OUT_SHIFT)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_DIGITAL_OUT_RANGE                   3:3
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_DIGITAL_OUT_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_DIGITAL_OUT_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_DIGITAL_OUT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_DIGITAL_OUT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_DIGITAL_OUT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_DIGITAL_OUT_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_DIGITAL_OUT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_DIGITAL_OUT_INIT_ENUM                       NO
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_DIGITAL_OUT_NO                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_DIGITAL_OUT_YES                     _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_INTERNAL_PANEL_SHIFT                        _MK_SHIFT_CONST(2)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_INTERNAL_PANEL_FIELD                        _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_INTERNAL_PANEL_SHIFT)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_INTERNAL_PANEL_RANGE                        2:2
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_INTERNAL_PANEL_WOFFSET                      0x0
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_INTERNAL_PANEL_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_INTERNAL_PANEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_INTERNAL_PANEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_INTERNAL_PANEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_INTERNAL_PANEL_PARITY_PROTECTION                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_INTERNAL_PANEL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_INTERNAL_PANEL_INIT_ENUM                    NO
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_INTERNAL_PANEL_NO                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_INTERNAL_PANEL_YES                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP1X_PROTECTED_SHIFT                      _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP1X_PROTECTED_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP1X_PROTECTED_SHIFT)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP1X_PROTECTED_RANGE                      1:1
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP1X_PROTECTED_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP1X_PROTECTED_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP1X_PROTECTED_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP1X_PROTECTED_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP1X_PROTECTED_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP1X_PROTECTED_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP1X_PROTECTED_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP1X_PROTECTED_INIT_ENUM                  NO
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP1X_PROTECTED_NO                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP1X_PROTECTED_YES                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP22_PROTECTED_SHIFT                      _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP22_PROTECTED_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP22_PROTECTED_SHIFT)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP22_PROTECTED_RANGE                      0:0
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP22_PROTECTED_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP22_PROTECTED_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP22_PROTECTED_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP22_PROTECTED_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP22_PROTECTED_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP22_PROTECTED_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP22_PROTECTED_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP22_PROTECTED_INIT_ENUM                  NO
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP22_PROTECTED_NO                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_VPR_POLICY_0_ALLOW_HDCP22_PROTECTED_YES                        _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_PLL5_0
#define SOR_NV_PDISP_SOR_PLL5_0                 _MK_ADDR_CONST(0x179)
#define SOR_NV_PDISP_SOR_PLL5_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_PLL5_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_PLL5_0_SCR                     0
#define SOR_NV_PDISP_SOR_PLL5_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_PLL5_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_RESET_MASK                      _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_SOR_PLL5_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_READ_MASK                       _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_SOR_PLL5_0_WRITE_MASK                      _MK_MASK_CONST(0x7fff)
#define SOR_NV_PDISP_SOR_PLL5_0_CLK_EN_DIFF_DET_SHIFT                   _MK_SHIFT_CONST(14)
#define SOR_NV_PDISP_SOR_PLL5_0_CLK_EN_DIFF_DET_FIELD                   _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL5_0_CLK_EN_DIFF_DET_SHIFT)
#define SOR_NV_PDISP_SOR_PLL5_0_CLK_EN_DIFF_DET_RANGE                   14:14
#define SOR_NV_PDISP_SOR_PLL5_0_CLK_EN_DIFF_DET_WOFFSET                 0x0
#define SOR_NV_PDISP_SOR_PLL5_0_CLK_EN_DIFF_DET_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_CLK_EN_DIFF_DET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL5_0_CLK_EN_DIFF_DET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_CLK_EN_DIFF_DET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_CLK_EN_DIFF_DET_PARITY_PROTECTION                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL5_0_CLK_EN_DIFF_DET_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL5_0_CLK_EN_DIFF_DET_INIT_ENUM                       DISABLE
#define SOR_NV_PDISP_SOR_PLL5_0_CLK_EN_DIFF_DET_DISABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL5_0_CLK_EN_DIFF_DET_ENABLE                  _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER_SHIFT                     _MK_SHIFT_CONST(11)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER_FIELD                     _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER_SHIFT)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER_RANGE                     13:11
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER_INIT_ENUM                 TREF_2_15
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER_TREF_2_15                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER_TREF_2_14                 _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER_TREF_2_13                 _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER_TREF_2_12                 _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER_TREF_2_11                 _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER_TREF_2_10                 _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER_TREF_2_9                  _MK_ENUM_CONST(6)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER_TREF_2_8                  _MK_ENUM_CONST(7)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER__PROD_C_RBR                       _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER__PROD_C_HBR                       _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER__PROD_C_HBR2                      _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER__PROD_C_HBR3                      _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER__PROD_C_R_HDMI_0M_54M                     _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER__PROD_C_R_HDMI_54M_111M                   _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER__PROD_C_R_HDMI_111M_223M                  _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER__PROD_C_R_HDMI_223M_300M                  _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_SEL_TIMER__PROD_C_R_HDMI_300M_600M                  _MK_ENUM_CONST(3)

#define SOR_NV_PDISP_SOR_PLL5_0_PLL_PD_TIMER_SHIFT                      _MK_SHIFT_CONST(10)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_PD_TIMER_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL5_0_PLL_PD_TIMER_SHIFT)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_PD_TIMER_RANGE                      10:10
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_PD_TIMER_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_PD_TIMER_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_PD_TIMER_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_PD_TIMER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_PD_TIMER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_PD_TIMER_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_PD_TIMER_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_PD_TIMER_INIT_ENUM                  ENABLE
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_PD_TIMER_ENABLE                     _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_PD_TIMER_DISABLE                    _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_PD_TIMER__PROD_C_R_HDMI_0M_54M                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_PD_TIMER__PROD_C_R_HDMI_54M_111M                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_PD_TIMER__PROD_C_R_HDMI_111M_223M                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_PD_TIMER__PROD_C_R_HDMI_223M_300M                   _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_PD_TIMER__PROD_C_R_HDMI_300M_600M                   _MK_ENUM_CONST(0)

#define SOR_NV_PDISP_SOR_PLL5_0_PLL_LOCKDET2_SETUPN_SHIFT                       _MK_SHIFT_CONST(7)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_LOCKDET2_SETUPN_FIELD                       _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_PLL5_0_PLL_LOCKDET2_SETUPN_SHIFT)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_LOCKDET2_SETUPN_RANGE                       9:7
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_LOCKDET2_SETUPN_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_LOCKDET2_SETUPN_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_LOCKDET2_SETUPN_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_LOCKDET2_SETUPN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_LOCKDET2_SETUPN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_LOCKDET2_SETUPN_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_LOCKDET2_SETUPN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_LOCKDET2_SETUPN__PROD_C_RBR                 _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_LOCKDET2_SETUPN__PROD_C_HBR                 _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_LOCKDET2_SETUPN__PROD_C_HBR2                        _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_LOCKDET2_SETUPN__PROD_C_HBR3                        _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_LOCKDET2_SETUPN__PROD_C_R_HDMI_0M_54M                       _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_LOCKDET2_SETUPN__PROD_C_R_HDMI_54M_111M                     _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_LOCKDET2_SETUPN__PROD_C_R_HDMI_111M_223M                    _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_LOCKDET2_SETUPN__PROD_C_R_HDMI_223M_300M                    _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_PLL5_0_PLL_LOCKDET2_SETUPN__PROD_C_R_HDMI_300M_600M                    _MK_ENUM_CONST(4)

#define SOR_NV_PDISP_SOR_PLL5_0_SERIAL_MODE_SHIFT                       _MK_SHIFT_CONST(6)
#define SOR_NV_PDISP_SOR_PLL5_0_SERIAL_MODE_FIELD                       _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL5_0_SERIAL_MODE_SHIFT)
#define SOR_NV_PDISP_SOR_PLL5_0_SERIAL_MODE_RANGE                       6:6
#define SOR_NV_PDISP_SOR_PLL5_0_SERIAL_MODE_WOFFSET                     0x0
#define SOR_NV_PDISP_SOR_PLL5_0_SERIAL_MODE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_SERIAL_MODE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL5_0_SERIAL_MODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_SERIAL_MODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_SERIAL_MODE_PARITY_PROTECTION                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL5_0_SERIAL_MODE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_FLOCK_SHIFT                  _MK_SHIFT_CONST(5)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_FLOCK_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_FLOCK_SHIFT)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_FLOCK_RANGE                  5:5
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_FLOCK_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_FLOCK_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_FLOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_FLOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_FLOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_FLOCK_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_FLOCK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_FLOCK_INIT_ENUM                      ENABLE
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_FLOCK_ENABLE                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_FLOCK_DISABLE                        _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_TBD_SHIFT                    _MK_SHIFT_CONST(3)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_TBD_FIELD                    _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_TBD_SHIFT)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_TBD_RANGE                    4:3
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_TBD_WOFFSET                  0x0
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_TBD_DEFAULT                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_TBD_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_TBD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_TBD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_TBD_PARITY_PROTECTION                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_TBD_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_RATIO_SHIFT                  _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_RATIO_FIELD                  _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_RATIO_SHIFT)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_RATIO_RANGE                  2:1
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_RATIO_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_RATIO_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_RATIO_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_RATIO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_RATIO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_RATIO_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_RATIO_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_RATIO_INIT_ENUM                      PLL_SEL_TIMER_1_2
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_RATIO_PLL_SEL_TIMER_1_2                      _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_RATIO_PLL_SEL_TIMER_1_4                      _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_RATIO_PLL_SEL_TIMER_1_8                      _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_RATIO_PLL_SEL_TIMER_1_16                     _MK_ENUM_CONST(3)

#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_EN_SHIFT                     _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_EN_FIELD                     _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_EN_SHIFT)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_EN_RANGE                     0:0
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_EN_WOFFSET                   0x0
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_EN_INIT_ENUM                 ENABLE
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_EN_ENABLE                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_PLL5_0_SETUP_LCKDET_TIMER_EN_DISABLE                   _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_AFIFO_CTRL_0
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0                   _MK_ADDR_CONST(0x17c)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_SECURE                    0x0
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_DUAL                      0x0
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_SCR                       0
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_WORD_COUNT                        0x1
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_RESET_VAL                         _MK_MASK_CONST(0x7)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_READ_MASK                         _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_VAL_SHIFT                  _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_VAL_FIELD                  _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_VAL_SHIFT)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_VAL_RANGE                  3:1
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_VAL_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_VAL_DEFAULT                        _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_VAL_WATER0                 _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_VAL_WATER1                 _MK_ENUM_CONST(1)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_VAL_WATER2                 _MK_ENUM_CONST(2)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_VAL_WATER3                 _MK_ENUM_CONST(3)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_VAL_WATER4                 _MK_ENUM_CONST(4)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_VAL_WATER5                 _MK_ENUM_CONST(5)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_VAL_WATER6                 _MK_ENUM_CONST(6)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_VAL_WATER7                 _MK_ENUM_CONST(7)

#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_SHIFT                      _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_FIELD                      _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_SHIFT)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_RANGE                      0:0
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_WOFFSET                    0x0
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_DEFAULT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_PARITY_PROTECTION                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_INIT_ENUM                  ENABLE
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_DISABLE                    _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_AFIFO_CTRL_0_AFIFOWATER_OVR_ENABLE                     _MK_ENUM_CONST(1)

// Register SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0                 _MK_ADDR_CONST(0x17d)
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_SECURE                  0x0
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_DUAL                    0x0
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_SCR                     0
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_WORD_COUNT                      0x1
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_RESET_MASK                      _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_READ_MASK                       _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_WRITE_MASK                      _MK_MASK_CONST(0x3)
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_PCLK_MUX_SEL_SHIFT                 _MK_SHIFT_CONST(0)
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_PCLK_MUX_SEL_FIELD                 _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_PCLK_MUX_SEL_SHIFT)
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_PCLK_MUX_SEL_RANGE                 0:0
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_PCLK_MUX_SEL_WOFFSET                       0x0
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_PCLK_MUX_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_PCLK_MUX_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_PCLK_MUX_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_PCLK_MUX_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_PCLK_MUX_SEL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_PCLK_MUX_SEL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_PCLK_MUX_SEL_INIT_ENUM                     HDMI
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_PCLK_MUX_SEL_HDMI                  _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_PCLK_MUX_SEL_DP                    _MK_ENUM_CONST(1)

#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_HDMI420_SEL_SHIFT                  _MK_SHIFT_CONST(1)
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_HDMI420_SEL_FIELD                  _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_HDMI420_SEL_SHIFT)
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_HDMI420_SEL_RANGE                  1:1
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_HDMI420_SEL_WOFFSET                        0x0
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_HDMI420_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_HDMI420_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_HDMI420_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_HDMI420_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_HDMI420_SEL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_HDMI420_SEL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_HDMI420_SEL_INIT_ENUM                      DISABLE
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_HDMI420_SEL_DISABLE                        _MK_ENUM_CONST(0)
#define SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0_FPGA_HDMI420_SEL_ENABLE                 _MK_ENUM_CONST(1)

// Reserved address 0x204

// Reserved address 0x208

// Reserved address 0x209

// Reserved address 0x20a

// Reserved address 0x20b

// Reserved address 0x213

// Reserved address 0x215

// Reserved address 0x216

// Reserved address 0x217

//
// REGISTER LIST
//
#define LIST_ARSOR1_REGS(_op_) \
_op_(SOR_NV_PDISP_SOR_SUPER_STATE0_0) \
_op_(SOR_NV_PDISP_SOR_SUPER_STATE1_0) \
_op_(SOR_NV_PDISP_SOR_STATE0_0) \
_op_(SOR_NV_PDISP_SOR_STATE1_0) \
_op_(SOR_NV_PDISP_SOR_CRC_CNTRL_0) \
_op_(SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0) \
_op_(SOR_NV_PDISP_SOR_CLK_CNTRL_0) \
_op_(SOR_NV_PDISP_SOR_CAP_0) \
_op_(SOR_NV_PDISP_SOR_PWR_0) \
_op_(SOR_NV_PDISP_SOR_TEST_0) \
_op_(SOR_NV_PDISP_SOR_CSTM_0) \
_op_(SOR_NV_PDISP_SOR_LVDS_0) \
_op_(SOR_NV_PDISP_SOR_CRCA_0) \
_op_(SOR_NV_PDISP_SOR_CRCB_0) \
_op_(SOR_NV_PDISP_SOR_BLANK_0) \
_op_(SOR_NV_PDISP_SOR_SEQ_CTL_0) \
_op_(SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0) \
_op_(SOR_NV_PDISP_SOR_SEQ_INST0_0) \
_op_(SOR_NV_PDISP_SOR_SEQ_INST1_0) \
_op_(SOR_NV_PDISP_SOR_SEQ_INST2_0) \
_op_(SOR_NV_PDISP_SOR_SEQ_INST3_0) \
_op_(SOR_NV_PDISP_SOR_SEQ_INST4_0) \
_op_(SOR_NV_PDISP_SOR_SEQ_INST5_0) \
_op_(SOR_NV_PDISP_SOR_SEQ_INST6_0) \
_op_(SOR_NV_PDISP_SOR_SEQ_INST7_0) \
_op_(SOR_NV_PDISP_SOR_SEQ_INST8_0) \
_op_(SOR_NV_PDISP_SOR_SEQ_INST9_0) \
_op_(SOR_NV_PDISP_SOR_SEQ_INSTA_0) \
_op_(SOR_NV_PDISP_SOR_SEQ_INSTB_0) \
_op_(SOR_NV_PDISP_SOR_SEQ_INSTC_0) \
_op_(SOR_NV_PDISP_SOR_SEQ_INSTD_0) \
_op_(SOR_NV_PDISP_SOR_SEQ_INSTE_0) \
_op_(SOR_NV_PDISP_SOR_SEQ_INSTF_0) \
_op_(SOR_NV_PDISP_SOR_PWM_DIV_0) \
_op_(SOR_NV_PDISP_SOR_PWM_CTL_0) \
_op_(SOR_NV_PDISP_SOR_VCRCA0_0) \
_op_(SOR_NV_PDISP_SOR_VCRCA1_0) \
_op_(SOR_NV_PDISP_SOR_VCRCB0_0) \
_op_(SOR_NV_PDISP_SOR_VCRCB1_0) \
_op_(SOR_NV_PDISP_SOR_CCRCA0_0) \
_op_(SOR_NV_PDISP_SOR_CCRCA1_0) \
_op_(SOR_NV_PDISP_SOR_CCRCB0_0) \
_op_(SOR_NV_PDISP_SOR_CCRCB1_0) \
_op_(SOR_NV_PDISP_SOR_EDATAA0_0) \
_op_(SOR_NV_PDISP_SOR_EDATAA1_0) \
_op_(SOR_NV_PDISP_SOR_EDATAB0_0) \
_op_(SOR_NV_PDISP_SOR_EDATAB1_0) \
_op_(SOR_NV_PDISP_SOR_COUNTA0_0) \
_op_(SOR_NV_PDISP_SOR_COUNTA1_0) \
_op_(SOR_NV_PDISP_SOR_COUNTB0_0) \
_op_(SOR_NV_PDISP_SOR_COUNTB1_0) \
_op_(SOR_NV_PDISP_SOR_DEBUGA0_0) \
_op_(SOR_NV_PDISP_SOR_DEBUGA1_0) \
_op_(SOR_NV_PDISP_SOR_DEBUGB0_0) \
_op_(SOR_NV_PDISP_SOR_DEBUGB1_0) \
_op_(SOR_NV_PDISP_SOR_TRIG_0) \
_op_(SOR_NV_PDISP_SOR_MSCHECK_0) \
_op_(SOR_NV_PDISP_SOR_XBAR_CTRL_0) \
_op_(SOR_NV_PDISP_SOR_XBAR_POL_0) \
_op_(SOR_NV_PDISP_SOR_DP_LINKCTL0_0) \
_op_(SOR_NV_PDISP_SOR_DP_LINKCTL1_0) \
_op_(SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0) \
_op_(SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0) \
_op_(SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0) \
_op_(SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0) \
_op_(SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0) \
_op_(SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0) \
_op_(SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0) \
_op_(SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0) \
_op_(SOR_NV_PDISP_SOR_POSTCURSOR0_0) \
_op_(SOR_NV_PDISP_SOR_POSTCURSOR1_0) \
_op_(SOR_NV_PDISP_SOR_DP_CONFIG0_0) \
_op_(SOR_NV_PDISP_SOR_DP_CONFIG1_0) \
_op_(SOR_NV_PDISP_SOR_DP_MN0_0) \
_op_(SOR_NV_PDISP_SOR_DP_MN1_0) \
_op_(SOR_NV_PDISP_SOR_DP_DEBUG0_0) \
_op_(SOR_NV_PDISP_SOR_DP_DEBUG1_0) \
_op_(SOR_NV_PDISP_SOR_DP_SPARE0_0) \
_op_(SOR_NV_PDISP_SOR_DP_SPARE1_0) \
_op_(SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0) \
_op_(SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0) \
_op_(SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0) \
_op_(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0) \
_op_(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0) \
_op_(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0) \
_op_(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0) \
_op_(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0) \
_op_(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0) \
_op_(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0) \
_op_(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0) \
_op_(SOR_NV_PDISP_SOR_DP_TPG_0) \
_op_(SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0) \
_op_(SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0) \
_op_(SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0) \
_op_(SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0) \
_op_(SOR_NV_PDISP_SOR_DP_HDCP_AN_MSB_0) \
_op_(SOR_NV_PDISP_SOR_DP_HDCP_AN_LSB_0) \
_op_(SOR_NV_PDISP_SOR_DP_HDCP_AKSV_MSB_0) \
_op_(SOR_NV_PDISP_SOR_DP_HDCP_AKSV_LSB_0) \
_op_(SOR_NV_PDISP_SOR_DP_HDCP_BKSV_MSB_0) \
_op_(SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB_0) \
_op_(SOR_NV_PDISP_SOR_DP_HDCP_CTRL_0) \
_op_(SOR_NV_PDISP_SOR_DP_HDCP_RI_0) \
_op_(SOR_NV_PDISP_SOR_DP_HDCP_EMU0_0) \
_op_(SOR_NV_PDISP_SOR_DP_HDCP_EMU1_0) \
_op_(SOR_NV_PDISP_SOR_DP_HDCP_CYA_0) \
_op_(SOR_NV_PDISP_SOR_TMDS_HDCP_AN_MSB_0) \
_op_(SOR_NV_PDISP_SOR_TMDS_HDCP_AN_LSB_0) \
_op_(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB_0) \
_op_(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB_0) \
_op_(SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_MSB_0) \
_op_(SOR_NV_PDISP_SOR_TMDS_HDCP_AKSV_LSB_0) \
_op_(SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_MSB_0) \
_op_(SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB_0) \
_op_(SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_MSB_0) \
_op_(SOR_NV_PDISP_SOR_TMDS_HDCP_CKSV_LSB_0) \
_op_(SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_MSB_0) \
_op_(SOR_NV_PDISP_SOR_TMDS_HDCP_DKSV_LSB_0) \
_op_(SOR_NV_PDISP_SOR_TMDS_HDCP_CTRL_0) \
_op_(SOR_NV_PDISP_SOR_TMDS_HDCP_CMODE_0) \
_op_(SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_MSB_0) \
_op_(SOR_NV_PDISP_SOR_TMDS_HDCP_MPRIME_LSB_0) \
_op_(SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_MSB_0) \
_op_(SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB2_0) \
_op_(SOR_NV_PDISP_SOR_TMDS_HDCP_SPRIME_LSB1_0) \
_op_(SOR_NV_PDISP_SOR_TMDS_HDCP_RI_0) \
_op_(SOR_NV_PDISP_SOR_TMDS_HDCP_CS_MSB_0) \
_op_(SOR_NV_PDISP_SOR_TMDS_HDCP_CS_LSB_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU0_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU_RDATA0_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU1_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_AUDIO_EMU2_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_CTRL_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_STATUS_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_HEADER_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_CTRL_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_STATUS_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_HEADER_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_GENERIC_CTRL_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_GENERIC_STATUS_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_GENERIC_HEADER_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_LOW_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK0_HIGH_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_LOW_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK1_HIGH_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_LOW_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK2_HIGH_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_LOW_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_GENERIC_SUBPACK3_HIGH_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_ACR_CTRL_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_LOW_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_ACR_0320_SUBPACK_HIGH_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_LOW_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_ACR_0441_SUBPACK_HIGH_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_LOW_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_ACR_0882_SUBPACK_HIGH_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_LOW_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_ACR_1764_SUBPACK_HIGH_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_LOW_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_ACR_0480_SUBPACK_HIGH_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_LOW_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_ACR_0960_SUBPACK_HIGH_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_LOW_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_ACR_1920_SUBPACK_HIGH_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_CTRL_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_VSYNC_KEEPOUT_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_VSYNC_WINDOW_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_GCP_CTRL_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_GCP_STATUS_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_GCP_SUBPACK_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS1_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_CHANNEL_STATUS2_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_EMU0_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_EMU1_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_EMU1_RDATA_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_SPARE_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS1_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0) \
_op_(SOR_NV_PDISP_HDCPRIF_ROM_CTRL_0) \
_op_(SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0) \
_op_(SOR_NV_PDISP_SOR_REFCLK_0) \
_op_(SOR_NV_PDISP_CRC_CONTROL_0) \
_op_(SOR_NV_PDISP_INPUT_CONTROL_0) \
_op_(SOR_NV_PDISP_SCRATCH_0) \
_op_(SOR_NV_PDISP_KEY_CTRL_0) \
_op_(SOR_NV_PDISP_KEY_DEBUG0_0) \
_op_(SOR_NV_PDISP_KEY_DEBUG1_0) \
_op_(SOR_NV_PDISP_KEY_DEBUG2_0) \
_op_(SOR_NV_PDISP_KEY_HDCP_KEY_0_0) \
_op_(SOR_NV_PDISP_KEY_HDCP_KEY_1_0) \
_op_(SOR_NV_PDISP_KEY_HDCP_KEY_2_0) \
_op_(SOR_NV_PDISP_KEY_HDCP_KEY_3_0) \
_op_(SOR_NV_PDISP_KEY_HDCP_KEY_TRIG_0) \
_op_(SOR_NV_PDISP_KEY_SKEY_INDEX_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_DEBUG_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_SPARE0_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_NVAL_0320_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_NVAL_0441_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_NVAL_0882_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_NVAL_1764_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_NVAL_0480_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_NVAL_0960_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_NVAL_1920_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_HDA_CP_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_AVAL_0320_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_AVAL_0441_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_AVAL_0882_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_AVAL_1764_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_AVAL_0480_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_AVAL_0960_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_AVAL_1920_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT_0) \
_op_(SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0) \
_op_(SOR_NV_PDISP_INT_STATUS_0) \
_op_(SOR_NV_PDISP_INT_MASK_0) \
_op_(SOR_NV_PDISP_INT_ENABLE_0) \
_op_(SOR_NV_PDISP_SOR_TMDS_HDCP_M0_LO_0) \
_op_(SOR_NV_PDISP_SOR_TMDS_HDCP_M0_HI_0) \
_op_(SOR_NV_PDISP_SOR_TMDS_HDCP_STATUS_0) \
_op_(SOR_NV_HDACODEC_AUDIO_GEN_CTL_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_CTRL_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_STATUS_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_HEADER_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW_0) \
_op_(SOR_NV_PDISP_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH_0) \
_op_(SOR_NV_PDISP_SOR_DP_AUDIO_CRC_0) \
_op_(SOR_NV_PDISP_SOR_DP_AUDIO_MN_0) \
_op_(SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_HEADER_0) \
_op_(SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_LOW_0) \
_op_(SOR_NV_PDISP_SOR_DP_AUDIO_INFOFRAME_SUBPACK0_HIGH_0) \
_op_(SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0320_0) \
_op_(SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0441_0) \
_op_(SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0882_0) \
_op_(SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1764_0) \
_op_(SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0480_0) \
_op_(SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_0960_0) \
_op_(SOR_NV_PDISP_SOR_DP_AUDIO_TIMESTAMP_1920_0) \
_op_(SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS1_0) \
_op_(SOR_NV_PDISP_SOR_DP_OUTPUT_CHANNEL_STATUS2_0) \
_op_(SOR_NV_PDISP_HDMI_AUDIO_N_0) \
_op_(SOR_NV_PDISP_HDMI_LANE_CALIB_FUSE_0) \
_op_(SOR_NV_PDISP_SOR_HDMI2_CTRL_0) \
_op_(SOR_NV_PDISP_SOR_HDMI2_LFSR0_0) \
_op_(SOR_NV_PDISP_SOR_HDMI2_LFSR1_0) \
_op_(SOR_NV_PDISP_SOR_HDCP22_CTRL_0) \
_op_(SOR_NV_PDISP_SOR_HDCP22_STATUS_0) \
_op_(SOR_NV_PDISP_SOR_HDCP22_DEBUG0_0) \
_op_(SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_MSB_0) \
_op_(SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB1_0) \
_op_(SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB2_0) \
_op_(SOR_NV_PDISP_SOR_HDCP22_AES_CTR_KEY_LSB3_0) \
_op_(SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_MSB_0) \
_op_(SOR_NV_PDISP_SOR_HDCP22_AES_CTR_DATA_LSB_0) \
_op_(SOR_NV_PDISP_SOR_HDCP22_SST_DP_TYPE_0) \
_op_(SOR_NV_PDISP_SOR_HDCP22_LC128_MSB_0) \
_op_(SOR_NV_PDISP_SOR_HDCP22_LC128_LSB1_0) \
_op_(SOR_NV_PDISP_SOR_HDCP22_LC128_LSB2_0) \
_op_(SOR_NV_PDISP_SOR_HDCP22_LC128_LSB3_0) \
_op_(SOR_CTXSW_NEXT_0) \
_op_(SOR_CTXSW_0) \
_op_(SOR_NV_PDISP_HEAD_STATE0_0) \
_op_(SOR_NV_PDISP_HEAD_STATE0) \
_op_(SOR_NV_PDISP_HEAD_STATE0_1) \
_op_(SOR_NV_PDISP_HEAD_STATE0_2) \
_op_(SOR_NV_PDISP_HEAD_STATE0_3) \
_op_(SOR_NV_PDISP_HEAD_STATE1_0) \
_op_(SOR_NV_PDISP_HEAD_STATE1) \
_op_(SOR_NV_PDISP_HEAD_STATE1_1) \
_op_(SOR_NV_PDISP_HEAD_STATE1_2) \
_op_(SOR_NV_PDISP_HEAD_STATE1_3) \
_op_(SOR_NV_PDISP_HEAD_STATE2_0) \
_op_(SOR_NV_PDISP_HEAD_STATE2) \
_op_(SOR_NV_PDISP_HEAD_STATE2_1) \
_op_(SOR_NV_PDISP_HEAD_STATE2_2) \
_op_(SOR_NV_PDISP_HEAD_STATE2_3) \
_op_(SOR_NV_PDISP_HEAD_STATE3_0) \
_op_(SOR_NV_PDISP_HEAD_STATE3) \
_op_(SOR_NV_PDISP_HEAD_STATE3_1) \
_op_(SOR_NV_PDISP_HEAD_STATE3_2) \
_op_(SOR_NV_PDISP_HEAD_STATE3_3) \
_op_(SOR_NV_PDISP_HEAD_STATE4_0) \
_op_(SOR_NV_PDISP_HEAD_STATE4) \
_op_(SOR_NV_PDISP_HEAD_STATE4_1) \
_op_(SOR_NV_PDISP_HEAD_STATE4_2) \
_op_(SOR_NV_PDISP_HEAD_STATE4_3) \
_op_(SOR_NV_PDISP_HEAD_STATE5_0) \
_op_(SOR_NV_PDISP_HEAD_STATE5) \
_op_(SOR_NV_PDISP_HEAD_STATE5_1) \
_op_(SOR_NV_PDISP_HEAD_STATE5_2) \
_op_(SOR_NV_PDISP_HEAD_STATE5_3) \
_op_(SOR_NV_PDISP_SOR_PLL0_0) \
_op_(SOR_NV_PDISP_SOR_PLL1_0) \
_op_(SOR_NV_PDISP_SOR_PLL2_0) \
_op_(SOR_NV_PDISP_SOR_PLL3_0) \
_op_(SOR_NV_PDISP_SOR_PLL4_0) \
_op_(SOR_NV_PDISP_SOR_DP_PADCTL0_0) \
_op_(SOR_NV_PDISP_SOR_DP_PADCTL1_0) \
_op_(SOR_NV_PDISP_SOR_DP_PADCTL2_0) \
_op_(SOR_NV_PDISP_SOR_DP_PADCTL3_0) \
_op_(SOR_NV_PDISP_SOR_DP_BS_0) \
_op_(SOR_NV_PDISP_SOR_DP_MISC1_OVERRIDE_0) \
_op_(SOR_NV_PDISP_SOR_DP_MISC1_BIT6_0) \
_op_(SOR_NV_PDISP_DP_INT_STATUS_0) \
_op_(SOR_NV_PDISP_DP_INT_MASK_0) \
_op_(SOR_NV_PDISP_DP_INT_ENABLE_0) \
_op_(SOR_NV_PDISP_SOR_VPR_POLICY_0) \
_op_(SOR_NV_PDISP_SOR_PLL5_0) \
_op_(SOR_NV_PDISP_SOR_AFIFO_CTRL_0) \
_op_(SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0) \

//
// ADDRESS SPACES
//

#define BASE_ADDRESS_SOR        0x00000000
#define BASE_ADDRESS_SOR_EC_REGS        0x00000200

//
// ARSOR1 REGISTER BANKS
//

#define SOR0_FIRST_REG 0x0001 // SOR_NV_PDISP_SOR_SUPER_STATE0_0
#define SOR0_LAST_REG 0x0004 // SOR_NV_PDISP_SOR_STATE1_0
#define SOR1_FIRST_REG 0x0011 // SOR_NV_PDISP_SOR_CRC_CNTRL_0
#define SOR1_LAST_REG 0x0016 // SOR_NV_PDISP_SOR_TEST_0
#define SOR2_FIRST_REG 0x001b // SOR_NV_PDISP_SOR_CSTM_0
#define SOR2_LAST_REG 0x005b // SOR_NV_PDISP_SOR_DP_MN1_0
#define SOR3_FIRST_REG 0x005e // SOR_NV_PDISP_SOR_DP_DEBUG0_0
#define SOR3_LAST_REG 0x0071 // SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0
#define SOR4_FIRST_REG 0x0075 // SOR_NV_PDISP_SOR_DP_HDCP_AN_MSB_0
#define SOR4_LAST_REG 0x00cd // SOR_NV_PDISP_SOR_HDMI_SPDIF_CHN_STATUS2_0
#define SOR5_FIRST_REG 0x00cf // SOR_NV_PDISP_HDCPRIF_ROM_CTRL_0
#define SOR5_LAST_REG 0x00cf // SOR_NV_PDISP_HDCPRIF_ROM_CTRL_0
#define SOR6_FIRST_REG 0x00e5 // SOR_NV_PDISP_HDCPRIF_ROM_TIMING_0
#define SOR6_LAST_REG 0x00f3 // SOR_NV_PDISP_KEY_SKEY_INDEX_0
#define SOR7_FIRST_REG 0x00fc // SOR_NV_PDISP_SOR_AUDIO_CNTRL0_0
#define SOR7_LAST_REG 0x0117 // SOR_NV_PDISP_SOR_AUDIO_GEN_CTRL_0
#define SOR8_FIRST_REG 0x011c // SOR_NV_PDISP_INT_STATUS_0
#define SOR8_LAST_REG 0x017d // SOR_NV_PDISP_SOR_FPGA_CLK_SEL_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif
#ifndef _MK_FIELD_CONST
  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
#endif

#endif // ifndef ___ARSOR1_H_INC_
