//
// Copyright (c) 2018 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ___ARPWM_H_INC_
#define ___ARPWM_H_INC_
#define NV_MOBILE_ARPWM_H_UNIT_OF_OFFSET 1B


// Register PWM_CONTROLLER_PWM_CSR_0_0
#define PWM_CONTROLLER_PWM_CSR_0_0                      _MK_ADDR_CONST(0x0)
#define PWM_CONTROLLER_PWM_CSR_0_0_SECURE                       0x0
#define PWM_CONTROLLER_PWM_CSR_0_0_DUAL                         0x0
#define PWM_CONTROLLER_PWM_CSR_0_0_SCR                  0
#define PWM_CONTROLLER_PWM_CSR_0_0_WORD_COUNT                   0x1
#define PWM_CONTROLLER_PWM_CSR_0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define PWM_CONTROLLER_PWM_CSR_0_0_RESET_MASK                   _MK_MASK_CONST(0xffff1fff)
#define PWM_CONTROLLER_PWM_CSR_0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define PWM_CONTROLLER_PWM_CSR_0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define PWM_CONTROLLER_PWM_CSR_0_0_READ_MASK                    _MK_MASK_CONST(0xffff1fff)
#define PWM_CONTROLLER_PWM_CSR_0_0_WRITE_MASK                   _MK_MASK_CONST(0xffff1fff)
#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_FIELD                    _MK_FIELD_CONST(0x1, PWM_CONTROLLER_PWM_CSR_0_0_ENB_SHIFT)
#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_RANGE                    31:31
#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_WOFFSET                  0x0
#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_ENABLE                   _MK_ENUM_CONST(1)

#define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_SHIFT                  _MK_SHIFT_CONST(16)
#define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_FIELD                  _MK_FIELD_CONST(0x7fff, PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_SHIFT)
#define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_RANGE                  30:16
#define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_WOFFSET                        0x0
#define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_DEFAULT                        _MK_MASK_CONST(0x0)
#define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_DEFAULT_MASK                   _MK_MASK_CONST(0x7fff)
#define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_SHIFT                  _MK_SHIFT_CONST(0)
#define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_FIELD                  _MK_FIELD_CONST(0x1fff, PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_SHIFT)
#define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_RANGE                  12:0
#define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_WOFFSET                        0x0
#define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_DEFAULT                        _MK_MASK_CONST(0x0)
#define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1fff)
#define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


//
// REGISTER LIST
//
#define LIST_ARPWM_REGS(_op_) \
_op_(PWM_CONTROLLER_PWM_CSR_0_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_PWM_CONTROLLER     0x00000000

//
// ARPWM REGISTER BANKS
//

#define PWM_CONTROLLER0_FIRST_REG 0x0000 // PWM_CONTROLLER_PWM_CSR_0_0
#define PWM_CONTROLLER0_LAST_REG 0x0000 // PWM_CONTROLLER_PWM_CSR_0_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif
#ifndef _MK_FIELD_CONST
  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
#endif

#endif // ifndef ___ARPWM_H_INC_
