//
// Copyright (c) 2018 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ___ARFUSE_H_INC_
#define ___ARFUSE_H_INC_
#define NV_MOBILE_ARFUSE_H_UNIT_OF_OFFSET 1B

#define fuse_clk_period_in_nanosecs     21

// Register FUSE_FUSECTRL_0
#define FUSE_FUSECTRL_0                 _MK_ADDR_CONST(0x0)
#define FUSE_FUSECTRL_0_SECURE                  0x0
#define FUSE_FUSECTRL_0_DUAL                    0x0
#define FUSE_FUSECTRL_0_SCR                     0
#define FUSE_FUSECTRL_0_WORD_COUNT                      0x1
#define FUSE_FUSECTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_RESET_MASK                      _MK_MASK_CONST(0x17e00003)
#define FUSE_FUSECTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_READ_MASK                       _MK_MASK_CONST(0xd7ff0000)
#define FUSE_FUSECTRL_0_WRITE_MASK                      _MK_MASK_CONST(0x17e00003)
#define FUSE_FUSECTRL_0_FUSECTRL_CMD_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_FUSECTRL_0_FUSECTRL_CMD_FIELD                      _MK_FIELD_CONST(0x3, FUSE_FUSECTRL_0_FUSECTRL_CMD_SHIFT)
#define FUSE_FUSECTRL_0_FUSECTRL_CMD_RANGE                      1:0
#define FUSE_FUSECTRL_0_FUSECTRL_CMD_WOFFSET                    0x0
#define FUSE_FUSECTRL_0_FUSECTRL_CMD_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_CMD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define FUSE_FUSECTRL_0_FUSECTRL_CMD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_CMD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_CMD_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_CMD_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define FUSE_FUSECTRL_0_FUSECTRL_CMD_INIT_ENUM                  IDLE
#define FUSE_FUSECTRL_0_FUSECTRL_CMD_IDLE                       _MK_ENUM_CONST(0)
#define FUSE_FUSECTRL_0_FUSECTRL_CMD_READ                       _MK_ENUM_CONST(1)
#define FUSE_FUSECTRL_0_FUSECTRL_CMD_WRITE                      _MK_ENUM_CONST(2)
#define FUSE_FUSECTRL_0_FUSECTRL_CMD_SENSE_CTRL                 _MK_ENUM_CONST(3)

#define FUSE_FUSECTRL_0_FUSECTRL_STATE_SHIFT                    _MK_SHIFT_CONST(16)
#define FUSE_FUSECTRL_0_FUSECTRL_STATE_FIELD                    _MK_FIELD_CONST(0x1f, FUSE_FUSECTRL_0_FUSECTRL_STATE_SHIFT)
#define FUSE_FUSECTRL_0_FUSECTRL_STATE_RANGE                    20:16
#define FUSE_FUSECTRL_0_FUSECTRL_STATE_WOFFSET                  0x0
#define FUSE_FUSECTRL_0_FUSECTRL_STATE_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_STATE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_STATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_STATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_STATE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_STATE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_RESET                      _MK_ENUM_CONST(0)
#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_POST_RESET                 _MK_ENUM_CONST(1)
#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_LOAD_ROW0                  _MK_ENUM_CONST(2)
#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_LOAD_ROW1                  _MK_ENUM_CONST(3)
#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_IDLE                       _MK_ENUM_CONST(4)
#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_READ_SETUP                 _MK_ENUM_CONST(5)
#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_READ_STROBE                        _MK_ENUM_CONST(6)
#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_SAMPLE_FUSES                       _MK_ENUM_CONST(7)
#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_READ_HOLD                  _MK_ENUM_CONST(8)
#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_FUSE_SRC_SETUP                     _MK_ENUM_CONST(9)
#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_WRITE_SETUP                        _MK_ENUM_CONST(10)
#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_WRITE_ADDR_SETUP                   _MK_ENUM_CONST(11)
#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_WRITE_PROGRAM                      _MK_ENUM_CONST(12)
#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_WRITE_ADDR_HOLD                    _MK_ENUM_CONST(13)
#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_FUSE_SRC_HOLD                      _MK_ENUM_CONST(14)
#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_LOAD_RIR                   _MK_ENUM_CONST(15)
#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_READ_BEFORE_WRITE_SETUP                    _MK_ENUM_CONST(16)
#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_READ_DEASSERT_PD                   _MK_ENUM_CONST(17)

#define FUSE_FUSECTRL_0_FUSECTRL_MARGIN_READ_SHIFT                      _MK_SHIFT_CONST(21)
#define FUSE_FUSECTRL_0_FUSECTRL_MARGIN_READ_FIELD                      _MK_FIELD_CONST(0x1, FUSE_FUSECTRL_0_FUSECTRL_MARGIN_READ_SHIFT)
#define FUSE_FUSECTRL_0_FUSECTRL_MARGIN_READ_RANGE                      21:21
#define FUSE_FUSECTRL_0_FUSECTRL_MARGIN_READ_WOFFSET                    0x0
#define FUSE_FUSECTRL_0_FUSECTRL_MARGIN_READ_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_MARGIN_READ_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_FUSECTRL_0_FUSECTRL_MARGIN_READ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_MARGIN_READ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_MARGIN_READ_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_MARGIN_READ_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define FUSE_FUSECTRL_0_FUSECTRL_RWL_SHIFT                      _MK_SHIFT_CONST(22)
#define FUSE_FUSECTRL_0_FUSECTRL_RWL_FIELD                      _MK_FIELD_CONST(0x1, FUSE_FUSECTRL_0_FUSECTRL_RWL_SHIFT)
#define FUSE_FUSECTRL_0_FUSECTRL_RWL_RANGE                      22:22
#define FUSE_FUSECTRL_0_FUSECTRL_RWL_WOFFSET                    0x0
#define FUSE_FUSECTRL_0_FUSECTRL_RWL_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_RWL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_FUSECTRL_0_FUSECTRL_RWL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_RWL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_RWL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_RWL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define FUSE_FUSECTRL_0_FUSECTRL_TRCS_SHIFT                     _MK_SHIFT_CONST(23)
#define FUSE_FUSECTRL_0_FUSECTRL_TRCS_FIELD                     _MK_FIELD_CONST(0x1, FUSE_FUSECTRL_0_FUSECTRL_TRCS_SHIFT)
#define FUSE_FUSECTRL_0_FUSECTRL_TRCS_RANGE                     23:23
#define FUSE_FUSECTRL_0_FUSECTRL_TRCS_WOFFSET                   0x0
#define FUSE_FUSECTRL_0_FUSECTRL_TRCS_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_TRCS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_FUSECTRL_0_FUSECTRL_TRCS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_TRCS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_TRCS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_TRCS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define FUSE_FUSECTRL_0_FUSECTRL_AT1_SHIFT                      _MK_SHIFT_CONST(24)
#define FUSE_FUSECTRL_0_FUSECTRL_AT1_FIELD                      _MK_FIELD_CONST(0x1, FUSE_FUSECTRL_0_FUSECTRL_AT1_SHIFT)
#define FUSE_FUSECTRL_0_FUSECTRL_AT1_RANGE                      24:24
#define FUSE_FUSECTRL_0_FUSECTRL_AT1_WOFFSET                    0x0
#define FUSE_FUSECTRL_0_FUSECTRL_AT1_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_AT1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_FUSECTRL_0_FUSECTRL_AT1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_AT1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_AT1_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_AT1_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define FUSE_FUSECTRL_0_FUSECTRL_AT0_SHIFT                      _MK_SHIFT_CONST(25)
#define FUSE_FUSECTRL_0_FUSECTRL_AT0_FIELD                      _MK_FIELD_CONST(0x1, FUSE_FUSECTRL_0_FUSECTRL_AT0_SHIFT)
#define FUSE_FUSECTRL_0_FUSECTRL_AT0_RANGE                      25:25
#define FUSE_FUSECTRL_0_FUSECTRL_AT0_WOFFSET                    0x0
#define FUSE_FUSECTRL_0_FUSECTRL_AT0_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_AT0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_FUSECTRL_0_FUSECTRL_AT0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_AT0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_AT0_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_AT0_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define FUSE_FUSECTRL_0_FUSECTRL_PD_CTRL_SHIFT                  _MK_SHIFT_CONST(26)
#define FUSE_FUSECTRL_0_FUSECTRL_PD_CTRL_FIELD                  _MK_FIELD_CONST(0x1, FUSE_FUSECTRL_0_FUSECTRL_PD_CTRL_SHIFT)
#define FUSE_FUSECTRL_0_FUSECTRL_PD_CTRL_RANGE                  26:26
#define FUSE_FUSECTRL_0_FUSECTRL_PD_CTRL_WOFFSET                        0x0
#define FUSE_FUSECTRL_0_FUSECTRL_PD_CTRL_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_PD_CTRL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_FUSECTRL_0_FUSECTRL_PD_CTRL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_PD_CTRL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_PD_CTRL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_PD_CTRL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define FUSE_FUSECTRL_0_FUSECTRL_DISABLE_MIRROR_SHIFT                   _MK_SHIFT_CONST(28)
#define FUSE_FUSECTRL_0_FUSECTRL_DISABLE_MIRROR_FIELD                   _MK_FIELD_CONST(0x1, FUSE_FUSECTRL_0_FUSECTRL_DISABLE_MIRROR_SHIFT)
#define FUSE_FUSECTRL_0_FUSECTRL_DISABLE_MIRROR_RANGE                   28:28
#define FUSE_FUSECTRL_0_FUSECTRL_DISABLE_MIRROR_WOFFSET                 0x0
#define FUSE_FUSECTRL_0_FUSECTRL_DISABLE_MIRROR_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_DISABLE_MIRROR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_FUSECTRL_0_FUSECTRL_DISABLE_MIRROR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_DISABLE_MIRROR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_DISABLE_MIRROR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_DISABLE_MIRROR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_SHIFT                  _MK_SHIFT_CONST(30)
#define FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_FIELD                  _MK_FIELD_CONST(0x1, FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_SHIFT)
#define FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_RANGE                  30:30
#define FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_WOFFSET                        0x0
#define FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define FUSE_FUSECTRL_0_FUSECTRL_RECORD_SHIFT_DONE_SHIFT                        _MK_SHIFT_CONST(31)
#define FUSE_FUSECTRL_0_FUSECTRL_RECORD_SHIFT_DONE_FIELD                        _MK_FIELD_CONST(0x1, FUSE_FUSECTRL_0_FUSECTRL_RECORD_SHIFT_DONE_SHIFT)
#define FUSE_FUSECTRL_0_FUSECTRL_RECORD_SHIFT_DONE_RANGE                        31:31
#define FUSE_FUSECTRL_0_FUSECTRL_RECORD_SHIFT_DONE_WOFFSET                      0x0
#define FUSE_FUSECTRL_0_FUSECTRL_RECORD_SHIFT_DONE_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_RECORD_SHIFT_DONE_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_RECORD_SHIFT_DONE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_RECORD_SHIFT_DONE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_RECORD_SHIFT_DONE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_FUSECTRL_0_FUSECTRL_RECORD_SHIFT_DONE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_FUSEADDR_0
#define FUSE_FUSEADDR_0                 _MK_ADDR_CONST(0x4)
#define FUSE_FUSEADDR_0_SECURE                  0x0
#define FUSE_FUSEADDR_0_DUAL                    0x0
#define FUSE_FUSEADDR_0_SCR                     0
#define FUSE_FUSEADDR_0_WORD_COUNT                      0x1
#define FUSE_FUSEADDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_FUSEADDR_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define FUSE_FUSEADDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_FUSEADDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_FUSEADDR_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define FUSE_FUSEADDR_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
#define FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_SHIFT                   _MK_SHIFT_CONST(0)
#define FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_FIELD                   _MK_FIELD_CONST(0xff, FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_SHIFT)
#define FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_RANGE                   7:0
#define FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_WOFFSET                 0x0
#define FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
#define FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register FUSE_FUSERDATA_0
#define FUSE_FUSERDATA_0                        _MK_ADDR_CONST(0x8)
#define FUSE_FUSERDATA_0_SECURE                         0x0
#define FUSE_FUSERDATA_0_DUAL                   0x0
#define FUSE_FUSERDATA_0_SCR                    0
#define FUSE_FUSERDATA_0_WORD_COUNT                     0x1
#define FUSE_FUSERDATA_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_FUSERDATA_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_FUSERDATA_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_FUSERDATA_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_FUSERDATA_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define FUSE_FUSERDATA_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_FUSERDATA_0_FUSERDATA_DATA_SHIFT                   _MK_SHIFT_CONST(0)
#define FUSE_FUSERDATA_0_FUSERDATA_DATA_FIELD                   _MK_FIELD_CONST(0xffffffff, FUSE_FUSERDATA_0_FUSERDATA_DATA_SHIFT)
#define FUSE_FUSERDATA_0_FUSERDATA_DATA_RANGE                   31:0
#define FUSE_FUSERDATA_0_FUSERDATA_DATA_WOFFSET                 0x0
#define FUSE_FUSERDATA_0_FUSERDATA_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_FUSERDATA_0_FUSERDATA_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_FUSERDATA_0_FUSERDATA_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_FUSERDATA_0_FUSERDATA_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define FUSE_FUSERDATA_0_FUSERDATA_DATA_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define FUSE_FUSERDATA_0_FUSERDATA_DATA_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register FUSE_FUSEWDATA_0
#define FUSE_FUSEWDATA_0                        _MK_ADDR_CONST(0xc)
#define FUSE_FUSEWDATA_0_SECURE                         0x0
#define FUSE_FUSEWDATA_0_DUAL                   0x0
#define FUSE_FUSEWDATA_0_SCR                    0
#define FUSE_FUSEWDATA_0_WORD_COUNT                     0x1
#define FUSE_FUSEWDATA_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_FUSEWDATA_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_FUSEWDATA_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_FUSEWDATA_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_FUSEWDATA_0_READ_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_FUSEWDATA_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_FUSEWDATA_0_FUSEWDATA_DATA_SHIFT                   _MK_SHIFT_CONST(0)
#define FUSE_FUSEWDATA_0_FUSEWDATA_DATA_FIELD                   _MK_FIELD_CONST(0xffffffff, FUSE_FUSEWDATA_0_FUSEWDATA_DATA_SHIFT)
#define FUSE_FUSEWDATA_0_FUSEWDATA_DATA_RANGE                   31:0
#define FUSE_FUSEWDATA_0_FUSEWDATA_DATA_WOFFSET                 0x0
#define FUSE_FUSEWDATA_0_FUSEWDATA_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_FUSEWDATA_0_FUSEWDATA_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define FUSE_FUSEWDATA_0_FUSEWDATA_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_FUSEWDATA_0_FUSEWDATA_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define FUSE_FUSEWDATA_0_FUSEWDATA_DATA_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define FUSE_FUSEWDATA_0_FUSEWDATA_DATA_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define FUSETIME_RD1_TSUR_MAX_NANOSECONDS       104
#define FUSETIME_RD1_TSUR_FUSEOUT_NANOSECONDS   104
#define FUSETIME_RD1_THR_MAX_NANOSECONDS        124

// Register FUSE_FUSETIME_RD1_0
#define FUSE_FUSETIME_RD1_0                     _MK_ADDR_CONST(0x10)
#define FUSE_FUSETIME_RD1_0_SECURE                      0x0
#define FUSE_FUSETIME_RD1_0_DUAL                        0x0
#define FUSE_FUSETIME_RD1_0_SCR                         0
#define FUSE_FUSETIME_RD1_0_WORD_COUNT                  0x1
#define FUSE_FUSETIME_RD1_0_RESET_VAL                   _MK_MASK_CONST(0x60505)
#define FUSE_FUSETIME_RD1_0_RESET_MASK                  _MK_MASK_CONST(0xffffff)
#define FUSE_FUSETIME_RD1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_RD1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_RD1_0_READ_MASK                   _MK_MASK_CONST(0xffffff)
#define FUSE_FUSETIME_RD1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_SHIFT                 _MK_SHIFT_CONST(0)
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_FIELD                 _MK_FIELD_CONST(0xff, FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_SHIFT)
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_RANGE                 7:0
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_WOFFSET                       0x0
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_DEFAULT                       _MK_MASK_CONST(0x5)
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_SHIFT                     _MK_SHIFT_CONST(8)
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_FIELD                     _MK_FIELD_CONST(0xff, FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_SHIFT)
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_RANGE                     15:8
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_WOFFSET                   0x0
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_DEFAULT                   _MK_MASK_CONST(0x5)
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_SHIFT                  _MK_SHIFT_CONST(16)
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_FIELD                  _MK_FIELD_CONST(0xff, FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_SHIFT)
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_RANGE                  23:16
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_WOFFSET                        0x0
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_DEFAULT                        _MK_MASK_CONST(0x6)
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define FUSETIME_RD2_TWIDTH_RD_NANOSECONDS      1187

// Register FUSE_FUSETIME_RD2_0
#define FUSE_FUSETIME_RD2_0                     _MK_ADDR_CONST(0x14)
#define FUSE_FUSETIME_RD2_0_SECURE                      0x0
#define FUSE_FUSETIME_RD2_0_DUAL                        0x0
#define FUSE_FUSETIME_RD2_0_SCR                         0
#define FUSE_FUSETIME_RD2_0_WORD_COUNT                  0x1
#define FUSE_FUSETIME_RD2_0_RESET_VAL                   _MK_MASK_CONST(0x39)
#define FUSE_FUSETIME_RD2_0_RESET_MASK                  _MK_MASK_CONST(0xffff)
#define FUSE_FUSETIME_RD2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_RD2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_RD2_0_READ_MASK                   _MK_MASK_CONST(0xffff)
#define FUSE_FUSETIME_RD2_0_WRITE_MASK                  _MK_MASK_CONST(0xffff)
#define FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_FIELD                        _MK_FIELD_CONST(0xffff, FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_SHIFT)
#define FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_RANGE                        15:0
#define FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_WOFFSET                      0x0
#define FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_DEFAULT                      _MK_MASK_CONST(0x39)
#define FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define FUSETIME_PGM1_TSUP_MAX_NANOSECONDS      20
#define FUSETIME_PGM1_TSUP_ADDR_NANOSECONDS     104
#define FUSETIME_PGM1_THP_ADDR_NANOSECONDS      104
#define FUSETIME_PGM1_THP_PS_NANOSECONDS        124

// Register FUSE_FUSETIME_PGM1_0
#define FUSE_FUSETIME_PGM1_0                    _MK_ADDR_CONST(0x18)
#define FUSE_FUSETIME_PGM1_0_SECURE                     0x0
#define FUSE_FUSETIME_PGM1_0_DUAL                       0x0
#define FUSE_FUSETIME_PGM1_0_SCR                        0
#define FUSE_FUSETIME_PGM1_0_WORD_COUNT                         0x1
#define FUSE_FUSETIME_PGM1_0_RESET_VAL                  _MK_MASK_CONST(0x6050501)
#define FUSE_FUSETIME_PGM1_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_FUSETIME_PGM1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_PGM1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_PGM1_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_FUSETIME_PGM1_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_SHIFT                       _MK_SHIFT_CONST(0)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_FIELD                       _MK_FIELD_CONST(0xff, FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_SHIFT)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_RANGE                       7:0
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_WOFFSET                     0x0
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_DEFAULT                     _MK_MASK_CONST(0x1)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_SHIFT                      _MK_SHIFT_CONST(8)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_FIELD                      _MK_FIELD_CONST(0xff, FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_SHIFT)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_RANGE                      15:8
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_WOFFSET                    0x0
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_DEFAULT                    _MK_MASK_CONST(0x5)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_SHIFT                       _MK_SHIFT_CONST(16)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_FIELD                       _MK_FIELD_CONST(0xff, FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_SHIFT)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_RANGE                       23:16
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_WOFFSET                     0x0
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_DEFAULT                     _MK_MASK_CONST(0x5)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_PS_SHIFT                 _MK_SHIFT_CONST(24)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_PS_FIELD                 _MK_FIELD_CONST(0xff, FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_PS_SHIFT)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_PS_RANGE                 31:24
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_PS_WOFFSET                       0x0
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_PS_DEFAULT                       _MK_MASK_CONST(0x6)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_PS_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_PS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_PS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_PS_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_PS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define FUSETIME_PGM2_TWIDTH_PGM_NANOSECONDS    5020
#define FUSETIME_PGM2_TSUP_PS_NANOSECONDS       145
#define FUSETIME_PGM2_THP_CSPS_NANOSECONDS      124

// Register FUSE_FUSETIME_PGM2_0
#define FUSE_FUSETIME_PGM2_0                    _MK_ADDR_CONST(0x1c)
#define FUSE_FUSETIME_PGM2_0_SECURE                     0x0
#define FUSE_FUSETIME_PGM2_0_DUAL                       0x0
#define FUSE_FUSETIME_PGM2_0_SCR                        0
#define FUSE_FUSETIME_PGM2_0_WORD_COUNT                         0x1
#define FUSE_FUSETIME_PGM2_0_RESET_VAL                  _MK_MASK_CONST(0x60700f1)
#define FUSE_FUSETIME_PGM2_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_FUSETIME_PGM2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_PGM2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_PGM2_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_FUSETIME_PGM2_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_SHIFT                     _MK_SHIFT_CONST(0)
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_FIELD                     _MK_FIELD_CONST(0xffff, FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_SHIFT)
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_RANGE                     15:0
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_WOFFSET                   0x0
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_DEFAULT                   _MK_MASK_CONST(0xf1)
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TSUP_PS_SHIFT                        _MK_SHIFT_CONST(16)
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TSUP_PS_FIELD                        _MK_FIELD_CONST(0xff, FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TSUP_PS_SHIFT)
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TSUP_PS_RANGE                        23:16
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TSUP_PS_WOFFSET                      0x0
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TSUP_PS_DEFAULT                      _MK_MASK_CONST(0x7)
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TSUP_PS_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TSUP_PS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TSUP_PS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TSUP_PS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TSUP_PS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_THP_CSPS_SHIFT                       _MK_SHIFT_CONST(24)
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_THP_CSPS_FIELD                       _MK_FIELD_CONST(0xff, FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_THP_CSPS_SHIFT)
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_THP_CSPS_RANGE                       31:24
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_THP_CSPS_WOFFSET                     0x0
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_THP_CSPS_DEFAULT                     _MK_MASK_CONST(0x6)
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_THP_CSPS_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_THP_CSPS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_THP_CSPS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_THP_CSPS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_THP_CSPS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

// Register FUSE_PRIV2INTFC_START_0
#define FUSE_PRIV2INTFC_START_0                 _MK_ADDR_CONST(0x20)
#define FUSE_PRIV2INTFC_START_0_SECURE                  0x0
#define FUSE_PRIV2INTFC_START_0_DUAL                    0x0
#define FUSE_PRIV2INTFC_START_0_SCR                     0
#define FUSE_PRIV2INTFC_START_0_WORD_COUNT                      0x1
#define FUSE_PRIV2INTFC_START_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_PRIV2INTFC_START_0_RESET_MASK                      _MK_MASK_CONST(0x3)
#define FUSE_PRIV2INTFC_START_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_PRIV2INTFC_START_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_PRIV2INTFC_START_0_READ_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_PRIV2INTFC_START_0_WRITE_MASK                      _MK_MASK_CONST(0x3)
#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_SHIFT                     _MK_SHIFT_CONST(0)
#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_FIELD                     _MK_FIELD_CONST(0x1, FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_SHIFT)
#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_RANGE                     0:0
#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_WOFFSET                   0x0
#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RECORDS_SHIFT                   _MK_SHIFT_CONST(1)
#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RECORDS_FIELD                   _MK_FIELD_CONST(0x1, FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RECORDS_SHIFT)
#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RECORDS_RANGE                   1:1
#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RECORDS_WOFFSET                 0x0
#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RECORDS_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RECORDS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RECORDS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RECORDS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RECORDS_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RECORDS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

// Register FUSE_FUSEBYPASS_0
#define FUSE_FUSEBYPASS_0                       _MK_ADDR_CONST(0x24)
#define FUSE_FUSEBYPASS_0_SECURE                        0x0
#define FUSE_FUSEBYPASS_0_DUAL                  0x0
#define FUSE_FUSEBYPASS_0_SCR                   0
#define FUSE_FUSEBYPASS_0_WORD_COUNT                    0x1
#define FUSE_FUSEBYPASS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_FUSEBYPASS_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_FUSEBYPASS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_FUSEBYPASS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_FUSEBYPASS_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_FUSEBYPASS_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_FIELD                  _MK_FIELD_CONST(0x1, FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_SHIFT)
#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_RANGE                  0:0
#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_WOFFSET                        0x0
#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_INIT_ENUM                      DISABLED
#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_DISABLED                       _MK_ENUM_CONST(0)
#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_ENABLED                        _MK_ENUM_CONST(1)
#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_DISABLE                        _MK_ENUM_CONST(0)
#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_ENABLE                 _MK_ENUM_CONST(1)

// Register FUSE_PRIVATEKEYDISABLE_0
#define FUSE_PRIVATEKEYDISABLE_0                        _MK_ADDR_CONST(0x28)
#define FUSE_PRIVATEKEYDISABLE_0_SECURE                         0x0
#define FUSE_PRIVATEKEYDISABLE_0_DUAL                   0x0
#define FUSE_PRIVATEKEYDISABLE_0_SCR                    0
#define FUSE_PRIVATEKEYDISABLE_0_WORD_COUNT                     0x1
#define FUSE_PRIVATEKEYDISABLE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_PRIVATEKEYDISABLE_0_RESET_MASK                     _MK_MASK_CONST(0x11)
#define FUSE_PRIVATEKEYDISABLE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_PRIVATEKEYDISABLE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_PRIVATEKEYDISABLE_0_READ_MASK                      _MK_MASK_CONST(0x11)
#define FUSE_PRIVATEKEYDISABLE_0_WRITE_MASK                     _MK_MASK_CONST(0x11)
#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_SHIFT)
#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_RANGE                    0:0
#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_WOFFSET                  0x0
#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_INIT_ENUM                        KEY_VISIBLE
#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_KEY_VISIBLE                      _MK_ENUM_CONST(0)
#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_KEY_INVISIBLE                    _MK_ENUM_CONST(1)

#define FUSE_PRIVATEKEYDISABLE_0_TZ_STICKY_BIT_VAL_SHIFT                        _MK_SHIFT_CONST(4)
#define FUSE_PRIVATEKEYDISABLE_0_TZ_STICKY_BIT_VAL_FIELD                        _MK_FIELD_CONST(0x1, FUSE_PRIVATEKEYDISABLE_0_TZ_STICKY_BIT_VAL_SHIFT)
#define FUSE_PRIVATEKEYDISABLE_0_TZ_STICKY_BIT_VAL_RANGE                        4:4
#define FUSE_PRIVATEKEYDISABLE_0_TZ_STICKY_BIT_VAL_WOFFSET                      0x0
#define FUSE_PRIVATEKEYDISABLE_0_TZ_STICKY_BIT_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_PRIVATEKEYDISABLE_0_TZ_STICKY_BIT_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define FUSE_PRIVATEKEYDISABLE_0_TZ_STICKY_BIT_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_PRIVATEKEYDISABLE_0_TZ_STICKY_BIT_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_PRIVATEKEYDISABLE_0_TZ_STICKY_BIT_VAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_PRIVATEKEYDISABLE_0_TZ_STICKY_BIT_VAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define FUSE_PRIVATEKEYDISABLE_0_TZ_STICKY_BIT_VAL_INIT_ENUM                    KEY_VISIBLE
#define FUSE_PRIVATEKEYDISABLE_0_TZ_STICKY_BIT_VAL_KEY_VISIBLE                  _MK_ENUM_CONST(0)
#define FUSE_PRIVATEKEYDISABLE_0_TZ_STICKY_BIT_VAL_KEY_INVISIBLE                        _MK_ENUM_CONST(1)

// Register FUSE_DISABLEREGPROGRAM_0
#define FUSE_DISABLEREGPROGRAM_0                        _MK_ADDR_CONST(0x2c)
#define FUSE_DISABLEREGPROGRAM_0_SECURE                         0x0
#define FUSE_DISABLEREGPROGRAM_0_DUAL                   0x0
#define FUSE_DISABLEREGPROGRAM_0_SCR                    0
#define FUSE_DISABLEREGPROGRAM_0_WORD_COUNT                     0x1
#define FUSE_DISABLEREGPROGRAM_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_DISABLEREGPROGRAM_0_RESET_MASK                     _MK_MASK_CONST(0x31)
#define FUSE_DISABLEREGPROGRAM_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_DISABLEREGPROGRAM_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_DISABLEREGPROGRAM_0_READ_MASK                      _MK_MASK_CONST(0x31)
#define FUSE_DISABLEREGPROGRAM_0_WRITE_MASK                     _MK_MASK_CONST(0x31)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_SHIFT)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_RANGE                    0:0
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_WOFFSET                  0x0
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_INIT_ENUM                        DISABLED
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_DISABLED                 _MK_ENUM_CONST(0)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_ENABLED                  _MK_ENUM_CONST(1)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_DISABLE                  _MK_ENUM_CONST(0)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_ENABLE                   _MK_ENUM_CONST(1)

#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_NV_SHIFT                  _MK_SHIFT_CONST(4)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_NV_FIELD                  _MK_FIELD_CONST(0x1, FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_NV_SHIFT)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_NV_RANGE                  4:4
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_NV_WOFFSET                        0x0
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_NV_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_NV_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_NV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_NV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_NV_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_NV_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_NV_INIT_ENUM                      DISABLED
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_NV_DISABLED                       _MK_ENUM_CONST(0)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_NV_ENABLED                        _MK_ENUM_CONST(1)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_NV_DISABLE                        _MK_ENUM_CONST(0)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_NV_ENABLE                 _MK_ENUM_CONST(1)

#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_ODM_SHIFT                 _MK_SHIFT_CONST(5)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_ODM_FIELD                 _MK_FIELD_CONST(0x1, FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_ODM_SHIFT)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_ODM_RANGE                 5:5
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_ODM_WOFFSET                       0x0
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_ODM_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_ODM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_ODM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_ODM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_ODM_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_ODM_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_ODM_INIT_ENUM                     DISABLED
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_ODM_DISABLED                      _MK_ENUM_CONST(0)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_ODM_ENABLED                       _MK_ENUM_CONST(1)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_ODM_DISABLE                       _MK_ENUM_CONST(0)
#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_FIELD_BURN_DISABLE_ODM_ENABLE                        _MK_ENUM_CONST(1)

// Register FUSE_WRITE_ACCESS_SW_0
#define FUSE_WRITE_ACCESS_SW_0                  _MK_ADDR_CONST(0x30)
#define FUSE_WRITE_ACCESS_SW_0_SECURE                   0x0
#define FUSE_WRITE_ACCESS_SW_0_DUAL                     0x0
#define FUSE_WRITE_ACCESS_SW_0_SCR                      0
#define FUSE_WRITE_ACCESS_SW_0_WORD_COUNT                       0x1
#define FUSE_WRITE_ACCESS_SW_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define FUSE_WRITE_ACCESS_SW_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_WRITE_ACCESS_SW_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_WRITE_ACCESS_SW_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_WRITE_ACCESS_SW_0_READ_MASK                        _MK_MASK_CONST(0x10001)
#define FUSE_WRITE_ACCESS_SW_0_WRITE_MASK                       _MK_MASK_CONST(0x10001)
#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_SHIFT                       _MK_SHIFT_CONST(0)
#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_SHIFT)
#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_RANGE                       0:0
#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_WOFFSET                     0x0
#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_DEFAULT                     _MK_MASK_CONST(0x1)
#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_INIT_ENUM                   READONLY
#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_READWRITE                   _MK_ENUM_CONST(0)
#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_READONLY                    _MK_ENUM_CONST(1)

#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_SHIFT                     _MK_SHIFT_CONST(16)
#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_FIELD                     _MK_FIELD_CONST(0x1, FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_SHIFT)
#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_RANGE                     16:16
#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_WOFFSET                   0x0
#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_NOWRITE                   _MK_ENUM_CONST(0)
#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_WRITE                     _MK_ENUM_CONST(1)

// Reserved address 0x34

// Reserved address 0x38

// Reserved address 0x3c

// Reserved address 0x40

// Reserved address 0x44

// Reserved address 0x48
#define FUSETIME_RD3_TSUR_PDCS_NANOSECONDS      791

// Register FUSE_FUSETIME_RD3_0
#define FUSE_FUSETIME_RD3_0                     _MK_ADDR_CONST(0x4c)
#define FUSE_FUSETIME_RD3_0_SECURE                      0x0
#define FUSE_FUSETIME_RD3_0_DUAL                        0x0
#define FUSE_FUSETIME_RD3_0_SCR                         0
#define FUSE_FUSETIME_RD3_0_WORD_COUNT                  0x1
#define FUSE_FUSETIME_RD3_0_RESET_VAL                   _MK_MASK_CONST(0x26)
#define FUSE_FUSETIME_RD3_0_RESET_MASK                  _MK_MASK_CONST(0xffff)
#define FUSE_FUSETIME_RD3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_RD3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_RD3_0_READ_MASK                   _MK_MASK_CONST(0xffff)
#define FUSE_FUSETIME_RD3_0_WRITE_MASK                  _MK_MASK_CONST(0xffff)
#define FUSE_FUSETIME_RD3_0_FUSETIME_RD3_TSUR_PDCS_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_FUSETIME_RD3_0_FUSETIME_RD3_TSUR_PDCS_FIELD                        _MK_FIELD_CONST(0xffff, FUSE_FUSETIME_RD3_0_FUSETIME_RD3_TSUR_PDCS_SHIFT)
#define FUSE_FUSETIME_RD3_0_FUSETIME_RD3_TSUR_PDCS_RANGE                        15:0
#define FUSE_FUSETIME_RD3_0_FUSETIME_RD3_TSUR_PDCS_WOFFSET                      0x0
#define FUSE_FUSETIME_RD3_0_FUSETIME_RD3_TSUR_PDCS_DEFAULT                      _MK_MASK_CONST(0x26)
#define FUSE_FUSETIME_RD3_0_FUSETIME_RD3_TSUR_PDCS_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define FUSE_FUSETIME_RD3_0_FUSETIME_RD3_TSUR_PDCS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_RD3_0_FUSETIME_RD3_TSUR_PDCS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_RD3_0_FUSETIME_RD3_TSUR_PDCS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_FUSETIME_RD3_0_FUSETIME_RD3_TSUR_PDCS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Reserved address 0x50

// Reserved address 0x54

// Reserved address 0x58

// Reserved address 0x5c

// Register FUSE_SPARE_ADDR_START_0
#define FUSE_SPARE_ADDR_START_0                 _MK_ADDR_CONST(0x60)
#define FUSE_SPARE_ADDR_START_0_SECURE                  0x0
#define FUSE_SPARE_ADDR_START_0_DUAL                    0x0
#define FUSE_SPARE_ADDR_START_0_SCR                     0
#define FUSE_SPARE_ADDR_START_0_WORD_COUNT                      0x1
#define FUSE_SPARE_ADDR_START_0_RESET_VAL                       _MK_MASK_CONST(0x60c)
#define FUSE_SPARE_ADDR_START_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define FUSE_SPARE_ADDR_START_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_ADDR_START_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_SPARE_ADDR_START_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_SPARE_ADDR_START_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_ADDR_START_0_SPARE_ADDR_START_DATA_SHIFT                     _MK_SHIFT_CONST(0)
#define FUSE_SPARE_ADDR_START_0_SPARE_ADDR_START_DATA_FIELD                     _MK_FIELD_CONST(0xffffffff, FUSE_SPARE_ADDR_START_0_SPARE_ADDR_START_DATA_SHIFT)
#define FUSE_SPARE_ADDR_START_0_SPARE_ADDR_START_DATA_RANGE                     31:0
#define FUSE_SPARE_ADDR_START_0_SPARE_ADDR_START_DATA_WOFFSET                   0x0
#define FUSE_SPARE_ADDR_START_0_SPARE_ADDR_START_DATA_DEFAULT                   _MK_MASK_CONST(0x60c)
#define FUSE_SPARE_ADDR_START_0_SPARE_ADDR_START_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define FUSE_SPARE_ADDR_START_0_SPARE_ADDR_START_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_ADDR_START_0_SPARE_ADDR_START_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_ADDR_START_0_SPARE_ADDR_START_DATA_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_SPARE_ADDR_START_0_SPARE_ADDR_START_DATA_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Reserved address 0x64

// Register FUSE_CRC_STATUS_0
#define FUSE_CRC_STATUS_0                       _MK_ADDR_CONST(0x68)
#define FUSE_CRC_STATUS_0_SECURE                        0x0
#define FUSE_CRC_STATUS_0_DUAL                  0x0
#define FUSE_CRC_STATUS_0_SCR                   0
#define FUSE_CRC_STATUS_0_WORD_COUNT                    0x1
#define FUSE_CRC_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_CRC_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x7777)
#define FUSE_CRC_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_CRC_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_CRC_STATUS_0_READ_MASK                     _MK_MASK_CONST(0x7777)
#define FUSE_CRC_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H0_SHIFT                   _MK_SHIFT_CONST(0)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H0_FIELD                   _MK_FIELD_CONST(0x7, FUSE_CRC_STATUS_0_CRC_STATUS_H0_SHIFT)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H0_RANGE                   2:0
#define FUSE_CRC_STATUS_0_CRC_STATUS_H0_WOFFSET                 0x0
#define FUSE_CRC_STATUS_0_CRC_STATUS_H0_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H0_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H0_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H0_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H0_INIT_ENUM                       CRC_NOT_PARSED_YET
#define FUSE_CRC_STATUS_0_CRC_STATUS_H0_CRC_NOT_PARSED_YET                      _MK_ENUM_CONST(0)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H0_CRC_NOT_PRESENT                 _MK_ENUM_CONST(4)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H0_CRC_PRESENT_NO_ERRORS                   _MK_ENUM_CONST(5)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H0_CRC_PRESENT_CORRECTED_ERRORS                    _MK_ENUM_CONST(6)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H0_CRC_PRESENT_UNCORRECTED_ERRORS                  _MK_ENUM_CONST(7)

#define FUSE_CRC_STATUS_0_CRC_STATUS_H1_SHIFT                   _MK_SHIFT_CONST(4)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H1_FIELD                   _MK_FIELD_CONST(0x7, FUSE_CRC_STATUS_0_CRC_STATUS_H1_SHIFT)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H1_RANGE                   6:4
#define FUSE_CRC_STATUS_0_CRC_STATUS_H1_WOFFSET                 0x0
#define FUSE_CRC_STATUS_0_CRC_STATUS_H1_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H1_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H1_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H1_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H1_INIT_ENUM                       CRC_NOT_PARSED_YET
#define FUSE_CRC_STATUS_0_CRC_STATUS_H1_CRC_NOT_PARSED_YET                      _MK_ENUM_CONST(0)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H1_CRC_NOT_PRESENT                 _MK_ENUM_CONST(4)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H1_CRC_PRESENT_NO_ERRORS                   _MK_ENUM_CONST(5)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H1_CRC_PRESENT_CORRECTED_ERRORS                    _MK_ENUM_CONST(6)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H1_CRC_PRESENT_UNCORRECTED_ERRORS                  _MK_ENUM_CONST(7)

#define FUSE_CRC_STATUS_0_CRC_STATUS_H2_SHIFT                   _MK_SHIFT_CONST(8)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H2_FIELD                   _MK_FIELD_CONST(0x7, FUSE_CRC_STATUS_0_CRC_STATUS_H2_SHIFT)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H2_RANGE                   10:8
#define FUSE_CRC_STATUS_0_CRC_STATUS_H2_WOFFSET                 0x0
#define FUSE_CRC_STATUS_0_CRC_STATUS_H2_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H2_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H2_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H2_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H2_INIT_ENUM                       CRC_NOT_PARSED_YET
#define FUSE_CRC_STATUS_0_CRC_STATUS_H2_CRC_NOT_PARSED_YET                      _MK_ENUM_CONST(0)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H2_CRC_NOT_PRESENT                 _MK_ENUM_CONST(4)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H2_CRC_PRESENT_NO_ERRORS                   _MK_ENUM_CONST(5)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H2_CRC_PRESENT_CORRECTED_ERRORS                    _MK_ENUM_CONST(6)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H2_CRC_PRESENT_UNCORRECTED_ERRORS                  _MK_ENUM_CONST(7)

#define FUSE_CRC_STATUS_0_CRC_STATUS_H3_SHIFT                   _MK_SHIFT_CONST(12)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H3_FIELD                   _MK_FIELD_CONST(0x7, FUSE_CRC_STATUS_0_CRC_STATUS_H3_SHIFT)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H3_RANGE                   14:12
#define FUSE_CRC_STATUS_0_CRC_STATUS_H3_WOFFSET                 0x0
#define FUSE_CRC_STATUS_0_CRC_STATUS_H3_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H3_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H3_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H3_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H3_INIT_ENUM                       CRC_NOT_PARSED_YET
#define FUSE_CRC_STATUS_0_CRC_STATUS_H3_CRC_NOT_PARSED_YET                      _MK_ENUM_CONST(0)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H3_CRC_NOT_PRESENT                 _MK_ENUM_CONST(4)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H3_CRC_PRESENT_NO_ERRORS                   _MK_ENUM_CONST(5)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H3_CRC_PRESENT_CORRECTED_ERRORS                    _MK_ENUM_CONST(6)
#define FUSE_CRC_STATUS_0_CRC_STATUS_H3_CRC_PRESENT_UNCORRECTED_ERRORS                  _MK_ENUM_CONST(7)

// Register FUSE_CONTROL_WORD_STATUS_0
#define FUSE_CONTROL_WORD_STATUS_0                      _MK_ADDR_CONST(0x6c)
#define FUSE_CONTROL_WORD_STATUS_0_SECURE                       0x0
#define FUSE_CONTROL_WORD_STATUS_0_DUAL                         0x0
#define FUSE_CONTROL_WORD_STATUS_0_SCR                  0
#define FUSE_CONTROL_WORD_STATUS_0_WORD_COUNT                   0x1
#define FUSE_CONTROL_WORD_STATUS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_CONTROL_WORD_STATUS_0_RESET_MASK                   _MK_MASK_CONST(0x1f)
#define FUSE_CONTROL_WORD_STATUS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_CONTROL_WORD_STATUS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_CONTROL_WORD_STATUS_0_READ_MASK                    _MK_MASK_CONST(0x1f)
#define FUSE_CONTROL_WORD_STATUS_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_CONTROL_WORD_STATUS_0_OR_INTEGRITY_SHIFT                   _MK_SHIFT_CONST(0)
#define FUSE_CONTROL_WORD_STATUS_0_OR_INTEGRITY_FIELD                   _MK_FIELD_CONST(0x1, FUSE_CONTROL_WORD_STATUS_0_OR_INTEGRITY_SHIFT)
#define FUSE_CONTROL_WORD_STATUS_0_OR_INTEGRITY_RANGE                   0:0
#define FUSE_CONTROL_WORD_STATUS_0_OR_INTEGRITY_WOFFSET                 0x0
#define FUSE_CONTROL_WORD_STATUS_0_OR_INTEGRITY_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_CONTROL_WORD_STATUS_0_OR_INTEGRITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_CONTROL_WORD_STATUS_0_OR_INTEGRITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_CONTROL_WORD_STATUS_0_OR_INTEGRITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define FUSE_CONTROL_WORD_STATUS_0_OR_INTEGRITY_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define FUSE_CONTROL_WORD_STATUS_0_OR_INTEGRITY_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define FUSE_CONTROL_WORD_STATUS_0_FUSE_ENABLE_NOK_SHIFT                        _MK_SHIFT_CONST(1)
#define FUSE_CONTROL_WORD_STATUS_0_FUSE_ENABLE_NOK_FIELD                        _MK_FIELD_CONST(0x1, FUSE_CONTROL_WORD_STATUS_0_FUSE_ENABLE_NOK_SHIFT)
#define FUSE_CONTROL_WORD_STATUS_0_FUSE_ENABLE_NOK_RANGE                        1:1
#define FUSE_CONTROL_WORD_STATUS_0_FUSE_ENABLE_NOK_WOFFSET                      0x0
#define FUSE_CONTROL_WORD_STATUS_0_FUSE_ENABLE_NOK_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_CONTROL_WORD_STATUS_0_FUSE_ENABLE_NOK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define FUSE_CONTROL_WORD_STATUS_0_FUSE_ENABLE_NOK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_CONTROL_WORD_STATUS_0_FUSE_ENABLE_NOK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_CONTROL_WORD_STATUS_0_FUSE_ENABLE_NOK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_CONTROL_WORD_STATUS_0_FUSE_ENABLE_NOK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define FUSE_CONTROL_WORD_STATUS_0_PRODUCTION_MODE_NOK_SHIFT                    _MK_SHIFT_CONST(2)
#define FUSE_CONTROL_WORD_STATUS_0_PRODUCTION_MODE_NOK_FIELD                    _MK_FIELD_CONST(0x1, FUSE_CONTROL_WORD_STATUS_0_PRODUCTION_MODE_NOK_SHIFT)
#define FUSE_CONTROL_WORD_STATUS_0_PRODUCTION_MODE_NOK_RANGE                    2:2
#define FUSE_CONTROL_WORD_STATUS_0_PRODUCTION_MODE_NOK_WOFFSET                  0x0
#define FUSE_CONTROL_WORD_STATUS_0_PRODUCTION_MODE_NOK_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_CONTROL_WORD_STATUS_0_PRODUCTION_MODE_NOK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_CONTROL_WORD_STATUS_0_PRODUCTION_MODE_NOK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_CONTROL_WORD_STATUS_0_PRODUCTION_MODE_NOK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_CONTROL_WORD_STATUS_0_PRODUCTION_MODE_NOK_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_CONTROL_WORD_STATUS_0_PRODUCTION_MODE_NOK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define FUSE_CONTROL_WORD_STATUS_0_SECURITY_MODE_NOK_SHIFT                      _MK_SHIFT_CONST(3)
#define FUSE_CONTROL_WORD_STATUS_0_SECURITY_MODE_NOK_FIELD                      _MK_FIELD_CONST(0x1, FUSE_CONTROL_WORD_STATUS_0_SECURITY_MODE_NOK_SHIFT)
#define FUSE_CONTROL_WORD_STATUS_0_SECURITY_MODE_NOK_RANGE                      3:3
#define FUSE_CONTROL_WORD_STATUS_0_SECURITY_MODE_NOK_WOFFSET                    0x0
#define FUSE_CONTROL_WORD_STATUS_0_SECURITY_MODE_NOK_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_CONTROL_WORD_STATUS_0_SECURITY_MODE_NOK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_CONTROL_WORD_STATUS_0_SECURITY_MODE_NOK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_CONTROL_WORD_STATUS_0_SECURITY_MODE_NOK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_CONTROL_WORD_STATUS_0_SECURITY_MODE_NOK_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_CONTROL_WORD_STATUS_0_SECURITY_MODE_NOK_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define FUSE_CONTROL_WORD_STATUS_0_CONTROL_WORD_ZERO_SHIFT                      _MK_SHIFT_CONST(4)
#define FUSE_CONTROL_WORD_STATUS_0_CONTROL_WORD_ZERO_FIELD                      _MK_FIELD_CONST(0x1, FUSE_CONTROL_WORD_STATUS_0_CONTROL_WORD_ZERO_SHIFT)
#define FUSE_CONTROL_WORD_STATUS_0_CONTROL_WORD_ZERO_RANGE                      4:4
#define FUSE_CONTROL_WORD_STATUS_0_CONTROL_WORD_ZERO_WOFFSET                    0x0
#define FUSE_CONTROL_WORD_STATUS_0_CONTROL_WORD_ZERO_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_CONTROL_WORD_STATUS_0_CONTROL_WORD_ZERO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_CONTROL_WORD_STATUS_0_CONTROL_WORD_ZERO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_CONTROL_WORD_STATUS_0_CONTROL_WORD_ZERO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_CONTROL_WORD_STATUS_0_CONTROL_WORD_ZERO_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_CONTROL_WORD_STATUS_0_CONTROL_WORD_ZERO_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Reserved address 0x70

// Reserved address 0x74

// Reserved address 0x78

// Reserved address 0x7c

// Register FUSE_PRIVATE_KEY0_NONZERO_0
#define FUSE_PRIVATE_KEY0_NONZERO_0                     _MK_ADDR_CONST(0x80)
#define FUSE_PRIVATE_KEY0_NONZERO_0_SECURE                      0x0
#define FUSE_PRIVATE_KEY0_NONZERO_0_DUAL                        0x0
#define FUSE_PRIVATE_KEY0_NONZERO_0_SCR                         0
#define FUSE_PRIVATE_KEY0_NONZERO_0_WORD_COUNT                  0x1
#define FUSE_PRIVATE_KEY0_NONZERO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY0_NONZERO_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY0_NONZERO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY0_NONZERO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY0_NONZERO_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_PRIVATE_KEY0_NONZERO_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_SHIFT                     _MK_SHIFT_CONST(0)
#define FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_FIELD                     _MK_FIELD_CONST(0x1, FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_SHIFT)
#define FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_RANGE                     0:0
#define FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_WOFFSET                   0x0
#define FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register FUSE_PRIVATE_KEY1_NONZERO_0
#define FUSE_PRIVATE_KEY1_NONZERO_0                     _MK_ADDR_CONST(0x84)
#define FUSE_PRIVATE_KEY1_NONZERO_0_SECURE                      0x0
#define FUSE_PRIVATE_KEY1_NONZERO_0_DUAL                        0x0
#define FUSE_PRIVATE_KEY1_NONZERO_0_SCR                         0
#define FUSE_PRIVATE_KEY1_NONZERO_0_WORD_COUNT                  0x1
#define FUSE_PRIVATE_KEY1_NONZERO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY1_NONZERO_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY1_NONZERO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY1_NONZERO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY1_NONZERO_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_PRIVATE_KEY1_NONZERO_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_SHIFT                     _MK_SHIFT_CONST(0)
#define FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_FIELD                     _MK_FIELD_CONST(0x1, FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_SHIFT)
#define FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_RANGE                     0:0
#define FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_WOFFSET                   0x0
#define FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register FUSE_PRIVATE_KEY2_NONZERO_0
#define FUSE_PRIVATE_KEY2_NONZERO_0                     _MK_ADDR_CONST(0x88)
#define FUSE_PRIVATE_KEY2_NONZERO_0_SECURE                      0x0
#define FUSE_PRIVATE_KEY2_NONZERO_0_DUAL                        0x0
#define FUSE_PRIVATE_KEY2_NONZERO_0_SCR                         0
#define FUSE_PRIVATE_KEY2_NONZERO_0_WORD_COUNT                  0x1
#define FUSE_PRIVATE_KEY2_NONZERO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY2_NONZERO_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY2_NONZERO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY2_NONZERO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY2_NONZERO_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_PRIVATE_KEY2_NONZERO_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_SHIFT                     _MK_SHIFT_CONST(0)
#define FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_FIELD                     _MK_FIELD_CONST(0x1, FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_SHIFT)
#define FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_RANGE                     0:0
#define FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_WOFFSET                   0x0
#define FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register FUSE_PRIVATE_KEY3_NONZERO_0
#define FUSE_PRIVATE_KEY3_NONZERO_0                     _MK_ADDR_CONST(0x8c)
#define FUSE_PRIVATE_KEY3_NONZERO_0_SECURE                      0x0
#define FUSE_PRIVATE_KEY3_NONZERO_0_DUAL                        0x0
#define FUSE_PRIVATE_KEY3_NONZERO_0_SCR                         0
#define FUSE_PRIVATE_KEY3_NONZERO_0_WORD_COUNT                  0x1
#define FUSE_PRIVATE_KEY3_NONZERO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY3_NONZERO_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY3_NONZERO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY3_NONZERO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY3_NONZERO_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_PRIVATE_KEY3_NONZERO_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_SHIFT                     _MK_SHIFT_CONST(0)
#define FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_FIELD                     _MK_FIELD_CONST(0x1, FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_SHIFT)
#define FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_RANGE                     0:0
#define FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_WOFFSET                   0x0
#define FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

// Register FUSE_H2_NONZERO_0
#define FUSE_H2_NONZERO_0                       _MK_ADDR_CONST(0x90)
#define FUSE_H2_NONZERO_0_SECURE                        0x0
#define FUSE_H2_NONZERO_0_DUAL                  0x0
#define FUSE_H2_NONZERO_0_SCR                   0
#define FUSE_H2_NONZERO_0_WORD_COUNT                    0x1
#define FUSE_H2_NONZERO_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_H2_NONZERO_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_H2_NONZERO_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_H2_NONZERO_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_H2_NONZERO_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_H2_NONZERO_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_H2_NONZERO_0_H2_NONZERO_DATA_SHIFT                 _MK_SHIFT_CONST(0)
#define FUSE_H2_NONZERO_0_H2_NONZERO_DATA_FIELD                 _MK_FIELD_CONST(0x1, FUSE_H2_NONZERO_0_H2_NONZERO_DATA_SHIFT)
#define FUSE_H2_NONZERO_0_H2_NONZERO_DATA_RANGE                 0:0
#define FUSE_H2_NONZERO_0_H2_NONZERO_DATA_WOFFSET                       0x0
#define FUSE_H2_NONZERO_0_H2_NONZERO_DATA_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_H2_NONZERO_0_H2_NONZERO_DATA_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_H2_NONZERO_0_H2_NONZERO_DATA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_H2_NONZERO_0_H2_NONZERO_DATA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_H2_NONZERO_0_H2_NONZERO_DATA_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define FUSE_H2_NONZERO_0_H2_NONZERO_DATA_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

// Reserved address 0x94

// Reserved address 0x98

// Reserved address 0x9c

// Register FUSE_RESHIFT_TRIGGER_CHAIN_3_0
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0                  _MK_ADDR_CONST(0xa0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_SECURE                   0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_DUAL                     0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_SCR                      0
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_WORD_COUNT                       0x1
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESET_MASK                       _MK_MASK_CONST(0x7f)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_READ_MASK                        _MK_MASK_CONST(0x7f)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_WRITE_MASK                       _MK_MASK_CONST(0x7f)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU0_CLUSTER0_VAL_SHIFT                       _MK_SHIFT_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU0_CLUSTER0_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU0_CLUSTER0_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU0_CLUSTER0_VAL_RANGE                       0:0
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU0_CLUSTER0_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU0_CLUSTER0_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU0_CLUSTER0_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU0_CLUSTER0_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU0_CLUSTER0_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU0_CLUSTER0_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU0_CLUSTER0_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU0_CLUSTER0_VAL_INIT_ENUM                   DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU0_CLUSTER0_VAL_DISABLED                    _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU0_CLUSTER0_VAL_ENABLED                     _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU1_CLUSTER0_VAL_SHIFT                       _MK_SHIFT_CONST(1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU1_CLUSTER0_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU1_CLUSTER0_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU1_CLUSTER0_VAL_RANGE                       1:1
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU1_CLUSTER0_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU1_CLUSTER0_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU1_CLUSTER0_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU1_CLUSTER0_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU1_CLUSTER0_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU1_CLUSTER0_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU1_CLUSTER0_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU1_CLUSTER0_VAL_INIT_ENUM                   DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU1_CLUSTER0_VAL_DISABLED                    _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_IFU1_CLUSTER0_VAL_ENABLED                     _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_0_VAL_SHIFT                  _MK_SHIFT_CONST(2)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_0_VAL_FIELD                  _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_0_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_0_VAL_RANGE                  2:2
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_0_VAL_WOFFSET                        0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_0_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_0_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_0_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_0_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_0_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_0_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_0_VAL_INIT_ENUM                      DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_0_VAL_DISABLED                       _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_0_VAL_ENABLED                        _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_1_VAL_SHIFT                  _MK_SHIFT_CONST(3)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_1_VAL_FIELD                  _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_1_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_1_VAL_RANGE                  3:3
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_1_VAL_WOFFSET                        0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_1_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_1_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_1_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_1_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_1_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_1_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_1_VAL_INIT_ENUM                      DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_1_VAL_DISABLED                       _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_DATA_CLUSTER0_1_VAL_ENABLED                        _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_TAG_CLUSTER0_VAL_SHIFT                     _MK_SHIFT_CONST(4)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_TAG_CLUSTER0_VAL_FIELD                     _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_TAG_CLUSTER0_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_TAG_CLUSTER0_VAL_RANGE                     4:4
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_TAG_CLUSTER0_VAL_WOFFSET                   0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_TAG_CLUSTER0_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_TAG_CLUSTER0_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_TAG_CLUSTER0_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_TAG_CLUSTER0_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_TAG_CLUSTER0_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_TAG_CLUSTER0_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_TAG_CLUSTER0_VAL_INIT_ENUM                 DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_TAG_CLUSTER0_VAL_DISABLED                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_L2_TAG_CLUSTER0_VAL_ENABLED                   _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU0_CLUSTER0_VAL_SHIFT                       _MK_SHIFT_CONST(5)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU0_CLUSTER0_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU0_CLUSTER0_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU0_CLUSTER0_VAL_RANGE                       5:5
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU0_CLUSTER0_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU0_CLUSTER0_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU0_CLUSTER0_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU0_CLUSTER0_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU0_CLUSTER0_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU0_CLUSTER0_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU0_CLUSTER0_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU0_CLUSTER0_VAL_INIT_ENUM                   DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU0_CLUSTER0_VAL_DISABLED                    _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU0_CLUSTER0_VAL_ENABLED                     _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU1_CLUSTER0_VAL_SHIFT                       _MK_SHIFT_CONST(6)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU1_CLUSTER0_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU1_CLUSTER0_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU1_CLUSTER0_VAL_RANGE                       6:6
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU1_CLUSTER0_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU1_CLUSTER0_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU1_CLUSTER0_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU1_CLUSTER0_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU1_CLUSTER0_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU1_CLUSTER0_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU1_CLUSTER0_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU1_CLUSTER0_VAL_INIT_ENUM                   DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU1_CLUSTER0_VAL_DISABLED                    _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_3_0_RESHIFT_TRIGGER_CHAIN_3_SEG_CCPLEX_LSU1_CLUSTER0_VAL_ENABLED                     _MK_ENUM_CONST(1)

// Register FUSE_RESHIFT_STATUS_CHAIN_3_0
#define FUSE_RESHIFT_STATUS_CHAIN_3_0                   _MK_ADDR_CONST(0xa4)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_SECURE                    0x0
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_DUAL                      0x0
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_SCR                       0
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_WORD_COUNT                        0x1
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_READ_MASK                         _MK_MASK_CONST(0x7f)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_WRITE_MASK                        _MK_MASK_CONST(0x7f)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU0_CLUSTER0_VAL_SHIFT                 _MK_SHIFT_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU0_CLUSTER0_VAL_FIELD                 _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU0_CLUSTER0_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU0_CLUSTER0_VAL_RANGE                 0:0
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU0_CLUSTER0_VAL_WOFFSET                       0x0
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU0_CLUSTER0_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU0_CLUSTER0_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU0_CLUSTER0_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU0_CLUSTER0_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU0_CLUSTER0_VAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU0_CLUSTER0_VAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU0_CLUSTER0_VAL_INIT_ENUM                     CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU0_CLUSTER0_VAL_CHAIN_SHIFT_NOT_DONE                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU0_CLUSTER0_VAL_CHAIN_SHIFT_DONE                      _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU1_CLUSTER0_VAL_SHIFT                 _MK_SHIFT_CONST(1)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU1_CLUSTER0_VAL_FIELD                 _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU1_CLUSTER0_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU1_CLUSTER0_VAL_RANGE                 1:1
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU1_CLUSTER0_VAL_WOFFSET                       0x0
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU1_CLUSTER0_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU1_CLUSTER0_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU1_CLUSTER0_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU1_CLUSTER0_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU1_CLUSTER0_VAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU1_CLUSTER0_VAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU1_CLUSTER0_VAL_INIT_ENUM                     CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU1_CLUSTER0_VAL_CHAIN_SHIFT_NOT_DONE                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_IFU1_CLUSTER0_VAL_CHAIN_SHIFT_DONE                      _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_0_VAL_SHIFT                    _MK_SHIFT_CONST(2)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_0_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_0_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_0_VAL_RANGE                    2:2
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_0_VAL_WOFFSET                  0x0
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_0_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_0_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_0_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_0_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_0_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_0_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_0_VAL_INIT_ENUM                        CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_0_VAL_CHAIN_SHIFT_NOT_DONE                     _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_0_VAL_CHAIN_SHIFT_DONE                 _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_1_VAL_SHIFT                    _MK_SHIFT_CONST(3)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_1_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_1_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_1_VAL_RANGE                    3:3
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_1_VAL_WOFFSET                  0x0
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_1_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_1_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_1_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_1_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_1_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_1_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_1_VAL_INIT_ENUM                        CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_1_VAL_CHAIN_SHIFT_NOT_DONE                     _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_DATA_CLUSTER0_1_VAL_CHAIN_SHIFT_DONE                 _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_TAG_CLUSTER0_VAL_SHIFT                       _MK_SHIFT_CONST(4)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_TAG_CLUSTER0_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_TAG_CLUSTER0_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_TAG_CLUSTER0_VAL_RANGE                       4:4
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_TAG_CLUSTER0_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_TAG_CLUSTER0_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_TAG_CLUSTER0_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_TAG_CLUSTER0_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_TAG_CLUSTER0_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_TAG_CLUSTER0_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_TAG_CLUSTER0_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_TAG_CLUSTER0_VAL_INIT_ENUM                   CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_TAG_CLUSTER0_VAL_CHAIN_SHIFT_NOT_DONE                        _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_L2_TAG_CLUSTER0_VAL_CHAIN_SHIFT_DONE                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU0_CLUSTER0_VAL_SHIFT                 _MK_SHIFT_CONST(5)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU0_CLUSTER0_VAL_FIELD                 _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU0_CLUSTER0_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU0_CLUSTER0_VAL_RANGE                 5:5
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU0_CLUSTER0_VAL_WOFFSET                       0x0
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU0_CLUSTER0_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU0_CLUSTER0_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU0_CLUSTER0_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU0_CLUSTER0_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU0_CLUSTER0_VAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU0_CLUSTER0_VAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU0_CLUSTER0_VAL_INIT_ENUM                     CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU0_CLUSTER0_VAL_CHAIN_SHIFT_NOT_DONE                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU0_CLUSTER0_VAL_CHAIN_SHIFT_DONE                      _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU1_CLUSTER0_VAL_SHIFT                 _MK_SHIFT_CONST(6)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU1_CLUSTER0_VAL_FIELD                 _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU1_CLUSTER0_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU1_CLUSTER0_VAL_RANGE                 6:6
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU1_CLUSTER0_VAL_WOFFSET                       0x0
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU1_CLUSTER0_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU1_CLUSTER0_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU1_CLUSTER0_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU1_CLUSTER0_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU1_CLUSTER0_VAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU1_CLUSTER0_VAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU1_CLUSTER0_VAL_INIT_ENUM                     CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU1_CLUSTER0_VAL_CHAIN_SHIFT_NOT_DONE                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_3_0_RESHIFT_STATUS_CHAIN_3_SEC_CCPLEX_LSU1_CLUSTER0_VAL_CHAIN_SHIFT_DONE                      _MK_ENUM_CONST(1)

// Register FUSE_RESHIFT_TRIGGER_CHAIN_4_0
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0                  _MK_ADDR_CONST(0xa8)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_SECURE                   0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_DUAL                     0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_SCR                      0
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_WORD_COUNT                       0x1
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESET_MASK                       _MK_MASK_CONST(0x7f)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_READ_MASK                        _MK_MASK_CONST(0x7f)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_WRITE_MASK                       _MK_MASK_CONST(0x7f)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU0_CLUSTER1_VAL_SHIFT                       _MK_SHIFT_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU0_CLUSTER1_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU0_CLUSTER1_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU0_CLUSTER1_VAL_RANGE                       0:0
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU0_CLUSTER1_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU0_CLUSTER1_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU0_CLUSTER1_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU0_CLUSTER1_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU0_CLUSTER1_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU0_CLUSTER1_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU0_CLUSTER1_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU0_CLUSTER1_VAL_INIT_ENUM                   DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU0_CLUSTER1_VAL_DISABLED                    _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU0_CLUSTER1_VAL_ENABLED                     _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU1_CLUSTER1_VAL_SHIFT                       _MK_SHIFT_CONST(1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU1_CLUSTER1_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU1_CLUSTER1_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU1_CLUSTER1_VAL_RANGE                       1:1
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU1_CLUSTER1_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU1_CLUSTER1_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU1_CLUSTER1_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU1_CLUSTER1_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU1_CLUSTER1_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU1_CLUSTER1_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU1_CLUSTER1_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU1_CLUSTER1_VAL_INIT_ENUM                   DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU1_CLUSTER1_VAL_DISABLED                    _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_IFU1_CLUSTER1_VAL_ENABLED                     _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_0_VAL_SHIFT                  _MK_SHIFT_CONST(2)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_0_VAL_FIELD                  _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_0_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_0_VAL_RANGE                  2:2
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_0_VAL_WOFFSET                        0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_0_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_0_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_0_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_0_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_0_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_0_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_0_VAL_INIT_ENUM                      DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_0_VAL_DISABLED                       _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_0_VAL_ENABLED                        _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_1_VAL_SHIFT                  _MK_SHIFT_CONST(3)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_1_VAL_FIELD                  _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_1_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_1_VAL_RANGE                  3:3
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_1_VAL_WOFFSET                        0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_1_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_1_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_1_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_1_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_1_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_1_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_1_VAL_INIT_ENUM                      DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_1_VAL_DISABLED                       _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_DATA_CLUSTER1_1_VAL_ENABLED                        _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_TAG_CLUSTER1_VAL_SHIFT                     _MK_SHIFT_CONST(4)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_TAG_CLUSTER1_VAL_FIELD                     _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_TAG_CLUSTER1_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_TAG_CLUSTER1_VAL_RANGE                     4:4
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_TAG_CLUSTER1_VAL_WOFFSET                   0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_TAG_CLUSTER1_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_TAG_CLUSTER1_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_TAG_CLUSTER1_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_TAG_CLUSTER1_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_TAG_CLUSTER1_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_TAG_CLUSTER1_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_TAG_CLUSTER1_VAL_INIT_ENUM                 DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_TAG_CLUSTER1_VAL_DISABLED                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_L2_TAG_CLUSTER1_VAL_ENABLED                   _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU0_CLUSTER1_VAL_SHIFT                       _MK_SHIFT_CONST(5)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU0_CLUSTER1_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU0_CLUSTER1_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU0_CLUSTER1_VAL_RANGE                       5:5
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU0_CLUSTER1_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU0_CLUSTER1_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU0_CLUSTER1_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU0_CLUSTER1_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU0_CLUSTER1_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU0_CLUSTER1_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU0_CLUSTER1_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU0_CLUSTER1_VAL_INIT_ENUM                   DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU0_CLUSTER1_VAL_DISABLED                    _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU0_CLUSTER1_VAL_ENABLED                     _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU1_CLUSTER1_VAL_SHIFT                       _MK_SHIFT_CONST(6)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU1_CLUSTER1_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU1_CLUSTER1_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU1_CLUSTER1_VAL_RANGE                       6:6
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU1_CLUSTER1_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU1_CLUSTER1_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU1_CLUSTER1_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU1_CLUSTER1_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU1_CLUSTER1_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU1_CLUSTER1_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU1_CLUSTER1_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU1_CLUSTER1_VAL_INIT_ENUM                   DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU1_CLUSTER1_VAL_DISABLED                    _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_4_0_RESHIFT_TRIGGER_CHAIN_4_SEG_CCPLEX_LSU1_CLUSTER1_VAL_ENABLED                     _MK_ENUM_CONST(1)

// Register FUSE_RESHIFT_STATUS_CHAIN_4_0
#define FUSE_RESHIFT_STATUS_CHAIN_4_0                   _MK_ADDR_CONST(0xac)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_SECURE                    0x0
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_DUAL                      0x0
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_SCR                       0
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_WORD_COUNT                        0x1
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_READ_MASK                         _MK_MASK_CONST(0x7f)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_WRITE_MASK                        _MK_MASK_CONST(0x7f)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU0_CLUSTER1_VAL_SHIFT                 _MK_SHIFT_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU0_CLUSTER1_VAL_FIELD                 _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU0_CLUSTER1_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU0_CLUSTER1_VAL_RANGE                 0:0
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU0_CLUSTER1_VAL_WOFFSET                       0x0
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU0_CLUSTER1_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU0_CLUSTER1_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU0_CLUSTER1_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU0_CLUSTER1_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU0_CLUSTER1_VAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU0_CLUSTER1_VAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU0_CLUSTER1_VAL_INIT_ENUM                     CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU0_CLUSTER1_VAL_CHAIN_SHIFT_NOT_DONE                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU0_CLUSTER1_VAL_CHAIN_SHIFT_DONE                      _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU1_CLUSTER1_VAL_SHIFT                 _MK_SHIFT_CONST(1)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU1_CLUSTER1_VAL_FIELD                 _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU1_CLUSTER1_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU1_CLUSTER1_VAL_RANGE                 1:1
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU1_CLUSTER1_VAL_WOFFSET                       0x0
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU1_CLUSTER1_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU1_CLUSTER1_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU1_CLUSTER1_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU1_CLUSTER1_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU1_CLUSTER1_VAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU1_CLUSTER1_VAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU1_CLUSTER1_VAL_INIT_ENUM                     CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU1_CLUSTER1_VAL_CHAIN_SHIFT_NOT_DONE                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_IFU1_CLUSTER1_VAL_CHAIN_SHIFT_DONE                      _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_0_VAL_SHIFT                    _MK_SHIFT_CONST(2)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_0_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_0_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_0_VAL_RANGE                    2:2
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_0_VAL_WOFFSET                  0x0
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_0_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_0_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_0_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_0_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_0_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_0_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_0_VAL_INIT_ENUM                        CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_0_VAL_CHAIN_SHIFT_NOT_DONE                     _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_0_VAL_CHAIN_SHIFT_DONE                 _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_1_VAL_SHIFT                    _MK_SHIFT_CONST(3)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_1_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_1_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_1_VAL_RANGE                    3:3
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_1_VAL_WOFFSET                  0x0
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_1_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_1_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_1_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_1_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_1_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_1_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_1_VAL_INIT_ENUM                        CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_1_VAL_CHAIN_SHIFT_NOT_DONE                     _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_DATA_CLUSTER1_1_VAL_CHAIN_SHIFT_DONE                 _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_TAG_CLUSTER1_VAL_SHIFT                       _MK_SHIFT_CONST(4)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_TAG_CLUSTER1_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_TAG_CLUSTER1_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_TAG_CLUSTER1_VAL_RANGE                       4:4
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_TAG_CLUSTER1_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_TAG_CLUSTER1_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_TAG_CLUSTER1_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_TAG_CLUSTER1_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_TAG_CLUSTER1_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_TAG_CLUSTER1_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_TAG_CLUSTER1_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_TAG_CLUSTER1_VAL_INIT_ENUM                   CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_TAG_CLUSTER1_VAL_CHAIN_SHIFT_NOT_DONE                        _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_L2_TAG_CLUSTER1_VAL_CHAIN_SHIFT_DONE                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU0_CLUSTER1_VAL_SHIFT                 _MK_SHIFT_CONST(5)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU0_CLUSTER1_VAL_FIELD                 _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU0_CLUSTER1_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU0_CLUSTER1_VAL_RANGE                 5:5
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU0_CLUSTER1_VAL_WOFFSET                       0x0
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU0_CLUSTER1_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU0_CLUSTER1_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU0_CLUSTER1_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU0_CLUSTER1_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU0_CLUSTER1_VAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU0_CLUSTER1_VAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU0_CLUSTER1_VAL_INIT_ENUM                     CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU0_CLUSTER1_VAL_CHAIN_SHIFT_NOT_DONE                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU0_CLUSTER1_VAL_CHAIN_SHIFT_DONE                      _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU1_CLUSTER1_VAL_SHIFT                 _MK_SHIFT_CONST(6)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU1_CLUSTER1_VAL_FIELD                 _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU1_CLUSTER1_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU1_CLUSTER1_VAL_RANGE                 6:6
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU1_CLUSTER1_VAL_WOFFSET                       0x0
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU1_CLUSTER1_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU1_CLUSTER1_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU1_CLUSTER1_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU1_CLUSTER1_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU1_CLUSTER1_VAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU1_CLUSTER1_VAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU1_CLUSTER1_VAL_INIT_ENUM                     CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU1_CLUSTER1_VAL_CHAIN_SHIFT_NOT_DONE                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_4_0_RESHIFT_STATUS_CHAIN_4_SEC_CCPLEX_LSU1_CLUSTER1_VAL_CHAIN_SHIFT_DONE                      _MK_ENUM_CONST(1)

// Register FUSE_RESHIFT_TRIGGER_CHAIN_5_0
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0                  _MK_ADDR_CONST(0xb0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_SECURE                   0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_DUAL                     0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_SCR                      0
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_WORD_COUNT                       0x1
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESET_MASK                       _MK_MASK_CONST(0x7f)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_READ_MASK                        _MK_MASK_CONST(0x7f)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_WRITE_MASK                       _MK_MASK_CONST(0x7f)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU0_CLUSTER2_VAL_SHIFT                       _MK_SHIFT_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU0_CLUSTER2_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU0_CLUSTER2_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU0_CLUSTER2_VAL_RANGE                       0:0
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU0_CLUSTER2_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU0_CLUSTER2_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU0_CLUSTER2_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU0_CLUSTER2_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU0_CLUSTER2_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU0_CLUSTER2_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU0_CLUSTER2_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU0_CLUSTER2_VAL_INIT_ENUM                   DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU0_CLUSTER2_VAL_DISABLED                    _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU0_CLUSTER2_VAL_ENABLED                     _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU1_CLUSTER2_VAL_SHIFT                       _MK_SHIFT_CONST(1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU1_CLUSTER2_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU1_CLUSTER2_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU1_CLUSTER2_VAL_RANGE                       1:1
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU1_CLUSTER2_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU1_CLUSTER2_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU1_CLUSTER2_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU1_CLUSTER2_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU1_CLUSTER2_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU1_CLUSTER2_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU1_CLUSTER2_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU1_CLUSTER2_VAL_INIT_ENUM                   DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU1_CLUSTER2_VAL_DISABLED                    _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_IFU1_CLUSTER2_VAL_ENABLED                     _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_0_VAL_SHIFT                  _MK_SHIFT_CONST(2)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_0_VAL_FIELD                  _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_0_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_0_VAL_RANGE                  2:2
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_0_VAL_WOFFSET                        0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_0_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_0_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_0_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_0_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_0_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_0_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_0_VAL_INIT_ENUM                      DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_0_VAL_DISABLED                       _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_0_VAL_ENABLED                        _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_1_VAL_SHIFT                  _MK_SHIFT_CONST(3)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_1_VAL_FIELD                  _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_1_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_1_VAL_RANGE                  3:3
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_1_VAL_WOFFSET                        0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_1_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_1_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_1_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_1_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_1_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_1_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_1_VAL_INIT_ENUM                      DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_1_VAL_DISABLED                       _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_DATA_CLUSTER2_1_VAL_ENABLED                        _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_TAG_CLUSTER2_VAL_SHIFT                     _MK_SHIFT_CONST(4)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_TAG_CLUSTER2_VAL_FIELD                     _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_TAG_CLUSTER2_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_TAG_CLUSTER2_VAL_RANGE                     4:4
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_TAG_CLUSTER2_VAL_WOFFSET                   0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_TAG_CLUSTER2_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_TAG_CLUSTER2_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_TAG_CLUSTER2_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_TAG_CLUSTER2_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_TAG_CLUSTER2_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_TAG_CLUSTER2_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_TAG_CLUSTER2_VAL_INIT_ENUM                 DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_TAG_CLUSTER2_VAL_DISABLED                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_L2_TAG_CLUSTER2_VAL_ENABLED                   _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU0_CLUSTER2_VAL_SHIFT                       _MK_SHIFT_CONST(5)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU0_CLUSTER2_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU0_CLUSTER2_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU0_CLUSTER2_VAL_RANGE                       5:5
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU0_CLUSTER2_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU0_CLUSTER2_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU0_CLUSTER2_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU0_CLUSTER2_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU0_CLUSTER2_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU0_CLUSTER2_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU0_CLUSTER2_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU0_CLUSTER2_VAL_INIT_ENUM                   DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU0_CLUSTER2_VAL_DISABLED                    _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU0_CLUSTER2_VAL_ENABLED                     _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU1_CLUSTER2_VAL_SHIFT                       _MK_SHIFT_CONST(6)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU1_CLUSTER2_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU1_CLUSTER2_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU1_CLUSTER2_VAL_RANGE                       6:6
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU1_CLUSTER2_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU1_CLUSTER2_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU1_CLUSTER2_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU1_CLUSTER2_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU1_CLUSTER2_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU1_CLUSTER2_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU1_CLUSTER2_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU1_CLUSTER2_VAL_INIT_ENUM                   DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU1_CLUSTER2_VAL_DISABLED                    _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_5_0_RESHIFT_TRIGGER_CHAIN_5_SEG_CCPLEX_LSU1_CLUSTER2_VAL_ENABLED                     _MK_ENUM_CONST(1)

// Register FUSE_RESHIFT_STATUS_CHAIN_5_0
#define FUSE_RESHIFT_STATUS_CHAIN_5_0                   _MK_ADDR_CONST(0xb4)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_SECURE                    0x0
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_DUAL                      0x0
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_SCR                       0
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_WORD_COUNT                        0x1
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_READ_MASK                         _MK_MASK_CONST(0x7f)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_WRITE_MASK                        _MK_MASK_CONST(0x7f)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU0_CLUSTER2_VAL_SHIFT                 _MK_SHIFT_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU0_CLUSTER2_VAL_FIELD                 _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU0_CLUSTER2_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU0_CLUSTER2_VAL_RANGE                 0:0
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU0_CLUSTER2_VAL_WOFFSET                       0x0
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU0_CLUSTER2_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU0_CLUSTER2_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU0_CLUSTER2_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU0_CLUSTER2_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU0_CLUSTER2_VAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU0_CLUSTER2_VAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU0_CLUSTER2_VAL_INIT_ENUM                     CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU0_CLUSTER2_VAL_CHAIN_SHIFT_NOT_DONE                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU0_CLUSTER2_VAL_CHAIN_SHIFT_DONE                      _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU1_CLUSTER2_VAL_SHIFT                 _MK_SHIFT_CONST(1)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU1_CLUSTER2_VAL_FIELD                 _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU1_CLUSTER2_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU1_CLUSTER2_VAL_RANGE                 1:1
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU1_CLUSTER2_VAL_WOFFSET                       0x0
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU1_CLUSTER2_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU1_CLUSTER2_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU1_CLUSTER2_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU1_CLUSTER2_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU1_CLUSTER2_VAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU1_CLUSTER2_VAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU1_CLUSTER2_VAL_INIT_ENUM                     CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU1_CLUSTER2_VAL_CHAIN_SHIFT_NOT_DONE                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_IFU1_CLUSTER2_VAL_CHAIN_SHIFT_DONE                      _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_0_VAL_SHIFT                    _MK_SHIFT_CONST(2)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_0_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_0_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_0_VAL_RANGE                    2:2
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_0_VAL_WOFFSET                  0x0
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_0_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_0_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_0_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_0_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_0_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_0_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_0_VAL_INIT_ENUM                        CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_0_VAL_CHAIN_SHIFT_NOT_DONE                     _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_0_VAL_CHAIN_SHIFT_DONE                 _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_1_VAL_SHIFT                    _MK_SHIFT_CONST(3)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_1_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_1_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_1_VAL_RANGE                    3:3
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_1_VAL_WOFFSET                  0x0
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_1_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_1_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_1_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_1_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_1_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_1_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_1_VAL_INIT_ENUM                        CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_1_VAL_CHAIN_SHIFT_NOT_DONE                     _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_DATA_CLUSTER2_1_VAL_CHAIN_SHIFT_DONE                 _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_TAG_CLUSTER2_VAL_SHIFT                       _MK_SHIFT_CONST(4)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_TAG_CLUSTER2_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_TAG_CLUSTER2_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_TAG_CLUSTER2_VAL_RANGE                       4:4
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_TAG_CLUSTER2_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_TAG_CLUSTER2_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_TAG_CLUSTER2_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_TAG_CLUSTER2_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_TAG_CLUSTER2_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_TAG_CLUSTER2_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_TAG_CLUSTER2_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_TAG_CLUSTER2_VAL_INIT_ENUM                   CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_TAG_CLUSTER2_VAL_CHAIN_SHIFT_NOT_DONE                        _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_L2_TAG_CLUSTER2_VAL_CHAIN_SHIFT_DONE                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU0_CLUSTER2_VAL_SHIFT                 _MK_SHIFT_CONST(5)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU0_CLUSTER2_VAL_FIELD                 _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU0_CLUSTER2_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU0_CLUSTER2_VAL_RANGE                 5:5
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU0_CLUSTER2_VAL_WOFFSET                       0x0
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU0_CLUSTER2_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU0_CLUSTER2_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU0_CLUSTER2_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU0_CLUSTER2_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU0_CLUSTER2_VAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU0_CLUSTER2_VAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU0_CLUSTER2_VAL_INIT_ENUM                     CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU0_CLUSTER2_VAL_CHAIN_SHIFT_NOT_DONE                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU0_CLUSTER2_VAL_CHAIN_SHIFT_DONE                      _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU1_CLUSTER2_VAL_SHIFT                 _MK_SHIFT_CONST(6)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU1_CLUSTER2_VAL_FIELD                 _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU1_CLUSTER2_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU1_CLUSTER2_VAL_RANGE                 6:6
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU1_CLUSTER2_VAL_WOFFSET                       0x0
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU1_CLUSTER2_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU1_CLUSTER2_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU1_CLUSTER2_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU1_CLUSTER2_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU1_CLUSTER2_VAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU1_CLUSTER2_VAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU1_CLUSTER2_VAL_INIT_ENUM                     CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU1_CLUSTER2_VAL_CHAIN_SHIFT_NOT_DONE                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_5_0_RESHIFT_STATUS_CHAIN_5_SEC_CCPLEX_LSU1_CLUSTER2_VAL_CHAIN_SHIFT_DONE                      _MK_ENUM_CONST(1)

// Register FUSE_RESHIFT_TRIGGER_CHAIN_6_0
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0                  _MK_ADDR_CONST(0xb8)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_SECURE                   0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_DUAL                     0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_SCR                      0
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_WORD_COUNT                       0x1
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESET_MASK                       _MK_MASK_CONST(0x7f)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_READ_MASK                        _MK_MASK_CONST(0x7f)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_WRITE_MASK                       _MK_MASK_CONST(0x7f)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU0_CLUSTER3_VAL_SHIFT                       _MK_SHIFT_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU0_CLUSTER3_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU0_CLUSTER3_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU0_CLUSTER3_VAL_RANGE                       0:0
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU0_CLUSTER3_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU0_CLUSTER3_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU0_CLUSTER3_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU0_CLUSTER3_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU0_CLUSTER3_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU0_CLUSTER3_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU0_CLUSTER3_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU0_CLUSTER3_VAL_INIT_ENUM                   DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU0_CLUSTER3_VAL_DISABLED                    _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU0_CLUSTER3_VAL_ENABLED                     _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU1_CLUSTER3_VAL_SHIFT                       _MK_SHIFT_CONST(1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU1_CLUSTER3_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU1_CLUSTER3_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU1_CLUSTER3_VAL_RANGE                       1:1
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU1_CLUSTER3_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU1_CLUSTER3_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU1_CLUSTER3_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU1_CLUSTER3_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU1_CLUSTER3_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU1_CLUSTER3_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU1_CLUSTER3_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU1_CLUSTER3_VAL_INIT_ENUM                   DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU1_CLUSTER3_VAL_DISABLED                    _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_IFU1_CLUSTER3_VAL_ENABLED                     _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_0_VAL_SHIFT                  _MK_SHIFT_CONST(2)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_0_VAL_FIELD                  _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_0_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_0_VAL_RANGE                  2:2
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_0_VAL_WOFFSET                        0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_0_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_0_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_0_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_0_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_0_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_0_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_0_VAL_INIT_ENUM                      DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_0_VAL_DISABLED                       _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_0_VAL_ENABLED                        _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_1_VAL_SHIFT                  _MK_SHIFT_CONST(3)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_1_VAL_FIELD                  _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_1_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_1_VAL_RANGE                  3:3
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_1_VAL_WOFFSET                        0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_1_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_1_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_1_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_1_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_1_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_1_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_1_VAL_INIT_ENUM                      DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_1_VAL_DISABLED                       _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_DATA_CLUSTER3_1_VAL_ENABLED                        _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_TAG_CLUSTER3_VAL_SHIFT                     _MK_SHIFT_CONST(4)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_TAG_CLUSTER3_VAL_FIELD                     _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_TAG_CLUSTER3_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_TAG_CLUSTER3_VAL_RANGE                     4:4
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_TAG_CLUSTER3_VAL_WOFFSET                   0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_TAG_CLUSTER3_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_TAG_CLUSTER3_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_TAG_CLUSTER3_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_TAG_CLUSTER3_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_TAG_CLUSTER3_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_TAG_CLUSTER3_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_TAG_CLUSTER3_VAL_INIT_ENUM                 DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_TAG_CLUSTER3_VAL_DISABLED                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_L2_TAG_CLUSTER3_VAL_ENABLED                   _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU0_CLUSTER3_VAL_SHIFT                       _MK_SHIFT_CONST(5)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU0_CLUSTER3_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU0_CLUSTER3_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU0_CLUSTER3_VAL_RANGE                       5:5
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU0_CLUSTER3_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU0_CLUSTER3_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU0_CLUSTER3_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU0_CLUSTER3_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU0_CLUSTER3_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU0_CLUSTER3_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU0_CLUSTER3_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU0_CLUSTER3_VAL_INIT_ENUM                   DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU0_CLUSTER3_VAL_DISABLED                    _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU0_CLUSTER3_VAL_ENABLED                     _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU1_CLUSTER3_VAL_SHIFT                       _MK_SHIFT_CONST(6)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU1_CLUSTER3_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU1_CLUSTER3_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU1_CLUSTER3_VAL_RANGE                       6:6
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU1_CLUSTER3_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU1_CLUSTER3_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU1_CLUSTER3_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU1_CLUSTER3_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU1_CLUSTER3_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU1_CLUSTER3_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU1_CLUSTER3_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU1_CLUSTER3_VAL_INIT_ENUM                   DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU1_CLUSTER3_VAL_DISABLED                    _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_6_0_RESHIFT_TRIGGER_CHAIN_6_SEG_CCPLEX_LSU1_CLUSTER3_VAL_ENABLED                     _MK_ENUM_CONST(1)

// Register FUSE_RESHIFT_STATUS_CHAIN_6_0
#define FUSE_RESHIFT_STATUS_CHAIN_6_0                   _MK_ADDR_CONST(0xbc)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_SECURE                    0x0
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_DUAL                      0x0
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_SCR                       0
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_WORD_COUNT                        0x1
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_READ_MASK                         _MK_MASK_CONST(0x7f)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_WRITE_MASK                        _MK_MASK_CONST(0x7f)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU0_CLUSTER3_VAL_SHIFT                 _MK_SHIFT_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU0_CLUSTER3_VAL_FIELD                 _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU0_CLUSTER3_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU0_CLUSTER3_VAL_RANGE                 0:0
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU0_CLUSTER3_VAL_WOFFSET                       0x0
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU0_CLUSTER3_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU0_CLUSTER3_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU0_CLUSTER3_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU0_CLUSTER3_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU0_CLUSTER3_VAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU0_CLUSTER3_VAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU0_CLUSTER3_VAL_INIT_ENUM                     CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU0_CLUSTER3_VAL_CHAIN_SHIFT_NOT_DONE                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU0_CLUSTER3_VAL_CHAIN_SHIFT_DONE                      _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU1_CLUSTER3_VAL_SHIFT                 _MK_SHIFT_CONST(1)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU1_CLUSTER3_VAL_FIELD                 _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU1_CLUSTER3_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU1_CLUSTER3_VAL_RANGE                 1:1
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU1_CLUSTER3_VAL_WOFFSET                       0x0
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU1_CLUSTER3_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU1_CLUSTER3_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU1_CLUSTER3_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU1_CLUSTER3_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU1_CLUSTER3_VAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU1_CLUSTER3_VAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU1_CLUSTER3_VAL_INIT_ENUM                     CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU1_CLUSTER3_VAL_CHAIN_SHIFT_NOT_DONE                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_IFU1_CLUSTER3_VAL_CHAIN_SHIFT_DONE                      _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_0_VAL_SHIFT                    _MK_SHIFT_CONST(2)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_0_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_0_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_0_VAL_RANGE                    2:2
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_0_VAL_WOFFSET                  0x0
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_0_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_0_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_0_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_0_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_0_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_0_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_0_VAL_INIT_ENUM                        CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_0_VAL_CHAIN_SHIFT_NOT_DONE                     _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_0_VAL_CHAIN_SHIFT_DONE                 _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_1_VAL_SHIFT                    _MK_SHIFT_CONST(3)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_1_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_1_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_1_VAL_RANGE                    3:3
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_1_VAL_WOFFSET                  0x0
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_1_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_1_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_1_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_1_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_1_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_1_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_1_VAL_INIT_ENUM                        CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_1_VAL_CHAIN_SHIFT_NOT_DONE                     _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_DATA_CLUSTER3_1_VAL_CHAIN_SHIFT_DONE                 _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_TAG_CLUSTER3_VAL_SHIFT                       _MK_SHIFT_CONST(4)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_TAG_CLUSTER3_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_TAG_CLUSTER3_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_TAG_CLUSTER3_VAL_RANGE                       4:4
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_TAG_CLUSTER3_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_TAG_CLUSTER3_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_TAG_CLUSTER3_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_TAG_CLUSTER3_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_TAG_CLUSTER3_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_TAG_CLUSTER3_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_TAG_CLUSTER3_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_TAG_CLUSTER3_VAL_INIT_ENUM                   CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_TAG_CLUSTER3_VAL_CHAIN_SHIFT_NOT_DONE                        _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_L2_TAG_CLUSTER3_VAL_CHAIN_SHIFT_DONE                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU0_CLUSTER3_VAL_SHIFT                 _MK_SHIFT_CONST(5)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU0_CLUSTER3_VAL_FIELD                 _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU0_CLUSTER3_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU0_CLUSTER3_VAL_RANGE                 5:5
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU0_CLUSTER3_VAL_WOFFSET                       0x0
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU0_CLUSTER3_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU0_CLUSTER3_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU0_CLUSTER3_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU0_CLUSTER3_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU0_CLUSTER3_VAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU0_CLUSTER3_VAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU0_CLUSTER3_VAL_INIT_ENUM                     CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU0_CLUSTER3_VAL_CHAIN_SHIFT_NOT_DONE                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU0_CLUSTER3_VAL_CHAIN_SHIFT_DONE                      _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU1_CLUSTER3_VAL_SHIFT                 _MK_SHIFT_CONST(6)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU1_CLUSTER3_VAL_FIELD                 _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU1_CLUSTER3_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU1_CLUSTER3_VAL_RANGE                 6:6
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU1_CLUSTER3_VAL_WOFFSET                       0x0
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU1_CLUSTER3_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU1_CLUSTER3_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU1_CLUSTER3_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU1_CLUSTER3_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU1_CLUSTER3_VAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU1_CLUSTER3_VAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU1_CLUSTER3_VAL_INIT_ENUM                     CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU1_CLUSTER3_VAL_CHAIN_SHIFT_NOT_DONE                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_6_0_RESHIFT_STATUS_CHAIN_6_SEC_CCPLEX_LSU1_CLUSTER3_VAL_CHAIN_SHIFT_DONE                      _MK_ENUM_CONST(1)

// Register FUSE_RESHIFT_TRIGGER_CHAIN_7_0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0                  _MK_ADDR_CONST(0xc0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_SECURE                   0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_DUAL                     0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_SCR                      0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_WORD_COUNT                       0x1
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESET_MASK                       _MK_MASK_CONST(0x3fffffff)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_READ_MASK                        _MK_MASK_CONST(0x3fffffff)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_WRITE_MASK                       _MK_MASK_CONST(0x3fffffff)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS0_VAL_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS0_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS0_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS0_VAL_RANGE                    0:0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS0_VAL_WOFFSET                  0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS0_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS0_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS0_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS0_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS0_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS0_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS0_VAL_INIT_ENUM                        DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS0_VAL_DISABLED                 _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS0_VAL_ENABLED                  _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS1_VAL_SHIFT                    _MK_SHIFT_CONST(1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS1_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS1_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS1_VAL_RANGE                    1:1
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS1_VAL_WOFFSET                  0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS1_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS1_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS1_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS1_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS1_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS1_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS1_VAL_INIT_ENUM                        DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS1_VAL_DISABLED                 _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS1_VAL_ENABLED                  _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS2_VAL_SHIFT                    _MK_SHIFT_CONST(2)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS2_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS2_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS2_VAL_RANGE                    2:2
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS2_VAL_WOFFSET                  0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS2_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS2_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS2_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS2_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS2_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS2_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS2_VAL_INIT_ENUM                        DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS2_VAL_DISABLED                 _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS2_VAL_ENABLED                  _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS3_VAL_SHIFT                    _MK_SHIFT_CONST(3)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS3_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS3_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS3_VAL_RANGE                    3:3
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS3_VAL_WOFFSET                  0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS3_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS3_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS3_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS3_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS3_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS3_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS3_VAL_INIT_ENUM                        DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS3_VAL_DISABLED                 _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0LTS3_VAL_ENABLED                  _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP0_VAL_SHIFT                     _MK_SHIFT_CONST(4)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP0_VAL_FIELD                     _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP0_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP0_VAL_RANGE                     4:4
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP0_VAL_WOFFSET                   0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP0_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP0_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP0_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP0_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP0_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP0_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP0_VAL_INIT_ENUM                 DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP0_VAL_DISABLED                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP0_VAL_ENABLED                   _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP1_VAL_SHIFT                     _MK_SHIFT_CONST(5)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP1_VAL_FIELD                     _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP1_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP1_VAL_RANGE                     5:5
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP1_VAL_WOFFSET                   0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP1_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP1_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP1_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP1_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP1_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP1_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP1_VAL_INIT_ENUM                 DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP1_VAL_DISABLED                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCF0RP1_VAL_ENABLED                   _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0CP_VAL_SHIFT                      _MK_SHIFT_CONST(6)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0CP_VAL_FIELD                      _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0CP_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0CP_VAL_RANGE                      6:6
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0CP_VAL_WOFFSET                    0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0CP_VAL_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0CP_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0CP_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0CP_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0CP_VAL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0CP_VAL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0CP_VAL_INIT_ENUM                  DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0CP_VAL_DISABLED                   _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0CP_VAL_ENABLED                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0GP_VAL_SHIFT                      _MK_SHIFT_CONST(7)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0GP_VAL_FIELD                      _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0GP_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0GP_VAL_RANGE                      7:7
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0GP_VAL_WOFFSET                    0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0GP_VAL_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0GP_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0GP_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0GP_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0GP_VAL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0GP_VAL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0GP_VAL_INIT_ENUM                  DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0GP_VAL_DISABLED                   _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0GP_VAL_ENABLED                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0SC_VAL_SHIFT                      _MK_SHIFT_CONST(8)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0SC_VAL_FIELD                      _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0SC_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0SC_VAL_RANGE                      8:8
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0SC_VAL_WOFFSET                    0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0SC_VAL_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0SC_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0SC_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0SC_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0SC_VAL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0SC_VAL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0SC_VAL_INIT_ENUM                  DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0SC_VAL_DISABLED                   _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0SC_VAL_ENABLED                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0XBG_VAL_SHIFT                     _MK_SHIFT_CONST(9)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0XBG_VAL_FIELD                     _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0XBG_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0XBG_VAL_RANGE                     9:9
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0XBG_VAL_WOFFSET                   0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0XBG_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0XBG_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0XBG_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0XBG_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0XBG_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0XBG_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0XBG_VAL_INIT_ENUM                 DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0XBG_VAL_DISABLED                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0XBG_VAL_ENABLED                   _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0ZF_VAL_SHIFT                      _MK_SHIFT_CONST(10)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0ZF_VAL_FIELD                      _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0ZF_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0ZF_VAL_RANGE                      10:10
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0ZF_VAL_WOFFSET                    0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0ZF_VAL_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0ZF_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0ZF_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0ZF_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0ZF_VAL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0ZF_VAL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0ZF_VAL_INIT_ENUM                  DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0ZF_VAL_DISABLED                   _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCG0ZF_VAL_ENABLED                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP0PES_VAL_SHIFT                     _MK_SHIFT_CONST(11)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP0PES_VAL_FIELD                     _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP0PES_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP0PES_VAL_RANGE                     11:11
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP0PES_VAL_WOFFSET                   0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP0PES_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP0PES_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP0PES_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP0PES_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP0PES_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP0PES_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP0PES_VAL_INIT_ENUM                 DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP0PES_VAL_DISABLED                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP0PES_VAL_ENABLED                   _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP1PES_VAL_SHIFT                     _MK_SHIFT_CONST(12)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP1PES_VAL_FIELD                     _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP1PES_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP1PES_VAL_RANGE                     12:12
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP1PES_VAL_WOFFSET                   0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP1PES_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP1PES_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP1PES_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP1PES_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP1PES_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP1PES_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP1PES_VAL_INIT_ENUM                 DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP1PES_VAL_DISABLED                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCP1PES_VAL_ENABLED                   _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FBH_VAL_SHIFT                     _MK_SHIFT_CONST(13)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FBH_VAL_FIELD                     _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FBH_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FBH_VAL_RANGE                     13:13
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FBH_VAL_WOFFSET                   0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FBH_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FBH_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FBH_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FBH_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FBH_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FBH_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FBH_VAL_INIT_ENUM                 DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FBH_VAL_DISABLED                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FBH_VAL_ENABLED                   _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FE_VAL_SHIFT                      _MK_SHIFT_CONST(14)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FE_VAL_FIELD                      _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FE_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FE_VAL_RANGE                      14:14
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FE_VAL_WOFFSET                    0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FE_VAL_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FE_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FE_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FE_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FE_VAL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FE_VAL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FE_VAL_INIT_ENUM                  DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FE_VAL_DISABLED                   _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0FE_VAL_ENABLED                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0HB_VAL_SHIFT                      _MK_SHIFT_CONST(15)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0HB_VAL_FIELD                      _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0HB_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0HB_VAL_RANGE                      15:15
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0HB_VAL_WOFFSET                    0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0HB_VAL_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0HB_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0HB_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0HB_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0HB_VAL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0HB_VAL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0HB_VAL_INIT_ENUM                  DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0HB_VAL_DISABLED                   _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0HB_VAL_ENABLED                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0PD_VAL_SHIFT                      _MK_SHIFT_CONST(16)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0PD_VAL_FIELD                      _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0PD_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0PD_VAL_RANGE                      16:16
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0PD_VAL_WOFFSET                    0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0PD_VAL_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0PD_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0PD_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0PD_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0PD_VAL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0PD_VAL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0PD_VAL_INIT_ENUM                  DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0PD_VAL_DISABLED                   _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCS0PD_VAL_ENABLED                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCX0XB_VAL_SHIFT                      _MK_SHIFT_CONST(17)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCX0XB_VAL_FIELD                      _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCX0XB_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCX0XB_VAL_RANGE                      17:17
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCX0XB_VAL_WOFFSET                    0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCX0XB_VAL_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCX0XB_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCX0XB_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCX0XB_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCX0XB_VAL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCX0XB_VAL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCX0XB_VAL_INIT_ENUM                  DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCX0XB_VAL_DISABLED                   _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_OTHER_GVCX0XB_VAL_ENABLED                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0PE_VAL_SHIFT                      _MK_SHIFT_CONST(18)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0PE_VAL_FIELD                      _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0PE_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0PE_VAL_RANGE                      18:18
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0PE_VAL_WOFFSET                    0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0PE_VAL_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0PE_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0PE_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0PE_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0PE_VAL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0PE_VAL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0PE_VAL_INIT_ENUM                  DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0PE_VAL_DISABLED                   _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0PE_VAL_ENABLED                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX0_VAL_SHIFT                     _MK_SHIFT_CONST(19)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX0_VAL_FIELD                     _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX0_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX0_VAL_RANGE                     19:19
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX0_VAL_WOFFSET                   0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX0_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX0_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX0_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX0_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX0_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX0_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX0_VAL_INIT_ENUM                 DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX0_VAL_DISABLED                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX0_VAL_ENABLED                   _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX1_VAL_SHIFT                     _MK_SHIFT_CONST(20)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX1_VAL_FIELD                     _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX1_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX1_VAL_RANGE                     20:20
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX1_VAL_WOFFSET                   0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX1_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX1_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX1_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX1_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX1_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX1_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX1_VAL_INIT_ENUM                 DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX1_VAL_DISABLED                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC0_GVCT0TX1_VAL_ENABLED                   _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0PE_VAL_SHIFT                      _MK_SHIFT_CONST(21)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0PE_VAL_FIELD                      _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0PE_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0PE_VAL_RANGE                      21:21
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0PE_VAL_WOFFSET                    0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0PE_VAL_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0PE_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0PE_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0PE_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0PE_VAL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0PE_VAL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0PE_VAL_INIT_ENUM                  DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0PE_VAL_DISABLED                   _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0PE_VAL_ENABLED                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX0_VAL_SHIFT                     _MK_SHIFT_CONST(22)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX0_VAL_FIELD                     _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX0_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX0_VAL_RANGE                     22:22
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX0_VAL_WOFFSET                   0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX0_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX0_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX0_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX0_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX0_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX0_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX0_VAL_INIT_ENUM                 DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX0_VAL_DISABLED                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX0_VAL_ENABLED                   _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX1_VAL_SHIFT                     _MK_SHIFT_CONST(23)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX1_VAL_FIELD                     _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX1_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX1_VAL_RANGE                     23:23
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX1_VAL_WOFFSET                   0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX1_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX1_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX1_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX1_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX1_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX1_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX1_VAL_INIT_ENUM                 DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX1_VAL_DISABLED                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC1_GVCT0TX1_VAL_ENABLED                   _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0PE_VAL_SHIFT                      _MK_SHIFT_CONST(24)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0PE_VAL_FIELD                      _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0PE_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0PE_VAL_RANGE                      24:24
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0PE_VAL_WOFFSET                    0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0PE_VAL_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0PE_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0PE_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0PE_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0PE_VAL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0PE_VAL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0PE_VAL_INIT_ENUM                  DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0PE_VAL_DISABLED                   _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0PE_VAL_ENABLED                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX0_VAL_SHIFT                     _MK_SHIFT_CONST(25)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX0_VAL_FIELD                     _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX0_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX0_VAL_RANGE                     25:25
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX0_VAL_WOFFSET                   0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX0_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX0_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX0_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX0_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX0_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX0_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX0_VAL_INIT_ENUM                 DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX0_VAL_DISABLED                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX0_VAL_ENABLED                   _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX1_VAL_SHIFT                     _MK_SHIFT_CONST(26)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX1_VAL_FIELD                     _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX1_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX1_VAL_RANGE                     26:26
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX1_VAL_WOFFSET                   0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX1_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX1_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX1_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX1_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX1_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX1_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX1_VAL_INIT_ENUM                 DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX1_VAL_DISABLED                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC2_GVCT0TX1_VAL_ENABLED                   _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0PE_VAL_SHIFT                      _MK_SHIFT_CONST(27)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0PE_VAL_FIELD                      _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0PE_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0PE_VAL_RANGE                      27:27
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0PE_VAL_WOFFSET                    0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0PE_VAL_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0PE_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0PE_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0PE_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0PE_VAL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0PE_VAL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0PE_VAL_INIT_ENUM                  DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0PE_VAL_DISABLED                   _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0PE_VAL_ENABLED                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX0_VAL_SHIFT                     _MK_SHIFT_CONST(28)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX0_VAL_FIELD                     _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX0_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX0_VAL_RANGE                     28:28
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX0_VAL_WOFFSET                   0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX0_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX0_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX0_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX0_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX0_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX0_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX0_VAL_INIT_ENUM                 DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX0_VAL_DISABLED                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX0_VAL_ENABLED                   _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX1_VAL_SHIFT                     _MK_SHIFT_CONST(29)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX1_VAL_FIELD                     _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX1_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX1_VAL_RANGE                     29:29
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX1_VAL_WOFFSET                   0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX1_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX1_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX1_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX1_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX1_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX1_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX1_VAL_INIT_ENUM                 DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX1_VAL_DISABLED                  _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_7_0_RESHIFT_TRIGGER_CHAIN_7_SEG_STPC3_GVCT0TX1_VAL_ENABLED                   _MK_ENUM_CONST(1)

// Register FUSE_RESHIFT_STATUS_CHAIN_7_0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0                   _MK_ADDR_CONST(0xc4)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_SECURE                    0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_DUAL                      0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_SCR                       0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_WORD_COUNT                        0x1
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESET_MASK                        _MK_MASK_CONST(0x3fffffff)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_READ_MASK                         _MK_MASK_CONST(0x3fffffff)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_WRITE_MASK                        _MK_MASK_CONST(0x3fffffff)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS0_VAL_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS0_VAL_FIELD                      _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS0_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS0_VAL_RANGE                      0:0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS0_VAL_WOFFSET                    0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS0_VAL_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS0_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS0_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS0_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS0_VAL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS0_VAL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS0_VAL_INIT_ENUM                  CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS0_VAL_CHAIN_SHIFT_NOT_DONE                       _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS0_VAL_CHAIN_SHIFT_DONE                   _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS1_VAL_SHIFT                      _MK_SHIFT_CONST(1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS1_VAL_FIELD                      _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS1_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS1_VAL_RANGE                      1:1
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS1_VAL_WOFFSET                    0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS1_VAL_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS1_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS1_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS1_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS1_VAL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS1_VAL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS1_VAL_INIT_ENUM                  CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS1_VAL_CHAIN_SHIFT_NOT_DONE                       _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS1_VAL_CHAIN_SHIFT_DONE                   _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS2_VAL_SHIFT                      _MK_SHIFT_CONST(2)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS2_VAL_FIELD                      _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS2_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS2_VAL_RANGE                      2:2
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS2_VAL_WOFFSET                    0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS2_VAL_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS2_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS2_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS2_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS2_VAL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS2_VAL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS2_VAL_INIT_ENUM                  CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS2_VAL_CHAIN_SHIFT_NOT_DONE                       _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS2_VAL_CHAIN_SHIFT_DONE                   _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS3_VAL_SHIFT                      _MK_SHIFT_CONST(3)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS3_VAL_FIELD                      _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS3_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS3_VAL_RANGE                      3:3
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS3_VAL_WOFFSET                    0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS3_VAL_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS3_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS3_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS3_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS3_VAL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS3_VAL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS3_VAL_INIT_ENUM                  CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS3_VAL_CHAIN_SHIFT_NOT_DONE                       _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0LTS3_VAL_CHAIN_SHIFT_DONE                   _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP0_VAL_SHIFT                       _MK_SHIFT_CONST(4)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP0_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP0_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP0_VAL_RANGE                       4:4
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP0_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP0_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP0_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP0_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP0_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP0_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP0_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP0_VAL_INIT_ENUM                   CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP0_VAL_CHAIN_SHIFT_NOT_DONE                        _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP0_VAL_CHAIN_SHIFT_DONE                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP1_VAL_SHIFT                       _MK_SHIFT_CONST(5)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP1_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP1_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP1_VAL_RANGE                       5:5
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP1_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP1_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP1_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP1_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP1_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP1_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP1_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP1_VAL_INIT_ENUM                   CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP1_VAL_CHAIN_SHIFT_NOT_DONE                        _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCF0RP1_VAL_CHAIN_SHIFT_DONE                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0CP_VAL_SHIFT                        _MK_SHIFT_CONST(6)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0CP_VAL_FIELD                        _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0CP_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0CP_VAL_RANGE                        6:6
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0CP_VAL_WOFFSET                      0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0CP_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0CP_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0CP_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0CP_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0CP_VAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0CP_VAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0CP_VAL_INIT_ENUM                    CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0CP_VAL_CHAIN_SHIFT_NOT_DONE                 _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0CP_VAL_CHAIN_SHIFT_DONE                     _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0GP_VAL_SHIFT                        _MK_SHIFT_CONST(7)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0GP_VAL_FIELD                        _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0GP_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0GP_VAL_RANGE                        7:7
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0GP_VAL_WOFFSET                      0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0GP_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0GP_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0GP_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0GP_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0GP_VAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0GP_VAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0GP_VAL_INIT_ENUM                    CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0GP_VAL_CHAIN_SHIFT_NOT_DONE                 _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0GP_VAL_CHAIN_SHIFT_DONE                     _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0SC_VAL_SHIFT                        _MK_SHIFT_CONST(8)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0SC_VAL_FIELD                        _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0SC_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0SC_VAL_RANGE                        8:8
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0SC_VAL_WOFFSET                      0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0SC_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0SC_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0SC_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0SC_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0SC_VAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0SC_VAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0SC_VAL_INIT_ENUM                    CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0SC_VAL_CHAIN_SHIFT_NOT_DONE                 _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0SC_VAL_CHAIN_SHIFT_DONE                     _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0XBG_VAL_SHIFT                       _MK_SHIFT_CONST(9)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0XBG_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0XBG_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0XBG_VAL_RANGE                       9:9
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0XBG_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0XBG_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0XBG_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0XBG_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0XBG_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0XBG_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0XBG_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0XBG_VAL_INIT_ENUM                   CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0XBG_VAL_CHAIN_SHIFT_NOT_DONE                        _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0XBG_VAL_CHAIN_SHIFT_DONE                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0ZF_VAL_SHIFT                        _MK_SHIFT_CONST(10)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0ZF_VAL_FIELD                        _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0ZF_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0ZF_VAL_RANGE                        10:10
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0ZF_VAL_WOFFSET                      0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0ZF_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0ZF_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0ZF_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0ZF_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0ZF_VAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0ZF_VAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0ZF_VAL_INIT_ENUM                    CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0ZF_VAL_CHAIN_SHIFT_NOT_DONE                 _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCG0ZF_VAL_CHAIN_SHIFT_DONE                     _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP0PES_VAL_SHIFT                       _MK_SHIFT_CONST(11)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP0PES_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP0PES_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP0PES_VAL_RANGE                       11:11
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP0PES_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP0PES_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP0PES_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP0PES_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP0PES_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP0PES_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP0PES_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP0PES_VAL_INIT_ENUM                   CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP0PES_VAL_CHAIN_SHIFT_NOT_DONE                        _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP0PES_VAL_CHAIN_SHIFT_DONE                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP1PES_VAL_SHIFT                       _MK_SHIFT_CONST(12)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP1PES_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP1PES_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP1PES_VAL_RANGE                       12:12
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP1PES_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP1PES_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP1PES_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP1PES_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP1PES_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP1PES_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP1PES_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP1PES_VAL_INIT_ENUM                   CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP1PES_VAL_CHAIN_SHIFT_NOT_DONE                        _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCP1PES_VAL_CHAIN_SHIFT_DONE                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FBH_VAL_SHIFT                       _MK_SHIFT_CONST(13)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FBH_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FBH_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FBH_VAL_RANGE                       13:13
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FBH_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FBH_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FBH_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FBH_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FBH_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FBH_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FBH_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FBH_VAL_INIT_ENUM                   CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FBH_VAL_CHAIN_SHIFT_NOT_DONE                        _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FBH_VAL_CHAIN_SHIFT_DONE                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FE_VAL_SHIFT                        _MK_SHIFT_CONST(14)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FE_VAL_FIELD                        _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FE_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FE_VAL_RANGE                        14:14
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FE_VAL_WOFFSET                      0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FE_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FE_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FE_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FE_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FE_VAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FE_VAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FE_VAL_INIT_ENUM                    CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FE_VAL_CHAIN_SHIFT_NOT_DONE                 _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0FE_VAL_CHAIN_SHIFT_DONE                     _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0HB_VAL_SHIFT                        _MK_SHIFT_CONST(15)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0HB_VAL_FIELD                        _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0HB_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0HB_VAL_RANGE                        15:15
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0HB_VAL_WOFFSET                      0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0HB_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0HB_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0HB_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0HB_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0HB_VAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0HB_VAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0HB_VAL_INIT_ENUM                    CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0HB_VAL_CHAIN_SHIFT_NOT_DONE                 _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0HB_VAL_CHAIN_SHIFT_DONE                     _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0PD_VAL_SHIFT                        _MK_SHIFT_CONST(16)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0PD_VAL_FIELD                        _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0PD_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0PD_VAL_RANGE                        16:16
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0PD_VAL_WOFFSET                      0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0PD_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0PD_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0PD_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0PD_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0PD_VAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0PD_VAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0PD_VAL_INIT_ENUM                    CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0PD_VAL_CHAIN_SHIFT_NOT_DONE                 _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCS0PD_VAL_CHAIN_SHIFT_DONE                     _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCX0XB_VAL_SHIFT                        _MK_SHIFT_CONST(17)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCX0XB_VAL_FIELD                        _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCX0XB_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCX0XB_VAL_RANGE                        17:17
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCX0XB_VAL_WOFFSET                      0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCX0XB_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCX0XB_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCX0XB_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCX0XB_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCX0XB_VAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCX0XB_VAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCX0XB_VAL_INIT_ENUM                    CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCX0XB_VAL_CHAIN_SHIFT_NOT_DONE                 _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_OTHER_GVCX0XB_VAL_CHAIN_SHIFT_DONE                     _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0PE_VAL_SHIFT                        _MK_SHIFT_CONST(18)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0PE_VAL_FIELD                        _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0PE_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0PE_VAL_RANGE                        18:18
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0PE_VAL_WOFFSET                      0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0PE_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0PE_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0PE_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0PE_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0PE_VAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0PE_VAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0PE_VAL_INIT_ENUM                    CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0PE_VAL_CHAIN_SHIFT_NOT_DONE                 _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0PE_VAL_CHAIN_SHIFT_DONE                     _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX0_VAL_SHIFT                       _MK_SHIFT_CONST(19)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX0_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX0_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX0_VAL_RANGE                       19:19
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX0_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX0_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX0_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX0_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX0_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX0_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX0_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX0_VAL_INIT_ENUM                   CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX0_VAL_CHAIN_SHIFT_NOT_DONE                        _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX0_VAL_CHAIN_SHIFT_DONE                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX1_VAL_SHIFT                       _MK_SHIFT_CONST(20)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX1_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX1_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX1_VAL_RANGE                       20:20
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX1_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX1_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX1_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX1_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX1_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX1_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX1_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX1_VAL_INIT_ENUM                   CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX1_VAL_CHAIN_SHIFT_NOT_DONE                        _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC0_GVCT0TX1_VAL_CHAIN_SHIFT_DONE                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0PE_VAL_SHIFT                        _MK_SHIFT_CONST(21)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0PE_VAL_FIELD                        _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0PE_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0PE_VAL_RANGE                        21:21
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0PE_VAL_WOFFSET                      0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0PE_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0PE_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0PE_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0PE_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0PE_VAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0PE_VAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0PE_VAL_INIT_ENUM                    CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0PE_VAL_CHAIN_SHIFT_NOT_DONE                 _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0PE_VAL_CHAIN_SHIFT_DONE                     _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX0_VAL_SHIFT                       _MK_SHIFT_CONST(22)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX0_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX0_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX0_VAL_RANGE                       22:22
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX0_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX0_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX0_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX0_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX0_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX0_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX0_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX0_VAL_INIT_ENUM                   CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX0_VAL_CHAIN_SHIFT_NOT_DONE                        _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX0_VAL_CHAIN_SHIFT_DONE                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX1_VAL_SHIFT                       _MK_SHIFT_CONST(23)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX1_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX1_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX1_VAL_RANGE                       23:23
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX1_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX1_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX1_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX1_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX1_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX1_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX1_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX1_VAL_INIT_ENUM                   CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX1_VAL_CHAIN_SHIFT_NOT_DONE                        _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC1_GVCT0TX1_VAL_CHAIN_SHIFT_DONE                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0PE_VAL_SHIFT                        _MK_SHIFT_CONST(24)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0PE_VAL_FIELD                        _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0PE_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0PE_VAL_RANGE                        24:24
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0PE_VAL_WOFFSET                      0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0PE_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0PE_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0PE_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0PE_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0PE_VAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0PE_VAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0PE_VAL_INIT_ENUM                    CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0PE_VAL_CHAIN_SHIFT_NOT_DONE                 _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0PE_VAL_CHAIN_SHIFT_DONE                     _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX0_VAL_SHIFT                       _MK_SHIFT_CONST(25)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX0_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX0_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX0_VAL_RANGE                       25:25
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX0_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX0_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX0_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX0_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX0_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX0_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX0_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX0_VAL_INIT_ENUM                   CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX0_VAL_CHAIN_SHIFT_NOT_DONE                        _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX0_VAL_CHAIN_SHIFT_DONE                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX1_VAL_SHIFT                       _MK_SHIFT_CONST(26)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX1_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX1_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX1_VAL_RANGE                       26:26
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX1_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX1_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX1_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX1_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX1_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX1_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX1_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX1_VAL_INIT_ENUM                   CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX1_VAL_CHAIN_SHIFT_NOT_DONE                        _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC2_GVCT0TX1_VAL_CHAIN_SHIFT_DONE                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0PE_VAL_SHIFT                        _MK_SHIFT_CONST(27)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0PE_VAL_FIELD                        _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0PE_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0PE_VAL_RANGE                        27:27
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0PE_VAL_WOFFSET                      0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0PE_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0PE_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0PE_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0PE_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0PE_VAL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0PE_VAL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0PE_VAL_INIT_ENUM                    CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0PE_VAL_CHAIN_SHIFT_NOT_DONE                 _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0PE_VAL_CHAIN_SHIFT_DONE                     _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX0_VAL_SHIFT                       _MK_SHIFT_CONST(28)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX0_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX0_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX0_VAL_RANGE                       28:28
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX0_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX0_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX0_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX0_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX0_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX0_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX0_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX0_VAL_INIT_ENUM                   CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX0_VAL_CHAIN_SHIFT_NOT_DONE                        _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX0_VAL_CHAIN_SHIFT_DONE                    _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX1_VAL_SHIFT                       _MK_SHIFT_CONST(29)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX1_VAL_FIELD                       _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX1_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX1_VAL_RANGE                       29:29
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX1_VAL_WOFFSET                     0x0
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX1_VAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX1_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX1_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX1_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX1_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX1_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX1_VAL_INIT_ENUM                   CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX1_VAL_CHAIN_SHIFT_NOT_DONE                        _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_7_0_RESHIFT_STATUS_CHAIN_7_SEC_STPC3_GVCT0TX1_VAL_CHAIN_SHIFT_DONE                    _MK_ENUM_CONST(1)

// Register FUSE_RESHIFT_TRIGGER_CHAIN_8_0
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0                  _MK_ADDR_CONST(0xc8)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_SECURE                   0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_DUAL                     0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_SCR                      0
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_WORD_COUNT                       0x1
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESET_MASK                       _MK_MASK_CONST(0x3fffff)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_READ_MASK                        _MK_MASK_CONST(0x3fffff)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_WRITE_MASK                       _MK_MASK_CONST(0x3fffff)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_0_VAL_SHIFT                   _MK_SHIFT_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_0_VAL_FIELD                   _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_0_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_0_VAL_RANGE                   0:0
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_0_VAL_WOFFSET                 0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_0_VAL_INIT_ENUM                       DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_0_VAL_DISABLED                        _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_0_VAL_ENABLED                 _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_1_VAL_SHIFT                   _MK_SHIFT_CONST(1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_1_VAL_FIELD                   _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_1_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_1_VAL_RANGE                   1:1
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_1_VAL_WOFFSET                 0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_1_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_1_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_1_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_1_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_1_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_1_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_1_VAL_INIT_ENUM                       DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_1_VAL_DISABLED                        _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBA_1_VAL_ENABLED                 _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_0_VAL_SHIFT                   _MK_SHIFT_CONST(2)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_0_VAL_FIELD                   _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_0_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_0_VAL_RANGE                   2:2
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_0_VAL_WOFFSET                 0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_0_VAL_INIT_ENUM                       DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_0_VAL_DISABLED                        _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_0_VAL_ENABLED                 _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_1_VAL_SHIFT                   _MK_SHIFT_CONST(3)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_1_VAL_FIELD                   _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_1_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_1_VAL_RANGE                   3:3
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_1_VAL_WOFFSET                 0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_1_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_1_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_1_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_1_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_1_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_1_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_1_VAL_INIT_ENUM                       DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_1_VAL_DISABLED                        _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_CVNOC_GRTCVBBB_1_VAL_ENABLED                 _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAA_VAL_SHIFT                  _MK_SHIFT_CONST(4)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAA_VAL_FIELD                  _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAA_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAA_VAL_RANGE                  4:4
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAA_VAL_WOFFSET                        0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAA_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAA_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAA_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAA_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAA_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAA_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAA_VAL_INIT_ENUM                      DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAA_VAL_DISABLED                       _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAA_VAL_ENABLED                        _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAC_VAL_SHIFT                  _MK_SHIFT_CONST(5)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAC_VAL_FIELD                  _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAC_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAC_VAL_RANGE                  5:5
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAC_VAL_WOFFSET                        0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAC_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAC_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAC_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAC_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAC_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAC_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAC_VAL_INIT_ENUM                      DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAC_VAL_DISABLED                       _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAC_VAL_ENABLED                        _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM0_VAL_SHIFT                 _MK_SHIFT_CONST(6)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM0_VAL_FIELD                 _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM0_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM0_VAL_RANGE                 6:6
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM0_VAL_WOFFSET                       0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM0_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM0_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM0_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM0_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM0_VAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM0_VAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM0_VAL_INIT_ENUM                     DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM0_VAL_DISABLED                      _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM0_VAL_ENABLED                       _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM1_VAL_SHIFT                 _MK_SHIFT_CONST(7)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM1_VAL_FIELD                 _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM1_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM1_VAL_RANGE                 7:7
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM1_VAL_WOFFSET                       0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM1_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM1_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM1_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM1_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM1_VAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM1_VAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM1_VAL_INIT_ENUM                     DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM1_VAL_DISABLED                      _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAM1_VAL_ENABLED                       _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAO_VAL_SHIFT                  _MK_SHIFT_CONST(8)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAO_VAL_FIELD                  _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAO_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAO_VAL_RANGE                  8:8
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAO_VAL_WOFFSET                        0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAO_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAO_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAO_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAO_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAO_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAO_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAO_VAL_INIT_ENUM                      DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAO_VAL_DISABLED                       _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAO_VAL_ENABLED                        _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAP_VAL_SHIFT                  _MK_SHIFT_CONST(9)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAP_VAL_FIELD                  _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAP_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAP_VAL_RANGE                  9:9
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAP_VAL_WOFFSET                        0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAP_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAP_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAP_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAP_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAP_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAP_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAP_VAL_INIT_ENUM                      DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAP_VAL_DISABLED                       _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA0_DLAP_VAL_ENABLED                        _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAA_VAL_SHIFT                  _MK_SHIFT_CONST(10)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAA_VAL_FIELD                  _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAA_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAA_VAL_RANGE                  10:10
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAA_VAL_WOFFSET                        0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAA_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAA_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAA_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAA_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAA_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAA_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAA_VAL_INIT_ENUM                      DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAA_VAL_DISABLED                       _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAA_VAL_ENABLED                        _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAC_VAL_SHIFT                  _MK_SHIFT_CONST(11)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAC_VAL_FIELD                  _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAC_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAC_VAL_RANGE                  11:11
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAC_VAL_WOFFSET                        0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAC_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAC_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAC_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAC_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAC_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAC_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAC_VAL_INIT_ENUM                      DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAC_VAL_DISABLED                       _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAC_VAL_ENABLED                        _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM0_VAL_SHIFT                 _MK_SHIFT_CONST(12)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM0_VAL_FIELD                 _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM0_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM0_VAL_RANGE                 12:12
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM0_VAL_WOFFSET                       0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM0_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM0_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM0_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM0_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM0_VAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM0_VAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM0_VAL_INIT_ENUM                     DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM0_VAL_DISABLED                      _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM0_VAL_ENABLED                       _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM1_VAL_SHIFT                 _MK_SHIFT_CONST(13)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM1_VAL_FIELD                 _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM1_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM1_VAL_RANGE                 13:13
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM1_VAL_WOFFSET                       0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM1_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM1_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM1_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM1_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM1_VAL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM1_VAL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM1_VAL_INIT_ENUM                     DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM1_VAL_DISABLED                      _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAM1_VAL_ENABLED                       _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAO_VAL_SHIFT                  _MK_SHIFT_CONST(14)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAO_VAL_FIELD                  _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAO_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAO_VAL_RANGE                  14:14
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAO_VAL_WOFFSET                        0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAO_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAO_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAO_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAO_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAO_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAO_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAO_VAL_INIT_ENUM                      DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAO_VAL_DISABLED                       _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAO_VAL_ENABLED                        _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAP_VAL_SHIFT                  _MK_SHIFT_CONST(15)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAP_VAL_FIELD                  _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAP_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAP_VAL_RANGE                  15:15
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAP_VAL_WOFFSET                        0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAP_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAP_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAP_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAP_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAP_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAP_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAP_VAL_INIT_ENUM                      DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAP_VAL_DISABLED                       _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_DLA1_DLAP_VAL_ENABLED                        _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_PVAC_VAL_SHIFT                  _MK_SHIFT_CONST(16)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_PVAC_VAL_FIELD                  _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_PVAC_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_PVAC_VAL_RANGE                  16:16
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_PVAC_VAL_WOFFSET                        0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_PVAC_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_PVAC_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_PVAC_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_PVAC_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_PVAC_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_PVAC_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_PVAC_VAL_INIT_ENUM                      DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_PVAC_VAL_DISABLED                       _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_PVAC_VAL_ENABLED                        _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS0_VAL_SHIFT                  _MK_SHIFT_CONST(17)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS0_VAL_FIELD                  _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS0_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS0_VAL_RANGE                  17:17
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS0_VAL_WOFFSET                        0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS0_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS0_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS0_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS0_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS0_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS0_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS0_VAL_INIT_ENUM                      DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS0_VAL_DISABLED                       _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS0_VAL_ENABLED                        _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS1_VAL_SHIFT                  _MK_SHIFT_CONST(18)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS1_VAL_FIELD                  _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS1_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS1_VAL_RANGE                  18:18
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS1_VAL_WOFFSET                        0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS1_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS1_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS1_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS1_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS1_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS1_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS1_VAL_INIT_ENUM                      DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS1_VAL_DISABLED                       _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA0_VPS1_VAL_ENABLED                        _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_PVAC_VAL_SHIFT                  _MK_SHIFT_CONST(19)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_PVAC_VAL_FIELD                  _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_PVAC_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_PVAC_VAL_RANGE                  19:19
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_PVAC_VAL_WOFFSET                        0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_PVAC_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_PVAC_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_PVAC_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_PVAC_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_PVAC_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_PVAC_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_PVAC_VAL_INIT_ENUM                      DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_PVAC_VAL_DISABLED                       _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_PVAC_VAL_ENABLED                        _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS0_VAL_SHIFT                  _MK_SHIFT_CONST(20)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS0_VAL_FIELD                  _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS0_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS0_VAL_RANGE                  20:20
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS0_VAL_WOFFSET                        0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS0_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS0_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS0_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS0_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS0_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS0_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS0_VAL_INIT_ENUM                      DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS0_VAL_DISABLED                       _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS0_VAL_ENABLED                        _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS1_VAL_SHIFT                  _MK_SHIFT_CONST(21)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS1_VAL_FIELD                  _MK_FIELD_CONST(0x1, FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS1_VAL_SHIFT)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS1_VAL_RANGE                  21:21
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS1_VAL_WOFFSET                        0x0
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS1_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS1_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS1_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS1_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS1_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS1_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS1_VAL_INIT_ENUM                      DISABLED
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS1_VAL_DISABLED                       _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_TRIGGER_CHAIN_8_0_RESHIFT_TRIGGER_CHAIN_8_SEG_PVA1_VPS1_VAL_ENABLED                        _MK_ENUM_CONST(1)

// Register FUSE_RESHIFT_STATUS_CHAIN_8_0
#define FUSE_RESHIFT_STATUS_CHAIN_8_0                   _MK_ADDR_CONST(0xcc)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_SECURE                    0x0
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_DUAL                      0x0
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_SCR                       0
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_WORD_COUNT                        0x1
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESET_MASK                        _MK_MASK_CONST(0x3fffff)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_READ_MASK                         _MK_MASK_CONST(0x3fffff)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_WRITE_MASK                        _MK_MASK_CONST(0x3fffff)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_0_VAL_SHIFT                     _MK_SHIFT_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_0_VAL_FIELD                     _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_0_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_0_VAL_RANGE                     0:0
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_0_VAL_WOFFSET                   0x0
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_0_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_0_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_0_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_0_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_0_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_0_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_0_VAL_INIT_ENUM                 CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_0_VAL_CHAIN_SHIFT_NOT_DONE                      _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_0_VAL_CHAIN_SHIFT_DONE                  _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_1_VAL_SHIFT                     _MK_SHIFT_CONST(1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_1_VAL_FIELD                     _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_1_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_1_VAL_RANGE                     1:1
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_1_VAL_WOFFSET                   0x0
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_1_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_1_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_1_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_1_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_1_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_1_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_1_VAL_INIT_ENUM                 CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_1_VAL_CHAIN_SHIFT_NOT_DONE                      _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBA_1_VAL_CHAIN_SHIFT_DONE                  _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_0_VAL_SHIFT                     _MK_SHIFT_CONST(2)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_0_VAL_FIELD                     _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_0_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_0_VAL_RANGE                     2:2
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_0_VAL_WOFFSET                   0x0
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_0_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_0_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_0_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_0_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_0_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_0_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_0_VAL_INIT_ENUM                 CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_0_VAL_CHAIN_SHIFT_NOT_DONE                      _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_0_VAL_CHAIN_SHIFT_DONE                  _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_1_VAL_SHIFT                     _MK_SHIFT_CONST(3)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_1_VAL_FIELD                     _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_1_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_1_VAL_RANGE                     3:3
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_1_VAL_WOFFSET                   0x0
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_1_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_1_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_1_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_1_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_1_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_1_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_1_VAL_INIT_ENUM                 CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_1_VAL_CHAIN_SHIFT_NOT_DONE                      _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_CVNOC_GRTCVBBB_1_VAL_CHAIN_SHIFT_DONE                  _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAA_VAL_SHIFT                    _MK_SHIFT_CONST(4)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAA_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAA_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAA_VAL_RANGE                    4:4
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAA_VAL_WOFFSET                  0x0
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAA_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAA_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAA_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAA_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAA_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAA_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAA_VAL_INIT_ENUM                        CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAA_VAL_CHAIN_SHIFT_NOT_DONE                     _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAA_VAL_CHAIN_SHIFT_DONE                 _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAC_VAL_SHIFT                    _MK_SHIFT_CONST(5)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAC_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAC_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAC_VAL_RANGE                    5:5
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAC_VAL_WOFFSET                  0x0
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAC_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAC_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAC_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAC_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAC_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAC_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAC_VAL_INIT_ENUM                        CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAC_VAL_CHAIN_SHIFT_NOT_DONE                     _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAC_VAL_CHAIN_SHIFT_DONE                 _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM0_VAL_SHIFT                   _MK_SHIFT_CONST(6)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM0_VAL_FIELD                   _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM0_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM0_VAL_RANGE                   6:6
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM0_VAL_WOFFSET                 0x0
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM0_VAL_INIT_ENUM                       CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM0_VAL_CHAIN_SHIFT_NOT_DONE                    _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM0_VAL_CHAIN_SHIFT_DONE                        _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM1_VAL_SHIFT                   _MK_SHIFT_CONST(7)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM1_VAL_FIELD                   _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM1_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM1_VAL_RANGE                   7:7
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM1_VAL_WOFFSET                 0x0
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM1_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM1_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM1_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM1_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM1_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM1_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM1_VAL_INIT_ENUM                       CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM1_VAL_CHAIN_SHIFT_NOT_DONE                    _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAM1_VAL_CHAIN_SHIFT_DONE                        _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAO_VAL_SHIFT                    _MK_SHIFT_CONST(8)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAO_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAO_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAO_VAL_RANGE                    8:8
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAO_VAL_WOFFSET                  0x0
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAO_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAO_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAO_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAO_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAO_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAO_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAO_VAL_INIT_ENUM                        CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAO_VAL_CHAIN_SHIFT_NOT_DONE                     _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAO_VAL_CHAIN_SHIFT_DONE                 _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAP_VAL_SHIFT                    _MK_SHIFT_CONST(9)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAP_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAP_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAP_VAL_RANGE                    9:9
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAP_VAL_WOFFSET                  0x0
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAP_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAP_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAP_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAP_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAP_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAP_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAP_VAL_INIT_ENUM                        CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAP_VAL_CHAIN_SHIFT_NOT_DONE                     _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA0_DLAP_VAL_CHAIN_SHIFT_DONE                 _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAA_VAL_SHIFT                    _MK_SHIFT_CONST(10)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAA_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAA_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAA_VAL_RANGE                    10:10
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAA_VAL_WOFFSET                  0x0
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAA_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAA_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAA_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAA_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAA_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAA_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAA_VAL_INIT_ENUM                        CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAA_VAL_CHAIN_SHIFT_NOT_DONE                     _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAA_VAL_CHAIN_SHIFT_DONE                 _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAC_VAL_SHIFT                    _MK_SHIFT_CONST(11)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAC_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAC_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAC_VAL_RANGE                    11:11
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAC_VAL_WOFFSET                  0x0
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAC_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAC_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAC_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAC_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAC_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAC_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAC_VAL_INIT_ENUM                        CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAC_VAL_CHAIN_SHIFT_NOT_DONE                     _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAC_VAL_CHAIN_SHIFT_DONE                 _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM0_VAL_SHIFT                   _MK_SHIFT_CONST(12)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM0_VAL_FIELD                   _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM0_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM0_VAL_RANGE                   12:12
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM0_VAL_WOFFSET                 0x0
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM0_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM0_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM0_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM0_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM0_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM0_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM0_VAL_INIT_ENUM                       CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM0_VAL_CHAIN_SHIFT_NOT_DONE                    _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM0_VAL_CHAIN_SHIFT_DONE                        _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM1_VAL_SHIFT                   _MK_SHIFT_CONST(13)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM1_VAL_FIELD                   _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM1_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM1_VAL_RANGE                   13:13
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM1_VAL_WOFFSET                 0x0
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM1_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM1_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM1_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM1_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM1_VAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM1_VAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM1_VAL_INIT_ENUM                       CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM1_VAL_CHAIN_SHIFT_NOT_DONE                    _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAM1_VAL_CHAIN_SHIFT_DONE                        _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAO_VAL_SHIFT                    _MK_SHIFT_CONST(14)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAO_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAO_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAO_VAL_RANGE                    14:14
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAO_VAL_WOFFSET                  0x0
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAO_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAO_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAO_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAO_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAO_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAO_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAO_VAL_INIT_ENUM                        CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAO_VAL_CHAIN_SHIFT_NOT_DONE                     _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAO_VAL_CHAIN_SHIFT_DONE                 _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAP_VAL_SHIFT                    _MK_SHIFT_CONST(15)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAP_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAP_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAP_VAL_RANGE                    15:15
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAP_VAL_WOFFSET                  0x0
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAP_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAP_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAP_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAP_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAP_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAP_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAP_VAL_INIT_ENUM                        CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAP_VAL_CHAIN_SHIFT_NOT_DONE                     _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_DLA1_DLAP_VAL_CHAIN_SHIFT_DONE                 _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_PVAC_VAL_SHIFT                    _MK_SHIFT_CONST(16)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_PVAC_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_PVAC_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_PVAC_VAL_RANGE                    16:16
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_PVAC_VAL_WOFFSET                  0x0
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_PVAC_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_PVAC_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_PVAC_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_PVAC_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_PVAC_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_PVAC_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_PVAC_VAL_INIT_ENUM                        CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_PVAC_VAL_CHAIN_SHIFT_NOT_DONE                     _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_PVAC_VAL_CHAIN_SHIFT_DONE                 _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS0_VAL_SHIFT                    _MK_SHIFT_CONST(17)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS0_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS0_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS0_VAL_RANGE                    17:17
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS0_VAL_WOFFSET                  0x0
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS0_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS0_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS0_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS0_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS0_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS0_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS0_VAL_INIT_ENUM                        CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS0_VAL_CHAIN_SHIFT_NOT_DONE                     _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS0_VAL_CHAIN_SHIFT_DONE                 _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS1_VAL_SHIFT                    _MK_SHIFT_CONST(18)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS1_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS1_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS1_VAL_RANGE                    18:18
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS1_VAL_WOFFSET                  0x0
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS1_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS1_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS1_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS1_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS1_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS1_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS1_VAL_INIT_ENUM                        CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS1_VAL_CHAIN_SHIFT_NOT_DONE                     _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA0_VPS1_VAL_CHAIN_SHIFT_DONE                 _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_PVAC_VAL_SHIFT                    _MK_SHIFT_CONST(19)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_PVAC_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_PVAC_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_PVAC_VAL_RANGE                    19:19
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_PVAC_VAL_WOFFSET                  0x0
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_PVAC_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_PVAC_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_PVAC_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_PVAC_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_PVAC_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_PVAC_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_PVAC_VAL_INIT_ENUM                        CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_PVAC_VAL_CHAIN_SHIFT_NOT_DONE                     _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_PVAC_VAL_CHAIN_SHIFT_DONE                 _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS0_VAL_SHIFT                    _MK_SHIFT_CONST(20)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS0_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS0_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS0_VAL_RANGE                    20:20
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS0_VAL_WOFFSET                  0x0
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS0_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS0_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS0_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS0_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS0_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS0_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS0_VAL_INIT_ENUM                        CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS0_VAL_CHAIN_SHIFT_NOT_DONE                     _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS0_VAL_CHAIN_SHIFT_DONE                 _MK_ENUM_CONST(1)

#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS1_VAL_SHIFT                    _MK_SHIFT_CONST(21)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS1_VAL_FIELD                    _MK_FIELD_CONST(0x1, FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS1_VAL_SHIFT)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS1_VAL_RANGE                    21:21
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS1_VAL_WOFFSET                  0x0
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS1_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS1_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS1_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS1_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS1_VAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS1_VAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS1_VAL_INIT_ENUM                        CHAIN_SHIFT_NOT_DONE
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS1_VAL_CHAIN_SHIFT_NOT_DONE                     _MK_ENUM_CONST(0)
#define FUSE_RESHIFT_STATUS_CHAIN_8_0_RESHIFT_STATUS_CHAIN_8_SEC_PVA1_VPS1_VAL_CHAIN_SHIFT_DONE                 _MK_ENUM_CONST(1)

// Reserved address 0xd0

// Reserved address 0xd4

// Reserved address 0xd8

// Reserved address 0xdc

// Reserved address 0xe0

// Reserved address 0xe4

// Reserved address 0xe8

// Reserved address 0xec

// Reserved address 0xf0

// Reserved address 0xf4

// Reserved address 0xf8

// Reserved address 0xfc

// Register FUSE_PRODUCTION_MODE_0
#define FUSE_PRODUCTION_MODE_0                  _MK_ADDR_CONST(0x100)
#define FUSE_PRODUCTION_MODE_0_SECURE                   0x0
#define FUSE_PRODUCTION_MODE_0_DUAL                     0x0
#define FUSE_PRODUCTION_MODE_0_SCR                      0
#define FUSE_PRODUCTION_MODE_0_WORD_COUNT                       0x1
#define FUSE_PRODUCTION_MODE_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define FUSE_PRODUCTION_MODE_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_PRODUCTION_MODE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_PRODUCTION_MODE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_PRODUCTION_MODE_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_PRODUCTION_MODE_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_FIELD                    _MK_FIELD_CONST(0x1, FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_SHIFT)
#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_RANGE                    0:0
#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_WOFFSET                  0x0
#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_DEFAULT                  _MK_MASK_CONST(0x1)
#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_ODM_LOCK_0
#define FUSE_ODM_LOCK_0                 _MK_ADDR_CONST(0x108)
#define FUSE_ODM_LOCK_0_SECURE                  0x0
#define FUSE_ODM_LOCK_0_DUAL                    0x0
#define FUSE_ODM_LOCK_0_SCR                     0
#define FUSE_ODM_LOCK_0_WORD_COUNT                      0x1
#define FUSE_ODM_LOCK_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_ODM_LOCK_0_RESET_MASK                      _MK_MASK_CONST(0xf)
#define FUSE_ODM_LOCK_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_ODM_LOCK_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_ODM_LOCK_0_READ_MASK                       _MK_MASK_CONST(0xf)
#define FUSE_ODM_LOCK_0_WRITE_MASK                      _MK_MASK_CONST(0xf)
#define FUSE_ODM_LOCK_0_ODM_LOCK_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_ODM_LOCK_0_ODM_LOCK_FIELD                  _MK_FIELD_CONST(0xf, FUSE_ODM_LOCK_0_ODM_LOCK_SHIFT)
#define FUSE_ODM_LOCK_0_ODM_LOCK_RANGE                  3:0
#define FUSE_ODM_LOCK_0_ODM_LOCK_WOFFSET                        0x0
#define FUSE_ODM_LOCK_0_ODM_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_ODM_LOCK_0_ODM_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define FUSE_ODM_LOCK_0_ODM_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_ODM_LOCK_0_ODM_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_ODM_LOCK_0_ODM_LOCK_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_ODM_LOCK_0_ODM_LOCK_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_OPT_OPENGL_EN_0
#define FUSE_OPT_OPENGL_EN_0                    _MK_ADDR_CONST(0x10c)
#define FUSE_OPT_OPENGL_EN_0_SECURE                     0x0
#define FUSE_OPT_OPENGL_EN_0_DUAL                       0x0
#define FUSE_OPT_OPENGL_EN_0_SCR                        0
#define FUSE_OPT_OPENGL_EN_0_WORD_COUNT                         0x1
#define FUSE_OPT_OPENGL_EN_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_OPENGL_EN_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define FUSE_OPT_OPENGL_EN_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_OPENGL_EN_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_OPENGL_EN_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_OPT_OPENGL_EN_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define FUSE_OPT_OPENGL_EN_0_OPT_OPENGL_EN_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_OPT_OPENGL_EN_0_OPT_OPENGL_EN_FIELD                        _MK_FIELD_CONST(0x1, FUSE_OPT_OPENGL_EN_0_OPT_OPENGL_EN_SHIFT)
#define FUSE_OPT_OPENGL_EN_0_OPT_OPENGL_EN_RANGE                        0:0
#define FUSE_OPT_OPENGL_EN_0_OPT_OPENGL_EN_WOFFSET                      0x0
#define FUSE_OPT_OPENGL_EN_0_OPT_OPENGL_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_OPENGL_EN_0_OPT_OPENGL_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define FUSE_OPT_OPENGL_EN_0_OPT_OPENGL_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_OPENGL_EN_0_OPT_OPENGL_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_OPENGL_EN_0_OPT_OPENGL_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_OPENGL_EN_0_OPT_OPENGL_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_SKU_INFO_0
#define FUSE_SKU_INFO_0                 _MK_ADDR_CONST(0x110)
#define FUSE_SKU_INFO_0_SECURE                  0x0
#define FUSE_SKU_INFO_0_DUAL                    0x0
#define FUSE_SKU_INFO_0_SCR                     0
#define FUSE_SKU_INFO_0_WORD_COUNT                      0x1
#define FUSE_SKU_INFO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_SKU_INFO_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define FUSE_SKU_INFO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_SKU_INFO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_SKU_INFO_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define FUSE_SKU_INFO_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
#define FUSE_SKU_INFO_0_SKU_INFO_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SKU_INFO_0_SKU_INFO_FIELD                  _MK_FIELD_CONST(0xff, FUSE_SKU_INFO_0_SKU_INFO_SHIFT)
#define FUSE_SKU_INFO_0_SKU_INFO_RANGE                  7:0
#define FUSE_SKU_INFO_0_SKU_INFO_WOFFSET                        0x0
#define FUSE_SKU_INFO_0_SKU_INFO_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SKU_INFO_0_SKU_INFO_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define FUSE_SKU_INFO_0_SKU_INFO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SKU_INFO_0_SKU_INFO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SKU_INFO_0_SKU_INFO_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SKU_INFO_0_SKU_INFO_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_CPU_SPEEDO_CALIB_0
#define FUSE_CPU_SPEEDO_CALIB_0                 _MK_ADDR_CONST(0x114)
#define FUSE_CPU_SPEEDO_CALIB_0_SECURE                  0x0
#define FUSE_CPU_SPEEDO_CALIB_0_DUAL                    0x0
#define FUSE_CPU_SPEEDO_CALIB_0_SCR                     0
#define FUSE_CPU_SPEEDO_CALIB_0_WORD_COUNT                      0x1
#define FUSE_CPU_SPEEDO_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_CPU_SPEEDO_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0xfff)
#define FUSE_CPU_SPEEDO_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_CPU_SPEEDO_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_CPU_SPEEDO_CALIB_0_READ_MASK                       _MK_MASK_CONST(0xfff)
#define FUSE_CPU_SPEEDO_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0xfff)
#define FUSE_CPU_SPEEDO_CALIB_0_CPU_SPEEDO_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_CPU_SPEEDO_CALIB_0_CPU_SPEEDO_CALIB_FIELD                  _MK_FIELD_CONST(0xfff, FUSE_CPU_SPEEDO_CALIB_0_CPU_SPEEDO_CALIB_SHIFT)
#define FUSE_CPU_SPEEDO_CALIB_0_CPU_SPEEDO_CALIB_RANGE                  11:0
#define FUSE_CPU_SPEEDO_CALIB_0_CPU_SPEEDO_CALIB_WOFFSET                        0x0
#define FUSE_CPU_SPEEDO_CALIB_0_CPU_SPEEDO_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_CPU_SPEEDO_CALIB_0_CPU_SPEEDO_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0xfff)
#define FUSE_CPU_SPEEDO_CALIB_0_CPU_SPEEDO_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_CPU_SPEEDO_CALIB_0_CPU_SPEEDO_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_CPU_SPEEDO_CALIB_0_CPU_SPEEDO_CALIB_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_CPU_SPEEDO_CALIB_0_CPU_SPEEDO_CALIB_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_CPU1_HT_IDDQ_CALIB_0
#define FUSE_CPU1_HT_IDDQ_CALIB_0                       _MK_ADDR_CONST(0x118)
#define FUSE_CPU1_HT_IDDQ_CALIB_0_SECURE                        0x0
#define FUSE_CPU1_HT_IDDQ_CALIB_0_DUAL                  0x0
#define FUSE_CPU1_HT_IDDQ_CALIB_0_SCR                   0
#define FUSE_CPU1_HT_IDDQ_CALIB_0_WORD_COUNT                    0x1
#define FUSE_CPU1_HT_IDDQ_CALIB_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_CPU1_HT_IDDQ_CALIB_0_RESET_MASK                    _MK_MASK_CONST(0xfff)
#define FUSE_CPU1_HT_IDDQ_CALIB_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_CPU1_HT_IDDQ_CALIB_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_CPU1_HT_IDDQ_CALIB_0_READ_MASK                     _MK_MASK_CONST(0xfff)
#define FUSE_CPU1_HT_IDDQ_CALIB_0_WRITE_MASK                    _MK_MASK_CONST(0xfff)
#define FUSE_CPU1_HT_IDDQ_CALIB_0_CPU1_HT_IDDQ_CALIB_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_CPU1_HT_IDDQ_CALIB_0_CPU1_HT_IDDQ_CALIB_FIELD                      _MK_FIELD_CONST(0xfff, FUSE_CPU1_HT_IDDQ_CALIB_0_CPU1_HT_IDDQ_CALIB_SHIFT)
#define FUSE_CPU1_HT_IDDQ_CALIB_0_CPU1_HT_IDDQ_CALIB_RANGE                      11:0
#define FUSE_CPU1_HT_IDDQ_CALIB_0_CPU1_HT_IDDQ_CALIB_WOFFSET                    0x0
#define FUSE_CPU1_HT_IDDQ_CALIB_0_CPU1_HT_IDDQ_CALIB_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_CPU1_HT_IDDQ_CALIB_0_CPU1_HT_IDDQ_CALIB_DEFAULT_MASK                       _MK_MASK_CONST(0xfff)
#define FUSE_CPU1_HT_IDDQ_CALIB_0_CPU1_HT_IDDQ_CALIB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_CPU1_HT_IDDQ_CALIB_0_CPU1_HT_IDDQ_CALIB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_CPU1_HT_IDDQ_CALIB_0_CPU1_HT_IDDQ_CALIB_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_CPU1_HT_IDDQ_CALIB_0_CPU1_HT_IDDQ_CALIB_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Reserved address 0x11c

// Reserved address 0x120

// Reserved address 0x124

// Register FUSE_OPT_FT_REV_0
#define FUSE_OPT_FT_REV_0                       _MK_ADDR_CONST(0x128)
#define FUSE_OPT_FT_REV_0_SECURE                        0x0
#define FUSE_OPT_FT_REV_0_DUAL                  0x0
#define FUSE_OPT_FT_REV_0_SCR                   0
#define FUSE_OPT_FT_REV_0_WORD_COUNT                    0x1
#define FUSE_OPT_FT_REV_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_FT_REV_0_RESET_MASK                    _MK_MASK_CONST(0x7ff)
#define FUSE_OPT_FT_REV_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_FT_REV_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_FT_REV_0_READ_MASK                     _MK_MASK_CONST(0x7ff)
#define FUSE_OPT_FT_REV_0_WRITE_MASK                    _MK_MASK_CONST(0x7ff)
#define FUSE_OPT_FT_REV_0_OPT_FT_REV_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_FT_REV_0_OPT_FT_REV_FIELD                      _MK_FIELD_CONST(0x7ff, FUSE_OPT_FT_REV_0_OPT_FT_REV_SHIFT)
#define FUSE_OPT_FT_REV_0_OPT_FT_REV_RANGE                      10:0
#define FUSE_OPT_FT_REV_0_OPT_FT_REV_WOFFSET                    0x0
#define FUSE_OPT_FT_REV_0_OPT_FT_REV_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_FT_REV_0_OPT_FT_REV_DEFAULT_MASK                       _MK_MASK_CONST(0x7ff)
#define FUSE_OPT_FT_REV_0_OPT_FT_REV_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_FT_REV_0_OPT_FT_REV_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_FT_REV_0_OPT_FT_REV_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_FT_REV_0_OPT_FT_REV_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_CV_SPEEDO_CALIB_0
#define FUSE_CV_SPEEDO_CALIB_0                  _MK_ADDR_CONST(0x12c)
#define FUSE_CV_SPEEDO_CALIB_0_SECURE                   0x0
#define FUSE_CV_SPEEDO_CALIB_0_DUAL                     0x0
#define FUSE_CV_SPEEDO_CALIB_0_SCR                      0
#define FUSE_CV_SPEEDO_CALIB_0_WORD_COUNT                       0x1
#define FUSE_CV_SPEEDO_CALIB_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_CV_SPEEDO_CALIB_0_RESET_MASK                       _MK_MASK_CONST(0xfff)
#define FUSE_CV_SPEEDO_CALIB_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_CV_SPEEDO_CALIB_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_CV_SPEEDO_CALIB_0_READ_MASK                        _MK_MASK_CONST(0xfff)
#define FUSE_CV_SPEEDO_CALIB_0_WRITE_MASK                       _MK_MASK_CONST(0xfff)
#define FUSE_CV_SPEEDO_CALIB_0_CV_SPEEDO_CALIB_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_CV_SPEEDO_CALIB_0_CV_SPEEDO_CALIB_FIELD                    _MK_FIELD_CONST(0xfff, FUSE_CV_SPEEDO_CALIB_0_CV_SPEEDO_CALIB_SHIFT)
#define FUSE_CV_SPEEDO_CALIB_0_CV_SPEEDO_CALIB_RANGE                    11:0
#define FUSE_CV_SPEEDO_CALIB_0_CV_SPEEDO_CALIB_WOFFSET                  0x0
#define FUSE_CV_SPEEDO_CALIB_0_CV_SPEEDO_CALIB_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_CV_SPEEDO_CALIB_0_CV_SPEEDO_CALIB_DEFAULT_MASK                     _MK_MASK_CONST(0xfff)
#define FUSE_CV_SPEEDO_CALIB_0_CV_SPEEDO_CALIB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_CV_SPEEDO_CALIB_0_CV_SPEEDO_CALIB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_CV_SPEEDO_CALIB_0_CV_SPEEDO_CALIB_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_CV_SPEEDO_CALIB_0_CV_SPEEDO_CALIB_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_GPU_SPEEDO_CALIB_0
#define FUSE_GPU_SPEEDO_CALIB_0                 _MK_ADDR_CONST(0x130)
#define FUSE_GPU_SPEEDO_CALIB_0_SECURE                  0x0
#define FUSE_GPU_SPEEDO_CALIB_0_DUAL                    0x0
#define FUSE_GPU_SPEEDO_CALIB_0_SCR                     0
#define FUSE_GPU_SPEEDO_CALIB_0_WORD_COUNT                      0x1
#define FUSE_GPU_SPEEDO_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_GPU_SPEEDO_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0xfff)
#define FUSE_GPU_SPEEDO_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_GPU_SPEEDO_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_GPU_SPEEDO_CALIB_0_READ_MASK                       _MK_MASK_CONST(0xfff)
#define FUSE_GPU_SPEEDO_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0xfff)
#define FUSE_GPU_SPEEDO_CALIB_0_GPU_SPEEDO_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_GPU_SPEEDO_CALIB_0_GPU_SPEEDO_CALIB_FIELD                  _MK_FIELD_CONST(0xfff, FUSE_GPU_SPEEDO_CALIB_0_GPU_SPEEDO_CALIB_SHIFT)
#define FUSE_GPU_SPEEDO_CALIB_0_GPU_SPEEDO_CALIB_RANGE                  11:0
#define FUSE_GPU_SPEEDO_CALIB_0_GPU_SPEEDO_CALIB_WOFFSET                        0x0
#define FUSE_GPU_SPEEDO_CALIB_0_GPU_SPEEDO_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_GPU_SPEEDO_CALIB_0_GPU_SPEEDO_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0xfff)
#define FUSE_GPU_SPEEDO_CALIB_0_GPU_SPEEDO_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_GPU_SPEEDO_CALIB_0_GPU_SPEEDO_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_GPU_SPEEDO_CALIB_0_GPU_SPEEDO_CALIB_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_GPU_SPEEDO_CALIB_0_GPU_SPEEDO_CALIB_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SOC_SPEEDO_CALIB_0
#define FUSE_SOC_SPEEDO_CALIB_0                 _MK_ADDR_CONST(0x134)
#define FUSE_SOC_SPEEDO_CALIB_0_SECURE                  0x0
#define FUSE_SOC_SPEEDO_CALIB_0_DUAL                    0x0
#define FUSE_SOC_SPEEDO_CALIB_0_SCR                     0
#define FUSE_SOC_SPEEDO_CALIB_0_WORD_COUNT                      0x1
#define FUSE_SOC_SPEEDO_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_SOC_SPEEDO_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0xfff)
#define FUSE_SOC_SPEEDO_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_SOC_SPEEDO_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_SOC_SPEEDO_CALIB_0_READ_MASK                       _MK_MASK_CONST(0xfff)
#define FUSE_SOC_SPEEDO_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0xfff)
#define FUSE_SOC_SPEEDO_CALIB_0_SOC_SPEEDO_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SOC_SPEEDO_CALIB_0_SOC_SPEEDO_CALIB_FIELD                  _MK_FIELD_CONST(0xfff, FUSE_SOC_SPEEDO_CALIB_0_SOC_SPEEDO_CALIB_SHIFT)
#define FUSE_SOC_SPEEDO_CALIB_0_SOC_SPEEDO_CALIB_RANGE                  11:0
#define FUSE_SOC_SPEEDO_CALIB_0_SOC_SPEEDO_CALIB_WOFFSET                        0x0
#define FUSE_SOC_SPEEDO_CALIB_0_SOC_SPEEDO_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SOC_SPEEDO_CALIB_0_SOC_SPEEDO_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0xfff)
#define FUSE_SOC_SPEEDO_CALIB_0_SOC_SPEEDO_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SOC_SPEEDO_CALIB_0_SOC_SPEEDO_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SOC_SPEEDO_CALIB_0_SOC_SPEEDO_CALIB_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SOC_SPEEDO_CALIB_0_SOC_SPEEDO_CALIB_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_RESERVED_0_SPEEDO_CALIB_0
#define FUSE_RESERVED_0_SPEEDO_CALIB_0                  _MK_ADDR_CONST(0x138)
#define FUSE_RESERVED_0_SPEEDO_CALIB_0_SECURE                   0x0
#define FUSE_RESERVED_0_SPEEDO_CALIB_0_DUAL                     0x0
#define FUSE_RESERVED_0_SPEEDO_CALIB_0_SCR                      0
#define FUSE_RESERVED_0_SPEEDO_CALIB_0_WORD_COUNT                       0x1
#define FUSE_RESERVED_0_SPEEDO_CALIB_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_0_SPEEDO_CALIB_0_RESET_MASK                       _MK_MASK_CONST(0xfff)
#define FUSE_RESERVED_0_SPEEDO_CALIB_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_0_SPEEDO_CALIB_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_0_SPEEDO_CALIB_0_READ_MASK                        _MK_MASK_CONST(0xfff)
#define FUSE_RESERVED_0_SPEEDO_CALIB_0_WRITE_MASK                       _MK_MASK_CONST(0xfff)
#define FUSE_RESERVED_0_SPEEDO_CALIB_0_RESERVED_0_SPEEDO_CALIB_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_RESERVED_0_SPEEDO_CALIB_0_RESERVED_0_SPEEDO_CALIB_FIELD                    _MK_FIELD_CONST(0xfff, FUSE_RESERVED_0_SPEEDO_CALIB_0_RESERVED_0_SPEEDO_CALIB_SHIFT)
#define FUSE_RESERVED_0_SPEEDO_CALIB_0_RESERVED_0_SPEEDO_CALIB_RANGE                    11:0
#define FUSE_RESERVED_0_SPEEDO_CALIB_0_RESERVED_0_SPEEDO_CALIB_WOFFSET                  0x0
#define FUSE_RESERVED_0_SPEEDO_CALIB_0_RESERVED_0_SPEEDO_CALIB_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_0_SPEEDO_CALIB_0_RESERVED_0_SPEEDO_CALIB_DEFAULT_MASK                     _MK_MASK_CONST(0xfff)
#define FUSE_RESERVED_0_SPEEDO_CALIB_0_RESERVED_0_SPEEDO_CALIB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_0_SPEEDO_CALIB_0_RESERVED_0_SPEEDO_CALIB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_0_SPEEDO_CALIB_0_RESERVED_0_SPEEDO_CALIB_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_0_SPEEDO_CALIB_0_RESERVED_0_SPEEDO_CALIB_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_RESERVED_1_SPEEDO_CALIB_0
#define FUSE_RESERVED_1_SPEEDO_CALIB_0                  _MK_ADDR_CONST(0x13c)
#define FUSE_RESERVED_1_SPEEDO_CALIB_0_SECURE                   0x0
#define FUSE_RESERVED_1_SPEEDO_CALIB_0_DUAL                     0x0
#define FUSE_RESERVED_1_SPEEDO_CALIB_0_SCR                      0
#define FUSE_RESERVED_1_SPEEDO_CALIB_0_WORD_COUNT                       0x1
#define FUSE_RESERVED_1_SPEEDO_CALIB_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_1_SPEEDO_CALIB_0_RESET_MASK                       _MK_MASK_CONST(0xfff)
#define FUSE_RESERVED_1_SPEEDO_CALIB_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_1_SPEEDO_CALIB_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_1_SPEEDO_CALIB_0_READ_MASK                        _MK_MASK_CONST(0xfff)
#define FUSE_RESERVED_1_SPEEDO_CALIB_0_WRITE_MASK                       _MK_MASK_CONST(0xfff)
#define FUSE_RESERVED_1_SPEEDO_CALIB_0_RESERVED_1_SPEEDO_CALIB_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_RESERVED_1_SPEEDO_CALIB_0_RESERVED_1_SPEEDO_CALIB_FIELD                    _MK_FIELD_CONST(0xfff, FUSE_RESERVED_1_SPEEDO_CALIB_0_RESERVED_1_SPEEDO_CALIB_SHIFT)
#define FUSE_RESERVED_1_SPEEDO_CALIB_0_RESERVED_1_SPEEDO_CALIB_RANGE                    11:0
#define FUSE_RESERVED_1_SPEEDO_CALIB_0_RESERVED_1_SPEEDO_CALIB_WOFFSET                  0x0
#define FUSE_RESERVED_1_SPEEDO_CALIB_0_RESERVED_1_SPEEDO_CALIB_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_1_SPEEDO_CALIB_0_RESERVED_1_SPEEDO_CALIB_DEFAULT_MASK                     _MK_MASK_CONST(0xfff)
#define FUSE_RESERVED_1_SPEEDO_CALIB_0_RESERVED_1_SPEEDO_CALIB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_1_SPEEDO_CALIB_0_RESERVED_1_SPEEDO_CALIB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_1_SPEEDO_CALIB_0_RESERVED_1_SPEEDO_CALIB_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_1_SPEEDO_CALIB_0_RESERVED_1_SPEEDO_CALIB_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_SOC_HT_IDDQ_CALIB_0
#define FUSE_SOC_HT_IDDQ_CALIB_0                        _MK_ADDR_CONST(0x140)
#define FUSE_SOC_HT_IDDQ_CALIB_0_SECURE                         0x0
#define FUSE_SOC_HT_IDDQ_CALIB_0_DUAL                   0x0
#define FUSE_SOC_HT_IDDQ_CALIB_0_SCR                    0
#define FUSE_SOC_HT_IDDQ_CALIB_0_WORD_COUNT                     0x1
#define FUSE_SOC_HT_IDDQ_CALIB_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SOC_HT_IDDQ_CALIB_0_RESET_MASK                     _MK_MASK_CONST(0xfff)
#define FUSE_SOC_HT_IDDQ_CALIB_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_SOC_HT_IDDQ_CALIB_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SOC_HT_IDDQ_CALIB_0_READ_MASK                      _MK_MASK_CONST(0xfff)
#define FUSE_SOC_HT_IDDQ_CALIB_0_WRITE_MASK                     _MK_MASK_CONST(0xfff)
#define FUSE_SOC_HT_IDDQ_CALIB_0_SOC_HT_IDDQ_CALIB_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_SOC_HT_IDDQ_CALIB_0_SOC_HT_IDDQ_CALIB_FIELD                        _MK_FIELD_CONST(0xfff, FUSE_SOC_HT_IDDQ_CALIB_0_SOC_HT_IDDQ_CALIB_SHIFT)
#define FUSE_SOC_HT_IDDQ_CALIB_0_SOC_HT_IDDQ_CALIB_RANGE                        11:0
#define FUSE_SOC_HT_IDDQ_CALIB_0_SOC_HT_IDDQ_CALIB_WOFFSET                      0x0
#define FUSE_SOC_HT_IDDQ_CALIB_0_SOC_HT_IDDQ_CALIB_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_SOC_HT_IDDQ_CALIB_0_SOC_HT_IDDQ_CALIB_DEFAULT_MASK                 _MK_MASK_CONST(0xfff)
#define FUSE_SOC_HT_IDDQ_CALIB_0_SOC_HT_IDDQ_CALIB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_SOC_HT_IDDQ_CALIB_0_SOC_HT_IDDQ_CALIB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_SOC_HT_IDDQ_CALIB_0_SOC_HT_IDDQ_CALIB_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_SOC_HT_IDDQ_CALIB_0_SOC_HT_IDDQ_CALIB_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Reserved address 0x144

// Register FUSE_RESERVED_PRODUCTION_0
#define FUSE_RESERVED_PRODUCTION_0                      _MK_ADDR_CONST(0x14c)
#define FUSE_RESERVED_PRODUCTION_0_SECURE                       0x0
#define FUSE_RESERVED_PRODUCTION_0_DUAL                         0x0
#define FUSE_RESERVED_PRODUCTION_0_SCR                  0
#define FUSE_RESERVED_PRODUCTION_0_WORD_COUNT                   0x1
#define FUSE_RESERVED_PRODUCTION_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_PRODUCTION_0_RESET_MASK                   _MK_MASK_CONST(0x3ff)
#define FUSE_RESERVED_PRODUCTION_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_PRODUCTION_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_PRODUCTION_0_READ_MASK                    _MK_MASK_CONST(0x3ff)
#define FUSE_RESERVED_PRODUCTION_0_WRITE_MASK                   _MK_MASK_CONST(0x3ff)
#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_FIELD                    _MK_FIELD_CONST(0x3ff, FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_SHIFT)
#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_RANGE                    9:0
#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_WOFFSET                  0x0
#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_DEFAULT_MASK                     _MK_MASK_CONST(0x3ff)
#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_HDMI_LANE0_CALIB_0
#define FUSE_HDMI_LANE0_CALIB_0                 _MK_ADDR_CONST(0x150)
#define FUSE_HDMI_LANE0_CALIB_0_SECURE                  0x0
#define FUSE_HDMI_LANE0_CALIB_0_DUAL                    0x0
#define FUSE_HDMI_LANE0_CALIB_0_SCR                     0
#define FUSE_HDMI_LANE0_CALIB_0_WORD_COUNT                      0x1
#define FUSE_HDMI_LANE0_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE0_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define FUSE_HDMI_LANE0_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE0_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE0_CALIB_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define FUSE_HDMI_LANE0_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_FIELD                  _MK_FIELD_CONST(0xff, FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_SHIFT)
#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_RANGE                  7:0
#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_WOFFSET                        0x0
#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_HDMI_LANE1_CALIB_0
#define FUSE_HDMI_LANE1_CALIB_0                 _MK_ADDR_CONST(0x154)
#define FUSE_HDMI_LANE1_CALIB_0_SECURE                  0x0
#define FUSE_HDMI_LANE1_CALIB_0_DUAL                    0x0
#define FUSE_HDMI_LANE1_CALIB_0_SCR                     0
#define FUSE_HDMI_LANE1_CALIB_0_WORD_COUNT                      0x1
#define FUSE_HDMI_LANE1_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE1_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define FUSE_HDMI_LANE1_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE1_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE1_CALIB_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define FUSE_HDMI_LANE1_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_FIELD                  _MK_FIELD_CONST(0xff, FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_SHIFT)
#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_RANGE                  7:0
#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_WOFFSET                        0x0
#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_HDMI_LANE2_CALIB_0
#define FUSE_HDMI_LANE2_CALIB_0                 _MK_ADDR_CONST(0x158)
#define FUSE_HDMI_LANE2_CALIB_0_SECURE                  0x0
#define FUSE_HDMI_LANE2_CALIB_0_DUAL                    0x0
#define FUSE_HDMI_LANE2_CALIB_0_SCR                     0
#define FUSE_HDMI_LANE2_CALIB_0_WORD_COUNT                      0x1
#define FUSE_HDMI_LANE2_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE2_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define FUSE_HDMI_LANE2_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE2_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE2_CALIB_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define FUSE_HDMI_LANE2_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_FIELD                  _MK_FIELD_CONST(0xff, FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_SHIFT)
#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_RANGE                  7:0
#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_WOFFSET                        0x0
#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_HDMI_LANE3_CALIB_0
#define FUSE_HDMI_LANE3_CALIB_0                 _MK_ADDR_CONST(0x15c)
#define FUSE_HDMI_LANE3_CALIB_0_SECURE                  0x0
#define FUSE_HDMI_LANE3_CALIB_0_DUAL                    0x0
#define FUSE_HDMI_LANE3_CALIB_0_SCR                     0
#define FUSE_HDMI_LANE3_CALIB_0_WORD_COUNT                      0x1
#define FUSE_HDMI_LANE3_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE3_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define FUSE_HDMI_LANE3_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE3_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE3_CALIB_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define FUSE_HDMI_LANE3_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_FIELD                  _MK_FIELD_CONST(0xff, FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_SHIFT)
#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_RANGE                  7:0
#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_WOFFSET                        0x0
#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Reserved address 0x160

// Register FUSE_PUBLIC_KEY0_0
#define FUSE_PUBLIC_KEY0_0                      _MK_ADDR_CONST(0x164)
#define FUSE_PUBLIC_KEY0_0_SECURE                       0x0
#define FUSE_PUBLIC_KEY0_0_DUAL                         0x0
#define FUSE_PUBLIC_KEY0_0_SCR                  0
#define FUSE_PUBLIC_KEY0_0_WORD_COUNT                   0x1
#define FUSE_PUBLIC_KEY0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY0_0_PUBLIC_KEY0_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_PUBLIC_KEY0_0_PUBLIC_KEY0_FIELD                    _MK_FIELD_CONST(0xffffffff, FUSE_PUBLIC_KEY0_0_PUBLIC_KEY0_SHIFT)
#define FUSE_PUBLIC_KEY0_0_PUBLIC_KEY0_RANGE                    31:0
#define FUSE_PUBLIC_KEY0_0_PUBLIC_KEY0_WOFFSET                  0x0
#define FUSE_PUBLIC_KEY0_0_PUBLIC_KEY0_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY0_0_PUBLIC_KEY0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY0_0_PUBLIC_KEY0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY0_0_PUBLIC_KEY0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY0_0_PUBLIC_KEY0_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY0_0_PUBLIC_KEY0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_PUBLIC_KEY1_0
#define FUSE_PUBLIC_KEY1_0                      _MK_ADDR_CONST(0x168)
#define FUSE_PUBLIC_KEY1_0_SECURE                       0x0
#define FUSE_PUBLIC_KEY1_0_DUAL                         0x0
#define FUSE_PUBLIC_KEY1_0_SCR                  0
#define FUSE_PUBLIC_KEY1_0_WORD_COUNT                   0x1
#define FUSE_PUBLIC_KEY1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY1_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY1_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY1_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY1_0_PUBLIC_KEY1_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_PUBLIC_KEY1_0_PUBLIC_KEY1_FIELD                    _MK_FIELD_CONST(0xffffffff, FUSE_PUBLIC_KEY1_0_PUBLIC_KEY1_SHIFT)
#define FUSE_PUBLIC_KEY1_0_PUBLIC_KEY1_RANGE                    31:0
#define FUSE_PUBLIC_KEY1_0_PUBLIC_KEY1_WOFFSET                  0x0
#define FUSE_PUBLIC_KEY1_0_PUBLIC_KEY1_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY1_0_PUBLIC_KEY1_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY1_0_PUBLIC_KEY1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY1_0_PUBLIC_KEY1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY1_0_PUBLIC_KEY1_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY1_0_PUBLIC_KEY1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_PUBLIC_KEY2_0
#define FUSE_PUBLIC_KEY2_0                      _MK_ADDR_CONST(0x16c)
#define FUSE_PUBLIC_KEY2_0_SECURE                       0x0
#define FUSE_PUBLIC_KEY2_0_DUAL                         0x0
#define FUSE_PUBLIC_KEY2_0_SCR                  0
#define FUSE_PUBLIC_KEY2_0_WORD_COUNT                   0x1
#define FUSE_PUBLIC_KEY2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY2_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY2_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY2_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY2_0_PUBLIC_KEY2_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_PUBLIC_KEY2_0_PUBLIC_KEY2_FIELD                    _MK_FIELD_CONST(0xffffffff, FUSE_PUBLIC_KEY2_0_PUBLIC_KEY2_SHIFT)
#define FUSE_PUBLIC_KEY2_0_PUBLIC_KEY2_RANGE                    31:0
#define FUSE_PUBLIC_KEY2_0_PUBLIC_KEY2_WOFFSET                  0x0
#define FUSE_PUBLIC_KEY2_0_PUBLIC_KEY2_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY2_0_PUBLIC_KEY2_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY2_0_PUBLIC_KEY2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY2_0_PUBLIC_KEY2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY2_0_PUBLIC_KEY2_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY2_0_PUBLIC_KEY2_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_PUBLIC_KEY3_0
#define FUSE_PUBLIC_KEY3_0                      _MK_ADDR_CONST(0x170)
#define FUSE_PUBLIC_KEY3_0_SECURE                       0x0
#define FUSE_PUBLIC_KEY3_0_DUAL                         0x0
#define FUSE_PUBLIC_KEY3_0_SCR                  0
#define FUSE_PUBLIC_KEY3_0_WORD_COUNT                   0x1
#define FUSE_PUBLIC_KEY3_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY3_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY3_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY3_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY3_0_PUBLIC_KEY3_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_PUBLIC_KEY3_0_PUBLIC_KEY3_FIELD                    _MK_FIELD_CONST(0xffffffff, FUSE_PUBLIC_KEY3_0_PUBLIC_KEY3_SHIFT)
#define FUSE_PUBLIC_KEY3_0_PUBLIC_KEY3_RANGE                    31:0
#define FUSE_PUBLIC_KEY3_0_PUBLIC_KEY3_WOFFSET                  0x0
#define FUSE_PUBLIC_KEY3_0_PUBLIC_KEY3_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY3_0_PUBLIC_KEY3_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY3_0_PUBLIC_KEY3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY3_0_PUBLIC_KEY3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY3_0_PUBLIC_KEY3_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY3_0_PUBLIC_KEY3_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_PUBLIC_KEY4_0
#define FUSE_PUBLIC_KEY4_0                      _MK_ADDR_CONST(0x174)
#define FUSE_PUBLIC_KEY4_0_SECURE                       0x0
#define FUSE_PUBLIC_KEY4_0_DUAL                         0x0
#define FUSE_PUBLIC_KEY4_0_SCR                  0
#define FUSE_PUBLIC_KEY4_0_WORD_COUNT                   0x1
#define FUSE_PUBLIC_KEY4_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY4_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY4_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY4_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY4_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY4_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY4_0_PUBLIC_KEY4_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_PUBLIC_KEY4_0_PUBLIC_KEY4_FIELD                    _MK_FIELD_CONST(0xffffffff, FUSE_PUBLIC_KEY4_0_PUBLIC_KEY4_SHIFT)
#define FUSE_PUBLIC_KEY4_0_PUBLIC_KEY4_RANGE                    31:0
#define FUSE_PUBLIC_KEY4_0_PUBLIC_KEY4_WOFFSET                  0x0
#define FUSE_PUBLIC_KEY4_0_PUBLIC_KEY4_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY4_0_PUBLIC_KEY4_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY4_0_PUBLIC_KEY4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY4_0_PUBLIC_KEY4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY4_0_PUBLIC_KEY4_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY4_0_PUBLIC_KEY4_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_PUBLIC_KEY5_0
#define FUSE_PUBLIC_KEY5_0                      _MK_ADDR_CONST(0x178)
#define FUSE_PUBLIC_KEY5_0_SECURE                       0x0
#define FUSE_PUBLIC_KEY5_0_DUAL                         0x0
#define FUSE_PUBLIC_KEY5_0_SCR                  0
#define FUSE_PUBLIC_KEY5_0_WORD_COUNT                   0x1
#define FUSE_PUBLIC_KEY5_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY5_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY5_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY5_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY5_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY5_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY5_0_PUBLIC_KEY5_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_PUBLIC_KEY5_0_PUBLIC_KEY5_FIELD                    _MK_FIELD_CONST(0xffffffff, FUSE_PUBLIC_KEY5_0_PUBLIC_KEY5_SHIFT)
#define FUSE_PUBLIC_KEY5_0_PUBLIC_KEY5_RANGE                    31:0
#define FUSE_PUBLIC_KEY5_0_PUBLIC_KEY5_WOFFSET                  0x0
#define FUSE_PUBLIC_KEY5_0_PUBLIC_KEY5_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY5_0_PUBLIC_KEY5_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY5_0_PUBLIC_KEY5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY5_0_PUBLIC_KEY5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY5_0_PUBLIC_KEY5_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY5_0_PUBLIC_KEY5_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_PUBLIC_KEY6_0
#define FUSE_PUBLIC_KEY6_0                      _MK_ADDR_CONST(0x17c)
#define FUSE_PUBLIC_KEY6_0_SECURE                       0x0
#define FUSE_PUBLIC_KEY6_0_DUAL                         0x0
#define FUSE_PUBLIC_KEY6_0_SCR                  0
#define FUSE_PUBLIC_KEY6_0_WORD_COUNT                   0x1
#define FUSE_PUBLIC_KEY6_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY6_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY6_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY6_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY6_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY6_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY6_0_PUBLIC_KEY6_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_PUBLIC_KEY6_0_PUBLIC_KEY6_FIELD                    _MK_FIELD_CONST(0xffffffff, FUSE_PUBLIC_KEY6_0_PUBLIC_KEY6_SHIFT)
#define FUSE_PUBLIC_KEY6_0_PUBLIC_KEY6_RANGE                    31:0
#define FUSE_PUBLIC_KEY6_0_PUBLIC_KEY6_WOFFSET                  0x0
#define FUSE_PUBLIC_KEY6_0_PUBLIC_KEY6_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY6_0_PUBLIC_KEY6_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY6_0_PUBLIC_KEY6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY6_0_PUBLIC_KEY6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY6_0_PUBLIC_KEY6_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY6_0_PUBLIC_KEY6_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_PUBLIC_KEY7_0
#define FUSE_PUBLIC_KEY7_0                      _MK_ADDR_CONST(0x180)
#define FUSE_PUBLIC_KEY7_0_SECURE                       0x0
#define FUSE_PUBLIC_KEY7_0_DUAL                         0x0
#define FUSE_PUBLIC_KEY7_0_SCR                  0
#define FUSE_PUBLIC_KEY7_0_WORD_COUNT                   0x1
#define FUSE_PUBLIC_KEY7_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY7_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY7_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY7_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY7_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY7_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY7_0_PUBLIC_KEY7_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_PUBLIC_KEY7_0_PUBLIC_KEY7_FIELD                    _MK_FIELD_CONST(0xffffffff, FUSE_PUBLIC_KEY7_0_PUBLIC_KEY7_SHIFT)
#define FUSE_PUBLIC_KEY7_0_PUBLIC_KEY7_RANGE                    31:0
#define FUSE_PUBLIC_KEY7_0_PUBLIC_KEY7_WOFFSET                  0x0
#define FUSE_PUBLIC_KEY7_0_PUBLIC_KEY7_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY7_0_PUBLIC_KEY7_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_PUBLIC_KEY7_0_PUBLIC_KEY7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY7_0_PUBLIC_KEY7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY7_0_PUBLIC_KEY7_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_PUBLIC_KEY7_0_PUBLIC_KEY7_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Reserved address 0x184

// Reserved address 0x188

// Reserved address 0x18c

// Register FUSE_OPT_CP_REV_0
#define FUSE_OPT_CP_REV_0                       _MK_ADDR_CONST(0x190)
#define FUSE_OPT_CP_REV_0_SECURE                        0x0
#define FUSE_OPT_CP_REV_0_DUAL                  0x0
#define FUSE_OPT_CP_REV_0_SCR                   0
#define FUSE_OPT_CP_REV_0_WORD_COUNT                    0x1
#define FUSE_OPT_CP_REV_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_CP_REV_0_RESET_MASK                    _MK_MASK_CONST(0x7ff)
#define FUSE_OPT_CP_REV_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_CP_REV_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_CP_REV_0_READ_MASK                     _MK_MASK_CONST(0x7ff)
#define FUSE_OPT_CP_REV_0_WRITE_MASK                    _MK_MASK_CONST(0x7ff)
#define FUSE_OPT_CP_REV_0_OPT_CP_REV_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_CP_REV_0_OPT_CP_REV_FIELD                      _MK_FIELD_CONST(0x7ff, FUSE_OPT_CP_REV_0_OPT_CP_REV_SHIFT)
#define FUSE_OPT_CP_REV_0_OPT_CP_REV_RANGE                      10:0
#define FUSE_OPT_CP_REV_0_OPT_CP_REV_WOFFSET                    0x0
#define FUSE_OPT_CP_REV_0_OPT_CP_REV_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_CP_REV_0_OPT_CP_REV_DEFAULT_MASK                       _MK_MASK_CONST(0x7ff)
#define FUSE_OPT_CP_REV_0_OPT_CP_REV_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_CP_REV_0_OPT_CP_REV_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_CP_REV_0_OPT_CP_REV_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_CP_REV_0_OPT_CP_REV_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_PFG_0
#define FUSE_OPT_PFG_0                  _MK_ADDR_CONST(0x194)
#define FUSE_OPT_PFG_0_SECURE                   0x0
#define FUSE_OPT_PFG_0_DUAL                     0x0
#define FUSE_OPT_PFG_0_SCR                      0
#define FUSE_OPT_PFG_0_WORD_COUNT                       0x1
#define FUSE_OPT_PFG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_PFG_0_RESET_MASK                       _MK_MASK_CONST(0x3fff)
#define FUSE_OPT_PFG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_PFG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PFG_0_READ_MASK                        _MK_MASK_CONST(0x3fff)
#define FUSE_OPT_PFG_0_WRITE_MASK                       _MK_MASK_CONST(0x3fff)
#define FUSE_OPT_PFG_0_OPT_PFG_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_PFG_0_OPT_PFG_FIELD                    _MK_FIELD_CONST(0x3fff, FUSE_OPT_PFG_0_OPT_PFG_SHIFT)
#define FUSE_OPT_PFG_0_OPT_PFG_RANGE                    13:0
#define FUSE_OPT_PFG_0_OPT_PFG_WOFFSET                  0x0
#define FUSE_OPT_PFG_0_OPT_PFG_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PFG_0_OPT_PFG_DEFAULT_MASK                     _MK_MASK_CONST(0x3fff)
#define FUSE_OPT_PFG_0_OPT_PFG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_PFG_0_OPT_PFG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PFG_0_OPT_PFG_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_PFG_0_OPT_PFG_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Reserved address 0x198

// Reserved address 0x19c

// Register FUSE_SECURITY_MODE_0
#define FUSE_SECURITY_MODE_0                    _MK_ADDR_CONST(0x1a0)
#define FUSE_SECURITY_MODE_0_SECURE                     0x0
#define FUSE_SECURITY_MODE_0_DUAL                       0x0
#define FUSE_SECURITY_MODE_0_SCR                        0
#define FUSE_SECURITY_MODE_0_WORD_COUNT                         0x1
#define FUSE_SECURITY_MODE_0_RESET_VAL                  _MK_MASK_CONST(0x1)
#define FUSE_SECURITY_MODE_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define FUSE_SECURITY_MODE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_SECURITY_MODE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_SECURITY_MODE_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SECURITY_MODE_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define FUSE_SECURITY_MODE_0_SECURITY_MODE_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_SECURITY_MODE_0_SECURITY_MODE_FIELD                        _MK_FIELD_CONST(0x1, FUSE_SECURITY_MODE_0_SECURITY_MODE_SHIFT)
#define FUSE_SECURITY_MODE_0_SECURITY_MODE_RANGE                        0:0
#define FUSE_SECURITY_MODE_0_SECURITY_MODE_WOFFSET                      0x0
#define FUSE_SECURITY_MODE_0_SECURITY_MODE_DEFAULT                      _MK_MASK_CONST(0x1)
#define FUSE_SECURITY_MODE_0_SECURITY_MODE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define FUSE_SECURITY_MODE_0_SECURITY_MODE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_SECURITY_MODE_0_SECURITY_MODE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_SECURITY_MODE_0_SECURITY_MODE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_SECURITY_MODE_0_SECURITY_MODE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_PRIVATE_KEY0_0
#define FUSE_PRIVATE_KEY0_0                     _MK_ADDR_CONST(0x1a4)
#define FUSE_PRIVATE_KEY0_0_SECURE                      0x0
#define FUSE_PRIVATE_KEY0_0_DUAL                        0x0
#define FUSE_PRIVATE_KEY0_0_SCR                         0
#define FUSE_PRIVATE_KEY0_0_WORD_COUNT                  0x1
#define FUSE_PRIVATE_KEY0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_PRIVATE_KEY0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PRIVATE_KEY0_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_FIELD                  _MK_FIELD_CONST(0xffffffff, FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_SHIFT)
#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_RANGE                  31:0
#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_WOFFSET                        0x0
#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_PRIVATE_KEY1_0
#define FUSE_PRIVATE_KEY1_0                     _MK_ADDR_CONST(0x1a8)
#define FUSE_PRIVATE_KEY1_0_SECURE                      0x0
#define FUSE_PRIVATE_KEY1_0_DUAL                        0x0
#define FUSE_PRIVATE_KEY1_0_SCR                         0
#define FUSE_PRIVATE_KEY1_0_WORD_COUNT                  0x1
#define FUSE_PRIVATE_KEY1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_PRIVATE_KEY1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PRIVATE_KEY1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_FIELD                  _MK_FIELD_CONST(0xffffffff, FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_SHIFT)
#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_RANGE                  31:0
#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_WOFFSET                        0x0
#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_PRIVATE_KEY2_0
#define FUSE_PRIVATE_KEY2_0                     _MK_ADDR_CONST(0x1ac)
#define FUSE_PRIVATE_KEY2_0_SECURE                      0x0
#define FUSE_PRIVATE_KEY2_0_DUAL                        0x0
#define FUSE_PRIVATE_KEY2_0_SCR                         0
#define FUSE_PRIVATE_KEY2_0_WORD_COUNT                  0x1
#define FUSE_PRIVATE_KEY2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_PRIVATE_KEY2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PRIVATE_KEY2_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_FIELD                  _MK_FIELD_CONST(0xffffffff, FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_SHIFT)
#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_RANGE                  31:0
#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_WOFFSET                        0x0
#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_PRIVATE_KEY3_0
#define FUSE_PRIVATE_KEY3_0                     _MK_ADDR_CONST(0x1b0)
#define FUSE_PRIVATE_KEY3_0_SECURE                      0x0
#define FUSE_PRIVATE_KEY3_0_DUAL                        0x0
#define FUSE_PRIVATE_KEY3_0_SCR                         0
#define FUSE_PRIVATE_KEY3_0_WORD_COUNT                  0x1
#define FUSE_PRIVATE_KEY3_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_PRIVATE_KEY3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PRIVATE_KEY3_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_FIELD                  _MK_FIELD_CONST(0xffffffff, FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_SHIFT)
#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_RANGE                  31:0
#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_WOFFSET                        0x0
#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Reserved address 0x1b4

// Register FUSE_ARM_JTAG_DIS_0
#define FUSE_ARM_JTAG_DIS_0                     _MK_ADDR_CONST(0x1b8)
#define FUSE_ARM_JTAG_DIS_0_SECURE                      0x0
#define FUSE_ARM_JTAG_DIS_0_DUAL                        0x0
#define FUSE_ARM_JTAG_DIS_0_SCR                         0
#define FUSE_ARM_JTAG_DIS_0_WORD_COUNT                  0x1
#define FUSE_ARM_JTAG_DIS_0_RESET_VAL                   _MK_MASK_CONST(0x1)
#define FUSE_ARM_JTAG_DIS_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_ARM_JTAG_DIS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_ARM_JTAG_DIS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_ARM_JTAG_DIS_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_ARM_JTAG_DIS_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_FIELD                  _MK_FIELD_CONST(0x1, FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_SHIFT)
#define FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_RANGE                  0:0
#define FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_WOFFSET                        0x0
#define FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_DEFAULT                        _MK_MASK_CONST(0x1)
#define FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_BOOT_DEVICE_INFO_0
#define FUSE_BOOT_DEVICE_INFO_0                 _MK_ADDR_CONST(0x1bc)
#define FUSE_BOOT_DEVICE_INFO_0_SECURE                  0x0
#define FUSE_BOOT_DEVICE_INFO_0_DUAL                    0x0
#define FUSE_BOOT_DEVICE_INFO_0_SCR                     0
#define FUSE_BOOT_DEVICE_INFO_0_WORD_COUNT                      0x1
#define FUSE_BOOT_DEVICE_INFO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_BOOT_DEVICE_INFO_0_RESET_MASK                      _MK_MASK_CONST(0xffffff)
#define FUSE_BOOT_DEVICE_INFO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_BOOT_DEVICE_INFO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_BOOT_DEVICE_INFO_0_READ_MASK                       _MK_MASK_CONST(0xffffff)
#define FUSE_BOOT_DEVICE_INFO_0_WRITE_MASK                      _MK_MASK_CONST(0xffffff)
#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_FIELD                  _MK_FIELD_CONST(0xffffff, FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_SHIFT)
#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_RANGE                  23:0
#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_WOFFSET                        0x0
#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_DEFAULT_MASK                   _MK_MASK_CONST(0xffffff)
#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_RESERVED_SW_0
#define FUSE_RESERVED_SW_0                      _MK_ADDR_CONST(0x1c0)
#define FUSE_RESERVED_SW_0_SECURE                       0x0
#define FUSE_RESERVED_SW_0_DUAL                         0x0
#define FUSE_RESERVED_SW_0_SCR                  0
#define FUSE_RESERVED_SW_0_WORD_COUNT                   0x1
#define FUSE_RESERVED_SW_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_SW_0_RESET_MASK                   _MK_MASK_CONST(0xffffff)
#define FUSE_RESERVED_SW_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_SW_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_SW_0_READ_MASK                    _MK_MASK_CONST(0xffffff)
#define FUSE_RESERVED_SW_0_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
#define FUSE_RESERVED_SW_0_RESERVED_SW_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_RESERVED_SW_0_RESERVED_SW_FIELD                    _MK_FIELD_CONST(0xffffff, FUSE_RESERVED_SW_0_RESERVED_SW_SHIFT)
#define FUSE_RESERVED_SW_0_RESERVED_SW_RANGE                    23:0
#define FUSE_RESERVED_SW_0_RESERVED_SW_WOFFSET                  0x0
#define FUSE_RESERVED_SW_0_RESERVED_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_SW_0_RESERVED_SW_DEFAULT_MASK                     _MK_MASK_CONST(0xffffff)
#define FUSE_RESERVED_SW_0_RESERVED_SW_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_SW_0_RESERVED_SW_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_SW_0_RESERVED_SW_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_SW_0_RESERVED_SW_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_VP9_DISABLE_0
#define FUSE_OPT_VP9_DISABLE_0                  _MK_ADDR_CONST(0x1c4)
#define FUSE_OPT_VP9_DISABLE_0_SECURE                   0x0
#define FUSE_OPT_VP9_DISABLE_0_DUAL                     0x0
#define FUSE_OPT_VP9_DISABLE_0_SCR                      0
#define FUSE_OPT_VP9_DISABLE_0_WORD_COUNT                       0x1
#define FUSE_OPT_VP9_DISABLE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_VP9_DISABLE_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_OPT_VP9_DISABLE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_VP9_DISABLE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_VP9_DISABLE_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_OPT_VP9_DISABLE_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_OPT_VP9_DISABLE_0_OPT_VP9_DISABLE_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_VP9_DISABLE_0_OPT_VP9_DISABLE_FIELD                    _MK_FIELD_CONST(0x1, FUSE_OPT_VP9_DISABLE_0_OPT_VP9_DISABLE_SHIFT)
#define FUSE_OPT_VP9_DISABLE_0_OPT_VP9_DISABLE_RANGE                    0:0
#define FUSE_OPT_VP9_DISABLE_0_OPT_VP9_DISABLE_WOFFSET                  0x0
#define FUSE_OPT_VP9_DISABLE_0_OPT_VP9_DISABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_VP9_DISABLE_0_OPT_VP9_DISABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_OPT_VP9_DISABLE_0_OPT_VP9_DISABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_VP9_DISABLE_0_OPT_VP9_DISABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_VP9_DISABLE_0_OPT_VP9_DISABLE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_VP9_DISABLE_0_OPT_VP9_DISABLE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_RESERVED_ODM0_0
#define FUSE_RESERVED_ODM0_0                    _MK_ADDR_CONST(0x1c8)
#define FUSE_RESERVED_ODM0_0_SECURE                     0x0
#define FUSE_RESERVED_ODM0_0_DUAL                       0x0
#define FUSE_RESERVED_ODM0_0_SCR                        0
#define FUSE_RESERVED_ODM0_0_WORD_COUNT                         0x1
#define FUSE_RESERVED_ODM0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM0_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM0_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM0_0_RESERVED_ODM0_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_RESERVED_ODM0_0_RESERVED_ODM0_FIELD                        _MK_FIELD_CONST(0xffffffff, FUSE_RESERVED_ODM0_0_RESERVED_ODM0_SHIFT)
#define FUSE_RESERVED_ODM0_0_RESERVED_ODM0_RANGE                        31:0
#define FUSE_RESERVED_ODM0_0_RESERVED_ODM0_WOFFSET                      0x0
#define FUSE_RESERVED_ODM0_0_RESERVED_ODM0_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM0_0_RESERVED_ODM0_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM0_0_RESERVED_ODM0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM0_0_RESERVED_ODM0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM0_0_RESERVED_ODM0_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM0_0_RESERVED_ODM0_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_RESERVED_ODM1_0
#define FUSE_RESERVED_ODM1_0                    _MK_ADDR_CONST(0x1cc)
#define FUSE_RESERVED_ODM1_0_SECURE                     0x0
#define FUSE_RESERVED_ODM1_0_DUAL                       0x0
#define FUSE_RESERVED_ODM1_0_SCR                        0
#define FUSE_RESERVED_ODM1_0_WORD_COUNT                         0x1
#define FUSE_RESERVED_ODM1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM1_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM1_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM1_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM1_0_RESERVED_ODM1_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_RESERVED_ODM1_0_RESERVED_ODM1_FIELD                        _MK_FIELD_CONST(0xffffffff, FUSE_RESERVED_ODM1_0_RESERVED_ODM1_SHIFT)
#define FUSE_RESERVED_ODM1_0_RESERVED_ODM1_RANGE                        31:0
#define FUSE_RESERVED_ODM1_0_RESERVED_ODM1_WOFFSET                      0x0
#define FUSE_RESERVED_ODM1_0_RESERVED_ODM1_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM1_0_RESERVED_ODM1_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM1_0_RESERVED_ODM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM1_0_RESERVED_ODM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM1_0_RESERVED_ODM1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM1_0_RESERVED_ODM1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_RESERVED_ODM2_0
#define FUSE_RESERVED_ODM2_0                    _MK_ADDR_CONST(0x1d0)
#define FUSE_RESERVED_ODM2_0_SECURE                     0x0
#define FUSE_RESERVED_ODM2_0_DUAL                       0x0
#define FUSE_RESERVED_ODM2_0_SCR                        0
#define FUSE_RESERVED_ODM2_0_WORD_COUNT                         0x1
#define FUSE_RESERVED_ODM2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM2_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM2_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM2_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM2_0_RESERVED_ODM2_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_RESERVED_ODM2_0_RESERVED_ODM2_FIELD                        _MK_FIELD_CONST(0xffffffff, FUSE_RESERVED_ODM2_0_RESERVED_ODM2_SHIFT)
#define FUSE_RESERVED_ODM2_0_RESERVED_ODM2_RANGE                        31:0
#define FUSE_RESERVED_ODM2_0_RESERVED_ODM2_WOFFSET                      0x0
#define FUSE_RESERVED_ODM2_0_RESERVED_ODM2_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM2_0_RESERVED_ODM2_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM2_0_RESERVED_ODM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM2_0_RESERVED_ODM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM2_0_RESERVED_ODM2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM2_0_RESERVED_ODM2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_RESERVED_ODM3_0
#define FUSE_RESERVED_ODM3_0                    _MK_ADDR_CONST(0x1d4)
#define FUSE_RESERVED_ODM3_0_SECURE                     0x0
#define FUSE_RESERVED_ODM3_0_DUAL                       0x0
#define FUSE_RESERVED_ODM3_0_SCR                        0
#define FUSE_RESERVED_ODM3_0_WORD_COUNT                         0x1
#define FUSE_RESERVED_ODM3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM3_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM3_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM3_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM3_0_RESERVED_ODM3_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_RESERVED_ODM3_0_RESERVED_ODM3_FIELD                        _MK_FIELD_CONST(0xffffffff, FUSE_RESERVED_ODM3_0_RESERVED_ODM3_SHIFT)
#define FUSE_RESERVED_ODM3_0_RESERVED_ODM3_RANGE                        31:0
#define FUSE_RESERVED_ODM3_0_RESERVED_ODM3_WOFFSET                      0x0
#define FUSE_RESERVED_ODM3_0_RESERVED_ODM3_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM3_0_RESERVED_ODM3_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM3_0_RESERVED_ODM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM3_0_RESERVED_ODM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM3_0_RESERVED_ODM3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM3_0_RESERVED_ODM3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_RESERVED_ODM4_0
#define FUSE_RESERVED_ODM4_0                    _MK_ADDR_CONST(0x1d8)
#define FUSE_RESERVED_ODM4_0_SECURE                     0x0
#define FUSE_RESERVED_ODM4_0_DUAL                       0x0
#define FUSE_RESERVED_ODM4_0_SCR                        0
#define FUSE_RESERVED_ODM4_0_WORD_COUNT                         0x1
#define FUSE_RESERVED_ODM4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM4_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM4_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM4_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM4_0_RESERVED_ODM4_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_RESERVED_ODM4_0_RESERVED_ODM4_FIELD                        _MK_FIELD_CONST(0xffffffff, FUSE_RESERVED_ODM4_0_RESERVED_ODM4_SHIFT)
#define FUSE_RESERVED_ODM4_0_RESERVED_ODM4_RANGE                        31:0
#define FUSE_RESERVED_ODM4_0_RESERVED_ODM4_WOFFSET                      0x0
#define FUSE_RESERVED_ODM4_0_RESERVED_ODM4_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM4_0_RESERVED_ODM4_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM4_0_RESERVED_ODM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM4_0_RESERVED_ODM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM4_0_RESERVED_ODM4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM4_0_RESERVED_ODM4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_RESERVED_ODM5_0
#define FUSE_RESERVED_ODM5_0                    _MK_ADDR_CONST(0x1dc)
#define FUSE_RESERVED_ODM5_0_SECURE                     0x0
#define FUSE_RESERVED_ODM5_0_DUAL                       0x0
#define FUSE_RESERVED_ODM5_0_SCR                        0
#define FUSE_RESERVED_ODM5_0_WORD_COUNT                         0x1
#define FUSE_RESERVED_ODM5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM5_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM5_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM5_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM5_0_RESERVED_ODM5_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_RESERVED_ODM5_0_RESERVED_ODM5_FIELD                        _MK_FIELD_CONST(0xffffffff, FUSE_RESERVED_ODM5_0_RESERVED_ODM5_SHIFT)
#define FUSE_RESERVED_ODM5_0_RESERVED_ODM5_RANGE                        31:0
#define FUSE_RESERVED_ODM5_0_RESERVED_ODM5_WOFFSET                      0x0
#define FUSE_RESERVED_ODM5_0_RESERVED_ODM5_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM5_0_RESERVED_ODM5_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM5_0_RESERVED_ODM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM5_0_RESERVED_ODM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM5_0_RESERVED_ODM5_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM5_0_RESERVED_ODM5_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_RESERVED_ODM6_0
#define FUSE_RESERVED_ODM6_0                    _MK_ADDR_CONST(0x1e0)
#define FUSE_RESERVED_ODM6_0_SECURE                     0x0
#define FUSE_RESERVED_ODM6_0_DUAL                       0x0
#define FUSE_RESERVED_ODM6_0_SCR                        0
#define FUSE_RESERVED_ODM6_0_WORD_COUNT                         0x1
#define FUSE_RESERVED_ODM6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM6_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM6_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM6_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM6_0_RESERVED_ODM6_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_RESERVED_ODM6_0_RESERVED_ODM6_FIELD                        _MK_FIELD_CONST(0xffffffff, FUSE_RESERVED_ODM6_0_RESERVED_ODM6_SHIFT)
#define FUSE_RESERVED_ODM6_0_RESERVED_ODM6_RANGE                        31:0
#define FUSE_RESERVED_ODM6_0_RESERVED_ODM6_WOFFSET                      0x0
#define FUSE_RESERVED_ODM6_0_RESERVED_ODM6_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM6_0_RESERVED_ODM6_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM6_0_RESERVED_ODM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM6_0_RESERVED_ODM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM6_0_RESERVED_ODM6_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM6_0_RESERVED_ODM6_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_RESERVED_ODM7_0
#define FUSE_RESERVED_ODM7_0                    _MK_ADDR_CONST(0x1e4)
#define FUSE_RESERVED_ODM7_0_SECURE                     0x0
#define FUSE_RESERVED_ODM7_0_DUAL                       0x0
#define FUSE_RESERVED_ODM7_0_SCR                        0
#define FUSE_RESERVED_ODM7_0_WORD_COUNT                         0x1
#define FUSE_RESERVED_ODM7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM7_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM7_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM7_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM7_0_RESERVED_ODM7_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_RESERVED_ODM7_0_RESERVED_ODM7_FIELD                        _MK_FIELD_CONST(0xffffffff, FUSE_RESERVED_ODM7_0_RESERVED_ODM7_SHIFT)
#define FUSE_RESERVED_ODM7_0_RESERVED_ODM7_RANGE                        31:0
#define FUSE_RESERVED_ODM7_0_RESERVED_ODM7_WOFFSET                      0x0
#define FUSE_RESERVED_ODM7_0_RESERVED_ODM7_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM7_0_RESERVED_ODM7_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM7_0_RESERVED_ODM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM7_0_RESERVED_ODM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM7_0_RESERVED_ODM7_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM7_0_RESERVED_ODM7_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_USB_CALIB_0
#define FUSE_USB_CALIB_0                        _MK_ADDR_CONST(0x1f0)
#define FUSE_USB_CALIB_0_SECURE                         0x0
#define FUSE_USB_CALIB_0_DUAL                   0x0
#define FUSE_USB_CALIB_0_SCR                    0
#define FUSE_USB_CALIB_0_WORD_COUNT                     0x1
#define FUSE_USB_CALIB_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_USB_CALIB_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_USB_CALIB_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_USB_CALIB_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_USB_CALIB_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define FUSE_USB_CALIB_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_USB_CALIB_0_USB_CALIB_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_USB_CALIB_0_USB_CALIB_FIELD                        _MK_FIELD_CONST(0xffffffff, FUSE_USB_CALIB_0_USB_CALIB_SHIFT)
#define FUSE_USB_CALIB_0_USB_CALIB_RANGE                        31:0
#define FUSE_USB_CALIB_0_USB_CALIB_WOFFSET                      0x0
#define FUSE_USB_CALIB_0_USB_CALIB_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_USB_CALIB_0_USB_CALIB_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define FUSE_USB_CALIB_0_USB_CALIB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_USB_CALIB_0_USB_CALIB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_USB_CALIB_0_USB_CALIB_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_USB_CALIB_0_USB_CALIB_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_SKU_DIRECT_CONFIG_0
#define FUSE_SKU_DIRECT_CONFIG_0                        _MK_ADDR_CONST(0x1f4)
#define FUSE_SKU_DIRECT_CONFIG_0_SECURE                         0x0
#define FUSE_SKU_DIRECT_CONFIG_0_DUAL                   0x0
#define FUSE_SKU_DIRECT_CONFIG_0_SCR                    0
#define FUSE_SKU_DIRECT_CONFIG_0_WORD_COUNT                     0x1
#define FUSE_SKU_DIRECT_CONFIG_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SKU_DIRECT_CONFIG_0_RESET_MASK                     _MK_MASK_CONST(0xff)
#define FUSE_SKU_DIRECT_CONFIG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_SKU_DIRECT_CONFIG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SKU_DIRECT_CONFIG_0_READ_MASK                      _MK_MASK_CONST(0xff)
#define FUSE_SKU_DIRECT_CONFIG_0_WRITE_MASK                     _MK_MASK_CONST(0xff)
#define FUSE_SKU_DIRECT_CONFIG_0_SKU_DIRECT_CONFIG_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_SKU_DIRECT_CONFIG_0_SKU_DIRECT_CONFIG_FIELD                        _MK_FIELD_CONST(0xff, FUSE_SKU_DIRECT_CONFIG_0_SKU_DIRECT_CONFIG_SHIFT)
#define FUSE_SKU_DIRECT_CONFIG_0_SKU_DIRECT_CONFIG_RANGE                        7:0
#define FUSE_SKU_DIRECT_CONFIG_0_SKU_DIRECT_CONFIG_WOFFSET                      0x0
#define FUSE_SKU_DIRECT_CONFIG_0_SKU_DIRECT_CONFIG_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_SKU_DIRECT_CONFIG_0_SKU_DIRECT_CONFIG_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define FUSE_SKU_DIRECT_CONFIG_0_SKU_DIRECT_CONFIG_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_SKU_DIRECT_CONFIG_0_SKU_DIRECT_CONFIG_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_SKU_DIRECT_CONFIG_0_SKU_DIRECT_CONFIG_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_SKU_DIRECT_CONFIG_0_SKU_DIRECT_CONFIG_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_KFUSE_PRIVKEY_CTRL_0
#define FUSE_KFUSE_PRIVKEY_CTRL_0                       _MK_ADDR_CONST(0x1f8)
#define FUSE_KFUSE_PRIVKEY_CTRL_0_SECURE                        0x0
#define FUSE_KFUSE_PRIVKEY_CTRL_0_DUAL                  0x0
#define FUSE_KFUSE_PRIVKEY_CTRL_0_SCR                   0
#define FUSE_KFUSE_PRIVKEY_CTRL_0_WORD_COUNT                    0x1
#define FUSE_KFUSE_PRIVKEY_CTRL_0_RESET_VAL                     _MK_MASK_CONST(0x3)
#define FUSE_KFUSE_PRIVKEY_CTRL_0_RESET_MASK                    _MK_MASK_CONST(0x3)
#define FUSE_KFUSE_PRIVKEY_CTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_KFUSE_PRIVKEY_CTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_KFUSE_PRIVKEY_CTRL_0_READ_MASK                     _MK_MASK_CONST(0x3)
#define FUSE_KFUSE_PRIVKEY_CTRL_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_FIELD                      _MK_FIELD_CONST(0x3, FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_SHIFT)
#define FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_RANGE                      1:0
#define FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_WOFFSET                    0x0
#define FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_DEFAULT                    _MK_MASK_CONST(0x3)
#define FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_PACKAGE_INFO_0
#define FUSE_PACKAGE_INFO_0                     _MK_ADDR_CONST(0x1fc)
#define FUSE_PACKAGE_INFO_0_SECURE                      0x0
#define FUSE_PACKAGE_INFO_0_DUAL                        0x0
#define FUSE_PACKAGE_INFO_0_SCR                         0
#define FUSE_PACKAGE_INFO_0_WORD_COUNT                  0x1
#define FUSE_PACKAGE_INFO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_PACKAGE_INFO_0_RESET_MASK                  _MK_MASK_CONST(0xf)
#define FUSE_PACKAGE_INFO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_PACKAGE_INFO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_PACKAGE_INFO_0_READ_MASK                   _MK_MASK_CONST(0xf)
#define FUSE_PACKAGE_INFO_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
#define FUSE_PACKAGE_INFO_0_PACKAGE_INFO_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_PACKAGE_INFO_0_PACKAGE_INFO_FIELD                  _MK_FIELD_CONST(0xf, FUSE_PACKAGE_INFO_0_PACKAGE_INFO_SHIFT)
#define FUSE_PACKAGE_INFO_0_PACKAGE_INFO_RANGE                  3:0
#define FUSE_PACKAGE_INFO_0_PACKAGE_INFO_WOFFSET                        0x0
#define FUSE_PACKAGE_INFO_0_PACKAGE_INFO_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_PACKAGE_INFO_0_PACKAGE_INFO_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define FUSE_PACKAGE_INFO_0_PACKAGE_INFO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_PACKAGE_INFO_0_PACKAGE_INFO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_PACKAGE_INFO_0_PACKAGE_INFO_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_PACKAGE_INFO_0_PACKAGE_INFO_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_OPT_VENDOR_CODE_0
#define FUSE_OPT_VENDOR_CODE_0                  _MK_ADDR_CONST(0x200)
#define FUSE_OPT_VENDOR_CODE_0_SECURE                   0x0
#define FUSE_OPT_VENDOR_CODE_0_DUAL                     0x0
#define FUSE_OPT_VENDOR_CODE_0_SCR                      0
#define FUSE_OPT_VENDOR_CODE_0_WORD_COUNT                       0x1
#define FUSE_OPT_VENDOR_CODE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_VENDOR_CODE_0_RESET_MASK                       _MK_MASK_CONST(0xf)
#define FUSE_OPT_VENDOR_CODE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_VENDOR_CODE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_VENDOR_CODE_0_READ_MASK                        _MK_MASK_CONST(0xf)
#define FUSE_OPT_VENDOR_CODE_0_WRITE_MASK                       _MK_MASK_CONST(0xf)
#define FUSE_OPT_VENDOR_CODE_0_OPT_VENDOR_CODE_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_VENDOR_CODE_0_OPT_VENDOR_CODE_FIELD                    _MK_FIELD_CONST(0xf, FUSE_OPT_VENDOR_CODE_0_OPT_VENDOR_CODE_SHIFT)
#define FUSE_OPT_VENDOR_CODE_0_OPT_VENDOR_CODE_RANGE                    3:0
#define FUSE_OPT_VENDOR_CODE_0_OPT_VENDOR_CODE_WOFFSET                  0x0
#define FUSE_OPT_VENDOR_CODE_0_OPT_VENDOR_CODE_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_VENDOR_CODE_0_OPT_VENDOR_CODE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define FUSE_OPT_VENDOR_CODE_0_OPT_VENDOR_CODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_VENDOR_CODE_0_OPT_VENDOR_CODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_VENDOR_CODE_0_OPT_VENDOR_CODE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_VENDOR_CODE_0_OPT_VENDOR_CODE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_FAB_CODE_0
#define FUSE_OPT_FAB_CODE_0                     _MK_ADDR_CONST(0x204)
#define FUSE_OPT_FAB_CODE_0_SECURE                      0x0
#define FUSE_OPT_FAB_CODE_0_DUAL                        0x0
#define FUSE_OPT_FAB_CODE_0_SCR                         0
#define FUSE_OPT_FAB_CODE_0_WORD_COUNT                  0x1
#define FUSE_OPT_FAB_CODE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_FAB_CODE_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define FUSE_OPT_FAB_CODE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_FAB_CODE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_FAB_CODE_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define FUSE_OPT_FAB_CODE_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define FUSE_OPT_FAB_CODE_0_OPT_FAB_CODE_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_OPT_FAB_CODE_0_OPT_FAB_CODE_FIELD                  _MK_FIELD_CONST(0x3f, FUSE_OPT_FAB_CODE_0_OPT_FAB_CODE_SHIFT)
#define FUSE_OPT_FAB_CODE_0_OPT_FAB_CODE_RANGE                  5:0
#define FUSE_OPT_FAB_CODE_0_OPT_FAB_CODE_WOFFSET                        0x0
#define FUSE_OPT_FAB_CODE_0_OPT_FAB_CODE_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_FAB_CODE_0_OPT_FAB_CODE_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
#define FUSE_OPT_FAB_CODE_0_OPT_FAB_CODE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_FAB_CODE_0_OPT_FAB_CODE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_FAB_CODE_0_OPT_FAB_CODE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_FAB_CODE_0_OPT_FAB_CODE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_OPT_LOT_CODE_0_0
#define FUSE_OPT_LOT_CODE_0_0                   _MK_ADDR_CONST(0x208)
#define FUSE_OPT_LOT_CODE_0_0_SECURE                    0x0
#define FUSE_OPT_LOT_CODE_0_0_DUAL                      0x0
#define FUSE_OPT_LOT_CODE_0_0_SCR                       0
#define FUSE_OPT_LOT_CODE_0_0_WORD_COUNT                        0x1
#define FUSE_OPT_LOT_CODE_0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_LOT_CODE_0_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_LOT_CODE_0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_LOT_CODE_0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_LOT_CODE_0_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_LOT_CODE_0_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_LOT_CODE_0_0_OPT_LOT_CODE_0_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_LOT_CODE_0_0_OPT_LOT_CODE_0_FIELD                      _MK_FIELD_CONST(0xffffffff, FUSE_OPT_LOT_CODE_0_0_OPT_LOT_CODE_0_SHIFT)
#define FUSE_OPT_LOT_CODE_0_0_OPT_LOT_CODE_0_RANGE                      31:0
#define FUSE_OPT_LOT_CODE_0_0_OPT_LOT_CODE_0_WOFFSET                    0x0
#define FUSE_OPT_LOT_CODE_0_0_OPT_LOT_CODE_0_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_LOT_CODE_0_0_OPT_LOT_CODE_0_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_LOT_CODE_0_0_OPT_LOT_CODE_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_LOT_CODE_0_0_OPT_LOT_CODE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_LOT_CODE_0_0_OPT_LOT_CODE_0_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_LOT_CODE_0_0_OPT_LOT_CODE_0_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_LOT_CODE_1_0
#define FUSE_OPT_LOT_CODE_1_0                   _MK_ADDR_CONST(0x20c)
#define FUSE_OPT_LOT_CODE_1_0_SECURE                    0x0
#define FUSE_OPT_LOT_CODE_1_0_DUAL                      0x0
#define FUSE_OPT_LOT_CODE_1_0_SCR                       0
#define FUSE_OPT_LOT_CODE_1_0_WORD_COUNT                        0x1
#define FUSE_OPT_LOT_CODE_1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_LOT_CODE_1_0_RESET_MASK                        _MK_MASK_CONST(0xfffffff)
#define FUSE_OPT_LOT_CODE_1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_LOT_CODE_1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_LOT_CODE_1_0_READ_MASK                         _MK_MASK_CONST(0xfffffff)
#define FUSE_OPT_LOT_CODE_1_0_WRITE_MASK                        _MK_MASK_CONST(0xfffffff)
#define FUSE_OPT_LOT_CODE_1_0_OPT_LOT_CODE_1_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_LOT_CODE_1_0_OPT_LOT_CODE_1_FIELD                      _MK_FIELD_CONST(0xfffffff, FUSE_OPT_LOT_CODE_1_0_OPT_LOT_CODE_1_SHIFT)
#define FUSE_OPT_LOT_CODE_1_0_OPT_LOT_CODE_1_RANGE                      27:0
#define FUSE_OPT_LOT_CODE_1_0_OPT_LOT_CODE_1_WOFFSET                    0x0
#define FUSE_OPT_LOT_CODE_1_0_OPT_LOT_CODE_1_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_LOT_CODE_1_0_OPT_LOT_CODE_1_DEFAULT_MASK                       _MK_MASK_CONST(0xfffffff)
#define FUSE_OPT_LOT_CODE_1_0_OPT_LOT_CODE_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_LOT_CODE_1_0_OPT_LOT_CODE_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_LOT_CODE_1_0_OPT_LOT_CODE_1_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_LOT_CODE_1_0_OPT_LOT_CODE_1_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_WAFER_ID_0
#define FUSE_OPT_WAFER_ID_0                     _MK_ADDR_CONST(0x210)
#define FUSE_OPT_WAFER_ID_0_SECURE                      0x0
#define FUSE_OPT_WAFER_ID_0_DUAL                        0x0
#define FUSE_OPT_WAFER_ID_0_SCR                         0
#define FUSE_OPT_WAFER_ID_0_WORD_COUNT                  0x1
#define FUSE_OPT_WAFER_ID_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_WAFER_ID_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define FUSE_OPT_WAFER_ID_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_WAFER_ID_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_WAFER_ID_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define FUSE_OPT_WAFER_ID_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define FUSE_OPT_WAFER_ID_0_OPT_WAFER_ID_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_OPT_WAFER_ID_0_OPT_WAFER_ID_FIELD                  _MK_FIELD_CONST(0x3f, FUSE_OPT_WAFER_ID_0_OPT_WAFER_ID_SHIFT)
#define FUSE_OPT_WAFER_ID_0_OPT_WAFER_ID_RANGE                  5:0
#define FUSE_OPT_WAFER_ID_0_OPT_WAFER_ID_WOFFSET                        0x0
#define FUSE_OPT_WAFER_ID_0_OPT_WAFER_ID_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_WAFER_ID_0_OPT_WAFER_ID_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
#define FUSE_OPT_WAFER_ID_0_OPT_WAFER_ID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_WAFER_ID_0_OPT_WAFER_ID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_WAFER_ID_0_OPT_WAFER_ID_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_WAFER_ID_0_OPT_WAFER_ID_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_OPT_X_COORDINATE_0
#define FUSE_OPT_X_COORDINATE_0                 _MK_ADDR_CONST(0x214)
#define FUSE_OPT_X_COORDINATE_0_SECURE                  0x0
#define FUSE_OPT_X_COORDINATE_0_DUAL                    0x0
#define FUSE_OPT_X_COORDINATE_0_SCR                     0
#define FUSE_OPT_X_COORDINATE_0_WORD_COUNT                      0x1
#define FUSE_OPT_X_COORDINATE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_X_COORDINATE_0_RESET_MASK                      _MK_MASK_CONST(0x1ff)
#define FUSE_OPT_X_COORDINATE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_X_COORDINATE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_X_COORDINATE_0_READ_MASK                       _MK_MASK_CONST(0x1ff)
#define FUSE_OPT_X_COORDINATE_0_WRITE_MASK                      _MK_MASK_CONST(0x1ff)
#define FUSE_OPT_X_COORDINATE_0_OPT_X_COORDINATE_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_OPT_X_COORDINATE_0_OPT_X_COORDINATE_FIELD                  _MK_FIELD_CONST(0x1ff, FUSE_OPT_X_COORDINATE_0_OPT_X_COORDINATE_SHIFT)
#define FUSE_OPT_X_COORDINATE_0_OPT_X_COORDINATE_RANGE                  8:0
#define FUSE_OPT_X_COORDINATE_0_OPT_X_COORDINATE_WOFFSET                        0x0
#define FUSE_OPT_X_COORDINATE_0_OPT_X_COORDINATE_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_X_COORDINATE_0_OPT_X_COORDINATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1ff)
#define FUSE_OPT_X_COORDINATE_0_OPT_X_COORDINATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_X_COORDINATE_0_OPT_X_COORDINATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_X_COORDINATE_0_OPT_X_COORDINATE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_X_COORDINATE_0_OPT_X_COORDINATE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_OPT_Y_COORDINATE_0
#define FUSE_OPT_Y_COORDINATE_0                 _MK_ADDR_CONST(0x218)
#define FUSE_OPT_Y_COORDINATE_0_SECURE                  0x0
#define FUSE_OPT_Y_COORDINATE_0_DUAL                    0x0
#define FUSE_OPT_Y_COORDINATE_0_SCR                     0
#define FUSE_OPT_Y_COORDINATE_0_WORD_COUNT                      0x1
#define FUSE_OPT_Y_COORDINATE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_Y_COORDINATE_0_RESET_MASK                      _MK_MASK_CONST(0x1ff)
#define FUSE_OPT_Y_COORDINATE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_Y_COORDINATE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_Y_COORDINATE_0_READ_MASK                       _MK_MASK_CONST(0x1ff)
#define FUSE_OPT_Y_COORDINATE_0_WRITE_MASK                      _MK_MASK_CONST(0x1ff)
#define FUSE_OPT_Y_COORDINATE_0_OPT_Y_COORDINATE_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_OPT_Y_COORDINATE_0_OPT_Y_COORDINATE_FIELD                  _MK_FIELD_CONST(0x1ff, FUSE_OPT_Y_COORDINATE_0_OPT_Y_COORDINATE_SHIFT)
#define FUSE_OPT_Y_COORDINATE_0_OPT_Y_COORDINATE_RANGE                  8:0
#define FUSE_OPT_Y_COORDINATE_0_OPT_Y_COORDINATE_WOFFSET                        0x0
#define FUSE_OPT_Y_COORDINATE_0_OPT_Y_COORDINATE_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_Y_COORDINATE_0_OPT_Y_COORDINATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1ff)
#define FUSE_OPT_Y_COORDINATE_0_OPT_Y_COORDINATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_Y_COORDINATE_0_OPT_Y_COORDINATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_Y_COORDINATE_0_OPT_Y_COORDINATE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_Y_COORDINATE_0_OPT_Y_COORDINATE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_OPT_OPS_RESERVED_0
#define FUSE_OPT_OPS_RESERVED_0                 _MK_ADDR_CONST(0x220)
#define FUSE_OPT_OPS_RESERVED_0_SECURE                  0x0
#define FUSE_OPT_OPS_RESERVED_0_DUAL                    0x0
#define FUSE_OPT_OPS_RESERVED_0_SCR                     0
#define FUSE_OPT_OPS_RESERVED_0_WORD_COUNT                      0x1
#define FUSE_OPT_OPS_RESERVED_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_OPS_RESERVED_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
#define FUSE_OPT_OPS_RESERVED_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_OPS_RESERVED_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_OPS_RESERVED_0_READ_MASK                       _MK_MASK_CONST(0x3f)
#define FUSE_OPT_OPS_RESERVED_0_WRITE_MASK                      _MK_MASK_CONST(0x3f)
#define FUSE_OPT_OPS_RESERVED_0_OPT_OPS_RESERVED_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_OPT_OPS_RESERVED_0_OPT_OPS_RESERVED_FIELD                  _MK_FIELD_CONST(0x3f, FUSE_OPT_OPS_RESERVED_0_OPT_OPS_RESERVED_SHIFT)
#define FUSE_OPT_OPS_RESERVED_0_OPT_OPS_RESERVED_RANGE                  5:0
#define FUSE_OPT_OPS_RESERVED_0_OPT_OPS_RESERVED_WOFFSET                        0x0
#define FUSE_OPT_OPS_RESERVED_0_OPT_OPS_RESERVED_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_OPS_RESERVED_0_OPT_OPS_RESERVED_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
#define FUSE_OPT_OPS_RESERVED_0_OPT_OPS_RESERVED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_OPS_RESERVED_0_OPT_OPS_RESERVED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_OPS_RESERVED_0_OPT_OPS_RESERVED_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_OPS_RESERVED_0_OPT_OPS_RESERVED_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SATA_MPHY_ODM_CALIB_0
#define FUSE_SATA_MPHY_ODM_CALIB_0                      _MK_ADDR_CONST(0x224)
#define FUSE_SATA_MPHY_ODM_CALIB_0_SECURE                       0x0
#define FUSE_SATA_MPHY_ODM_CALIB_0_DUAL                         0x0
#define FUSE_SATA_MPHY_ODM_CALIB_0_SCR                  0
#define FUSE_SATA_MPHY_ODM_CALIB_0_WORD_COUNT                   0x1
#define FUSE_SATA_MPHY_ODM_CALIB_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_SATA_MPHY_ODM_CALIB_0_RESET_MASK                   _MK_MASK_CONST(0xf)
#define FUSE_SATA_MPHY_ODM_CALIB_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_SATA_MPHY_ODM_CALIB_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_SATA_MPHY_ODM_CALIB_0_READ_MASK                    _MK_MASK_CONST(0xf)
#define FUSE_SATA_MPHY_ODM_CALIB_0_WRITE_MASK                   _MK_MASK_CONST(0xf)
#define FUSE_SATA_MPHY_ODM_CALIB_0_SATA_MPHY_ODM_CALIB_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_SATA_MPHY_ODM_CALIB_0_SATA_MPHY_ODM_CALIB_FIELD                    _MK_FIELD_CONST(0xf, FUSE_SATA_MPHY_ODM_CALIB_0_SATA_MPHY_ODM_CALIB_SHIFT)
#define FUSE_SATA_MPHY_ODM_CALIB_0_SATA_MPHY_ODM_CALIB_RANGE                    3:0
#define FUSE_SATA_MPHY_ODM_CALIB_0_SATA_MPHY_ODM_CALIB_WOFFSET                  0x0
#define FUSE_SATA_MPHY_ODM_CALIB_0_SATA_MPHY_ODM_CALIB_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_SATA_MPHY_ODM_CALIB_0_SATA_MPHY_ODM_CALIB_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define FUSE_SATA_MPHY_ODM_CALIB_0_SATA_MPHY_ODM_CALIB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_SATA_MPHY_ODM_CALIB_0_SATA_MPHY_ODM_CALIB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SATA_MPHY_ODM_CALIB_0_SATA_MPHY_ODM_CALIB_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_SATA_MPHY_ODM_CALIB_0_SATA_MPHY_ODM_CALIB_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_GPU_HT_IDDQ_CALIB_0
#define FUSE_GPU_HT_IDDQ_CALIB_0                        _MK_ADDR_CONST(0x228)
#define FUSE_GPU_HT_IDDQ_CALIB_0_SECURE                         0x0
#define FUSE_GPU_HT_IDDQ_CALIB_0_DUAL                   0x0
#define FUSE_GPU_HT_IDDQ_CALIB_0_SCR                    0
#define FUSE_GPU_HT_IDDQ_CALIB_0_WORD_COUNT                     0x1
#define FUSE_GPU_HT_IDDQ_CALIB_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_GPU_HT_IDDQ_CALIB_0_RESET_MASK                     _MK_MASK_CONST(0xfff)
#define FUSE_GPU_HT_IDDQ_CALIB_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_GPU_HT_IDDQ_CALIB_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_GPU_HT_IDDQ_CALIB_0_READ_MASK                      _MK_MASK_CONST(0xfff)
#define FUSE_GPU_HT_IDDQ_CALIB_0_WRITE_MASK                     _MK_MASK_CONST(0xfff)
#define FUSE_GPU_HT_IDDQ_CALIB_0_GPU_HT_IDDQ_CALIB_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_GPU_HT_IDDQ_CALIB_0_GPU_HT_IDDQ_CALIB_FIELD                        _MK_FIELD_CONST(0xfff, FUSE_GPU_HT_IDDQ_CALIB_0_GPU_HT_IDDQ_CALIB_SHIFT)
#define FUSE_GPU_HT_IDDQ_CALIB_0_GPU_HT_IDDQ_CALIB_RANGE                        11:0
#define FUSE_GPU_HT_IDDQ_CALIB_0_GPU_HT_IDDQ_CALIB_WOFFSET                      0x0
#define FUSE_GPU_HT_IDDQ_CALIB_0_GPU_HT_IDDQ_CALIB_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_GPU_HT_IDDQ_CALIB_0_GPU_HT_IDDQ_CALIB_DEFAULT_MASK                 _MK_MASK_CONST(0xfff)
#define FUSE_GPU_HT_IDDQ_CALIB_0_GPU_HT_IDDQ_CALIB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_GPU_HT_IDDQ_CALIB_0_GPU_HT_IDDQ_CALIB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_GPU_HT_IDDQ_CALIB_0_GPU_HT_IDDQ_CALIB_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_GPU_HT_IDDQ_CALIB_0_GPU_HT_IDDQ_CALIB_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Reserved address 0x22c

// Register FUSE_CLOCK_BONDOUT0_0
#define FUSE_CLOCK_BONDOUT0_0                   _MK_ADDR_CONST(0x230)
#define FUSE_CLOCK_BONDOUT0_0_SECURE                    0x0
#define FUSE_CLOCK_BONDOUT0_0_DUAL                      0x0
#define FUSE_CLOCK_BONDOUT0_0_SCR                       0
#define FUSE_CLOCK_BONDOUT0_0_WORD_COUNT                        0x1
#define FUSE_CLOCK_BONDOUT0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_CLOCK_BONDOUT0_0_RESET_MASK                        _MK_MASK_CONST(0x1fffffff)
#define FUSE_CLOCK_BONDOUT0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_CLOCK_BONDOUT0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_CLOCK_BONDOUT0_0_READ_MASK                         _MK_MASK_CONST(0x1fffffff)
#define FUSE_CLOCK_BONDOUT0_0_WRITE_MASK                        _MK_MASK_CONST(0x1fffffff)
#define FUSE_CLOCK_BONDOUT0_0_CLOCK_BONDOUT0_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_CLOCK_BONDOUT0_0_CLOCK_BONDOUT0_FIELD                      _MK_FIELD_CONST(0x1fffffff, FUSE_CLOCK_BONDOUT0_0_CLOCK_BONDOUT0_SHIFT)
#define FUSE_CLOCK_BONDOUT0_0_CLOCK_BONDOUT0_RANGE                      28:0
#define FUSE_CLOCK_BONDOUT0_0_CLOCK_BONDOUT0_WOFFSET                    0x0
#define FUSE_CLOCK_BONDOUT0_0_CLOCK_BONDOUT0_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_CLOCK_BONDOUT0_0_CLOCK_BONDOUT0_DEFAULT_MASK                       _MK_MASK_CONST(0x1fffffff)
#define FUSE_CLOCK_BONDOUT0_0_CLOCK_BONDOUT0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_CLOCK_BONDOUT0_0_CLOCK_BONDOUT0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_CLOCK_BONDOUT0_0_CLOCK_BONDOUT0_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_CLOCK_BONDOUT0_0_CLOCK_BONDOUT0_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_CLOCK_BONDOUT1_0
#define FUSE_CLOCK_BONDOUT1_0                   _MK_ADDR_CONST(0x234)
#define FUSE_CLOCK_BONDOUT1_0_SECURE                    0x0
#define FUSE_CLOCK_BONDOUT1_0_DUAL                      0x0
#define FUSE_CLOCK_BONDOUT1_0_SCR                       0
#define FUSE_CLOCK_BONDOUT1_0_WORD_COUNT                        0x1
#define FUSE_CLOCK_BONDOUT1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_CLOCK_BONDOUT1_0_RESET_MASK                        _MK_MASK_CONST(0x1fffffff)
#define FUSE_CLOCK_BONDOUT1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_CLOCK_BONDOUT1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_CLOCK_BONDOUT1_0_READ_MASK                         _MK_MASK_CONST(0x1fffffff)
#define FUSE_CLOCK_BONDOUT1_0_WRITE_MASK                        _MK_MASK_CONST(0x1fffffff)
#define FUSE_CLOCK_BONDOUT1_0_CLOCK_BONDOUT1_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_CLOCK_BONDOUT1_0_CLOCK_BONDOUT1_FIELD                      _MK_FIELD_CONST(0x1fffffff, FUSE_CLOCK_BONDOUT1_0_CLOCK_BONDOUT1_SHIFT)
#define FUSE_CLOCK_BONDOUT1_0_CLOCK_BONDOUT1_RANGE                      28:0
#define FUSE_CLOCK_BONDOUT1_0_CLOCK_BONDOUT1_WOFFSET                    0x0
#define FUSE_CLOCK_BONDOUT1_0_CLOCK_BONDOUT1_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_CLOCK_BONDOUT1_0_CLOCK_BONDOUT1_DEFAULT_MASK                       _MK_MASK_CONST(0x1fffffff)
#define FUSE_CLOCK_BONDOUT1_0_CLOCK_BONDOUT1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_CLOCK_BONDOUT1_0_CLOCK_BONDOUT1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_CLOCK_BONDOUT1_0_CLOCK_BONDOUT1_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_CLOCK_BONDOUT1_0_CLOCK_BONDOUT1_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Reserved address 0x238

// Reserved address 0x23c

// Reserved address 0x240

// Register FUSE_OPT_SAMPLE_TYPE_0
#define FUSE_OPT_SAMPLE_TYPE_0                  _MK_ADDR_CONST(0x244)
#define FUSE_OPT_SAMPLE_TYPE_0_SECURE                   0x0
#define FUSE_OPT_SAMPLE_TYPE_0_DUAL                     0x0
#define FUSE_OPT_SAMPLE_TYPE_0_SCR                      0
#define FUSE_OPT_SAMPLE_TYPE_0_WORD_COUNT                       0x1
#define FUSE_OPT_SAMPLE_TYPE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_SAMPLE_TYPE_0_RESET_MASK                       _MK_MASK_CONST(0x3)
#define FUSE_OPT_SAMPLE_TYPE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_SAMPLE_TYPE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_SAMPLE_TYPE_0_READ_MASK                        _MK_MASK_CONST(0x3)
#define FUSE_OPT_SAMPLE_TYPE_0_WRITE_MASK                       _MK_MASK_CONST(0x3)
#define FUSE_OPT_SAMPLE_TYPE_0_OPT_SAMPLE_TYPE_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_SAMPLE_TYPE_0_OPT_SAMPLE_TYPE_FIELD                    _MK_FIELD_CONST(0x3, FUSE_OPT_SAMPLE_TYPE_0_OPT_SAMPLE_TYPE_SHIFT)
#define FUSE_OPT_SAMPLE_TYPE_0_OPT_SAMPLE_TYPE_RANGE                    1:0
#define FUSE_OPT_SAMPLE_TYPE_0_OPT_SAMPLE_TYPE_WOFFSET                  0x0
#define FUSE_OPT_SAMPLE_TYPE_0_OPT_SAMPLE_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_SAMPLE_TYPE_0_OPT_SAMPLE_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define FUSE_OPT_SAMPLE_TYPE_0_OPT_SAMPLE_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_SAMPLE_TYPE_0_OPT_SAMPLE_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_SAMPLE_TYPE_0_OPT_SAMPLE_TYPE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_SAMPLE_TYPE_0_OPT_SAMPLE_TYPE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_SUBREVISION_0
#define FUSE_OPT_SUBREVISION_0                  _MK_ADDR_CONST(0x248)
#define FUSE_OPT_SUBREVISION_0_SECURE                   0x0
#define FUSE_OPT_SUBREVISION_0_DUAL                     0x0
#define FUSE_OPT_SUBREVISION_0_SCR                      0
#define FUSE_OPT_SUBREVISION_0_WORD_COUNT                       0x1
#define FUSE_OPT_SUBREVISION_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_SUBREVISION_0_RESET_MASK                       _MK_MASK_CONST(0xf)
#define FUSE_OPT_SUBREVISION_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_SUBREVISION_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_SUBREVISION_0_READ_MASK                        _MK_MASK_CONST(0xf)
#define FUSE_OPT_SUBREVISION_0_WRITE_MASK                       _MK_MASK_CONST(0xf)
#define FUSE_OPT_SUBREVISION_0_OPT_SUBREVISION_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_SUBREVISION_0_OPT_SUBREVISION_FIELD                    _MK_FIELD_CONST(0xf, FUSE_OPT_SUBREVISION_0_OPT_SUBREVISION_SHIFT)
#define FUSE_OPT_SUBREVISION_0_OPT_SUBREVISION_RANGE                    3:0
#define FUSE_OPT_SUBREVISION_0_OPT_SUBREVISION_WOFFSET                  0x0
#define FUSE_OPT_SUBREVISION_0_OPT_SUBREVISION_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_SUBREVISION_0_OPT_SUBREVISION_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define FUSE_OPT_SUBREVISION_0_OPT_SUBREVISION_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_SUBREVISION_0_OPT_SUBREVISION_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_SUBREVISION_0_OPT_SUBREVISION_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_SUBREVISION_0_OPT_SUBREVISION_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_SW_RESERVED_0_0
#define FUSE_OPT_SW_RESERVED_0_0                        _MK_ADDR_CONST(0x24c)
#define FUSE_OPT_SW_RESERVED_0_0_SECURE                         0x0
#define FUSE_OPT_SW_RESERVED_0_0_DUAL                   0x0
#define FUSE_OPT_SW_RESERVED_0_0_SCR                    0
#define FUSE_OPT_SW_RESERVED_0_0_WORD_COUNT                     0x1
#define FUSE_OPT_SW_RESERVED_0_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_SW_RESERVED_0_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_OPT_SW_RESERVED_0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_SW_RESERVED_0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_SW_RESERVED_0_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_OPT_SW_RESERVED_0_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_OPT_SW_RESERVED_0_0_OPT_SW_RESERVED_0_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_OPT_SW_RESERVED_0_0_OPT_SW_RESERVED_0_FIELD                        _MK_FIELD_CONST(0x1, FUSE_OPT_SW_RESERVED_0_0_OPT_SW_RESERVED_0_SHIFT)
#define FUSE_OPT_SW_RESERVED_0_0_OPT_SW_RESERVED_0_RANGE                        0:0
#define FUSE_OPT_SW_RESERVED_0_0_OPT_SW_RESERVED_0_WOFFSET                      0x0
#define FUSE_OPT_SW_RESERVED_0_0_OPT_SW_RESERVED_0_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_SW_RESERVED_0_0_OPT_SW_RESERVED_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define FUSE_OPT_SW_RESERVED_0_0_OPT_SW_RESERVED_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_SW_RESERVED_0_0_OPT_SW_RESERVED_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_SW_RESERVED_0_0_OPT_SW_RESERVED_0_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_SW_RESERVED_0_0_OPT_SW_RESERVED_0_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_OPT_SW_RESERVED_1_0
#define FUSE_OPT_SW_RESERVED_1_0                        _MK_ADDR_CONST(0x250)
#define FUSE_OPT_SW_RESERVED_1_0_SECURE                         0x0
#define FUSE_OPT_SW_RESERVED_1_0_DUAL                   0x0
#define FUSE_OPT_SW_RESERVED_1_0_SCR                    0
#define FUSE_OPT_SW_RESERVED_1_0_WORD_COUNT                     0x1
#define FUSE_OPT_SW_RESERVED_1_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_SW_RESERVED_1_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_OPT_SW_RESERVED_1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_SW_RESERVED_1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_SW_RESERVED_1_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_OPT_SW_RESERVED_1_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_OPT_SW_RESERVED_1_0_OPT_SW_RESERVED_1_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_OPT_SW_RESERVED_1_0_OPT_SW_RESERVED_1_FIELD                        _MK_FIELD_CONST(0x1, FUSE_OPT_SW_RESERVED_1_0_OPT_SW_RESERVED_1_SHIFT)
#define FUSE_OPT_SW_RESERVED_1_0_OPT_SW_RESERVED_1_RANGE                        0:0
#define FUSE_OPT_SW_RESERVED_1_0_OPT_SW_RESERVED_1_WOFFSET                      0x0
#define FUSE_OPT_SW_RESERVED_1_0_OPT_SW_RESERVED_1_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_SW_RESERVED_1_0_OPT_SW_RESERVED_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define FUSE_OPT_SW_RESERVED_1_0_OPT_SW_RESERVED_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_SW_RESERVED_1_0_OPT_SW_RESERVED_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_SW_RESERVED_1_0_OPT_SW_RESERVED_1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_SW_RESERVED_1_0_OPT_SW_RESERVED_1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_TSENSOR4_CALIB_0
#define FUSE_TSENSOR4_CALIB_0                   _MK_ADDR_CONST(0x254)
#define FUSE_TSENSOR4_CALIB_0_SECURE                    0x0
#define FUSE_TSENSOR4_CALIB_0_DUAL                      0x0
#define FUSE_TSENSOR4_CALIB_0_SCR                       0
#define FUSE_TSENSOR4_CALIB_0_WORD_COUNT                        0x1
#define FUSE_TSENSOR4_CALIB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR4_CALIB_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR4_CALIB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR4_CALIB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR4_CALIB_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR4_CALIB_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR4_CALIB_0_TSENSOR4_CALIB_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_TSENSOR4_CALIB_0_TSENSOR4_CALIB_FIELD                      _MK_FIELD_CONST(0xffffffff, FUSE_TSENSOR4_CALIB_0_TSENSOR4_CALIB_SHIFT)
#define FUSE_TSENSOR4_CALIB_0_TSENSOR4_CALIB_RANGE                      31:0
#define FUSE_TSENSOR4_CALIB_0_TSENSOR4_CALIB_WOFFSET                    0x0
#define FUSE_TSENSOR4_CALIB_0_TSENSOR4_CALIB_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR4_CALIB_0_TSENSOR4_CALIB_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR4_CALIB_0_TSENSOR4_CALIB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR4_CALIB_0_TSENSOR4_CALIB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR4_CALIB_0_TSENSOR4_CALIB_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR4_CALIB_0_TSENSOR4_CALIB_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_TSENSOR5_CALIB_0
#define FUSE_TSENSOR5_CALIB_0                   _MK_ADDR_CONST(0x258)
#define FUSE_TSENSOR5_CALIB_0_SECURE                    0x0
#define FUSE_TSENSOR5_CALIB_0_DUAL                      0x0
#define FUSE_TSENSOR5_CALIB_0_SCR                       0
#define FUSE_TSENSOR5_CALIB_0_WORD_COUNT                        0x1
#define FUSE_TSENSOR5_CALIB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR5_CALIB_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR5_CALIB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR5_CALIB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR5_CALIB_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR5_CALIB_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR5_CALIB_0_TSENSOR5_CALIB_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_TSENSOR5_CALIB_0_TSENSOR5_CALIB_FIELD                      _MK_FIELD_CONST(0xffffffff, FUSE_TSENSOR5_CALIB_0_TSENSOR5_CALIB_SHIFT)
#define FUSE_TSENSOR5_CALIB_0_TSENSOR5_CALIB_RANGE                      31:0
#define FUSE_TSENSOR5_CALIB_0_TSENSOR5_CALIB_WOFFSET                    0x0
#define FUSE_TSENSOR5_CALIB_0_TSENSOR5_CALIB_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR5_CALIB_0_TSENSOR5_CALIB_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR5_CALIB_0_TSENSOR5_CALIB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR5_CALIB_0_TSENSOR5_CALIB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR5_CALIB_0_TSENSOR5_CALIB_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR5_CALIB_0_TSENSOR5_CALIB_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_TSENSOR6_CALIB_0
#define FUSE_TSENSOR6_CALIB_0                   _MK_ADDR_CONST(0x25c)
#define FUSE_TSENSOR6_CALIB_0_SECURE                    0x0
#define FUSE_TSENSOR6_CALIB_0_DUAL                      0x0
#define FUSE_TSENSOR6_CALIB_0_SCR                       0
#define FUSE_TSENSOR6_CALIB_0_WORD_COUNT                        0x1
#define FUSE_TSENSOR6_CALIB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR6_CALIB_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR6_CALIB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR6_CALIB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR6_CALIB_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR6_CALIB_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR6_CALIB_0_TSENSOR6_CALIB_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_TSENSOR6_CALIB_0_TSENSOR6_CALIB_FIELD                      _MK_FIELD_CONST(0xffffffff, FUSE_TSENSOR6_CALIB_0_TSENSOR6_CALIB_SHIFT)
#define FUSE_TSENSOR6_CALIB_0_TSENSOR6_CALIB_RANGE                      31:0
#define FUSE_TSENSOR6_CALIB_0_TSENSOR6_CALIB_WOFFSET                    0x0
#define FUSE_TSENSOR6_CALIB_0_TSENSOR6_CALIB_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR6_CALIB_0_TSENSOR6_CALIB_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR6_CALIB_0_TSENSOR6_CALIB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR6_CALIB_0_TSENSOR6_CALIB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR6_CALIB_0_TSENSOR6_CALIB_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR6_CALIB_0_TSENSOR6_CALIB_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_TSENSOR7_CALIB_0
#define FUSE_TSENSOR7_CALIB_0                   _MK_ADDR_CONST(0x260)
#define FUSE_TSENSOR7_CALIB_0_SECURE                    0x0
#define FUSE_TSENSOR7_CALIB_0_DUAL                      0x0
#define FUSE_TSENSOR7_CALIB_0_SCR                       0
#define FUSE_TSENSOR7_CALIB_0_WORD_COUNT                        0x1
#define FUSE_TSENSOR7_CALIB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR7_CALIB_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR7_CALIB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR7_CALIB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR7_CALIB_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR7_CALIB_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR7_CALIB_0_TSENSOR7_CALIB_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_TSENSOR7_CALIB_0_TSENSOR7_CALIB_FIELD                      _MK_FIELD_CONST(0xffffffff, FUSE_TSENSOR7_CALIB_0_TSENSOR7_CALIB_SHIFT)
#define FUSE_TSENSOR7_CALIB_0_TSENSOR7_CALIB_RANGE                      31:0
#define FUSE_TSENSOR7_CALIB_0_TSENSOR7_CALIB_WOFFSET                    0x0
#define FUSE_TSENSOR7_CALIB_0_TSENSOR7_CALIB_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR7_CALIB_0_TSENSOR7_CALIB_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR7_CALIB_0_TSENSOR7_CALIB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR7_CALIB_0_TSENSOR7_CALIB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR7_CALIB_0_TSENSOR7_CALIB_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR7_CALIB_0_TSENSOR7_CALIB_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_PRIV_SEC_EN_0
#define FUSE_OPT_PRIV_SEC_EN_0                  _MK_ADDR_CONST(0x264)
#define FUSE_OPT_PRIV_SEC_EN_0_SECURE                   0x0
#define FUSE_OPT_PRIV_SEC_EN_0_DUAL                     0x0
#define FUSE_OPT_PRIV_SEC_EN_0_SCR                      0
#define FUSE_OPT_PRIV_SEC_EN_0_WORD_COUNT                       0x1
#define FUSE_OPT_PRIV_SEC_EN_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SEC_EN_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_OPT_PRIV_SEC_EN_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SEC_EN_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SEC_EN_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_OPT_PRIV_SEC_EN_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_OPT_PRIV_SEC_EN_0_OPT_PRIV_SEC_EN_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_PRIV_SEC_EN_0_OPT_PRIV_SEC_EN_FIELD                    _MK_FIELD_CONST(0x1, FUSE_OPT_PRIV_SEC_EN_0_OPT_PRIV_SEC_EN_SHIFT)
#define FUSE_OPT_PRIV_SEC_EN_0_OPT_PRIV_SEC_EN_RANGE                    0:0
#define FUSE_OPT_PRIV_SEC_EN_0_OPT_PRIV_SEC_EN_WOFFSET                  0x0
#define FUSE_OPT_PRIV_SEC_EN_0_OPT_PRIV_SEC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SEC_EN_0_OPT_PRIV_SEC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_OPT_PRIV_SEC_EN_0_OPT_PRIV_SEC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SEC_EN_0_OPT_PRIV_SEC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SEC_EN_0_OPT_PRIV_SEC_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SEC_EN_0_OPT_PRIV_SEC_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_BOOT_SECURITY_INFO_0
#define FUSE_BOOT_SECURITY_INFO_0                       _MK_ADDR_CONST(0x268)
#define FUSE_BOOT_SECURITY_INFO_0_SECURE                        0x0
#define FUSE_BOOT_SECURITY_INFO_0_DUAL                  0x0
#define FUSE_BOOT_SECURITY_INFO_0_SCR                   0
#define FUSE_BOOT_SECURITY_INFO_0_WORD_COUNT                    0x1
#define FUSE_BOOT_SECURITY_INFO_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_BOOT_SECURITY_INFO_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
#define FUSE_BOOT_SECURITY_INFO_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_BOOT_SECURITY_INFO_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_BOOT_SECURITY_INFO_0_READ_MASK                     _MK_MASK_CONST(0xffff)
#define FUSE_BOOT_SECURITY_INFO_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
#define FUSE_BOOT_SECURITY_INFO_0_BOOT_SECURITY_INFO_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_BOOT_SECURITY_INFO_0_BOOT_SECURITY_INFO_FIELD                      _MK_FIELD_CONST(0xffff, FUSE_BOOT_SECURITY_INFO_0_BOOT_SECURITY_INFO_SHIFT)
#define FUSE_BOOT_SECURITY_INFO_0_BOOT_SECURITY_INFO_RANGE                      15:0
#define FUSE_BOOT_SECURITY_INFO_0_BOOT_SECURITY_INFO_WOFFSET                    0x0
#define FUSE_BOOT_SECURITY_INFO_0_BOOT_SECURITY_INFO_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_BOOT_SECURITY_INFO_0_BOOT_SECURITY_INFO_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
#define FUSE_BOOT_SECURITY_INFO_0_BOOT_SECURITY_INFO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_BOOT_SECURITY_INFO_0_BOOT_SECURITY_INFO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_BOOT_SECURITY_INFO_0_BOOT_SECURITY_INFO_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_BOOT_SECURITY_INFO_0_BOOT_SECURITY_INFO_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Reserved address 0x26c

// Reserved address 0x270

// Reserved address 0x274

// Reserved address 0x278

// Register FUSE_FUSE2TSEC_DEBUG_DISABLE_0
#define FUSE_FUSE2TSEC_DEBUG_DISABLE_0                  _MK_ADDR_CONST(0x27c)
#define FUSE_FUSE2TSEC_DEBUG_DISABLE_0_SECURE                   0x0
#define FUSE_FUSE2TSEC_DEBUG_DISABLE_0_DUAL                     0x0
#define FUSE_FUSE2TSEC_DEBUG_DISABLE_0_SCR                      0
#define FUSE_FUSE2TSEC_DEBUG_DISABLE_0_WORD_COUNT                       0x1
#define FUSE_FUSE2TSEC_DEBUG_DISABLE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_FUSE2TSEC_DEBUG_DISABLE_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_FUSE2TSEC_DEBUG_DISABLE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_FUSE2TSEC_DEBUG_DISABLE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_FUSE2TSEC_DEBUG_DISABLE_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_FUSE2TSEC_DEBUG_DISABLE_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_FUSE2TSEC_DEBUG_DISABLE_0_FUSE2TSEC_DEBUG_DISABLE_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_FUSE2TSEC_DEBUG_DISABLE_0_FUSE2TSEC_DEBUG_DISABLE_FIELD                    _MK_FIELD_CONST(0x1, FUSE_FUSE2TSEC_DEBUG_DISABLE_0_FUSE2TSEC_DEBUG_DISABLE_SHIFT)
#define FUSE_FUSE2TSEC_DEBUG_DISABLE_0_FUSE2TSEC_DEBUG_DISABLE_RANGE                    0:0
#define FUSE_FUSE2TSEC_DEBUG_DISABLE_0_FUSE2TSEC_DEBUG_DISABLE_WOFFSET                  0x0
#define FUSE_FUSE2TSEC_DEBUG_DISABLE_0_FUSE2TSEC_DEBUG_DISABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_FUSE2TSEC_DEBUG_DISABLE_0_FUSE2TSEC_DEBUG_DISABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_FUSE2TSEC_DEBUG_DISABLE_0_FUSE2TSEC_DEBUG_DISABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_FUSE2TSEC_DEBUG_DISABLE_0_FUSE2TSEC_DEBUG_DISABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_FUSE2TSEC_DEBUG_DISABLE_0_FUSE2TSEC_DEBUG_DISABLE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_FUSE2TSEC_DEBUG_DISABLE_0_FUSE2TSEC_DEBUG_DISABLE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_TSENSOR_COMMON_T1_0
#define FUSE_TSENSOR_COMMON_T1_0                        _MK_ADDR_CONST(0x280)
#define FUSE_TSENSOR_COMMON_T1_0_SECURE                         0x0
#define FUSE_TSENSOR_COMMON_T1_0_DUAL                   0x0
#define FUSE_TSENSOR_COMMON_T1_0_SCR                    0
#define FUSE_TSENSOR_COMMON_T1_0_WORD_COUNT                     0x1
#define FUSE_TSENSOR_COMMON_T1_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR_COMMON_T1_0_RESET_MASK                     _MK_MASK_CONST(0x7ffff)
#define FUSE_TSENSOR_COMMON_T1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR_COMMON_T1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR_COMMON_T1_0_READ_MASK                      _MK_MASK_CONST(0x7ffff)
#define FUSE_TSENSOR_COMMON_T1_0_WRITE_MASK                     _MK_MASK_CONST(0x7ffff)
#define FUSE_TSENSOR_COMMON_T1_0_TSENSOR_COMMON_T1_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_TSENSOR_COMMON_T1_0_TSENSOR_COMMON_T1_FIELD                        _MK_FIELD_CONST(0x7ffff, FUSE_TSENSOR_COMMON_T1_0_TSENSOR_COMMON_T1_SHIFT)
#define FUSE_TSENSOR_COMMON_T1_0_TSENSOR_COMMON_T1_RANGE                        18:0
#define FUSE_TSENSOR_COMMON_T1_0_TSENSOR_COMMON_T1_WOFFSET                      0x0
#define FUSE_TSENSOR_COMMON_T1_0_TSENSOR_COMMON_T1_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR_COMMON_T1_0_TSENSOR_COMMON_T1_DEFAULT_MASK                 _MK_MASK_CONST(0x7ffff)
#define FUSE_TSENSOR_COMMON_T1_0_TSENSOR_COMMON_T1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR_COMMON_T1_0_TSENSOR_COMMON_T1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR_COMMON_T1_0_TSENSOR_COMMON_T1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR_COMMON_T1_0_TSENSOR_COMMON_T1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_OPT_CP_BIN_0
#define FUSE_OPT_CP_BIN_0                       _MK_ADDR_CONST(0x284)
#define FUSE_OPT_CP_BIN_0_SECURE                        0x0
#define FUSE_OPT_CP_BIN_0_DUAL                  0x0
#define FUSE_OPT_CP_BIN_0_SCR                   0
#define FUSE_OPT_CP_BIN_0_WORD_COUNT                    0x1
#define FUSE_OPT_CP_BIN_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_CP_BIN_0_RESET_MASK                    _MK_MASK_CONST(0x3)
#define FUSE_OPT_CP_BIN_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_CP_BIN_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_CP_BIN_0_READ_MASK                     _MK_MASK_CONST(0x3)
#define FUSE_OPT_CP_BIN_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
#define FUSE_OPT_CP_BIN_0_OPT_CP_BIN_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_CP_BIN_0_OPT_CP_BIN_FIELD                      _MK_FIELD_CONST(0x3, FUSE_OPT_CP_BIN_0_OPT_CP_BIN_SHIFT)
#define FUSE_OPT_CP_BIN_0_OPT_CP_BIN_RANGE                      1:0
#define FUSE_OPT_CP_BIN_0_OPT_CP_BIN_WOFFSET                    0x0
#define FUSE_OPT_CP_BIN_0_OPT_CP_BIN_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_CP_BIN_0_OPT_CP_BIN_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define FUSE_OPT_CP_BIN_0_OPT_CP_BIN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_CP_BIN_0_OPT_CP_BIN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_CP_BIN_0_OPT_CP_BIN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_CP_BIN_0_OPT_CP_BIN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_GPU_DISABLE_0
#define FUSE_OPT_GPU_DISABLE_0                  _MK_ADDR_CONST(0x288)
#define FUSE_OPT_GPU_DISABLE_0_SECURE                   0x0
#define FUSE_OPT_GPU_DISABLE_0_DUAL                     0x0
#define FUSE_OPT_GPU_DISABLE_0_SCR                      0
#define FUSE_OPT_GPU_DISABLE_0_WORD_COUNT                       0x1
#define FUSE_OPT_GPU_DISABLE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_GPU_DISABLE_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_OPT_GPU_DISABLE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_GPU_DISABLE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_GPU_DISABLE_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_OPT_GPU_DISABLE_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_OPT_GPU_DISABLE_0_OPT_GPU_DISABLE_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_GPU_DISABLE_0_OPT_GPU_DISABLE_FIELD                    _MK_FIELD_CONST(0x1, FUSE_OPT_GPU_DISABLE_0_OPT_GPU_DISABLE_SHIFT)
#define FUSE_OPT_GPU_DISABLE_0_OPT_GPU_DISABLE_RANGE                    0:0
#define FUSE_OPT_GPU_DISABLE_0_OPT_GPU_DISABLE_WOFFSET                  0x0
#define FUSE_OPT_GPU_DISABLE_0_OPT_GPU_DISABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_GPU_DISABLE_0_OPT_GPU_DISABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_OPT_GPU_DISABLE_0_OPT_GPU_DISABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_GPU_DISABLE_0_OPT_GPU_DISABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_GPU_DISABLE_0_OPT_GPU_DISABLE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_GPU_DISABLE_0_OPT_GPU_DISABLE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_FT_DONE_0
#define FUSE_OPT_FT_DONE_0                      _MK_ADDR_CONST(0x28c)
#define FUSE_OPT_FT_DONE_0_SECURE                       0x0
#define FUSE_OPT_FT_DONE_0_DUAL                         0x0
#define FUSE_OPT_FT_DONE_0_SCR                  0
#define FUSE_OPT_FT_DONE_0_WORD_COUNT                   0x1
#define FUSE_OPT_FT_DONE_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_FT_DONE_0_RESET_MASK                   _MK_MASK_CONST(0x3ff)
#define FUSE_OPT_FT_DONE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_FT_DONE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_FT_DONE_0_READ_MASK                    _MK_MASK_CONST(0x3ff)
#define FUSE_OPT_FT_DONE_0_WRITE_MASK                   _MK_MASK_CONST(0x3ff)
#define FUSE_OPT_FT_DONE_0_OPT_FT_DONE_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_FT_DONE_0_OPT_FT_DONE_FIELD                    _MK_FIELD_CONST(0x3ff, FUSE_OPT_FT_DONE_0_OPT_FT_DONE_SHIFT)
#define FUSE_OPT_FT_DONE_0_OPT_FT_DONE_RANGE                    9:0
#define FUSE_OPT_FT_DONE_0_OPT_FT_DONE_WOFFSET                  0x0
#define FUSE_OPT_FT_DONE_0_OPT_FT_DONE_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_FT_DONE_0_OPT_FT_DONE_DEFAULT_MASK                     _MK_MASK_CONST(0x3ff)
#define FUSE_OPT_FT_DONE_0_OPT_FT_DONE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_FT_DONE_0_OPT_FT_DONE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_FT_DONE_0_OPT_FT_DONE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_FT_DONE_0_OPT_FT_DONE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_DONE_MAP_0
#define FUSE_OPT_DONE_MAP_0                     _MK_ADDR_CONST(0x290)
#define FUSE_OPT_DONE_MAP_0_SECURE                      0x0
#define FUSE_OPT_DONE_MAP_0_DUAL                        0x0
#define FUSE_OPT_DONE_MAP_0_SCR                         0
#define FUSE_OPT_DONE_MAP_0_WORD_COUNT                  0x1
#define FUSE_OPT_DONE_MAP_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_DONE_MAP_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define FUSE_OPT_DONE_MAP_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_DONE_MAP_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_DONE_MAP_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define FUSE_OPT_DONE_MAP_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define FUSE_OPT_DONE_MAP_0_OPT_DONE_MAP_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_OPT_DONE_MAP_0_OPT_DONE_MAP_FIELD                  _MK_FIELD_CONST(0xff, FUSE_OPT_DONE_MAP_0_OPT_DONE_MAP_SHIFT)
#define FUSE_OPT_DONE_MAP_0_OPT_DONE_MAP_RANGE                  7:0
#define FUSE_OPT_DONE_MAP_0_OPT_DONE_MAP_WOFFSET                        0x0
#define FUSE_OPT_DONE_MAP_0_OPT_DONE_MAP_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_DONE_MAP_0_OPT_DONE_MAP_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define FUSE_OPT_DONE_MAP_0_OPT_DONE_MAP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_DONE_MAP_0_OPT_DONE_MAP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_DONE_MAP_0_OPT_DONE_MAP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_DONE_MAP_0_OPT_DONE_MAP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Reserved address 0x294

// Register FUSE_ODM_INFO_0
#define FUSE_ODM_INFO_0                 _MK_ADDR_CONST(0x29c)
#define FUSE_ODM_INFO_0_SECURE                  0x0
#define FUSE_ODM_INFO_0_DUAL                    0x0
#define FUSE_ODM_INFO_0_SCR                     0
#define FUSE_ODM_INFO_0_WORD_COUNT                      0x1
#define FUSE_ODM_INFO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_ODM_INFO_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
#define FUSE_ODM_INFO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_ODM_INFO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_ODM_INFO_0_READ_MASK                       _MK_MASK_CONST(0xffff)
#define FUSE_ODM_INFO_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
#define FUSE_ODM_INFO_0_ODM_INFO_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_ODM_INFO_0_ODM_INFO_FIELD                  _MK_FIELD_CONST(0xffff, FUSE_ODM_INFO_0_ODM_INFO_SHIFT)
#define FUSE_ODM_INFO_0_ODM_INFO_RANGE                  15:0
#define FUSE_ODM_INFO_0_ODM_INFO_WOFFSET                        0x0
#define FUSE_ODM_INFO_0_ODM_INFO_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_ODM_INFO_0_ODM_INFO_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
#define FUSE_ODM_INFO_0_ODM_INFO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_ODM_INFO_0_ODM_INFO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_ODM_INFO_0_ODM_INFO_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_ODM_INFO_0_ODM_INFO_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Reserved address 0x2a0

// Reserved address 0x2a4

// Register FUSE_ARM_CRYPT_DE_FEATURE_0
#define FUSE_ARM_CRYPT_DE_FEATURE_0                     _MK_ADDR_CONST(0x2a8)
#define FUSE_ARM_CRYPT_DE_FEATURE_0_SECURE                      0x0
#define FUSE_ARM_CRYPT_DE_FEATURE_0_DUAL                        0x0
#define FUSE_ARM_CRYPT_DE_FEATURE_0_SCR                         0
#define FUSE_ARM_CRYPT_DE_FEATURE_0_WORD_COUNT                  0x1
#define FUSE_ARM_CRYPT_DE_FEATURE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_ARM_CRYPT_DE_FEATURE_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_ARM_CRYPT_DE_FEATURE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_ARM_CRYPT_DE_FEATURE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_ARM_CRYPT_DE_FEATURE_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_ARM_CRYPT_DE_FEATURE_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_ARM_CRYPT_DE_FEATURE_0_ARM_CRYPT_DE_FEATURE_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_ARM_CRYPT_DE_FEATURE_0_ARM_CRYPT_DE_FEATURE_FIELD                  _MK_FIELD_CONST(0x1, FUSE_ARM_CRYPT_DE_FEATURE_0_ARM_CRYPT_DE_FEATURE_SHIFT)
#define FUSE_ARM_CRYPT_DE_FEATURE_0_ARM_CRYPT_DE_FEATURE_RANGE                  0:0
#define FUSE_ARM_CRYPT_DE_FEATURE_0_ARM_CRYPT_DE_FEATURE_WOFFSET                        0x0
#define FUSE_ARM_CRYPT_DE_FEATURE_0_ARM_CRYPT_DE_FEATURE_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_ARM_CRYPT_DE_FEATURE_0_ARM_CRYPT_DE_FEATURE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_ARM_CRYPT_DE_FEATURE_0_ARM_CRYPT_DE_FEATURE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_ARM_CRYPT_DE_FEATURE_0_ARM_CRYPT_DE_FEATURE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_ARM_CRYPT_DE_FEATURE_0_ARM_CRYPT_DE_FEATURE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_ARM_CRYPT_DE_FEATURE_0_ARM_CRYPT_DE_FEATURE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_CCPLEX_UCODE_MISC_0
#define FUSE_CCPLEX_UCODE_MISC_0                        _MK_ADDR_CONST(0x2ac)
#define FUSE_CCPLEX_UCODE_MISC_0_SECURE                         0x0
#define FUSE_CCPLEX_UCODE_MISC_0_DUAL                   0x0
#define FUSE_CCPLEX_UCODE_MISC_0_SCR                    0
#define FUSE_CCPLEX_UCODE_MISC_0_WORD_COUNT                     0x1
#define FUSE_CCPLEX_UCODE_MISC_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MISC_0_RESET_MASK                     _MK_MASK_CONST(0x3ff)
#define FUSE_CCPLEX_UCODE_MISC_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MISC_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MISC_0_READ_MASK                      _MK_MASK_CONST(0x3ff)
#define FUSE_CCPLEX_UCODE_MISC_0_WRITE_MASK                     _MK_MASK_CONST(0x3ff)
#define FUSE_CCPLEX_UCODE_MISC_0_CCPLEX_UCODE_MISC_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_CCPLEX_UCODE_MISC_0_CCPLEX_UCODE_MISC_FIELD                        _MK_FIELD_CONST(0x3ff, FUSE_CCPLEX_UCODE_MISC_0_CCPLEX_UCODE_MISC_SHIFT)
#define FUSE_CCPLEX_UCODE_MISC_0_CCPLEX_UCODE_MISC_RANGE                        9:0
#define FUSE_CCPLEX_UCODE_MISC_0_CCPLEX_UCODE_MISC_WOFFSET                      0x0
#define FUSE_CCPLEX_UCODE_MISC_0_CCPLEX_UCODE_MISC_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MISC_0_CCPLEX_UCODE_MISC_DEFAULT_MASK                 _MK_MASK_CONST(0x3ff)
#define FUSE_CCPLEX_UCODE_MISC_0_CCPLEX_UCODE_MISC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MISC_0_CCPLEX_UCODE_MISC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MISC_0_CCPLEX_UCODE_MISC_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MISC_0_CCPLEX_UCODE_MISC_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Reserved address 0x2b0

// Reserved address 0x2b4

// Reserved address 0x2b8

// Register FUSE_CCPLEX_DFD_ACCESS_DISABLE_0
#define FUSE_CCPLEX_DFD_ACCESS_DISABLE_0                        _MK_ADDR_CONST(0x2bc)
#define FUSE_CCPLEX_DFD_ACCESS_DISABLE_0_SECURE                         0x0
#define FUSE_CCPLEX_DFD_ACCESS_DISABLE_0_DUAL                   0x0
#define FUSE_CCPLEX_DFD_ACCESS_DISABLE_0_SCR                    0
#define FUSE_CCPLEX_DFD_ACCESS_DISABLE_0_WORD_COUNT                     0x1
#define FUSE_CCPLEX_DFD_ACCESS_DISABLE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_DFD_ACCESS_DISABLE_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_CCPLEX_DFD_ACCESS_DISABLE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_DFD_ACCESS_DISABLE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_DFD_ACCESS_DISABLE_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_CCPLEX_DFD_ACCESS_DISABLE_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_CCPLEX_DFD_ACCESS_DISABLE_0_CCPLEX_DFD_ACCESS_DISABLE_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_CCPLEX_DFD_ACCESS_DISABLE_0_CCPLEX_DFD_ACCESS_DISABLE_FIELD                        _MK_FIELD_CONST(0x1, FUSE_CCPLEX_DFD_ACCESS_DISABLE_0_CCPLEX_DFD_ACCESS_DISABLE_SHIFT)
#define FUSE_CCPLEX_DFD_ACCESS_DISABLE_0_CCPLEX_DFD_ACCESS_DISABLE_RANGE                        0:0
#define FUSE_CCPLEX_DFD_ACCESS_DISABLE_0_CCPLEX_DFD_ACCESS_DISABLE_WOFFSET                      0x0
#define FUSE_CCPLEX_DFD_ACCESS_DISABLE_0_CCPLEX_DFD_ACCESS_DISABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_DFD_ACCESS_DISABLE_0_CCPLEX_DFD_ACCESS_DISABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define FUSE_CCPLEX_DFD_ACCESS_DISABLE_0_CCPLEX_DFD_ACCESS_DISABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_DFD_ACCESS_DISABLE_0_CCPLEX_DFD_ACCESS_DISABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_DFD_ACCESS_DISABLE_0_CCPLEX_DFD_ACCESS_DISABLE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_DFD_ACCESS_DISABLE_0_CCPLEX_DFD_ACCESS_DISABLE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_WOA_SKU_FLAG_0
#define FUSE_WOA_SKU_FLAG_0                     _MK_ADDR_CONST(0x2c0)
#define FUSE_WOA_SKU_FLAG_0_SECURE                      0x0
#define FUSE_WOA_SKU_FLAG_0_DUAL                        0x0
#define FUSE_WOA_SKU_FLAG_0_SCR                         0
#define FUSE_WOA_SKU_FLAG_0_WORD_COUNT                  0x1
#define FUSE_WOA_SKU_FLAG_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_WOA_SKU_FLAG_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_WOA_SKU_FLAG_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_WOA_SKU_FLAG_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_WOA_SKU_FLAG_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_WOA_SKU_FLAG_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_WOA_SKU_FLAG_0_WOA_SKU_FLAG_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_WOA_SKU_FLAG_0_WOA_SKU_FLAG_FIELD                  _MK_FIELD_CONST(0x1, FUSE_WOA_SKU_FLAG_0_WOA_SKU_FLAG_SHIFT)
#define FUSE_WOA_SKU_FLAG_0_WOA_SKU_FLAG_RANGE                  0:0
#define FUSE_WOA_SKU_FLAG_0_WOA_SKU_FLAG_WOFFSET                        0x0
#define FUSE_WOA_SKU_FLAG_0_WOA_SKU_FLAG_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_WOA_SKU_FLAG_0_WOA_SKU_FLAG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_WOA_SKU_FLAG_0_WOA_SKU_FLAG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_WOA_SKU_FLAG_0_WOA_SKU_FLAG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_WOA_SKU_FLAG_0_WOA_SKU_FLAG_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_WOA_SKU_FLAG_0_WOA_SKU_FLAG_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_ECO_RESERVE_1_0
#define FUSE_ECO_RESERVE_1_0                    _MK_ADDR_CONST(0x2c4)
#define FUSE_ECO_RESERVE_1_0_SECURE                     0x0
#define FUSE_ECO_RESERVE_1_0_DUAL                       0x0
#define FUSE_ECO_RESERVE_1_0_SCR                        0
#define FUSE_ECO_RESERVE_1_0_WORD_COUNT                         0x1
#define FUSE_ECO_RESERVE_1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_ECO_RESERVE_1_0_RESET_MASK                         _MK_MASK_CONST(0xffff)
#define FUSE_ECO_RESERVE_1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_ECO_RESERVE_1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_ECO_RESERVE_1_0_READ_MASK                  _MK_MASK_CONST(0xffff)
#define FUSE_ECO_RESERVE_1_0_WRITE_MASK                         _MK_MASK_CONST(0xffff)
#define FUSE_ECO_RESERVE_1_0_ECO_RESERVE_1_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_ECO_RESERVE_1_0_ECO_RESERVE_1_FIELD                        _MK_FIELD_CONST(0xffff, FUSE_ECO_RESERVE_1_0_ECO_RESERVE_1_SHIFT)
#define FUSE_ECO_RESERVE_1_0_ECO_RESERVE_1_RANGE                        15:0
#define FUSE_ECO_RESERVE_1_0_ECO_RESERVE_1_WOFFSET                      0x0
#define FUSE_ECO_RESERVE_1_0_ECO_RESERVE_1_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_ECO_RESERVE_1_0_ECO_RESERVE_1_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
#define FUSE_ECO_RESERVE_1_0_ECO_RESERVE_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_ECO_RESERVE_1_0_ECO_RESERVE_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_ECO_RESERVE_1_0_ECO_RESERVE_1_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_ECO_RESERVE_1_0_ECO_RESERVE_1_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_GCPLEX_CONFIG_FUSE_0
#define FUSE_GCPLEX_CONFIG_FUSE_0                       _MK_ADDR_CONST(0x2c8)
#define FUSE_GCPLEX_CONFIG_FUSE_0_SECURE                        0x0
#define FUSE_GCPLEX_CONFIG_FUSE_0_DUAL                  0x0
#define FUSE_GCPLEX_CONFIG_FUSE_0_SCR                   0
#define FUSE_GCPLEX_CONFIG_FUSE_0_WORD_COUNT                    0x1
#define FUSE_GCPLEX_CONFIG_FUSE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_GCPLEX_CONFIG_FUSE_0_RESET_MASK                    _MK_MASK_CONST(0x7)
#define FUSE_GCPLEX_CONFIG_FUSE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_GCPLEX_CONFIG_FUSE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_GCPLEX_CONFIG_FUSE_0_READ_MASK                     _MK_MASK_CONST(0x7)
#define FUSE_GCPLEX_CONFIG_FUSE_0_WRITE_MASK                    _MK_MASK_CONST(0x7)
#define FUSE_GCPLEX_CONFIG_FUSE_0_GCPLEX_CONFIG_FUSE_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_GCPLEX_CONFIG_FUSE_0_GCPLEX_CONFIG_FUSE_FIELD                      _MK_FIELD_CONST(0x7, FUSE_GCPLEX_CONFIG_FUSE_0_GCPLEX_CONFIG_FUSE_SHIFT)
#define FUSE_GCPLEX_CONFIG_FUSE_0_GCPLEX_CONFIG_FUSE_RANGE                      2:0
#define FUSE_GCPLEX_CONFIG_FUSE_0_GCPLEX_CONFIG_FUSE_WOFFSET                    0x0
#define FUSE_GCPLEX_CONFIG_FUSE_0_GCPLEX_CONFIG_FUSE_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_GCPLEX_CONFIG_FUSE_0_GCPLEX_CONFIG_FUSE_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define FUSE_GCPLEX_CONFIG_FUSE_0_GCPLEX_CONFIG_FUSE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_GCPLEX_CONFIG_FUSE_0_GCPLEX_CONFIG_FUSE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_GCPLEX_CONFIG_FUSE_0_GCPLEX_CONFIG_FUSE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_GCPLEX_CONFIG_FUSE_0_GCPLEX_CONFIG_FUSE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_PRODUCTION_MONTH_0
#define FUSE_PRODUCTION_MONTH_0                 _MK_ADDR_CONST(0x2cc)
#define FUSE_PRODUCTION_MONTH_0_SECURE                  0x0
#define FUSE_PRODUCTION_MONTH_0_DUAL                    0x0
#define FUSE_PRODUCTION_MONTH_0_SCR                     0
#define FUSE_PRODUCTION_MONTH_0_WORD_COUNT                      0x1
#define FUSE_PRODUCTION_MONTH_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_PRODUCTION_MONTH_0_RESET_MASK                      _MK_MASK_CONST(0x7f)
#define FUSE_PRODUCTION_MONTH_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_PRODUCTION_MONTH_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_PRODUCTION_MONTH_0_READ_MASK                       _MK_MASK_CONST(0x7f)
#define FUSE_PRODUCTION_MONTH_0_WRITE_MASK                      _MK_MASK_CONST(0x7f)
#define FUSE_PRODUCTION_MONTH_0_PRODUCTION_MONTH_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_PRODUCTION_MONTH_0_PRODUCTION_MONTH_FIELD                  _MK_FIELD_CONST(0x7f, FUSE_PRODUCTION_MONTH_0_PRODUCTION_MONTH_SHIFT)
#define FUSE_PRODUCTION_MONTH_0_PRODUCTION_MONTH_RANGE                  6:0
#define FUSE_PRODUCTION_MONTH_0_PRODUCTION_MONTH_WOFFSET                        0x0
#define FUSE_PRODUCTION_MONTH_0_PRODUCTION_MONTH_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_PRODUCTION_MONTH_0_PRODUCTION_MONTH_DEFAULT_MASK                   _MK_MASK_CONST(0x7f)
#define FUSE_PRODUCTION_MONTH_0_PRODUCTION_MONTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_PRODUCTION_MONTH_0_PRODUCTION_MONTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_PRODUCTION_MONTH_0_PRODUCTION_MONTH_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_PRODUCTION_MONTH_0_PRODUCTION_MONTH_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_RAM_REPAIR_INDICATOR_0
#define FUSE_RAM_REPAIR_INDICATOR_0                     _MK_ADDR_CONST(0x2d0)
#define FUSE_RAM_REPAIR_INDICATOR_0_SECURE                      0x0
#define FUSE_RAM_REPAIR_INDICATOR_0_DUAL                        0x0
#define FUSE_RAM_REPAIR_INDICATOR_0_SCR                         0
#define FUSE_RAM_REPAIR_INDICATOR_0_WORD_COUNT                  0x1
#define FUSE_RAM_REPAIR_INDICATOR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_RAM_REPAIR_INDICATOR_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_RAM_REPAIR_INDICATOR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_RAM_REPAIR_INDICATOR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_RAM_REPAIR_INDICATOR_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_RAM_REPAIR_INDICATOR_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_RAM_REPAIR_INDICATOR_0_RAM_REPAIR_INDICATOR_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_RAM_REPAIR_INDICATOR_0_RAM_REPAIR_INDICATOR_FIELD                  _MK_FIELD_CONST(0x1, FUSE_RAM_REPAIR_INDICATOR_0_RAM_REPAIR_INDICATOR_SHIFT)
#define FUSE_RAM_REPAIR_INDICATOR_0_RAM_REPAIR_INDICATOR_RANGE                  0:0
#define FUSE_RAM_REPAIR_INDICATOR_0_RAM_REPAIR_INDICATOR_WOFFSET                        0x0
#define FUSE_RAM_REPAIR_INDICATOR_0_RAM_REPAIR_INDICATOR_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_RAM_REPAIR_INDICATOR_0_RAM_REPAIR_INDICATOR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_RAM_REPAIR_INDICATOR_0_RAM_REPAIR_INDICATOR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_RAM_REPAIR_INDICATOR_0_RAM_REPAIR_INDICATOR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_RAM_REPAIR_INDICATOR_0_RAM_REPAIR_INDICATOR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_RAM_REPAIR_INDICATOR_0_RAM_REPAIR_INDICATOR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_TSENSOR8_CALIB_0
#define FUSE_TSENSOR8_CALIB_0                   _MK_ADDR_CONST(0x2d4)
#define FUSE_TSENSOR8_CALIB_0_SECURE                    0x0
#define FUSE_TSENSOR8_CALIB_0_DUAL                      0x0
#define FUSE_TSENSOR8_CALIB_0_SCR                       0
#define FUSE_TSENSOR8_CALIB_0_WORD_COUNT                        0x1
#define FUSE_TSENSOR8_CALIB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR8_CALIB_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR8_CALIB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR8_CALIB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR8_CALIB_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR8_CALIB_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR8_CALIB_0_TSENSOR8_CALIB_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_TSENSOR8_CALIB_0_TSENSOR8_CALIB_FIELD                      _MK_FIELD_CONST(0xffffffff, FUSE_TSENSOR8_CALIB_0_TSENSOR8_CALIB_SHIFT)
#define FUSE_TSENSOR8_CALIB_0_TSENSOR8_CALIB_RANGE                      31:0
#define FUSE_TSENSOR8_CALIB_0_TSENSOR8_CALIB_WOFFSET                    0x0
#define FUSE_TSENSOR8_CALIB_0_TSENSOR8_CALIB_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR8_CALIB_0_TSENSOR8_CALIB_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR8_CALIB_0_TSENSOR8_CALIB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR8_CALIB_0_TSENSOR8_CALIB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR8_CALIB_0_TSENSOR8_CALIB_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR8_CALIB_0_TSENSOR8_CALIB_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Reserved address 0x2d8

// Register FUSE_VMIN_CALIBRATION_0
#define FUSE_VMIN_CALIBRATION_0                 _MK_ADDR_CONST(0x2dc)
#define FUSE_VMIN_CALIBRATION_0_SECURE                  0x0
#define FUSE_VMIN_CALIBRATION_0_DUAL                    0x0
#define FUSE_VMIN_CALIBRATION_0_SCR                     0
#define FUSE_VMIN_CALIBRATION_0_WORD_COUNT                      0x1
#define FUSE_VMIN_CALIBRATION_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_VMIN_CALIBRATION_0_RESET_MASK                      _MK_MASK_CONST(0xfff)
#define FUSE_VMIN_CALIBRATION_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_VMIN_CALIBRATION_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_VMIN_CALIBRATION_0_READ_MASK                       _MK_MASK_CONST(0xfff)
#define FUSE_VMIN_CALIBRATION_0_WRITE_MASK                      _MK_MASK_CONST(0xfff)
#define FUSE_VMIN_CALIBRATION_0_VMIN_CALIBRATION_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_VMIN_CALIBRATION_0_VMIN_CALIBRATION_FIELD                  _MK_FIELD_CONST(0xfff, FUSE_VMIN_CALIBRATION_0_VMIN_CALIBRATION_SHIFT)
#define FUSE_VMIN_CALIBRATION_0_VMIN_CALIBRATION_RANGE                  11:0
#define FUSE_VMIN_CALIBRATION_0_VMIN_CALIBRATION_WOFFSET                        0x0
#define FUSE_VMIN_CALIBRATION_0_VMIN_CALIBRATION_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_VMIN_CALIBRATION_0_VMIN_CALIBRATION_DEFAULT_MASK                   _MK_MASK_CONST(0xfff)
#define FUSE_VMIN_CALIBRATION_0_VMIN_CALIBRATION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_VMIN_CALIBRATION_0_VMIN_CALIBRATION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_VMIN_CALIBRATION_0_VMIN_CALIBRATION_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_VMIN_CALIBRATION_0_VMIN_CALIBRATION_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_AGING_SENSOR_CALIBRATION_0
#define FUSE_AGING_SENSOR_CALIBRATION_0                 _MK_ADDR_CONST(0x2e0)
#define FUSE_AGING_SENSOR_CALIBRATION_0_SECURE                  0x0
#define FUSE_AGING_SENSOR_CALIBRATION_0_DUAL                    0x0
#define FUSE_AGING_SENSOR_CALIBRATION_0_SCR                     0
#define FUSE_AGING_SENSOR_CALIBRATION_0_WORD_COUNT                      0x1
#define FUSE_AGING_SENSOR_CALIBRATION_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_AGING_SENSOR_CALIBRATION_0_RESET_MASK                      _MK_MASK_CONST(0xfffffff)
#define FUSE_AGING_SENSOR_CALIBRATION_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_AGING_SENSOR_CALIBRATION_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_AGING_SENSOR_CALIBRATION_0_READ_MASK                       _MK_MASK_CONST(0xfffffff)
#define FUSE_AGING_SENSOR_CALIBRATION_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffff)
#define FUSE_AGING_SENSOR_CALIBRATION_0_AGING_SENSOR_CALIBRATION_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_AGING_SENSOR_CALIBRATION_0_AGING_SENSOR_CALIBRATION_FIELD                  _MK_FIELD_CONST(0xfffffff, FUSE_AGING_SENSOR_CALIBRATION_0_AGING_SENSOR_CALIBRATION_SHIFT)
#define FUSE_AGING_SENSOR_CALIBRATION_0_AGING_SENSOR_CALIBRATION_RANGE                  27:0
#define FUSE_AGING_SENSOR_CALIBRATION_0_AGING_SENSOR_CALIBRATION_WOFFSET                        0x0
#define FUSE_AGING_SENSOR_CALIBRATION_0_AGING_SENSOR_CALIBRATION_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_AGING_SENSOR_CALIBRATION_0_AGING_SENSOR_CALIBRATION_DEFAULT_MASK                   _MK_MASK_CONST(0xfffffff)
#define FUSE_AGING_SENSOR_CALIBRATION_0_AGING_SENSOR_CALIBRATION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_AGING_SENSOR_CALIBRATION_0_AGING_SENSOR_CALIBRATION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_AGING_SENSOR_CALIBRATION_0_AGING_SENSOR_CALIBRATION_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_AGING_SENSOR_CALIBRATION_0_AGING_SENSOR_CALIBRATION_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_DEBUG_AUTHENTICATION_0
#define FUSE_DEBUG_AUTHENTICATION_0                     _MK_ADDR_CONST(0x2e4)
#define FUSE_DEBUG_AUTHENTICATION_0_SECURE                      0x0
#define FUSE_DEBUG_AUTHENTICATION_0_DUAL                        0x0
#define FUSE_DEBUG_AUTHENTICATION_0_SCR                         0
#define FUSE_DEBUG_AUTHENTICATION_0_WORD_COUNT                  0x1
#define FUSE_DEBUG_AUTHENTICATION_0_RESET_VAL                   _MK_MASK_CONST(0x1f)
#define FUSE_DEBUG_AUTHENTICATION_0_RESET_MASK                  _MK_MASK_CONST(0x1f)
#define FUSE_DEBUG_AUTHENTICATION_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_DEBUG_AUTHENTICATION_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_DEBUG_AUTHENTICATION_0_READ_MASK                   _MK_MASK_CONST(0x1f)
#define FUSE_DEBUG_AUTHENTICATION_0_WRITE_MASK                  _MK_MASK_CONST(0x1f)
#define FUSE_DEBUG_AUTHENTICATION_0_DEBUG_AUTHENTICATION_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_DEBUG_AUTHENTICATION_0_DEBUG_AUTHENTICATION_FIELD                  _MK_FIELD_CONST(0x1f, FUSE_DEBUG_AUTHENTICATION_0_DEBUG_AUTHENTICATION_SHIFT)
#define FUSE_DEBUG_AUTHENTICATION_0_DEBUG_AUTHENTICATION_RANGE                  4:0
#define FUSE_DEBUG_AUTHENTICATION_0_DEBUG_AUTHENTICATION_WOFFSET                        0x0
#define FUSE_DEBUG_AUTHENTICATION_0_DEBUG_AUTHENTICATION_DEFAULT                        _MK_MASK_CONST(0x1f)
#define FUSE_DEBUG_AUTHENTICATION_0_DEBUG_AUTHENTICATION_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define FUSE_DEBUG_AUTHENTICATION_0_DEBUG_AUTHENTICATION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_DEBUG_AUTHENTICATION_0_DEBUG_AUTHENTICATION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_DEBUG_AUTHENTICATION_0_DEBUG_AUTHENTICATION_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_DEBUG_AUTHENTICATION_0_DEBUG_AUTHENTICATION_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_OPT_GPU_DISABLE_CP_0
#define FUSE_OPT_GPU_DISABLE_CP_0                       _MK_ADDR_CONST(0x2f0)
#define FUSE_OPT_GPU_DISABLE_CP_0_SECURE                        0x0
#define FUSE_OPT_GPU_DISABLE_CP_0_DUAL                  0x0
#define FUSE_OPT_GPU_DISABLE_CP_0_SCR                   0
#define FUSE_OPT_GPU_DISABLE_CP_0_WORD_COUNT                    0x1
#define FUSE_OPT_GPU_DISABLE_CP_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_GPU_DISABLE_CP_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_OPT_GPU_DISABLE_CP_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_GPU_DISABLE_CP_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_GPU_DISABLE_CP_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_OPT_GPU_DISABLE_CP_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_OPT_GPU_DISABLE_CP_0_OPT_GPU_DISABLE_CP_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_GPU_DISABLE_CP_0_OPT_GPU_DISABLE_CP_FIELD                      _MK_FIELD_CONST(0x1, FUSE_OPT_GPU_DISABLE_CP_0_OPT_GPU_DISABLE_CP_SHIFT)
#define FUSE_OPT_GPU_DISABLE_CP_0_OPT_GPU_DISABLE_CP_RANGE                      0:0
#define FUSE_OPT_GPU_DISABLE_CP_0_OPT_GPU_DISABLE_CP_WOFFSET                    0x0
#define FUSE_OPT_GPU_DISABLE_CP_0_OPT_GPU_DISABLE_CP_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_GPU_DISABLE_CP_0_OPT_GPU_DISABLE_CP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_OPT_GPU_DISABLE_CP_0_OPT_GPU_DISABLE_CP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_GPU_DISABLE_CP_0_OPT_GPU_DISABLE_CP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_GPU_DISABLE_CP_0_OPT_GPU_DISABLE_CP_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_GPU_DISABLE_CP_0_OPT_GPU_DISABLE_CP_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_ENDIS_0
#define FUSE_SPARE_ENDIS_0                      _MK_ADDR_CONST(0x2f4)
#define FUSE_SPARE_ENDIS_0_SECURE                       0x0
#define FUSE_SPARE_ENDIS_0_DUAL                         0x0
#define FUSE_SPARE_ENDIS_0_SCR                  0
#define FUSE_SPARE_ENDIS_0_WORD_COUNT                   0x1
#define FUSE_SPARE_ENDIS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_SPARE_ENDIS_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_ENDIS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_SPARE_ENDIS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_ENDIS_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_SPARE_ENDIS_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_ENDIS_0_SPARE_ENDIS_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_SPARE_ENDIS_0_SPARE_ENDIS_FIELD                    _MK_FIELD_CONST(0x1, FUSE_SPARE_ENDIS_0_SPARE_ENDIS_SHIFT)
#define FUSE_SPARE_ENDIS_0_SPARE_ENDIS_RANGE                    0:0
#define FUSE_SPARE_ENDIS_0_SPARE_ENDIS_WOFFSET                  0x0
#define FUSE_SPARE_ENDIS_0_SPARE_ENDIS_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_ENDIS_0_SPARE_ENDIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_SPARE_ENDIS_0_SPARE_ENDIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_SPARE_ENDIS_0_SPARE_ENDIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_ENDIS_0_SPARE_ENDIS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_ENDIS_0_SPARE_ENDIS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_ECO_RESERVE_0_0
#define FUSE_ECO_RESERVE_0_0                    _MK_ADDR_CONST(0x2f8)
#define FUSE_ECO_RESERVE_0_0_SECURE                     0x0
#define FUSE_ECO_RESERVE_0_0_DUAL                       0x0
#define FUSE_ECO_RESERVE_0_0_SCR                        0
#define FUSE_ECO_RESERVE_0_0_WORD_COUNT                         0x1
#define FUSE_ECO_RESERVE_0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_ECO_RESERVE_0_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_ECO_RESERVE_0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_ECO_RESERVE_0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_ECO_RESERVE_0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_ECO_RESERVE_0_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_ECO_RESERVE_0_0_ECO_RESERVE_0_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_ECO_RESERVE_0_0_ECO_RESERVE_0_FIELD                        _MK_FIELD_CONST(0xffffffff, FUSE_ECO_RESERVE_0_0_ECO_RESERVE_0_SHIFT)
#define FUSE_ECO_RESERVE_0_0_ECO_RESERVE_0_RANGE                        31:0
#define FUSE_ECO_RESERVE_0_0_ECO_RESERVE_0_WOFFSET                      0x0
#define FUSE_ECO_RESERVE_0_0_ECO_RESERVE_0_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_ECO_RESERVE_0_0_ECO_RESERVE_0_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define FUSE_ECO_RESERVE_0_0_ECO_RESERVE_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_ECO_RESERVE_0_0_ECO_RESERVE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_ECO_RESERVE_0_0_ECO_RESERVE_0_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_ECO_RESERVE_0_0_ECO_RESERVE_0_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Reserved address 0x2fc

// Reserved address 0x300

// Register FUSE_USB3_RCM_CALIB0_0
#define FUSE_USB3_RCM_CALIB0_0                  _MK_ADDR_CONST(0x304)
#define FUSE_USB3_RCM_CALIB0_0_SECURE                   0x0
#define FUSE_USB3_RCM_CALIB0_0_DUAL                     0x0
#define FUSE_USB3_RCM_CALIB0_0_SCR                      0
#define FUSE_USB3_RCM_CALIB0_0_WORD_COUNT                       0x1
#define FUSE_USB3_RCM_CALIB0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_USB3_RCM_CALIB0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_USB3_RCM_CALIB0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_USB3_RCM_CALIB0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_USB3_RCM_CALIB0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_USB3_RCM_CALIB0_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_USB3_RCM_CALIB0_0_USB3_RCM_CALIB0_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_USB3_RCM_CALIB0_0_USB3_RCM_CALIB0_FIELD                    _MK_FIELD_CONST(0xffffffff, FUSE_USB3_RCM_CALIB0_0_USB3_RCM_CALIB0_SHIFT)
#define FUSE_USB3_RCM_CALIB0_0_USB3_RCM_CALIB0_RANGE                    31:0
#define FUSE_USB3_RCM_CALIB0_0_USB3_RCM_CALIB0_WOFFSET                  0x0
#define FUSE_USB3_RCM_CALIB0_0_USB3_RCM_CALIB0_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_USB3_RCM_CALIB0_0_USB3_RCM_CALIB0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_USB3_RCM_CALIB0_0_USB3_RCM_CALIB0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_USB3_RCM_CALIB0_0_USB3_RCM_CALIB0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_USB3_RCM_CALIB0_0_USB3_RCM_CALIB0_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_USB3_RCM_CALIB0_0_USB3_RCM_CALIB0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_USB3_RCM_CALIB1_0
#define FUSE_USB3_RCM_CALIB1_0                  _MK_ADDR_CONST(0x308)
#define FUSE_USB3_RCM_CALIB1_0_SECURE                   0x0
#define FUSE_USB3_RCM_CALIB1_0_DUAL                     0x0
#define FUSE_USB3_RCM_CALIB1_0_SCR                      0
#define FUSE_USB3_RCM_CALIB1_0_WORD_COUNT                       0x1
#define FUSE_USB3_RCM_CALIB1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_USB3_RCM_CALIB1_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_USB3_RCM_CALIB1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_USB3_RCM_CALIB1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_USB3_RCM_CALIB1_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_USB3_RCM_CALIB1_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_USB3_RCM_CALIB1_0_USB3_RCM_CALIB1_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_USB3_RCM_CALIB1_0_USB3_RCM_CALIB1_FIELD                    _MK_FIELD_CONST(0xffffffff, FUSE_USB3_RCM_CALIB1_0_USB3_RCM_CALIB1_SHIFT)
#define FUSE_USB3_RCM_CALIB1_0_USB3_RCM_CALIB1_RANGE                    31:0
#define FUSE_USB3_RCM_CALIB1_0_USB3_RCM_CALIB1_WOFFSET                  0x0
#define FUSE_USB3_RCM_CALIB1_0_USB3_RCM_CALIB1_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_USB3_RCM_CALIB1_0_USB3_RCM_CALIB1_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_USB3_RCM_CALIB1_0_USB3_RCM_CALIB1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_USB3_RCM_CALIB1_0_USB3_RCM_CALIB1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_USB3_RCM_CALIB1_0_USB3_RCM_CALIB1_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_USB3_RCM_CALIB1_0_USB3_RCM_CALIB1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_TPC_DISABLE_0
#define FUSE_OPT_TPC_DISABLE_0                  _MK_ADDR_CONST(0x30c)
#define FUSE_OPT_TPC_DISABLE_0_SECURE                   0x0
#define FUSE_OPT_TPC_DISABLE_0_DUAL                     0x0
#define FUSE_OPT_TPC_DISABLE_0_SCR                      0
#define FUSE_OPT_TPC_DISABLE_0_WORD_COUNT                       0x1
#define FUSE_OPT_TPC_DISABLE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_TPC_DISABLE_0_RESET_MASK                       _MK_MASK_CONST(0xf)
#define FUSE_OPT_TPC_DISABLE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_TPC_DISABLE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_TPC_DISABLE_0_READ_MASK                        _MK_MASK_CONST(0xf)
#define FUSE_OPT_TPC_DISABLE_0_WRITE_MASK                       _MK_MASK_CONST(0xf)
#define FUSE_OPT_TPC_DISABLE_0_OPT_TPC_DISABLE_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_TPC_DISABLE_0_OPT_TPC_DISABLE_FIELD                    _MK_FIELD_CONST(0xf, FUSE_OPT_TPC_DISABLE_0_OPT_TPC_DISABLE_SHIFT)
#define FUSE_OPT_TPC_DISABLE_0_OPT_TPC_DISABLE_RANGE                    3:0
#define FUSE_OPT_TPC_DISABLE_0_OPT_TPC_DISABLE_WOFFSET                  0x0
#define FUSE_OPT_TPC_DISABLE_0_OPT_TPC_DISABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_TPC_DISABLE_0_OPT_TPC_DISABLE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define FUSE_OPT_TPC_DISABLE_0_OPT_TPC_DISABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_TPC_DISABLE_0_OPT_TPC_DISABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_TPC_DISABLE_0_OPT_TPC_DISABLE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_TPC_DISABLE_0_OPT_TPC_DISABLE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_TPC_DISABLE_CP_0
#define FUSE_OPT_TPC_DISABLE_CP_0                       _MK_ADDR_CONST(0x310)
#define FUSE_OPT_TPC_DISABLE_CP_0_SECURE                        0x0
#define FUSE_OPT_TPC_DISABLE_CP_0_DUAL                  0x0
#define FUSE_OPT_TPC_DISABLE_CP_0_SCR                   0
#define FUSE_OPT_TPC_DISABLE_CP_0_WORD_COUNT                    0x1
#define FUSE_OPT_TPC_DISABLE_CP_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_TPC_DISABLE_CP_0_RESET_MASK                    _MK_MASK_CONST(0xf)
#define FUSE_OPT_TPC_DISABLE_CP_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_TPC_DISABLE_CP_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_TPC_DISABLE_CP_0_READ_MASK                     _MK_MASK_CONST(0xf)
#define FUSE_OPT_TPC_DISABLE_CP_0_WRITE_MASK                    _MK_MASK_CONST(0xf)
#define FUSE_OPT_TPC_DISABLE_CP_0_OPT_TPC_DISABLE_CP_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_TPC_DISABLE_CP_0_OPT_TPC_DISABLE_CP_FIELD                      _MK_FIELD_CONST(0xf, FUSE_OPT_TPC_DISABLE_CP_0_OPT_TPC_DISABLE_CP_SHIFT)
#define FUSE_OPT_TPC_DISABLE_CP_0_OPT_TPC_DISABLE_CP_RANGE                      3:0
#define FUSE_OPT_TPC_DISABLE_CP_0_OPT_TPC_DISABLE_CP_WOFFSET                    0x0
#define FUSE_OPT_TPC_DISABLE_CP_0_OPT_TPC_DISABLE_CP_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_TPC_DISABLE_CP_0_OPT_TPC_DISABLE_CP_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define FUSE_OPT_TPC_DISABLE_CP_0_OPT_TPC_DISABLE_CP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_TPC_DISABLE_CP_0_OPT_TPC_DISABLE_CP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_TPC_DISABLE_CP_0_OPT_TPC_DISABLE_CP_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_TPC_DISABLE_CP_0_OPT_TPC_DISABLE_CP_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_CCPLEX_CORE_DISABLE_0
#define FUSE_OPT_CCPLEX_CORE_DISABLE_0                  _MK_ADDR_CONST(0x314)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_0_SECURE                   0x0
#define FUSE_OPT_CCPLEX_CORE_DISABLE_0_DUAL                     0x0
#define FUSE_OPT_CCPLEX_CORE_DISABLE_0_SCR                      0
#define FUSE_OPT_CCPLEX_CORE_DISABLE_0_WORD_COUNT                       0x1
#define FUSE_OPT_CCPLEX_CORE_DISABLE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_0_OPT_CCPLEX_CORE_DISABLE_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_0_OPT_CCPLEX_CORE_DISABLE_FIELD                    _MK_FIELD_CONST(0xff, FUSE_OPT_CCPLEX_CORE_DISABLE_0_OPT_CCPLEX_CORE_DISABLE_SHIFT)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_0_OPT_CCPLEX_CORE_DISABLE_RANGE                    7:0
#define FUSE_OPT_CCPLEX_CORE_DISABLE_0_OPT_CCPLEX_CORE_DISABLE_WOFFSET                  0x0
#define FUSE_OPT_CCPLEX_CORE_DISABLE_0_OPT_CCPLEX_CORE_DISABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_0_OPT_CCPLEX_CORE_DISABLE_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_0_OPT_CCPLEX_CORE_DISABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_0_OPT_CCPLEX_CORE_DISABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_0_OPT_CCPLEX_CORE_DISABLE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_0_OPT_CCPLEX_CORE_DISABLE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_CCPLEX_CORE_DISABLE_CP_0
#define FUSE_OPT_CCPLEX_CORE_DISABLE_CP_0                       _MK_ADDR_CONST(0x318)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_CP_0_SECURE                        0x0
#define FUSE_OPT_CCPLEX_CORE_DISABLE_CP_0_DUAL                  0x0
#define FUSE_OPT_CCPLEX_CORE_DISABLE_CP_0_SCR                   0
#define FUSE_OPT_CCPLEX_CORE_DISABLE_CP_0_WORD_COUNT                    0x1
#define FUSE_OPT_CCPLEX_CORE_DISABLE_CP_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_CP_0_RESET_MASK                    _MK_MASK_CONST(0xff)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_CP_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_CP_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_CP_0_READ_MASK                     _MK_MASK_CONST(0xff)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_CP_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_CP_0_OPT_CCPLEX_CORE_DISABLE_CP_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_CP_0_OPT_CCPLEX_CORE_DISABLE_CP_FIELD                      _MK_FIELD_CONST(0xff, FUSE_OPT_CCPLEX_CORE_DISABLE_CP_0_OPT_CCPLEX_CORE_DISABLE_CP_SHIFT)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_CP_0_OPT_CCPLEX_CORE_DISABLE_CP_RANGE                      7:0
#define FUSE_OPT_CCPLEX_CORE_DISABLE_CP_0_OPT_CCPLEX_CORE_DISABLE_CP_WOFFSET                    0x0
#define FUSE_OPT_CCPLEX_CORE_DISABLE_CP_0_OPT_CCPLEX_CORE_DISABLE_CP_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_CP_0_OPT_CCPLEX_CORE_DISABLE_CP_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_CP_0_OPT_CCPLEX_CORE_DISABLE_CP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_CP_0_OPT_CCPLEX_CORE_DISABLE_CP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_CP_0_OPT_CCPLEX_CORE_DISABLE_CP_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_CORE_DISABLE_CP_0_OPT_CCPLEX_CORE_DISABLE_CP_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_TSENSOR9_CALIB_0
#define FUSE_TSENSOR9_CALIB_0                   _MK_ADDR_CONST(0x31c)
#define FUSE_TSENSOR9_CALIB_0_SECURE                    0x0
#define FUSE_TSENSOR9_CALIB_0_DUAL                      0x0
#define FUSE_TSENSOR9_CALIB_0_SCR                       0
#define FUSE_TSENSOR9_CALIB_0_WORD_COUNT                        0x1
#define FUSE_TSENSOR9_CALIB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR9_CALIB_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR9_CALIB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR9_CALIB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR9_CALIB_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR9_CALIB_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR9_CALIB_0_TSENSOR9_CALIB_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_TSENSOR9_CALIB_0_TSENSOR9_CALIB_FIELD                      _MK_FIELD_CONST(0xffffffff, FUSE_TSENSOR9_CALIB_0_TSENSOR9_CALIB_SHIFT)
#define FUSE_TSENSOR9_CALIB_0_TSENSOR9_CALIB_RANGE                      31:0
#define FUSE_TSENSOR9_CALIB_0_TSENSOR9_CALIB_WOFFSET                    0x0
#define FUSE_TSENSOR9_CALIB_0_TSENSOR9_CALIB_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR9_CALIB_0_TSENSOR9_CALIB_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR9_CALIB_0_TSENSOR9_CALIB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR9_CALIB_0_TSENSOR9_CALIB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR9_CALIB_0_TSENSOR9_CALIB_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR9_CALIB_0_TSENSOR9_CALIB_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_TSENSOR10_CALIB_0
#define FUSE_TSENSOR10_CALIB_0                  _MK_ADDR_CONST(0x320)
#define FUSE_TSENSOR10_CALIB_0_SECURE                   0x0
#define FUSE_TSENSOR10_CALIB_0_DUAL                     0x0
#define FUSE_TSENSOR10_CALIB_0_SCR                      0
#define FUSE_TSENSOR10_CALIB_0_WORD_COUNT                       0x1
#define FUSE_TSENSOR10_CALIB_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR10_CALIB_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR10_CALIB_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR10_CALIB_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR10_CALIB_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR10_CALIB_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR10_CALIB_0_TSENSOR10_CALIB_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_TSENSOR10_CALIB_0_TSENSOR10_CALIB_FIELD                    _MK_FIELD_CONST(0xffffffff, FUSE_TSENSOR10_CALIB_0_TSENSOR10_CALIB_SHIFT)
#define FUSE_TSENSOR10_CALIB_0_TSENSOR10_CALIB_RANGE                    31:0
#define FUSE_TSENSOR10_CALIB_0_TSENSOR10_CALIB_WOFFSET                  0x0
#define FUSE_TSENSOR10_CALIB_0_TSENSOR10_CALIB_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR10_CALIB_0_TSENSOR10_CALIB_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR10_CALIB_0_TSENSOR10_CALIB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR10_CALIB_0_TSENSOR10_CALIB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR10_CALIB_0_TSENSOR10_CALIB_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR10_CALIB_0_TSENSOR10_CALIB_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Reserved address 0x324

// Reserved address 0x328

// Reserved address 0x32c

// Reserved address 0x330

// Reserved address 0x334

// Reserved address 0x338

// Reserved address 0x33c

// Reserved address 0x340

// Reserved address 0x344

// Reserved address 0x348

// Reserved address 0x34c

// Register FUSE_USB_CALIB_EXT_0
#define FUSE_USB_CALIB_EXT_0                    _MK_ADDR_CONST(0x350)
#define FUSE_USB_CALIB_EXT_0_SECURE                     0x0
#define FUSE_USB_CALIB_EXT_0_DUAL                       0x0
#define FUSE_USB_CALIB_EXT_0_SCR                        0
#define FUSE_USB_CALIB_EXT_0_WORD_COUNT                         0x1
#define FUSE_USB_CALIB_EXT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_USB_CALIB_EXT_0_RESET_MASK                         _MK_MASK_CONST(0x1ffff)
#define FUSE_USB_CALIB_EXT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_USB_CALIB_EXT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_USB_CALIB_EXT_0_READ_MASK                  _MK_MASK_CONST(0x1ffff)
#define FUSE_USB_CALIB_EXT_0_WRITE_MASK                         _MK_MASK_CONST(0x1ffff)
#define FUSE_USB_CALIB_EXT_0_USB_CALIB_EXT_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_USB_CALIB_EXT_0_USB_CALIB_EXT_FIELD                        _MK_FIELD_CONST(0x1ffff, FUSE_USB_CALIB_EXT_0_USB_CALIB_EXT_SHIFT)
#define FUSE_USB_CALIB_EXT_0_USB_CALIB_EXT_RANGE                        16:0
#define FUSE_USB_CALIB_EXT_0_USB_CALIB_EXT_WOFFSET                      0x0
#define FUSE_USB_CALIB_EXT_0_USB_CALIB_EXT_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_USB_CALIB_EXT_0_USB_CALIB_EXT_DEFAULT_MASK                 _MK_MASK_CONST(0x1ffff)
#define FUSE_USB_CALIB_EXT_0_USB_CALIB_EXT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_USB_CALIB_EXT_0_USB_CALIB_EXT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_USB_CALIB_EXT_0_USB_CALIB_EXT_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_USB_CALIB_EXT_0_USB_CALIB_EXT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_HYPERVOLTAGING_0
#define FUSE_HYPERVOLTAGING_0                   _MK_ADDR_CONST(0x354)
#define FUSE_HYPERVOLTAGING_0_SECURE                    0x0
#define FUSE_HYPERVOLTAGING_0_DUAL                      0x0
#define FUSE_HYPERVOLTAGING_0_SCR                       0
#define FUSE_HYPERVOLTAGING_0_WORD_COUNT                        0x1
#define FUSE_HYPERVOLTAGING_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_HYPERVOLTAGING_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_HYPERVOLTAGING_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_HYPERVOLTAGING_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_HYPERVOLTAGING_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_HYPERVOLTAGING_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_HYPERVOLTAGING_0_HYPERVOLTAGING_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_HYPERVOLTAGING_0_HYPERVOLTAGING_FIELD                      _MK_FIELD_CONST(0xffffffff, FUSE_HYPERVOLTAGING_0_HYPERVOLTAGING_SHIFT)
#define FUSE_HYPERVOLTAGING_0_HYPERVOLTAGING_RANGE                      31:0
#define FUSE_HYPERVOLTAGING_0_HYPERVOLTAGING_WOFFSET                    0x0
#define FUSE_HYPERVOLTAGING_0_HYPERVOLTAGING_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_HYPERVOLTAGING_0_HYPERVOLTAGING_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_HYPERVOLTAGING_0_HYPERVOLTAGING_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_HYPERVOLTAGING_0_HYPERVOLTAGING_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_HYPERVOLTAGING_0_HYPERVOLTAGING_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_HYPERVOLTAGING_0_HYPERVOLTAGING_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_ECC_EN_0
#define FUSE_OPT_ECC_EN_0                       _MK_ADDR_CONST(0x358)
#define FUSE_OPT_ECC_EN_0_SECURE                        0x0
#define FUSE_OPT_ECC_EN_0_DUAL                  0x0
#define FUSE_OPT_ECC_EN_0_SCR                   0
#define FUSE_OPT_ECC_EN_0_WORD_COUNT                    0x1
#define FUSE_OPT_ECC_EN_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_ECC_EN_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_OPT_ECC_EN_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_ECC_EN_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_ECC_EN_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_OPT_ECC_EN_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_OPT_ECC_EN_0_OPT_ECC_EN_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_ECC_EN_0_OPT_ECC_EN_FIELD                      _MK_FIELD_CONST(0x1, FUSE_OPT_ECC_EN_0_OPT_ECC_EN_SHIFT)
#define FUSE_OPT_ECC_EN_0_OPT_ECC_EN_RANGE                      0:0
#define FUSE_OPT_ECC_EN_0_OPT_ECC_EN_WOFFSET                    0x0
#define FUSE_OPT_ECC_EN_0_OPT_ECC_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_ECC_EN_0_OPT_ECC_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_OPT_ECC_EN_0_OPT_ECC_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_ECC_EN_0_OPT_ECC_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_ECC_EN_0_OPT_ECC_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_ECC_EN_0_OPT_ECC_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_TSENSOR_COMMON_T2_0
#define FUSE_TSENSOR_COMMON_T2_0                        _MK_ADDR_CONST(0x35c)
#define FUSE_TSENSOR_COMMON_T2_0_SECURE                         0x0
#define FUSE_TSENSOR_COMMON_T2_0_DUAL                   0x0
#define FUSE_TSENSOR_COMMON_T2_0_SCR                    0
#define FUSE_TSENSOR_COMMON_T2_0_WORD_COUNT                     0x1
#define FUSE_TSENSOR_COMMON_T2_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR_COMMON_T2_0_RESET_MASK                     _MK_MASK_CONST(0x7ffff)
#define FUSE_TSENSOR_COMMON_T2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR_COMMON_T2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR_COMMON_T2_0_READ_MASK                      _MK_MASK_CONST(0x7ffff)
#define FUSE_TSENSOR_COMMON_T2_0_WRITE_MASK                     _MK_MASK_CONST(0x7ffff)
#define FUSE_TSENSOR_COMMON_T2_0_TSENSOR_COMMON_T2_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_TSENSOR_COMMON_T2_0_TSENSOR_COMMON_T2_FIELD                        _MK_FIELD_CONST(0x7ffff, FUSE_TSENSOR_COMMON_T2_0_TSENSOR_COMMON_T2_SHIFT)
#define FUSE_TSENSOR_COMMON_T2_0_TSENSOR_COMMON_T2_RANGE                        18:0
#define FUSE_TSENSOR_COMMON_T2_0_TSENSOR_COMMON_T2_WOFFSET                      0x0
#define FUSE_TSENSOR_COMMON_T2_0_TSENSOR_COMMON_T2_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR_COMMON_T2_0_TSENSOR_COMMON_T2_DEFAULT_MASK                 _MK_MASK_CONST(0x7ffff)
#define FUSE_TSENSOR_COMMON_T2_0_TSENSOR_COMMON_T2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR_COMMON_T2_0_TSENSOR_COMMON_T2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR_COMMON_T2_0_TSENSOR_COMMON_T2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR_COMMON_T2_0_TSENSOR_COMMON_T2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_TSENSOR_COMMON_T3_0
#define FUSE_TSENSOR_COMMON_T3_0                        _MK_ADDR_CONST(0x360)
#define FUSE_TSENSOR_COMMON_T3_0_SECURE                         0x0
#define FUSE_TSENSOR_COMMON_T3_0_DUAL                   0x0
#define FUSE_TSENSOR_COMMON_T3_0_SCR                    0
#define FUSE_TSENSOR_COMMON_T3_0_WORD_COUNT                     0x1
#define FUSE_TSENSOR_COMMON_T3_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR_COMMON_T3_0_RESET_MASK                     _MK_MASK_CONST(0x7ffff)
#define FUSE_TSENSOR_COMMON_T3_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR_COMMON_T3_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR_COMMON_T3_0_READ_MASK                      _MK_MASK_CONST(0x7ffff)
#define FUSE_TSENSOR_COMMON_T3_0_WRITE_MASK                     _MK_MASK_CONST(0x7ffff)
#define FUSE_TSENSOR_COMMON_T3_0_TSENSOR_COMMON_T3_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_TSENSOR_COMMON_T3_0_TSENSOR_COMMON_T3_FIELD                        _MK_FIELD_CONST(0x7ffff, FUSE_TSENSOR_COMMON_T3_0_TSENSOR_COMMON_T3_SHIFT)
#define FUSE_TSENSOR_COMMON_T3_0_TSENSOR_COMMON_T3_RANGE                        18:0
#define FUSE_TSENSOR_COMMON_T3_0_TSENSOR_COMMON_T3_WOFFSET                      0x0
#define FUSE_TSENSOR_COMMON_T3_0_TSENSOR_COMMON_T3_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR_COMMON_T3_0_TSENSOR_COMMON_T3_DEFAULT_MASK                 _MK_MASK_CONST(0x7ffff)
#define FUSE_TSENSOR_COMMON_T3_0_TSENSOR_COMMON_T3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR_COMMON_T3_0_TSENSOR_COMMON_T3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR_COMMON_T3_0_TSENSOR_COMMON_T3_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR_COMMON_T3_0_TSENSOR_COMMON_T3_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_CCPLEX_UCODE_NV_REV_0
#define FUSE_CCPLEX_UCODE_NV_REV_0                      _MK_ADDR_CONST(0x364)
#define FUSE_CCPLEX_UCODE_NV_REV_0_SECURE                       0x0
#define FUSE_CCPLEX_UCODE_NV_REV_0_DUAL                         0x0
#define FUSE_CCPLEX_UCODE_NV_REV_0_SCR                  0
#define FUSE_CCPLEX_UCODE_NV_REV_0_WORD_COUNT                   0x1
#define FUSE_CCPLEX_UCODE_NV_REV_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_NV_REV_0_RESET_MASK                   _MK_MASK_CONST(0x7f)
#define FUSE_CCPLEX_UCODE_NV_REV_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_NV_REV_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_NV_REV_0_READ_MASK                    _MK_MASK_CONST(0x7f)
#define FUSE_CCPLEX_UCODE_NV_REV_0_WRITE_MASK                   _MK_MASK_CONST(0x7f)
#define FUSE_CCPLEX_UCODE_NV_REV_0_CCPLEX_UCODE_NV_REV_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_CCPLEX_UCODE_NV_REV_0_CCPLEX_UCODE_NV_REV_FIELD                    _MK_FIELD_CONST(0x7f, FUSE_CCPLEX_UCODE_NV_REV_0_CCPLEX_UCODE_NV_REV_SHIFT)
#define FUSE_CCPLEX_UCODE_NV_REV_0_CCPLEX_UCODE_NV_REV_RANGE                    6:0
#define FUSE_CCPLEX_UCODE_NV_REV_0_CCPLEX_UCODE_NV_REV_WOFFSET                  0x0
#define FUSE_CCPLEX_UCODE_NV_REV_0_CCPLEX_UCODE_NV_REV_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_NV_REV_0_CCPLEX_UCODE_NV_REV_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
#define FUSE_CCPLEX_UCODE_NV_REV_0_CCPLEX_UCODE_NV_REV_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_NV_REV_0_CCPLEX_UCODE_NV_REV_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_NV_REV_0_CCPLEX_UCODE_NV_REV_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_NV_REV_0_CCPLEX_UCODE_NV_REV_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_0
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_0                     _MK_ADDR_CONST(0x368)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_0_SECURE                      0x0
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_0_DUAL                        0x0
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_0_SCR                         0
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_0_WORD_COUNT                  0x1
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_FIELD                  _MK_FIELD_CONST(0xffffffff, FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_SHIFT)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_RANGE                  31:0
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_WOFFSET                        0x0
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_CCPLEX_DFD_AUTH_REQD_0
#define FUSE_CCPLEX_DFD_AUTH_REQD_0                     _MK_ADDR_CONST(0x36c)
#define FUSE_CCPLEX_DFD_AUTH_REQD_0_SECURE                      0x0
#define FUSE_CCPLEX_DFD_AUTH_REQD_0_DUAL                        0x0
#define FUSE_CCPLEX_DFD_AUTH_REQD_0_SCR                         0
#define FUSE_CCPLEX_DFD_AUTH_REQD_0_WORD_COUNT                  0x1
#define FUSE_CCPLEX_DFD_AUTH_REQD_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_DFD_AUTH_REQD_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_CCPLEX_DFD_AUTH_REQD_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_DFD_AUTH_REQD_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_DFD_AUTH_REQD_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_CCPLEX_DFD_AUTH_REQD_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_CCPLEX_DFD_AUTH_REQD_0_CCPLEX_DFD_AUTH_REQD_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_CCPLEX_DFD_AUTH_REQD_0_CCPLEX_DFD_AUTH_REQD_FIELD                  _MK_FIELD_CONST(0x1, FUSE_CCPLEX_DFD_AUTH_REQD_0_CCPLEX_DFD_AUTH_REQD_SHIFT)
#define FUSE_CCPLEX_DFD_AUTH_REQD_0_CCPLEX_DFD_AUTH_REQD_RANGE                  0:0
#define FUSE_CCPLEX_DFD_AUTH_REQD_0_CCPLEX_DFD_AUTH_REQD_WOFFSET                        0x0
#define FUSE_CCPLEX_DFD_AUTH_REQD_0_CCPLEX_DFD_AUTH_REQD_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_DFD_AUTH_REQD_0_CCPLEX_DFD_AUTH_REQD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_CCPLEX_DFD_AUTH_REQD_0_CCPLEX_DFD_AUTH_REQD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_DFD_AUTH_REQD_0_CCPLEX_DFD_AUTH_REQD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_DFD_AUTH_REQD_0_CCPLEX_DFD_AUTH_REQD_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_DFD_AUTH_REQD_0_CCPLEX_DFD_AUTH_REQD_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Reserved address 0x370

// Register FUSE_VMIN_SENSOR_CALIBRATION_0
#define FUSE_VMIN_SENSOR_CALIBRATION_0                  _MK_ADDR_CONST(0x374)
#define FUSE_VMIN_SENSOR_CALIBRATION_0_SECURE                   0x0
#define FUSE_VMIN_SENSOR_CALIBRATION_0_DUAL                     0x0
#define FUSE_VMIN_SENSOR_CALIBRATION_0_SCR                      0
#define FUSE_VMIN_SENSOR_CALIBRATION_0_WORD_COUNT                       0x1
#define FUSE_VMIN_SENSOR_CALIBRATION_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_VMIN_SENSOR_CALIBRATION_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_VMIN_SENSOR_CALIBRATION_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_VMIN_SENSOR_CALIBRATION_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_VMIN_SENSOR_CALIBRATION_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_VMIN_SENSOR_CALIBRATION_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_VMIN_SENSOR_CALIBRATION_0_VMIN_SENSOR_CALIBRATION_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_VMIN_SENSOR_CALIBRATION_0_VMIN_SENSOR_CALIBRATION_FIELD                    _MK_FIELD_CONST(0xffffffff, FUSE_VMIN_SENSOR_CALIBRATION_0_VMIN_SENSOR_CALIBRATION_SHIFT)
#define FUSE_VMIN_SENSOR_CALIBRATION_0_VMIN_SENSOR_CALIBRATION_RANGE                    31:0
#define FUSE_VMIN_SENSOR_CALIBRATION_0_VMIN_SENSOR_CALIBRATION_WOFFSET                  0x0
#define FUSE_VMIN_SENSOR_CALIBRATION_0_VMIN_SENSOR_CALIBRATION_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_VMIN_SENSOR_CALIBRATION_0_VMIN_SENSOR_CALIBRATION_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_VMIN_SENSOR_CALIBRATION_0_VMIN_SENSOR_CALIBRATION_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_VMIN_SENSOR_CALIBRATION_0_VMIN_SENSOR_CALIBRATION_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_VMIN_SENSOR_CALIBRATION_0_VMIN_SENSOR_CALIBRATION_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_VMIN_SENSOR_CALIBRATION_0_VMIN_SENSOR_CALIBRATION_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_CCPLEX_L2S_DISABLE_0
#define FUSE_OPT_CCPLEX_L2S_DISABLE_0                   _MK_ADDR_CONST(0x378)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_0_SECURE                    0x0
#define FUSE_OPT_CCPLEX_L2S_DISABLE_0_DUAL                      0x0
#define FUSE_OPT_CCPLEX_L2S_DISABLE_0_SCR                       0
#define FUSE_OPT_CCPLEX_L2S_DISABLE_0_WORD_COUNT                        0x1
#define FUSE_OPT_CCPLEX_L2S_DISABLE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_0_RESET_MASK                        _MK_MASK_CONST(0xf)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_0_READ_MASK                         _MK_MASK_CONST(0xf)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_0_WRITE_MASK                        _MK_MASK_CONST(0xf)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_0_OPT_CCPLEX_L2S_DISABLE_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_0_OPT_CCPLEX_L2S_DISABLE_FIELD                      _MK_FIELD_CONST(0xf, FUSE_OPT_CCPLEX_L2S_DISABLE_0_OPT_CCPLEX_L2S_DISABLE_SHIFT)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_0_OPT_CCPLEX_L2S_DISABLE_RANGE                      3:0
#define FUSE_OPT_CCPLEX_L2S_DISABLE_0_OPT_CCPLEX_L2S_DISABLE_WOFFSET                    0x0
#define FUSE_OPT_CCPLEX_L2S_DISABLE_0_OPT_CCPLEX_L2S_DISABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_0_OPT_CCPLEX_L2S_DISABLE_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_0_OPT_CCPLEX_L2S_DISABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_0_OPT_CCPLEX_L2S_DISABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_0_OPT_CCPLEX_L2S_DISABLE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_0_OPT_CCPLEX_L2S_DISABLE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_CCPLEX_L2S_DISABLE_CP_0
#define FUSE_OPT_CCPLEX_L2S_DISABLE_CP_0                        _MK_ADDR_CONST(0x37c)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_CP_0_SECURE                         0x0
#define FUSE_OPT_CCPLEX_L2S_DISABLE_CP_0_DUAL                   0x0
#define FUSE_OPT_CCPLEX_L2S_DISABLE_CP_0_SCR                    0
#define FUSE_OPT_CCPLEX_L2S_DISABLE_CP_0_WORD_COUNT                     0x1
#define FUSE_OPT_CCPLEX_L2S_DISABLE_CP_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_CP_0_RESET_MASK                     _MK_MASK_CONST(0xf)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_CP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_CP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_CP_0_READ_MASK                      _MK_MASK_CONST(0xf)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_CP_0_WRITE_MASK                     _MK_MASK_CONST(0xf)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_CP_0_OPT_CCPLEX_L2S_DISABLE_CP_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_CP_0_OPT_CCPLEX_L2S_DISABLE_CP_FIELD                        _MK_FIELD_CONST(0xf, FUSE_OPT_CCPLEX_L2S_DISABLE_CP_0_OPT_CCPLEX_L2S_DISABLE_CP_SHIFT)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_CP_0_OPT_CCPLEX_L2S_DISABLE_CP_RANGE                        3:0
#define FUSE_OPT_CCPLEX_L2S_DISABLE_CP_0_OPT_CCPLEX_L2S_DISABLE_CP_WOFFSET                      0x0
#define FUSE_OPT_CCPLEX_L2S_DISABLE_CP_0_OPT_CCPLEX_L2S_DISABLE_CP_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_CP_0_OPT_CCPLEX_L2S_DISABLE_CP_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_CP_0_OPT_CCPLEX_L2S_DISABLE_CP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_CP_0_OPT_CCPLEX_L2S_DISABLE_CP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_CP_0_OPT_CCPLEX_L2S_DISABLE_CP_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_CCPLEX_L2S_DISABLE_CP_0_OPT_CCPLEX_L2S_DISABLE_CP_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Reserved address 0x380

// Reserved address 0x384

// Reserved address 0x388

// Reserved address 0x38c

// Register FUSE_EK0_0
#define FUSE_EK0_0                      _MK_ADDR_CONST(0x390)
#define FUSE_EK0_0_SECURE                       0x0
#define FUSE_EK0_0_DUAL                         0x0
#define FUSE_EK0_0_SCR                  0
#define FUSE_EK0_0_WORD_COUNT                   0x1
#define FUSE_EK0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_EK0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_EK0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_EK0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_EK0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define FUSE_EK0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_EK0_0_EK0_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_EK0_0_EK0_FIELD                    _MK_FIELD_CONST(0xffffffff, FUSE_EK0_0_EK0_SHIFT)
#define FUSE_EK0_0_EK0_RANGE                    31:0
#define FUSE_EK0_0_EK0_WOFFSET                  0x0
#define FUSE_EK0_0_EK0_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_EK0_0_EK0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_EK0_0_EK0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_EK0_0_EK0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_EK0_0_EK0_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_EK0_0_EK0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_EK1_0
#define FUSE_EK1_0                      _MK_ADDR_CONST(0x394)
#define FUSE_EK1_0_SECURE                       0x0
#define FUSE_EK1_0_DUAL                         0x0
#define FUSE_EK1_0_SCR                  0
#define FUSE_EK1_0_WORD_COUNT                   0x1
#define FUSE_EK1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_EK1_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_EK1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_EK1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_EK1_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define FUSE_EK1_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_EK1_0_EK1_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_EK1_0_EK1_FIELD                    _MK_FIELD_CONST(0xffffffff, FUSE_EK1_0_EK1_SHIFT)
#define FUSE_EK1_0_EK1_RANGE                    31:0
#define FUSE_EK1_0_EK1_WOFFSET                  0x0
#define FUSE_EK1_0_EK1_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_EK1_0_EK1_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_EK1_0_EK1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_EK1_0_EK1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_EK1_0_EK1_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_EK1_0_EK1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_EK2_0
#define FUSE_EK2_0                      _MK_ADDR_CONST(0x398)
#define FUSE_EK2_0_SECURE                       0x0
#define FUSE_EK2_0_DUAL                         0x0
#define FUSE_EK2_0_SCR                  0
#define FUSE_EK2_0_WORD_COUNT                   0x1
#define FUSE_EK2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_EK2_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_EK2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_EK2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_EK2_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define FUSE_EK2_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_EK2_0_EK2_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_EK2_0_EK2_FIELD                    _MK_FIELD_CONST(0xffffffff, FUSE_EK2_0_EK2_SHIFT)
#define FUSE_EK2_0_EK2_RANGE                    31:0
#define FUSE_EK2_0_EK2_WOFFSET                  0x0
#define FUSE_EK2_0_EK2_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_EK2_0_EK2_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_EK2_0_EK2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_EK2_0_EK2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_EK2_0_EK2_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_EK2_0_EK2_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_EK3_0
#define FUSE_EK3_0                      _MK_ADDR_CONST(0x39c)
#define FUSE_EK3_0_SECURE                       0x0
#define FUSE_EK3_0_DUAL                         0x0
#define FUSE_EK3_0_SCR                  0
#define FUSE_EK3_0_WORD_COUNT                   0x1
#define FUSE_EK3_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_EK3_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_EK3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_EK3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_EK3_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define FUSE_EK3_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_EK3_0_EK3_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_EK3_0_EK3_FIELD                    _MK_FIELD_CONST(0xffffffff, FUSE_EK3_0_EK3_SHIFT)
#define FUSE_EK3_0_EK3_RANGE                    31:0
#define FUSE_EK3_0_EK3_WOFFSET                  0x0
#define FUSE_EK3_0_EK3_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_EK3_0_EK3_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_EK3_0_EK3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_EK3_0_EK3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_EK3_0_EK3_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_EK3_0_EK3_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_EK4_0
#define FUSE_EK4_0                      _MK_ADDR_CONST(0x3a0)
#define FUSE_EK4_0_SECURE                       0x0
#define FUSE_EK4_0_DUAL                         0x0
#define FUSE_EK4_0_SCR                  0
#define FUSE_EK4_0_WORD_COUNT                   0x1
#define FUSE_EK4_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_EK4_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_EK4_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_EK4_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_EK4_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define FUSE_EK4_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_EK4_0_EK4_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_EK4_0_EK4_FIELD                    _MK_FIELD_CONST(0xffffffff, FUSE_EK4_0_EK4_SHIFT)
#define FUSE_EK4_0_EK4_RANGE                    31:0
#define FUSE_EK4_0_EK4_WOFFSET                  0x0
#define FUSE_EK4_0_EK4_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_EK4_0_EK4_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_EK4_0_EK4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_EK4_0_EK4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_EK4_0_EK4_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_EK4_0_EK4_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_EK5_0
#define FUSE_EK5_0                      _MK_ADDR_CONST(0x3a4)
#define FUSE_EK5_0_SECURE                       0x0
#define FUSE_EK5_0_DUAL                         0x0
#define FUSE_EK5_0_SCR                  0
#define FUSE_EK5_0_WORD_COUNT                   0x1
#define FUSE_EK5_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_EK5_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_EK5_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_EK5_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_EK5_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define FUSE_EK5_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_EK5_0_EK5_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_EK5_0_EK5_FIELD                    _MK_FIELD_CONST(0xffffffff, FUSE_EK5_0_EK5_SHIFT)
#define FUSE_EK5_0_EK5_RANGE                    31:0
#define FUSE_EK5_0_EK5_WOFFSET                  0x0
#define FUSE_EK5_0_EK5_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_EK5_0_EK5_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_EK5_0_EK5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_EK5_0_EK5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_EK5_0_EK5_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_EK5_0_EK5_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_EK6_0
#define FUSE_EK6_0                      _MK_ADDR_CONST(0x3a8)
#define FUSE_EK6_0_SECURE                       0x0
#define FUSE_EK6_0_DUAL                         0x0
#define FUSE_EK6_0_SCR                  0
#define FUSE_EK6_0_WORD_COUNT                   0x1
#define FUSE_EK6_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_EK6_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_EK6_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_EK6_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_EK6_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define FUSE_EK6_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_EK6_0_EK6_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_EK6_0_EK6_FIELD                    _MK_FIELD_CONST(0xffffffff, FUSE_EK6_0_EK6_SHIFT)
#define FUSE_EK6_0_EK6_RANGE                    31:0
#define FUSE_EK6_0_EK6_WOFFSET                  0x0
#define FUSE_EK6_0_EK6_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_EK6_0_EK6_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_EK6_0_EK6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_EK6_0_EK6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_EK6_0_EK6_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_EK6_0_EK6_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_EK7_0
#define FUSE_EK7_0                      _MK_ADDR_CONST(0x3ac)
#define FUSE_EK7_0_SECURE                       0x0
#define FUSE_EK7_0_DUAL                         0x0
#define FUSE_EK7_0_SCR                  0
#define FUSE_EK7_0_WORD_COUNT                   0x1
#define FUSE_EK7_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_EK7_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_EK7_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_EK7_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_EK7_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define FUSE_EK7_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_EK7_0_EK7_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_EK7_0_EK7_FIELD                    _MK_FIELD_CONST(0xffffffff, FUSE_EK7_0_EK7_SHIFT)
#define FUSE_EK7_0_EK7_RANGE                    31:0
#define FUSE_EK7_0_EK7_WOFFSET                  0x0
#define FUSE_EK7_0_EK7_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_EK7_0_EK7_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_EK7_0_EK7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_EK7_0_EK7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_EK7_0_EK7_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_EK7_0_EK7_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_PDK0_0
#define FUSE_PDK0_0                     _MK_ADDR_CONST(0x3b0)
#define FUSE_PDK0_0_SECURE                      0x0
#define FUSE_PDK0_0_DUAL                        0x0
#define FUSE_PDK0_0_SCR                         0
#define FUSE_PDK0_0_WORD_COUNT                  0x1
#define FUSE_PDK0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_PDK0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_PDK0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_PDK0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK0_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK0_0_PDK0_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_PDK0_0_PDK0_FIELD                  _MK_FIELD_CONST(0xffffffff, FUSE_PDK0_0_PDK0_SHIFT)
#define FUSE_PDK0_0_PDK0_RANGE                  31:0
#define FUSE_PDK0_0_PDK0_WOFFSET                        0x0
#define FUSE_PDK0_0_PDK0_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_PDK0_0_PDK0_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK0_0_PDK0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_PDK0_0_PDK0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_PDK0_0_PDK0_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_PDK0_0_PDK0_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_PDK1_0
#define FUSE_PDK1_0                     _MK_ADDR_CONST(0x3b4)
#define FUSE_PDK1_0_SECURE                      0x0
#define FUSE_PDK1_0_DUAL                        0x0
#define FUSE_PDK1_0_SCR                         0
#define FUSE_PDK1_0_WORD_COUNT                  0x1
#define FUSE_PDK1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_PDK1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_PDK1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_PDK1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK1_0_PDK1_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_PDK1_0_PDK1_FIELD                  _MK_FIELD_CONST(0xffffffff, FUSE_PDK1_0_PDK1_SHIFT)
#define FUSE_PDK1_0_PDK1_RANGE                  31:0
#define FUSE_PDK1_0_PDK1_WOFFSET                        0x0
#define FUSE_PDK1_0_PDK1_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_PDK1_0_PDK1_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK1_0_PDK1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_PDK1_0_PDK1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_PDK1_0_PDK1_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_PDK1_0_PDK1_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_PDK2_0
#define FUSE_PDK2_0                     _MK_ADDR_CONST(0x3b8)
#define FUSE_PDK2_0_SECURE                      0x0
#define FUSE_PDK2_0_DUAL                        0x0
#define FUSE_PDK2_0_SCR                         0
#define FUSE_PDK2_0_WORD_COUNT                  0x1
#define FUSE_PDK2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_PDK2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_PDK2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_PDK2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK2_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK2_0_PDK2_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_PDK2_0_PDK2_FIELD                  _MK_FIELD_CONST(0xffffffff, FUSE_PDK2_0_PDK2_SHIFT)
#define FUSE_PDK2_0_PDK2_RANGE                  31:0
#define FUSE_PDK2_0_PDK2_WOFFSET                        0x0
#define FUSE_PDK2_0_PDK2_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_PDK2_0_PDK2_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK2_0_PDK2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_PDK2_0_PDK2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_PDK2_0_PDK2_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_PDK2_0_PDK2_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_PDK3_0
#define FUSE_PDK3_0                     _MK_ADDR_CONST(0x3bc)
#define FUSE_PDK3_0_SECURE                      0x0
#define FUSE_PDK3_0_DUAL                        0x0
#define FUSE_PDK3_0_SCR                         0
#define FUSE_PDK3_0_WORD_COUNT                  0x1
#define FUSE_PDK3_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_PDK3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_PDK3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_PDK3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK3_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK3_0_PDK3_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_PDK3_0_PDK3_FIELD                  _MK_FIELD_CONST(0xffffffff, FUSE_PDK3_0_PDK3_SHIFT)
#define FUSE_PDK3_0_PDK3_RANGE                  31:0
#define FUSE_PDK3_0_PDK3_WOFFSET                        0x0
#define FUSE_PDK3_0_PDK3_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_PDK3_0_PDK3_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK3_0_PDK3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_PDK3_0_PDK3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_PDK3_0_PDK3_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_PDK3_0_PDK3_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_KEK00_0
#define FUSE_KEK00_0                    _MK_ADDR_CONST(0x3c0)
#define FUSE_KEK00_0_SECURE                     0x0
#define FUSE_KEK00_0_DUAL                       0x0
#define FUSE_KEK00_0_SCR                        0
#define FUSE_KEK00_0_WORD_COUNT                         0x1
#define FUSE_KEK00_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_KEK00_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK00_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_KEK00_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_KEK00_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK00_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK00_0_KEK00_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_KEK00_0_KEK00_FIELD                        _MK_FIELD_CONST(0xffffffff, FUSE_KEK00_0_KEK00_SHIFT)
#define FUSE_KEK00_0_KEK00_RANGE                        31:0
#define FUSE_KEK00_0_KEK00_WOFFSET                      0x0
#define FUSE_KEK00_0_KEK00_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_KEK00_0_KEK00_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK00_0_KEK00_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_KEK00_0_KEK00_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_KEK00_0_KEK00_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_KEK00_0_KEK00_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_KEK01_0
#define FUSE_KEK01_0                    _MK_ADDR_CONST(0x3c4)
#define FUSE_KEK01_0_SECURE                     0x0
#define FUSE_KEK01_0_DUAL                       0x0
#define FUSE_KEK01_0_SCR                        0
#define FUSE_KEK01_0_WORD_COUNT                         0x1
#define FUSE_KEK01_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_KEK01_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK01_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_KEK01_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_KEK01_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK01_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK01_0_KEK01_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_KEK01_0_KEK01_FIELD                        _MK_FIELD_CONST(0xffffffff, FUSE_KEK01_0_KEK01_SHIFT)
#define FUSE_KEK01_0_KEK01_RANGE                        31:0
#define FUSE_KEK01_0_KEK01_WOFFSET                      0x0
#define FUSE_KEK01_0_KEK01_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_KEK01_0_KEK01_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK01_0_KEK01_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_KEK01_0_KEK01_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_KEK01_0_KEK01_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_KEK01_0_KEK01_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_KEK02_0
#define FUSE_KEK02_0                    _MK_ADDR_CONST(0x3c8)
#define FUSE_KEK02_0_SECURE                     0x0
#define FUSE_KEK02_0_DUAL                       0x0
#define FUSE_KEK02_0_SCR                        0
#define FUSE_KEK02_0_WORD_COUNT                         0x1
#define FUSE_KEK02_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_KEK02_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK02_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_KEK02_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_KEK02_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK02_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK02_0_KEK02_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_KEK02_0_KEK02_FIELD                        _MK_FIELD_CONST(0xffffffff, FUSE_KEK02_0_KEK02_SHIFT)
#define FUSE_KEK02_0_KEK02_RANGE                        31:0
#define FUSE_KEK02_0_KEK02_WOFFSET                      0x0
#define FUSE_KEK02_0_KEK02_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_KEK02_0_KEK02_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK02_0_KEK02_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_KEK02_0_KEK02_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_KEK02_0_KEK02_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_KEK02_0_KEK02_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_KEK03_0
#define FUSE_KEK03_0                    _MK_ADDR_CONST(0x3cc)
#define FUSE_KEK03_0_SECURE                     0x0
#define FUSE_KEK03_0_DUAL                       0x0
#define FUSE_KEK03_0_SCR                        0
#define FUSE_KEK03_0_WORD_COUNT                         0x1
#define FUSE_KEK03_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_KEK03_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK03_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_KEK03_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_KEK03_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK03_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK03_0_KEK03_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_KEK03_0_KEK03_FIELD                        _MK_FIELD_CONST(0xffffffff, FUSE_KEK03_0_KEK03_SHIFT)
#define FUSE_KEK03_0_KEK03_RANGE                        31:0
#define FUSE_KEK03_0_KEK03_WOFFSET                      0x0
#define FUSE_KEK03_0_KEK03_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_KEK03_0_KEK03_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK03_0_KEK03_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_KEK03_0_KEK03_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_KEK03_0_KEK03_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_KEK03_0_KEK03_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_KEK10_0
#define FUSE_KEK10_0                    _MK_ADDR_CONST(0x3d0)
#define FUSE_KEK10_0_SECURE                     0x0
#define FUSE_KEK10_0_DUAL                       0x0
#define FUSE_KEK10_0_SCR                        0
#define FUSE_KEK10_0_WORD_COUNT                         0x1
#define FUSE_KEK10_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_KEK10_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK10_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_KEK10_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_KEK10_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK10_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK10_0_KEK10_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_KEK10_0_KEK10_FIELD                        _MK_FIELD_CONST(0xffffffff, FUSE_KEK10_0_KEK10_SHIFT)
#define FUSE_KEK10_0_KEK10_RANGE                        31:0
#define FUSE_KEK10_0_KEK10_WOFFSET                      0x0
#define FUSE_KEK10_0_KEK10_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_KEK10_0_KEK10_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK10_0_KEK10_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_KEK10_0_KEK10_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_KEK10_0_KEK10_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_KEK10_0_KEK10_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_KEK11_0
#define FUSE_KEK11_0                    _MK_ADDR_CONST(0x3d4)
#define FUSE_KEK11_0_SECURE                     0x0
#define FUSE_KEK11_0_DUAL                       0x0
#define FUSE_KEK11_0_SCR                        0
#define FUSE_KEK11_0_WORD_COUNT                         0x1
#define FUSE_KEK11_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_KEK11_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK11_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_KEK11_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_KEK11_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK11_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK11_0_KEK11_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_KEK11_0_KEK11_FIELD                        _MK_FIELD_CONST(0xffffffff, FUSE_KEK11_0_KEK11_SHIFT)
#define FUSE_KEK11_0_KEK11_RANGE                        31:0
#define FUSE_KEK11_0_KEK11_WOFFSET                      0x0
#define FUSE_KEK11_0_KEK11_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_KEK11_0_KEK11_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK11_0_KEK11_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_KEK11_0_KEK11_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_KEK11_0_KEK11_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_KEK11_0_KEK11_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_KEK12_0
#define FUSE_KEK12_0                    _MK_ADDR_CONST(0x3d8)
#define FUSE_KEK12_0_SECURE                     0x0
#define FUSE_KEK12_0_DUAL                       0x0
#define FUSE_KEK12_0_SCR                        0
#define FUSE_KEK12_0_WORD_COUNT                         0x1
#define FUSE_KEK12_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_KEK12_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK12_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_KEK12_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_KEK12_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK12_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK12_0_KEK12_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_KEK12_0_KEK12_FIELD                        _MK_FIELD_CONST(0xffffffff, FUSE_KEK12_0_KEK12_SHIFT)
#define FUSE_KEK12_0_KEK12_RANGE                        31:0
#define FUSE_KEK12_0_KEK12_WOFFSET                      0x0
#define FUSE_KEK12_0_KEK12_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_KEK12_0_KEK12_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK12_0_KEK12_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_KEK12_0_KEK12_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_KEK12_0_KEK12_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_KEK12_0_KEK12_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_KEK13_0
#define FUSE_KEK13_0                    _MK_ADDR_CONST(0x3dc)
#define FUSE_KEK13_0_SECURE                     0x0
#define FUSE_KEK13_0_DUAL                       0x0
#define FUSE_KEK13_0_SCR                        0
#define FUSE_KEK13_0_WORD_COUNT                         0x1
#define FUSE_KEK13_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_KEK13_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK13_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_KEK13_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_KEK13_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK13_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK13_0_KEK13_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_KEK13_0_KEK13_FIELD                        _MK_FIELD_CONST(0xffffffff, FUSE_KEK13_0_KEK13_SHIFT)
#define FUSE_KEK13_0_KEK13_RANGE                        31:0
#define FUSE_KEK13_0_KEK13_WOFFSET                      0x0
#define FUSE_KEK13_0_KEK13_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_KEK13_0_KEK13_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK13_0_KEK13_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_KEK13_0_KEK13_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_KEK13_0_KEK13_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_KEK13_0_KEK13_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_KEK20_0
#define FUSE_KEK20_0                    _MK_ADDR_CONST(0x3e0)
#define FUSE_KEK20_0_SECURE                     0x0
#define FUSE_KEK20_0_DUAL                       0x0
#define FUSE_KEK20_0_SCR                        0
#define FUSE_KEK20_0_WORD_COUNT                         0x1
#define FUSE_KEK20_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_KEK20_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK20_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_KEK20_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_KEK20_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK20_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK20_0_KEK20_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_KEK20_0_KEK20_FIELD                        _MK_FIELD_CONST(0xffffffff, FUSE_KEK20_0_KEK20_SHIFT)
#define FUSE_KEK20_0_KEK20_RANGE                        31:0
#define FUSE_KEK20_0_KEK20_WOFFSET                      0x0
#define FUSE_KEK20_0_KEK20_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_KEK20_0_KEK20_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK20_0_KEK20_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_KEK20_0_KEK20_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_KEK20_0_KEK20_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_KEK20_0_KEK20_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_KEK21_0
#define FUSE_KEK21_0                    _MK_ADDR_CONST(0x3e4)
#define FUSE_KEK21_0_SECURE                     0x0
#define FUSE_KEK21_0_DUAL                       0x0
#define FUSE_KEK21_0_SCR                        0
#define FUSE_KEK21_0_WORD_COUNT                         0x1
#define FUSE_KEK21_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_KEK21_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK21_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_KEK21_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_KEK21_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK21_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK21_0_KEK21_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_KEK21_0_KEK21_FIELD                        _MK_FIELD_CONST(0xffffffff, FUSE_KEK21_0_KEK21_SHIFT)
#define FUSE_KEK21_0_KEK21_RANGE                        31:0
#define FUSE_KEK21_0_KEK21_WOFFSET                      0x0
#define FUSE_KEK21_0_KEK21_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_KEK21_0_KEK21_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK21_0_KEK21_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_KEK21_0_KEK21_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_KEK21_0_KEK21_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_KEK21_0_KEK21_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_KEK22_0
#define FUSE_KEK22_0                    _MK_ADDR_CONST(0x3e8)
#define FUSE_KEK22_0_SECURE                     0x0
#define FUSE_KEK22_0_DUAL                       0x0
#define FUSE_KEK22_0_SCR                        0
#define FUSE_KEK22_0_WORD_COUNT                         0x1
#define FUSE_KEK22_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_KEK22_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK22_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_KEK22_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_KEK22_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK22_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK22_0_KEK22_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_KEK22_0_KEK22_FIELD                        _MK_FIELD_CONST(0xffffffff, FUSE_KEK22_0_KEK22_SHIFT)
#define FUSE_KEK22_0_KEK22_RANGE                        31:0
#define FUSE_KEK22_0_KEK22_WOFFSET                      0x0
#define FUSE_KEK22_0_KEK22_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_KEK22_0_KEK22_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK22_0_KEK22_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_KEK22_0_KEK22_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_KEK22_0_KEK22_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_KEK22_0_KEK22_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_KEK23_0
#define FUSE_KEK23_0                    _MK_ADDR_CONST(0x3ec)
#define FUSE_KEK23_0_SECURE                     0x0
#define FUSE_KEK23_0_DUAL                       0x0
#define FUSE_KEK23_0_SCR                        0
#define FUSE_KEK23_0_WORD_COUNT                         0x1
#define FUSE_KEK23_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_KEK23_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK23_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_KEK23_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_KEK23_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK23_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK23_0_KEK23_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_KEK23_0_KEK23_FIELD                        _MK_FIELD_CONST(0xffffffff, FUSE_KEK23_0_KEK23_SHIFT)
#define FUSE_KEK23_0_KEK23_RANGE                        31:0
#define FUSE_KEK23_0_KEK23_WOFFSET                      0x0
#define FUSE_KEK23_0_KEK23_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_KEK23_0_KEK23_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define FUSE_KEK23_0_KEK23_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_KEK23_0_KEK23_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_KEK23_0_KEK23_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_KEK23_0_KEK23_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_OPT_PRIV_SFK_0_0
#define FUSE_OPT_PRIV_SFK_0_0                   _MK_ADDR_CONST(0x3f0)
#define FUSE_OPT_PRIV_SFK_0_0_SECURE                    0x0
#define FUSE_OPT_PRIV_SFK_0_0_DUAL                      0x0
#define FUSE_OPT_PRIV_SFK_0_0_SCR                       0
#define FUSE_OPT_PRIV_SFK_0_0_WORD_COUNT                        0x1
#define FUSE_OPT_PRIV_SFK_0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_0_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK_0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_0_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK_0_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK_0_0_OPT_PRIV_SFK_0_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_PRIV_SFK_0_0_OPT_PRIV_SFK_0_FIELD                      _MK_FIELD_CONST(0xffffffff, FUSE_OPT_PRIV_SFK_0_0_OPT_PRIV_SFK_0_SHIFT)
#define FUSE_OPT_PRIV_SFK_0_0_OPT_PRIV_SFK_0_RANGE                      31:0
#define FUSE_OPT_PRIV_SFK_0_0_OPT_PRIV_SFK_0_WOFFSET                    0x0
#define FUSE_OPT_PRIV_SFK_0_0_OPT_PRIV_SFK_0_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_0_0_OPT_PRIV_SFK_0_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK_0_0_OPT_PRIV_SFK_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_0_0_OPT_PRIV_SFK_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_0_0_OPT_PRIV_SFK_0_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_0_0_OPT_PRIV_SFK_0_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_PRIV_SFK_1_0
#define FUSE_OPT_PRIV_SFK_1_0                   _MK_ADDR_CONST(0x3f4)
#define FUSE_OPT_PRIV_SFK_1_0_SECURE                    0x0
#define FUSE_OPT_PRIV_SFK_1_0_DUAL                      0x0
#define FUSE_OPT_PRIV_SFK_1_0_SCR                       0
#define FUSE_OPT_PRIV_SFK_1_0_WORD_COUNT                        0x1
#define FUSE_OPT_PRIV_SFK_1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_1_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK_1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK_1_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK_1_0_OPT_PRIV_SFK_1_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_PRIV_SFK_1_0_OPT_PRIV_SFK_1_FIELD                      _MK_FIELD_CONST(0xffffffff, FUSE_OPT_PRIV_SFK_1_0_OPT_PRIV_SFK_1_SHIFT)
#define FUSE_OPT_PRIV_SFK_1_0_OPT_PRIV_SFK_1_RANGE                      31:0
#define FUSE_OPT_PRIV_SFK_1_0_OPT_PRIV_SFK_1_WOFFSET                    0x0
#define FUSE_OPT_PRIV_SFK_1_0_OPT_PRIV_SFK_1_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_1_0_OPT_PRIV_SFK_1_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK_1_0_OPT_PRIV_SFK_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_1_0_OPT_PRIV_SFK_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_1_0_OPT_PRIV_SFK_1_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_1_0_OPT_PRIV_SFK_1_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_PRIV_SFK_2_0
#define FUSE_OPT_PRIV_SFK_2_0                   _MK_ADDR_CONST(0x3f8)
#define FUSE_OPT_PRIV_SFK_2_0_SECURE                    0x0
#define FUSE_OPT_PRIV_SFK_2_0_DUAL                      0x0
#define FUSE_OPT_PRIV_SFK_2_0_SCR                       0
#define FUSE_OPT_PRIV_SFK_2_0_WORD_COUNT                        0x1
#define FUSE_OPT_PRIV_SFK_2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_2_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK_2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_2_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK_2_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK_2_0_OPT_PRIV_SFK_2_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_PRIV_SFK_2_0_OPT_PRIV_SFK_2_FIELD                      _MK_FIELD_CONST(0xffffffff, FUSE_OPT_PRIV_SFK_2_0_OPT_PRIV_SFK_2_SHIFT)
#define FUSE_OPT_PRIV_SFK_2_0_OPT_PRIV_SFK_2_RANGE                      31:0
#define FUSE_OPT_PRIV_SFK_2_0_OPT_PRIV_SFK_2_WOFFSET                    0x0
#define FUSE_OPT_PRIV_SFK_2_0_OPT_PRIV_SFK_2_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_2_0_OPT_PRIV_SFK_2_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK_2_0_OPT_PRIV_SFK_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_2_0_OPT_PRIV_SFK_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_2_0_OPT_PRIV_SFK_2_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_2_0_OPT_PRIV_SFK_2_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_PRIV_SFK_3_0
#define FUSE_OPT_PRIV_SFK_3_0                   _MK_ADDR_CONST(0x3fc)
#define FUSE_OPT_PRIV_SFK_3_0_SECURE                    0x0
#define FUSE_OPT_PRIV_SFK_3_0_DUAL                      0x0
#define FUSE_OPT_PRIV_SFK_3_0_SCR                       0
#define FUSE_OPT_PRIV_SFK_3_0_WORD_COUNT                        0x1
#define FUSE_OPT_PRIV_SFK_3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_3_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK_3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_3_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK_3_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK_3_0_OPT_PRIV_SFK_3_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_PRIV_SFK_3_0_OPT_PRIV_SFK_3_FIELD                      _MK_FIELD_CONST(0xffffffff, FUSE_OPT_PRIV_SFK_3_0_OPT_PRIV_SFK_3_SHIFT)
#define FUSE_OPT_PRIV_SFK_3_0_OPT_PRIV_SFK_3_RANGE                      31:0
#define FUSE_OPT_PRIV_SFK_3_0_OPT_PRIV_SFK_3_WOFFSET                    0x0
#define FUSE_OPT_PRIV_SFK_3_0_OPT_PRIV_SFK_3_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_3_0_OPT_PRIV_SFK_3_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK_3_0_OPT_PRIV_SFK_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_3_0_OPT_PRIV_SFK_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_3_0_OPT_PRIV_SFK_3_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK_3_0_OPT_PRIV_SFK_3_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_PDI0_0
#define FUSE_PDI0_0                     _MK_ADDR_CONST(0x400)
#define FUSE_PDI0_0_SECURE                      0x0
#define FUSE_PDI0_0_DUAL                        0x0
#define FUSE_PDI0_0_SCR                         0
#define FUSE_PDI0_0_WORD_COUNT                  0x1
#define FUSE_PDI0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_PDI0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_PDI0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_PDI0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_PDI0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PDI0_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_PDI0_0_PDI0_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_PDI0_0_PDI0_FIELD                  _MK_FIELD_CONST(0xffffffff, FUSE_PDI0_0_PDI0_SHIFT)
#define FUSE_PDI0_0_PDI0_RANGE                  31:0
#define FUSE_PDI0_0_PDI0_WOFFSET                        0x0
#define FUSE_PDI0_0_PDI0_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_PDI0_0_PDI0_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PDI0_0_PDI0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_PDI0_0_PDI0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_PDI0_0_PDI0_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_PDI0_0_PDI0_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_PDI1_0
#define FUSE_PDI1_0                     _MK_ADDR_CONST(0x404)
#define FUSE_PDI1_0_SECURE                      0x0
#define FUSE_PDI1_0_DUAL                        0x0
#define FUSE_PDI1_0_SCR                         0
#define FUSE_PDI1_0_WORD_COUNT                  0x1
#define FUSE_PDI1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_PDI1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_PDI1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_PDI1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_PDI1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PDI1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_PDI1_0_PDI1_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_PDI1_0_PDI1_FIELD                  _MK_FIELD_CONST(0xffffffff, FUSE_PDI1_0_PDI1_SHIFT)
#define FUSE_PDI1_0_PDI1_RANGE                  31:0
#define FUSE_PDI1_0_PDI1_WOFFSET                        0x0
#define FUSE_PDI1_0_PDI1_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_PDI1_0_PDI1_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_PDI1_0_PDI1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_PDI1_0_PDI1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_PDI1_0_PDI1_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_PDI1_0_PDI1_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_ODMID0_0
#define FUSE_ODMID0_0                   _MK_ADDR_CONST(0x408)
#define FUSE_ODMID0_0_SECURE                    0x0
#define FUSE_ODMID0_0_DUAL                      0x0
#define FUSE_ODMID0_0_SCR                       0
#define FUSE_ODMID0_0_WORD_COUNT                        0x1
#define FUSE_ODMID0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_ODMID0_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_ODMID0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_ODMID0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_ODMID0_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_ODMID0_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_ODMID0_0_ODMID0_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_ODMID0_0_ODMID0_FIELD                      _MK_FIELD_CONST(0xffffffff, FUSE_ODMID0_0_ODMID0_SHIFT)
#define FUSE_ODMID0_0_ODMID0_RANGE                      31:0
#define FUSE_ODMID0_0_ODMID0_WOFFSET                    0x0
#define FUSE_ODMID0_0_ODMID0_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_ODMID0_0_ODMID0_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_ODMID0_0_ODMID0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_ODMID0_0_ODMID0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_ODMID0_0_ODMID0_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_ODMID0_0_ODMID0_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_ODMID1_0
#define FUSE_ODMID1_0                   _MK_ADDR_CONST(0x40c)
#define FUSE_ODMID1_0_SECURE                    0x0
#define FUSE_ODMID1_0_DUAL                      0x0
#define FUSE_ODMID1_0_SCR                       0
#define FUSE_ODMID1_0_WORD_COUNT                        0x1
#define FUSE_ODMID1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_ODMID1_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_ODMID1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_ODMID1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_ODMID1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_ODMID1_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_ODMID1_0_ODMID1_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_ODMID1_0_ODMID1_FIELD                      _MK_FIELD_CONST(0xffffffff, FUSE_ODMID1_0_ODMID1_SHIFT)
#define FUSE_ODMID1_0_ODMID1_RANGE                      31:0
#define FUSE_ODMID1_0_ODMID1_WOFFSET                    0x0
#define FUSE_ODMID1_0_ODMID1_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_ODMID1_0_ODMID1_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_ODMID1_0_ODMID1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_ODMID1_0_ODMID1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_ODMID1_0_ODMID1_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_ODMID1_0_ODMID1_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Reserved address 0x410

// Reserved address 0x414

// Reserved address 0x418

// Reserved address 0x41c

// Reserved address 0x420

// Reserved address 0x424

// Reserved address 0x428

// Reserved address 0x42c

// Reserved address 0x430

// Register FUSE_H0_0
#define FUSE_H0_0                       _MK_ADDR_CONST(0x434)
#define FUSE_H0_0_SECURE                        0x0
#define FUSE_H0_0_DUAL                  0x0
#define FUSE_H0_0_SCR                   0
#define FUSE_H0_0_WORD_COUNT                    0x1
#define FUSE_H0_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_H0_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define FUSE_H0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_H0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_H0_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_H0_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define FUSE_H0_0_H0_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_H0_0_H0_FIELD                      _MK_FIELD_CONST(0xffffffff, FUSE_H0_0_H0_SHIFT)
#define FUSE_H0_0_H0_RANGE                      31:0
#define FUSE_H0_0_H0_WOFFSET                    0x0
#define FUSE_H0_0_H0_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_H0_0_H0_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_H0_0_H0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_H0_0_H0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_H0_0_H0_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_H0_0_H0_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_H1_0
#define FUSE_H1_0                       _MK_ADDR_CONST(0x438)
#define FUSE_H1_0_SECURE                        0x0
#define FUSE_H1_0_DUAL                  0x0
#define FUSE_H1_0_SCR                   0
#define FUSE_H1_0_WORD_COUNT                    0x1
#define FUSE_H1_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_H1_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define FUSE_H1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_H1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_H1_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_H1_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define FUSE_H1_0_H1_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_H1_0_H1_FIELD                      _MK_FIELD_CONST(0xffffffff, FUSE_H1_0_H1_SHIFT)
#define FUSE_H1_0_H1_RANGE                      31:0
#define FUSE_H1_0_H1_WOFFSET                    0x0
#define FUSE_H1_0_H1_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_H1_0_H1_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_H1_0_H1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_H1_0_H1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_H1_0_H1_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_H1_0_H1_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_H2_0
#define FUSE_H2_0                       _MK_ADDR_CONST(0x43c)
#define FUSE_H2_0_SECURE                        0x0
#define FUSE_H2_0_DUAL                  0x0
#define FUSE_H2_0_SCR                   0
#define FUSE_H2_0_WORD_COUNT                    0x1
#define FUSE_H2_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_H2_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define FUSE_H2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_H2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_H2_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_H2_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define FUSE_H2_0_H2_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_H2_0_H2_FIELD                      _MK_FIELD_CONST(0xffffffff, FUSE_H2_0_H2_SHIFT)
#define FUSE_H2_0_H2_RANGE                      31:0
#define FUSE_H2_0_H2_WOFFSET                    0x0
#define FUSE_H2_0_H2_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_H2_0_H2_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_H2_0_H2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_H2_0_H2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_H2_0_H2_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_H2_0_H2_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_H3_0
#define FUSE_H3_0                       _MK_ADDR_CONST(0x440)
#define FUSE_H3_0_SECURE                        0x0
#define FUSE_H3_0_DUAL                  0x0
#define FUSE_H3_0_SCR                   0
#define FUSE_H3_0_WORD_COUNT                    0x1
#define FUSE_H3_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_H3_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define FUSE_H3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_H3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_H3_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_H3_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
#define FUSE_H3_0_H3_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_H3_0_H3_FIELD                      _MK_FIELD_CONST(0xffffffff, FUSE_H3_0_H3_SHIFT)
#define FUSE_H3_0_H3_RANGE                      31:0
#define FUSE_H3_0_H3_WOFFSET                    0x0
#define FUSE_H3_0_H3_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_H3_0_H3_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_H3_0_H3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_H3_0_H3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_H3_0_H3_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_H3_0_H3_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_SECURE_SCC_DIS_0
#define FUSE_OPT_SECURE_SCC_DIS_0                       _MK_ADDR_CONST(0x444)
#define FUSE_OPT_SECURE_SCC_DIS_0_SECURE                        0x0
#define FUSE_OPT_SECURE_SCC_DIS_0_DUAL                  0x0
#define FUSE_OPT_SECURE_SCC_DIS_0_SCR                   0
#define FUSE_OPT_SECURE_SCC_DIS_0_WORD_COUNT                    0x1
#define FUSE_OPT_SECURE_SCC_DIS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_SCC_DIS_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_OPT_SECURE_SCC_DIS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_SCC_DIS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_SCC_DIS_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_OPT_SECURE_SCC_DIS_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_OPT_SECURE_SCC_DIS_0_OPT_SECURE_SCC_DIS_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_SECURE_SCC_DIS_0_OPT_SECURE_SCC_DIS_FIELD                      _MK_FIELD_CONST(0x1, FUSE_OPT_SECURE_SCC_DIS_0_OPT_SECURE_SCC_DIS_SHIFT)
#define FUSE_OPT_SECURE_SCC_DIS_0_OPT_SECURE_SCC_DIS_RANGE                      0:0
#define FUSE_OPT_SECURE_SCC_DIS_0_OPT_SECURE_SCC_DIS_WOFFSET                    0x0
#define FUSE_OPT_SECURE_SCC_DIS_0_OPT_SECURE_SCC_DIS_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_SCC_DIS_0_OPT_SECURE_SCC_DIS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_OPT_SECURE_SCC_DIS_0_OPT_SECURE_SCC_DIS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_SCC_DIS_0_OPT_SECURE_SCC_DIS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_SCC_DIS_0_OPT_SECURE_SCC_DIS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_SCC_DIS_0_OPT_SECURE_SCC_DIS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_ADC_CAL_FUSE_REV_0
#define FUSE_OPT_ADC_CAL_FUSE_REV_0                     _MK_ADDR_CONST(0x448)
#define FUSE_OPT_ADC_CAL_FUSE_REV_0_SECURE                      0x0
#define FUSE_OPT_ADC_CAL_FUSE_REV_0_DUAL                        0x0
#define FUSE_OPT_ADC_CAL_FUSE_REV_0_SCR                         0
#define FUSE_OPT_ADC_CAL_FUSE_REV_0_WORD_COUNT                  0x1
#define FUSE_OPT_ADC_CAL_FUSE_REV_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_FUSE_REV_0_RESET_MASK                  _MK_MASK_CONST(0x7)
#define FUSE_OPT_ADC_CAL_FUSE_REV_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_FUSE_REV_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_FUSE_REV_0_READ_MASK                   _MK_MASK_CONST(0x7)
#define FUSE_OPT_ADC_CAL_FUSE_REV_0_WRITE_MASK                  _MK_MASK_CONST(0x7)
#define FUSE_OPT_ADC_CAL_FUSE_REV_0_OPT_ADC_CAL_FUSE_REV_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_OPT_ADC_CAL_FUSE_REV_0_OPT_ADC_CAL_FUSE_REV_FIELD                  _MK_FIELD_CONST(0x7, FUSE_OPT_ADC_CAL_FUSE_REV_0_OPT_ADC_CAL_FUSE_REV_SHIFT)
#define FUSE_OPT_ADC_CAL_FUSE_REV_0_OPT_ADC_CAL_FUSE_REV_RANGE                  2:0
#define FUSE_OPT_ADC_CAL_FUSE_REV_0_OPT_ADC_CAL_FUSE_REV_WOFFSET                        0x0
#define FUSE_OPT_ADC_CAL_FUSE_REV_0_OPT_ADC_CAL_FUSE_REV_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_FUSE_REV_0_OPT_ADC_CAL_FUSE_REV_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define FUSE_OPT_ADC_CAL_FUSE_REV_0_OPT_ADC_CAL_FUSE_REV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_FUSE_REV_0_OPT_ADC_CAL_FUSE_REV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_FUSE_REV_0_OPT_ADC_CAL_FUSE_REV_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_FUSE_REV_0_OPT_ADC_CAL_FUSE_REV_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_OPT_ADC_CAL_INSTANCE0_0
#define FUSE_OPT_ADC_CAL_INSTANCE0_0                    _MK_ADDR_CONST(0x44c)
#define FUSE_OPT_ADC_CAL_INSTANCE0_0_SECURE                     0x0
#define FUSE_OPT_ADC_CAL_INSTANCE0_0_DUAL                       0x0
#define FUSE_OPT_ADC_CAL_INSTANCE0_0_SCR                        0
#define FUSE_OPT_ADC_CAL_INSTANCE0_0_WORD_COUNT                         0x1
#define FUSE_OPT_ADC_CAL_INSTANCE0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE0_0_RESET_MASK                         _MK_MASK_CONST(0xfffffff)
#define FUSE_OPT_ADC_CAL_INSTANCE0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE0_0_READ_MASK                  _MK_MASK_CONST(0xfffffff)
#define FUSE_OPT_ADC_CAL_INSTANCE0_0_WRITE_MASK                         _MK_MASK_CONST(0xfffffff)
#define FUSE_OPT_ADC_CAL_INSTANCE0_0_OPT_ADC_CAL_INSTANCE0_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_OPT_ADC_CAL_INSTANCE0_0_OPT_ADC_CAL_INSTANCE0_FIELD                        _MK_FIELD_CONST(0xfffffff, FUSE_OPT_ADC_CAL_INSTANCE0_0_OPT_ADC_CAL_INSTANCE0_SHIFT)
#define FUSE_OPT_ADC_CAL_INSTANCE0_0_OPT_ADC_CAL_INSTANCE0_RANGE                        27:0
#define FUSE_OPT_ADC_CAL_INSTANCE0_0_OPT_ADC_CAL_INSTANCE0_WOFFSET                      0x0
#define FUSE_OPT_ADC_CAL_INSTANCE0_0_OPT_ADC_CAL_INSTANCE0_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE0_0_OPT_ADC_CAL_INSTANCE0_DEFAULT_MASK                 _MK_MASK_CONST(0xfffffff)
#define FUSE_OPT_ADC_CAL_INSTANCE0_0_OPT_ADC_CAL_INSTANCE0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE0_0_OPT_ADC_CAL_INSTANCE0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE0_0_OPT_ADC_CAL_INSTANCE0_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE0_0_OPT_ADC_CAL_INSTANCE0_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_OPT_ADC_CAL_INSTANCE1_DELTA_0
#define FUSE_OPT_ADC_CAL_INSTANCE1_DELTA_0                      _MK_ADDR_CONST(0x450)
#define FUSE_OPT_ADC_CAL_INSTANCE1_DELTA_0_SECURE                       0x0
#define FUSE_OPT_ADC_CAL_INSTANCE1_DELTA_0_DUAL                         0x0
#define FUSE_OPT_ADC_CAL_INSTANCE1_DELTA_0_SCR                  0
#define FUSE_OPT_ADC_CAL_INSTANCE1_DELTA_0_WORD_COUNT                   0x1
#define FUSE_OPT_ADC_CAL_INSTANCE1_DELTA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE1_DELTA_0_RESET_MASK                   _MK_MASK_CONST(0x7fffff)
#define FUSE_OPT_ADC_CAL_INSTANCE1_DELTA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE1_DELTA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE1_DELTA_0_READ_MASK                    _MK_MASK_CONST(0x7fffff)
#define FUSE_OPT_ADC_CAL_INSTANCE1_DELTA_0_WRITE_MASK                   _MK_MASK_CONST(0x7fffff)
#define FUSE_OPT_ADC_CAL_INSTANCE1_DELTA_0_OPT_ADC_CAL_INSTANCE1_DELTA_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_ADC_CAL_INSTANCE1_DELTA_0_OPT_ADC_CAL_INSTANCE1_DELTA_FIELD                    _MK_FIELD_CONST(0x7fffff, FUSE_OPT_ADC_CAL_INSTANCE1_DELTA_0_OPT_ADC_CAL_INSTANCE1_DELTA_SHIFT)
#define FUSE_OPT_ADC_CAL_INSTANCE1_DELTA_0_OPT_ADC_CAL_INSTANCE1_DELTA_RANGE                    22:0
#define FUSE_OPT_ADC_CAL_INSTANCE1_DELTA_0_OPT_ADC_CAL_INSTANCE1_DELTA_WOFFSET                  0x0
#define FUSE_OPT_ADC_CAL_INSTANCE1_DELTA_0_OPT_ADC_CAL_INSTANCE1_DELTA_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE1_DELTA_0_OPT_ADC_CAL_INSTANCE1_DELTA_DEFAULT_MASK                     _MK_MASK_CONST(0x7fffff)
#define FUSE_OPT_ADC_CAL_INSTANCE1_DELTA_0_OPT_ADC_CAL_INSTANCE1_DELTA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE1_DELTA_0_OPT_ADC_CAL_INSTANCE1_DELTA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE1_DELTA_0_OPT_ADC_CAL_INSTANCE1_DELTA_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE1_DELTA_0_OPT_ADC_CAL_INSTANCE1_DELTA_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_ADC_CAL_INSTANCE2_DELTA_0
#define FUSE_OPT_ADC_CAL_INSTANCE2_DELTA_0                      _MK_ADDR_CONST(0x454)
#define FUSE_OPT_ADC_CAL_INSTANCE2_DELTA_0_SECURE                       0x0
#define FUSE_OPT_ADC_CAL_INSTANCE2_DELTA_0_DUAL                         0x0
#define FUSE_OPT_ADC_CAL_INSTANCE2_DELTA_0_SCR                  0
#define FUSE_OPT_ADC_CAL_INSTANCE2_DELTA_0_WORD_COUNT                   0x1
#define FUSE_OPT_ADC_CAL_INSTANCE2_DELTA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE2_DELTA_0_RESET_MASK                   _MK_MASK_CONST(0x7fffff)
#define FUSE_OPT_ADC_CAL_INSTANCE2_DELTA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE2_DELTA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE2_DELTA_0_READ_MASK                    _MK_MASK_CONST(0x7fffff)
#define FUSE_OPT_ADC_CAL_INSTANCE2_DELTA_0_WRITE_MASK                   _MK_MASK_CONST(0x7fffff)
#define FUSE_OPT_ADC_CAL_INSTANCE2_DELTA_0_OPT_ADC_CAL_INSTANCE2_DELTA_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_ADC_CAL_INSTANCE2_DELTA_0_OPT_ADC_CAL_INSTANCE2_DELTA_FIELD                    _MK_FIELD_CONST(0x7fffff, FUSE_OPT_ADC_CAL_INSTANCE2_DELTA_0_OPT_ADC_CAL_INSTANCE2_DELTA_SHIFT)
#define FUSE_OPT_ADC_CAL_INSTANCE2_DELTA_0_OPT_ADC_CAL_INSTANCE2_DELTA_RANGE                    22:0
#define FUSE_OPT_ADC_CAL_INSTANCE2_DELTA_0_OPT_ADC_CAL_INSTANCE2_DELTA_WOFFSET                  0x0
#define FUSE_OPT_ADC_CAL_INSTANCE2_DELTA_0_OPT_ADC_CAL_INSTANCE2_DELTA_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE2_DELTA_0_OPT_ADC_CAL_INSTANCE2_DELTA_DEFAULT_MASK                     _MK_MASK_CONST(0x7fffff)
#define FUSE_OPT_ADC_CAL_INSTANCE2_DELTA_0_OPT_ADC_CAL_INSTANCE2_DELTA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE2_DELTA_0_OPT_ADC_CAL_INSTANCE2_DELTA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE2_DELTA_0_OPT_ADC_CAL_INSTANCE2_DELTA_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE2_DELTA_0_OPT_ADC_CAL_INSTANCE2_DELTA_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_ADC_CAL_INSTANCE3_DELTA_0
#define FUSE_OPT_ADC_CAL_INSTANCE3_DELTA_0                      _MK_ADDR_CONST(0x458)
#define FUSE_OPT_ADC_CAL_INSTANCE3_DELTA_0_SECURE                       0x0
#define FUSE_OPT_ADC_CAL_INSTANCE3_DELTA_0_DUAL                         0x0
#define FUSE_OPT_ADC_CAL_INSTANCE3_DELTA_0_SCR                  0
#define FUSE_OPT_ADC_CAL_INSTANCE3_DELTA_0_WORD_COUNT                   0x1
#define FUSE_OPT_ADC_CAL_INSTANCE3_DELTA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE3_DELTA_0_RESET_MASK                   _MK_MASK_CONST(0x7fffff)
#define FUSE_OPT_ADC_CAL_INSTANCE3_DELTA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE3_DELTA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE3_DELTA_0_READ_MASK                    _MK_MASK_CONST(0x7fffff)
#define FUSE_OPT_ADC_CAL_INSTANCE3_DELTA_0_WRITE_MASK                   _MK_MASK_CONST(0x7fffff)
#define FUSE_OPT_ADC_CAL_INSTANCE3_DELTA_0_OPT_ADC_CAL_INSTANCE3_DELTA_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_ADC_CAL_INSTANCE3_DELTA_0_OPT_ADC_CAL_INSTANCE3_DELTA_FIELD                    _MK_FIELD_CONST(0x7fffff, FUSE_OPT_ADC_CAL_INSTANCE3_DELTA_0_OPT_ADC_CAL_INSTANCE3_DELTA_SHIFT)
#define FUSE_OPT_ADC_CAL_INSTANCE3_DELTA_0_OPT_ADC_CAL_INSTANCE3_DELTA_RANGE                    22:0
#define FUSE_OPT_ADC_CAL_INSTANCE3_DELTA_0_OPT_ADC_CAL_INSTANCE3_DELTA_WOFFSET                  0x0
#define FUSE_OPT_ADC_CAL_INSTANCE3_DELTA_0_OPT_ADC_CAL_INSTANCE3_DELTA_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE3_DELTA_0_OPT_ADC_CAL_INSTANCE3_DELTA_DEFAULT_MASK                     _MK_MASK_CONST(0x7fffff)
#define FUSE_OPT_ADC_CAL_INSTANCE3_DELTA_0_OPT_ADC_CAL_INSTANCE3_DELTA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE3_DELTA_0_OPT_ADC_CAL_INSTANCE3_DELTA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE3_DELTA_0_OPT_ADC_CAL_INSTANCE3_DELTA_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE3_DELTA_0_OPT_ADC_CAL_INSTANCE3_DELTA_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_BPMP_CONFIG_0
#define FUSE_BPMP_CONFIG_0                      _MK_ADDR_CONST(0x45c)
#define FUSE_BPMP_CONFIG_0_SECURE                       0x0
#define FUSE_BPMP_CONFIG_0_DUAL                         0x0
#define FUSE_BPMP_CONFIG_0_SCR                  0
#define FUSE_BPMP_CONFIG_0_WORD_COUNT                   0x1
#define FUSE_BPMP_CONFIG_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_BPMP_CONFIG_0_RESET_MASK                   _MK_MASK_CONST(0xf)
#define FUSE_BPMP_CONFIG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_BPMP_CONFIG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_BPMP_CONFIG_0_READ_MASK                    _MK_MASK_CONST(0xf)
#define FUSE_BPMP_CONFIG_0_WRITE_MASK                   _MK_MASK_CONST(0xf)
#define FUSE_BPMP_CONFIG_0_BPMP_CONFIG_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_BPMP_CONFIG_0_BPMP_CONFIG_FIELD                    _MK_FIELD_CONST(0xf, FUSE_BPMP_CONFIG_0_BPMP_CONFIG_SHIFT)
#define FUSE_BPMP_CONFIG_0_BPMP_CONFIG_RANGE                    3:0
#define FUSE_BPMP_CONFIG_0_BPMP_CONFIG_WOFFSET                  0x0
#define FUSE_BPMP_CONFIG_0_BPMP_CONFIG_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_BPMP_CONFIG_0_BPMP_CONFIG_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define FUSE_BPMP_CONFIG_0_BPMP_CONFIG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_BPMP_CONFIG_0_BPMP_CONFIG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_BPMP_CONFIG_0_BPMP_CONFIG_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_BPMP_CONFIG_0_BPMP_CONFIG_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_0
#define FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_0                      _MK_ADDR_CONST(0x460)
#define FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_0_SECURE                       0x0
#define FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_0_DUAL                         0x0
#define FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_0_SCR                  0
#define FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_0_WORD_COUNT                   0x1
#define FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_0_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_0_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_FIELD                    _MK_FIELD_CONST(0x1, FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_0_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_SHIFT)
#define FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_0_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_RANGE                    0:0
#define FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_0_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_WOFFSET                  0x0
#define FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_0_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_DEFAULT                  _MK_MASK_CONST(0x1)
#define FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_0_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_0_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_0_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_0_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_0_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_FUSE_UCODE_ACR_HS_REV_0
#define FUSE_OPT_FUSE_UCODE_ACR_HS_REV_0                        _MK_ADDR_CONST(0x464)
#define FUSE_OPT_FUSE_UCODE_ACR_HS_REV_0_SECURE                         0x0
#define FUSE_OPT_FUSE_UCODE_ACR_HS_REV_0_DUAL                   0x0
#define FUSE_OPT_FUSE_UCODE_ACR_HS_REV_0_SCR                    0
#define FUSE_OPT_FUSE_UCODE_ACR_HS_REV_0_WORD_COUNT                     0x1
#define FUSE_OPT_FUSE_UCODE_ACR_HS_REV_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_ACR_HS_REV_0_RESET_MASK                     _MK_MASK_CONST(0x7)
#define FUSE_OPT_FUSE_UCODE_ACR_HS_REV_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_ACR_HS_REV_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_ACR_HS_REV_0_READ_MASK                      _MK_MASK_CONST(0x7)
#define FUSE_OPT_FUSE_UCODE_ACR_HS_REV_0_WRITE_MASK                     _MK_MASK_CONST(0x7)
#define FUSE_OPT_FUSE_UCODE_ACR_HS_REV_0_OPT_FUSE_UCODE_ACR_HS_REV_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_OPT_FUSE_UCODE_ACR_HS_REV_0_OPT_FUSE_UCODE_ACR_HS_REV_FIELD                        _MK_FIELD_CONST(0x7, FUSE_OPT_FUSE_UCODE_ACR_HS_REV_0_OPT_FUSE_UCODE_ACR_HS_REV_SHIFT)
#define FUSE_OPT_FUSE_UCODE_ACR_HS_REV_0_OPT_FUSE_UCODE_ACR_HS_REV_RANGE                        2:0
#define FUSE_OPT_FUSE_UCODE_ACR_HS_REV_0_OPT_FUSE_UCODE_ACR_HS_REV_WOFFSET                      0x0
#define FUSE_OPT_FUSE_UCODE_ACR_HS_REV_0_OPT_FUSE_UCODE_ACR_HS_REV_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_ACR_HS_REV_0_OPT_FUSE_UCODE_ACR_HS_REV_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define FUSE_OPT_FUSE_UCODE_ACR_HS_REV_0_OPT_FUSE_UCODE_ACR_HS_REV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_ACR_HS_REV_0_OPT_FUSE_UCODE_ACR_HS_REV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_ACR_HS_REV_0_OPT_FUSE_UCODE_ACR_HS_REV_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_ACR_HS_REV_0_OPT_FUSE_UCODE_ACR_HS_REV_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_OPT_FUSE_UCODE_NVDEC_REV_0
#define FUSE_OPT_FUSE_UCODE_NVDEC_REV_0                 _MK_ADDR_CONST(0x468)
#define FUSE_OPT_FUSE_UCODE_NVDEC_REV_0_SECURE                  0x0
#define FUSE_OPT_FUSE_UCODE_NVDEC_REV_0_DUAL                    0x0
#define FUSE_OPT_FUSE_UCODE_NVDEC_REV_0_SCR                     0
#define FUSE_OPT_FUSE_UCODE_NVDEC_REV_0_WORD_COUNT                      0x1
#define FUSE_OPT_FUSE_UCODE_NVDEC_REV_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_NVDEC_REV_0_RESET_MASK                      _MK_MASK_CONST(0x7)
#define FUSE_OPT_FUSE_UCODE_NVDEC_REV_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_NVDEC_REV_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_NVDEC_REV_0_READ_MASK                       _MK_MASK_CONST(0x7)
#define FUSE_OPT_FUSE_UCODE_NVDEC_REV_0_WRITE_MASK                      _MK_MASK_CONST(0x7)
#define FUSE_OPT_FUSE_UCODE_NVDEC_REV_0_OPT_FUSE_UCODE_NVDEC_REV_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_OPT_FUSE_UCODE_NVDEC_REV_0_OPT_FUSE_UCODE_NVDEC_REV_FIELD                  _MK_FIELD_CONST(0x7, FUSE_OPT_FUSE_UCODE_NVDEC_REV_0_OPT_FUSE_UCODE_NVDEC_REV_SHIFT)
#define FUSE_OPT_FUSE_UCODE_NVDEC_REV_0_OPT_FUSE_UCODE_NVDEC_REV_RANGE                  2:0
#define FUSE_OPT_FUSE_UCODE_NVDEC_REV_0_OPT_FUSE_UCODE_NVDEC_REV_WOFFSET                        0x0
#define FUSE_OPT_FUSE_UCODE_NVDEC_REV_0_OPT_FUSE_UCODE_NVDEC_REV_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_NVDEC_REV_0_OPT_FUSE_UCODE_NVDEC_REV_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define FUSE_OPT_FUSE_UCODE_NVDEC_REV_0_OPT_FUSE_UCODE_NVDEC_REV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_NVDEC_REV_0_OPT_FUSE_UCODE_NVDEC_REV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_NVDEC_REV_0_OPT_FUSE_UCODE_NVDEC_REV_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_NVDEC_REV_0_OPT_FUSE_UCODE_NVDEC_REV_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_VCM_REVISION_0
#define FUSE_VCM_REVISION_0                     _MK_ADDR_CONST(0x46c)
#define FUSE_VCM_REVISION_0_SECURE                      0x0
#define FUSE_VCM_REVISION_0_DUAL                        0x0
#define FUSE_VCM_REVISION_0_SCR                         0
#define FUSE_VCM_REVISION_0_WORD_COUNT                  0x1
#define FUSE_VCM_REVISION_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_VCM_REVISION_0_RESET_MASK                  _MK_MASK_CONST(0x1f)
#define FUSE_VCM_REVISION_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_VCM_REVISION_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_VCM_REVISION_0_READ_MASK                   _MK_MASK_CONST(0x1f)
#define FUSE_VCM_REVISION_0_WRITE_MASK                  _MK_MASK_CONST(0x1f)
#define FUSE_VCM_REVISION_0_VCM_REVISION_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_VCM_REVISION_0_VCM_REVISION_FIELD                  _MK_FIELD_CONST(0x1f, FUSE_VCM_REVISION_0_VCM_REVISION_SHIFT)
#define FUSE_VCM_REVISION_0_VCM_REVISION_RANGE                  4:0
#define FUSE_VCM_REVISION_0_VCM_REVISION_WOFFSET                        0x0
#define FUSE_VCM_REVISION_0_VCM_REVISION_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_VCM_REVISION_0_VCM_REVISION_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define FUSE_VCM_REVISION_0_VCM_REVISION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_VCM_REVISION_0_VCM_REVISION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_VCM_REVISION_0_VCM_REVISION_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_VCM_REVISION_0_VCM_REVISION_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_0
#define FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_0                       _MK_ADDR_CONST(0x470)
#define FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_0_SECURE                        0x0
#define FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_0_DUAL                  0x0
#define FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_0_SCR                   0
#define FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_0_WORD_COUNT                    0x1
#define FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_0_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_0_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_FIELD                      _MK_FIELD_CONST(0x1, FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_0_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_SHIFT)
#define FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_0_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_RANGE                      0:0
#define FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_0_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_WOFFSET                    0x0
#define FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_0_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_0_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_0_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_0_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_0_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_0_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_CV_LT_IDDQ_CALIB_0
#define FUSE_CV_LT_IDDQ_CALIB_0                 _MK_ADDR_CONST(0x474)
#define FUSE_CV_LT_IDDQ_CALIB_0_SECURE                  0x0
#define FUSE_CV_LT_IDDQ_CALIB_0_DUAL                    0x0
#define FUSE_CV_LT_IDDQ_CALIB_0_SCR                     0
#define FUSE_CV_LT_IDDQ_CALIB_0_WORD_COUNT                      0x1
#define FUSE_CV_LT_IDDQ_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_CV_LT_IDDQ_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
#define FUSE_CV_LT_IDDQ_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_CV_LT_IDDQ_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_CV_LT_IDDQ_CALIB_0_READ_MASK                       _MK_MASK_CONST(0x3f)
#define FUSE_CV_LT_IDDQ_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0x3f)
#define FUSE_CV_LT_IDDQ_CALIB_0_CV_LT_IDDQ_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_CV_LT_IDDQ_CALIB_0_CV_LT_IDDQ_CALIB_FIELD                  _MK_FIELD_CONST(0x3f, FUSE_CV_LT_IDDQ_CALIB_0_CV_LT_IDDQ_CALIB_SHIFT)
#define FUSE_CV_LT_IDDQ_CALIB_0_CV_LT_IDDQ_CALIB_RANGE                  5:0
#define FUSE_CV_LT_IDDQ_CALIB_0_CV_LT_IDDQ_CALIB_WOFFSET                        0x0
#define FUSE_CV_LT_IDDQ_CALIB_0_CV_LT_IDDQ_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_CV_LT_IDDQ_CALIB_0_CV_LT_IDDQ_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
#define FUSE_CV_LT_IDDQ_CALIB_0_CV_LT_IDDQ_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_CV_LT_IDDQ_CALIB_0_CV_LT_IDDQ_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_CV_LT_IDDQ_CALIB_0_CV_LT_IDDQ_CALIB_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_CV_LT_IDDQ_CALIB_0_CV_LT_IDDQ_CALIB_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_CPU0_HT_IDDQ_CALIB_0
#define FUSE_CPU0_HT_IDDQ_CALIB_0                       _MK_ADDR_CONST(0x478)
#define FUSE_CPU0_HT_IDDQ_CALIB_0_SECURE                        0x0
#define FUSE_CPU0_HT_IDDQ_CALIB_0_DUAL                  0x0
#define FUSE_CPU0_HT_IDDQ_CALIB_0_SCR                   0
#define FUSE_CPU0_HT_IDDQ_CALIB_0_WORD_COUNT                    0x1
#define FUSE_CPU0_HT_IDDQ_CALIB_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_CPU0_HT_IDDQ_CALIB_0_RESET_MASK                    _MK_MASK_CONST(0xfff)
#define FUSE_CPU0_HT_IDDQ_CALIB_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_CPU0_HT_IDDQ_CALIB_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_CPU0_HT_IDDQ_CALIB_0_READ_MASK                     _MK_MASK_CONST(0xfff)
#define FUSE_CPU0_HT_IDDQ_CALIB_0_WRITE_MASK                    _MK_MASK_CONST(0xfff)
#define FUSE_CPU0_HT_IDDQ_CALIB_0_CPU0_HT_IDDQ_CALIB_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_CPU0_HT_IDDQ_CALIB_0_CPU0_HT_IDDQ_CALIB_FIELD                      _MK_FIELD_CONST(0xfff, FUSE_CPU0_HT_IDDQ_CALIB_0_CPU0_HT_IDDQ_CALIB_SHIFT)
#define FUSE_CPU0_HT_IDDQ_CALIB_0_CPU0_HT_IDDQ_CALIB_RANGE                      11:0
#define FUSE_CPU0_HT_IDDQ_CALIB_0_CPU0_HT_IDDQ_CALIB_WOFFSET                    0x0
#define FUSE_CPU0_HT_IDDQ_CALIB_0_CPU0_HT_IDDQ_CALIB_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_CPU0_HT_IDDQ_CALIB_0_CPU0_HT_IDDQ_CALIB_DEFAULT_MASK                       _MK_MASK_CONST(0xfff)
#define FUSE_CPU0_HT_IDDQ_CALIB_0_CPU0_HT_IDDQ_CALIB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_CPU0_HT_IDDQ_CALIB_0_CPU0_HT_IDDQ_CALIB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_CPU0_HT_IDDQ_CALIB_0_CPU0_HT_IDDQ_CALIB_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_CPU0_HT_IDDQ_CALIB_0_CPU0_HT_IDDQ_CALIB_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_RESERVED_IDDQ_CALIB_0
#define FUSE_RESERVED_IDDQ_CALIB_0                      _MK_ADDR_CONST(0x47c)
#define FUSE_RESERVED_IDDQ_CALIB_0_SECURE                       0x0
#define FUSE_RESERVED_IDDQ_CALIB_0_DUAL                         0x0
#define FUSE_RESERVED_IDDQ_CALIB_0_SCR                  0
#define FUSE_RESERVED_IDDQ_CALIB_0_WORD_COUNT                   0x1
#define FUSE_RESERVED_IDDQ_CALIB_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_IDDQ_CALIB_0_RESET_MASK                   _MK_MASK_CONST(0x3f)
#define FUSE_RESERVED_IDDQ_CALIB_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_IDDQ_CALIB_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_IDDQ_CALIB_0_READ_MASK                    _MK_MASK_CONST(0x3f)
#define FUSE_RESERVED_IDDQ_CALIB_0_WRITE_MASK                   _MK_MASK_CONST(0x3f)
#define FUSE_RESERVED_IDDQ_CALIB_0_RESERVED_IDDQ_CALIB_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_RESERVED_IDDQ_CALIB_0_RESERVED_IDDQ_CALIB_FIELD                    _MK_FIELD_CONST(0x3f, FUSE_RESERVED_IDDQ_CALIB_0_RESERVED_IDDQ_CALIB_SHIFT)
#define FUSE_RESERVED_IDDQ_CALIB_0_RESERVED_IDDQ_CALIB_RANGE                    5:0
#define FUSE_RESERVED_IDDQ_CALIB_0_RESERVED_IDDQ_CALIB_WOFFSET                  0x0
#define FUSE_RESERVED_IDDQ_CALIB_0_RESERVED_IDDQ_CALIB_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_IDDQ_CALIB_0_RESERVED_IDDQ_CALIB_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
#define FUSE_RESERVED_IDDQ_CALIB_0_RESERVED_IDDQ_CALIB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_IDDQ_CALIB_0_RESERVED_IDDQ_CALIB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_IDDQ_CALIB_0_RESERVED_IDDQ_CALIB_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_IDDQ_CALIB_0_RESERVED_IDDQ_CALIB_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_CV_HT_IDDQ_CALIB_0
#define FUSE_CV_HT_IDDQ_CALIB_0                 _MK_ADDR_CONST(0x480)
#define FUSE_CV_HT_IDDQ_CALIB_0_SECURE                  0x0
#define FUSE_CV_HT_IDDQ_CALIB_0_DUAL                    0x0
#define FUSE_CV_HT_IDDQ_CALIB_0_SCR                     0
#define FUSE_CV_HT_IDDQ_CALIB_0_WORD_COUNT                      0x1
#define FUSE_CV_HT_IDDQ_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_CV_HT_IDDQ_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0xfff)
#define FUSE_CV_HT_IDDQ_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_CV_HT_IDDQ_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_CV_HT_IDDQ_CALIB_0_READ_MASK                       _MK_MASK_CONST(0xfff)
#define FUSE_CV_HT_IDDQ_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0xfff)
#define FUSE_CV_HT_IDDQ_CALIB_0_CV_HT_IDDQ_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_CV_HT_IDDQ_CALIB_0_CV_HT_IDDQ_CALIB_FIELD                  _MK_FIELD_CONST(0xfff, FUSE_CV_HT_IDDQ_CALIB_0_CV_HT_IDDQ_CALIB_SHIFT)
#define FUSE_CV_HT_IDDQ_CALIB_0_CV_HT_IDDQ_CALIB_RANGE                  11:0
#define FUSE_CV_HT_IDDQ_CALIB_0_CV_HT_IDDQ_CALIB_WOFFSET                        0x0
#define FUSE_CV_HT_IDDQ_CALIB_0_CV_HT_IDDQ_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_CV_HT_IDDQ_CALIB_0_CV_HT_IDDQ_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0xfff)
#define FUSE_CV_HT_IDDQ_CALIB_0_CV_HT_IDDQ_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_CV_HT_IDDQ_CALIB_0_CV_HT_IDDQ_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_CV_HT_IDDQ_CALIB_0_CV_HT_IDDQ_CALIB_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_CV_HT_IDDQ_CALIB_0_CV_HT_IDDQ_CALIB_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_CPU1_LT_IDDQ_CALIB_0
#define FUSE_CPU1_LT_IDDQ_CALIB_0                       _MK_ADDR_CONST(0x484)
#define FUSE_CPU1_LT_IDDQ_CALIB_0_SECURE                        0x0
#define FUSE_CPU1_LT_IDDQ_CALIB_0_DUAL                  0x0
#define FUSE_CPU1_LT_IDDQ_CALIB_0_SCR                   0
#define FUSE_CPU1_LT_IDDQ_CALIB_0_WORD_COUNT                    0x1
#define FUSE_CPU1_LT_IDDQ_CALIB_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_CPU1_LT_IDDQ_CALIB_0_RESET_MASK                    _MK_MASK_CONST(0x3f)
#define FUSE_CPU1_LT_IDDQ_CALIB_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_CPU1_LT_IDDQ_CALIB_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_CPU1_LT_IDDQ_CALIB_0_READ_MASK                     _MK_MASK_CONST(0x3f)
#define FUSE_CPU1_LT_IDDQ_CALIB_0_WRITE_MASK                    _MK_MASK_CONST(0x3f)
#define FUSE_CPU1_LT_IDDQ_CALIB_0_CPU1_LT_IDDQ_CALIB_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_CPU1_LT_IDDQ_CALIB_0_CPU1_LT_IDDQ_CALIB_FIELD                      _MK_FIELD_CONST(0x3f, FUSE_CPU1_LT_IDDQ_CALIB_0_CPU1_LT_IDDQ_CALIB_SHIFT)
#define FUSE_CPU1_LT_IDDQ_CALIB_0_CPU1_LT_IDDQ_CALIB_RANGE                      5:0
#define FUSE_CPU1_LT_IDDQ_CALIB_0_CPU1_LT_IDDQ_CALIB_WOFFSET                    0x0
#define FUSE_CPU1_LT_IDDQ_CALIB_0_CPU1_LT_IDDQ_CALIB_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_CPU1_LT_IDDQ_CALIB_0_CPU1_LT_IDDQ_CALIB_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
#define FUSE_CPU1_LT_IDDQ_CALIB_0_CPU1_LT_IDDQ_CALIB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_CPU1_LT_IDDQ_CALIB_0_CPU1_LT_IDDQ_CALIB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_CPU1_LT_IDDQ_CALIB_0_CPU1_LT_IDDQ_CALIB_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_CPU1_LT_IDDQ_CALIB_0_CPU1_LT_IDDQ_CALIB_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_CPU0_LT_IDDQ_CALIB_0
#define FUSE_CPU0_LT_IDDQ_CALIB_0                       _MK_ADDR_CONST(0x488)
#define FUSE_CPU0_LT_IDDQ_CALIB_0_SECURE                        0x0
#define FUSE_CPU0_LT_IDDQ_CALIB_0_DUAL                  0x0
#define FUSE_CPU0_LT_IDDQ_CALIB_0_SCR                   0
#define FUSE_CPU0_LT_IDDQ_CALIB_0_WORD_COUNT                    0x1
#define FUSE_CPU0_LT_IDDQ_CALIB_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_CPU0_LT_IDDQ_CALIB_0_RESET_MASK                    _MK_MASK_CONST(0x3f)
#define FUSE_CPU0_LT_IDDQ_CALIB_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_CPU0_LT_IDDQ_CALIB_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_CPU0_LT_IDDQ_CALIB_0_READ_MASK                     _MK_MASK_CONST(0x3f)
#define FUSE_CPU0_LT_IDDQ_CALIB_0_WRITE_MASK                    _MK_MASK_CONST(0x3f)
#define FUSE_CPU0_LT_IDDQ_CALIB_0_CPU0_LT_IDDQ_CALIB_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_CPU0_LT_IDDQ_CALIB_0_CPU0_LT_IDDQ_CALIB_FIELD                      _MK_FIELD_CONST(0x3f, FUSE_CPU0_LT_IDDQ_CALIB_0_CPU0_LT_IDDQ_CALIB_SHIFT)
#define FUSE_CPU0_LT_IDDQ_CALIB_0_CPU0_LT_IDDQ_CALIB_RANGE                      5:0
#define FUSE_CPU0_LT_IDDQ_CALIB_0_CPU0_LT_IDDQ_CALIB_WOFFSET                    0x0
#define FUSE_CPU0_LT_IDDQ_CALIB_0_CPU0_LT_IDDQ_CALIB_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_CPU0_LT_IDDQ_CALIB_0_CPU0_LT_IDDQ_CALIB_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
#define FUSE_CPU0_LT_IDDQ_CALIB_0_CPU0_LT_IDDQ_CALIB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_CPU0_LT_IDDQ_CALIB_0_CPU0_LT_IDDQ_CALIB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_CPU0_LT_IDDQ_CALIB_0_CPU0_LT_IDDQ_CALIB_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_CPU0_LT_IDDQ_CALIB_0_CPU0_LT_IDDQ_CALIB_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_SOC_LT_IDDQ_CALIB_0
#define FUSE_SOC_LT_IDDQ_CALIB_0                        _MK_ADDR_CONST(0x48c)
#define FUSE_SOC_LT_IDDQ_CALIB_0_SECURE                         0x0
#define FUSE_SOC_LT_IDDQ_CALIB_0_DUAL                   0x0
#define FUSE_SOC_LT_IDDQ_CALIB_0_SCR                    0
#define FUSE_SOC_LT_IDDQ_CALIB_0_WORD_COUNT                     0x1
#define FUSE_SOC_LT_IDDQ_CALIB_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SOC_LT_IDDQ_CALIB_0_RESET_MASK                     _MK_MASK_CONST(0x3f)
#define FUSE_SOC_LT_IDDQ_CALIB_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_SOC_LT_IDDQ_CALIB_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SOC_LT_IDDQ_CALIB_0_READ_MASK                      _MK_MASK_CONST(0x3f)
#define FUSE_SOC_LT_IDDQ_CALIB_0_WRITE_MASK                     _MK_MASK_CONST(0x3f)
#define FUSE_SOC_LT_IDDQ_CALIB_0_SOC_LT_IDDQ_CALIB_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_SOC_LT_IDDQ_CALIB_0_SOC_LT_IDDQ_CALIB_FIELD                        _MK_FIELD_CONST(0x3f, FUSE_SOC_LT_IDDQ_CALIB_0_SOC_LT_IDDQ_CALIB_SHIFT)
#define FUSE_SOC_LT_IDDQ_CALIB_0_SOC_LT_IDDQ_CALIB_RANGE                        5:0
#define FUSE_SOC_LT_IDDQ_CALIB_0_SOC_LT_IDDQ_CALIB_WOFFSET                      0x0
#define FUSE_SOC_LT_IDDQ_CALIB_0_SOC_LT_IDDQ_CALIB_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_SOC_LT_IDDQ_CALIB_0_SOC_LT_IDDQ_CALIB_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define FUSE_SOC_LT_IDDQ_CALIB_0_SOC_LT_IDDQ_CALIB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_SOC_LT_IDDQ_CALIB_0_SOC_LT_IDDQ_CALIB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_SOC_LT_IDDQ_CALIB_0_SOC_LT_IDDQ_CALIB_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_SOC_LT_IDDQ_CALIB_0_SOC_LT_IDDQ_CALIB_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_GPU_LT_IDDQ_CALIB_0
#define FUSE_GPU_LT_IDDQ_CALIB_0                        _MK_ADDR_CONST(0x490)
#define FUSE_GPU_LT_IDDQ_CALIB_0_SECURE                         0x0
#define FUSE_GPU_LT_IDDQ_CALIB_0_DUAL                   0x0
#define FUSE_GPU_LT_IDDQ_CALIB_0_SCR                    0
#define FUSE_GPU_LT_IDDQ_CALIB_0_WORD_COUNT                     0x1
#define FUSE_GPU_LT_IDDQ_CALIB_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_GPU_LT_IDDQ_CALIB_0_RESET_MASK                     _MK_MASK_CONST(0x3f)
#define FUSE_GPU_LT_IDDQ_CALIB_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_GPU_LT_IDDQ_CALIB_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_GPU_LT_IDDQ_CALIB_0_READ_MASK                      _MK_MASK_CONST(0x3f)
#define FUSE_GPU_LT_IDDQ_CALIB_0_WRITE_MASK                     _MK_MASK_CONST(0x3f)
#define FUSE_GPU_LT_IDDQ_CALIB_0_GPU_LT_IDDQ_CALIB_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_GPU_LT_IDDQ_CALIB_0_GPU_LT_IDDQ_CALIB_FIELD                        _MK_FIELD_CONST(0x3f, FUSE_GPU_LT_IDDQ_CALIB_0_GPU_LT_IDDQ_CALIB_SHIFT)
#define FUSE_GPU_LT_IDDQ_CALIB_0_GPU_LT_IDDQ_CALIB_RANGE                        5:0
#define FUSE_GPU_LT_IDDQ_CALIB_0_GPU_LT_IDDQ_CALIB_WOFFSET                      0x0
#define FUSE_GPU_LT_IDDQ_CALIB_0_GPU_LT_IDDQ_CALIB_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_GPU_LT_IDDQ_CALIB_0_GPU_LT_IDDQ_CALIB_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define FUSE_GPU_LT_IDDQ_CALIB_0_GPU_LT_IDDQ_CALIB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_GPU_LT_IDDQ_CALIB_0_GPU_LT_IDDQ_CALIB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_GPU_LT_IDDQ_CALIB_0_GPU_LT_IDDQ_CALIB_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_GPU_LT_IDDQ_CALIB_0_GPU_LT_IDDQ_CALIB_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_OPT_INTERNAL_SKU_0
#define FUSE_OPT_INTERNAL_SKU_0                 _MK_ADDR_CONST(0x494)
#define FUSE_OPT_INTERNAL_SKU_0_SECURE                  0x0
#define FUSE_OPT_INTERNAL_SKU_0_DUAL                    0x0
#define FUSE_OPT_INTERNAL_SKU_0_SCR                     0
#define FUSE_OPT_INTERNAL_SKU_0_WORD_COUNT                      0x1
#define FUSE_OPT_INTERNAL_SKU_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_INTERNAL_SKU_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_OPT_INTERNAL_SKU_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_INTERNAL_SKU_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_INTERNAL_SKU_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_OPT_INTERNAL_SKU_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_OPT_INTERNAL_SKU_0_OPT_INTERNAL_SKU_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_OPT_INTERNAL_SKU_0_OPT_INTERNAL_SKU_FIELD                  _MK_FIELD_CONST(0x1, FUSE_OPT_INTERNAL_SKU_0_OPT_INTERNAL_SKU_SHIFT)
#define FUSE_OPT_INTERNAL_SKU_0_OPT_INTERNAL_SKU_RANGE                  0:0
#define FUSE_OPT_INTERNAL_SKU_0_OPT_INTERNAL_SKU_WOFFSET                        0x0
#define FUSE_OPT_INTERNAL_SKU_0_OPT_INTERNAL_SKU_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_INTERNAL_SKU_0_OPT_INTERNAL_SKU_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_OPT_INTERNAL_SKU_0_OPT_INTERNAL_SKU_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_INTERNAL_SKU_0_OPT_INTERNAL_SKU_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_INTERNAL_SKU_0_OPT_INTERNAL_SKU_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_INTERNAL_SKU_0_OPT_INTERNAL_SKU_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_FUSE2NVDEC_DEBUG_DISABLE_0
#define FUSE_FUSE2NVDEC_DEBUG_DISABLE_0                 _MK_ADDR_CONST(0x498)
#define FUSE_FUSE2NVDEC_DEBUG_DISABLE_0_SECURE                  0x0
#define FUSE_FUSE2NVDEC_DEBUG_DISABLE_0_DUAL                    0x0
#define FUSE_FUSE2NVDEC_DEBUG_DISABLE_0_SCR                     0
#define FUSE_FUSE2NVDEC_DEBUG_DISABLE_0_WORD_COUNT                      0x1
#define FUSE_FUSE2NVDEC_DEBUG_DISABLE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_FUSE2NVDEC_DEBUG_DISABLE_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_FUSE2NVDEC_DEBUG_DISABLE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_FUSE2NVDEC_DEBUG_DISABLE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_FUSE2NVDEC_DEBUG_DISABLE_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_FUSE2NVDEC_DEBUG_DISABLE_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_FUSE2NVDEC_DEBUG_DISABLE_0_FUSE2NVDEC_DEBUG_DISABLE_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_FUSE2NVDEC_DEBUG_DISABLE_0_FUSE2NVDEC_DEBUG_DISABLE_FIELD                  _MK_FIELD_CONST(0x1, FUSE_FUSE2NVDEC_DEBUG_DISABLE_0_FUSE2NVDEC_DEBUG_DISABLE_SHIFT)
#define FUSE_FUSE2NVDEC_DEBUG_DISABLE_0_FUSE2NVDEC_DEBUG_DISABLE_RANGE                  0:0
#define FUSE_FUSE2NVDEC_DEBUG_DISABLE_0_FUSE2NVDEC_DEBUG_DISABLE_WOFFSET                        0x0
#define FUSE_FUSE2NVDEC_DEBUG_DISABLE_0_FUSE2NVDEC_DEBUG_DISABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_FUSE2NVDEC_DEBUG_DISABLE_0_FUSE2NVDEC_DEBUG_DISABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_FUSE2NVDEC_DEBUG_DISABLE_0_FUSE2NVDEC_DEBUG_DISABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_FUSE2NVDEC_DEBUG_DISABLE_0_FUSE2NVDEC_DEBUG_DISABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_FUSE2NVDEC_DEBUG_DISABLE_0_FUSE2NVDEC_DEBUG_DISABLE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_FUSE2NVDEC_DEBUG_DISABLE_0_FUSE2NVDEC_DEBUG_DISABLE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SATA_NV_CALIB_0
#define FUSE_SATA_NV_CALIB_0                    _MK_ADDR_CONST(0x49c)
#define FUSE_SATA_NV_CALIB_0_SECURE                     0x0
#define FUSE_SATA_NV_CALIB_0_DUAL                       0x0
#define FUSE_SATA_NV_CALIB_0_SCR                        0
#define FUSE_SATA_NV_CALIB_0_WORD_COUNT                         0x1
#define FUSE_SATA_NV_CALIB_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_SATA_NV_CALIB_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define FUSE_SATA_NV_CALIB_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_SATA_NV_CALIB_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_SATA_NV_CALIB_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define FUSE_SATA_NV_CALIB_0_WRITE_MASK                         _MK_MASK_CONST(0xf)
#define FUSE_SATA_NV_CALIB_0_SATA_NV_CALIB_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_SATA_NV_CALIB_0_SATA_NV_CALIB_FIELD                        _MK_FIELD_CONST(0xf, FUSE_SATA_NV_CALIB_0_SATA_NV_CALIB_SHIFT)
#define FUSE_SATA_NV_CALIB_0_SATA_NV_CALIB_RANGE                        3:0
#define FUSE_SATA_NV_CALIB_0_SATA_NV_CALIB_WOFFSET                      0x0
#define FUSE_SATA_NV_CALIB_0_SATA_NV_CALIB_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_SATA_NV_CALIB_0_SATA_NV_CALIB_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define FUSE_SATA_NV_CALIB_0_SATA_NV_CALIB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_SATA_NV_CALIB_0_SATA_NV_CALIB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_SATA_NV_CALIB_0_SATA_NV_CALIB_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_SATA_NV_CALIB_0_SATA_NV_CALIB_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_MPHY_NV_CALIB_0
#define FUSE_MPHY_NV_CALIB_0                    _MK_ADDR_CONST(0x4a0)
#define FUSE_MPHY_NV_CALIB_0_SECURE                     0x0
#define FUSE_MPHY_NV_CALIB_0_DUAL                       0x0
#define FUSE_MPHY_NV_CALIB_0_SCR                        0
#define FUSE_MPHY_NV_CALIB_0_WORD_COUNT                         0x1
#define FUSE_MPHY_NV_CALIB_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_MPHY_NV_CALIB_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
#define FUSE_MPHY_NV_CALIB_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_MPHY_NV_CALIB_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_MPHY_NV_CALIB_0_READ_MASK                  _MK_MASK_CONST(0x3f)
#define FUSE_MPHY_NV_CALIB_0_WRITE_MASK                         _MK_MASK_CONST(0x3f)
#define FUSE_MPHY_NV_CALIB_0_MPHY_NV_CALIB_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_MPHY_NV_CALIB_0_MPHY_NV_CALIB_FIELD                        _MK_FIELD_CONST(0x3f, FUSE_MPHY_NV_CALIB_0_MPHY_NV_CALIB_SHIFT)
#define FUSE_MPHY_NV_CALIB_0_MPHY_NV_CALIB_RANGE                        5:0
#define FUSE_MPHY_NV_CALIB_0_MPHY_NV_CALIB_WOFFSET                      0x0
#define FUSE_MPHY_NV_CALIB_0_MPHY_NV_CALIB_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_MPHY_NV_CALIB_0_MPHY_NV_CALIB_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define FUSE_MPHY_NV_CALIB_0_MPHY_NV_CALIB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_MPHY_NV_CALIB_0_MPHY_NV_CALIB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_MPHY_NV_CALIB_0_MPHY_NV_CALIB_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_MPHY_NV_CALIB_0_MPHY_NV_CALIB_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Reserved address 0x4a4

// Register FUSE_BOOTROM_PATCH_VERSION_0
#define FUSE_BOOTROM_PATCH_VERSION_0                    _MK_ADDR_CONST(0x4a8)
#define FUSE_BOOTROM_PATCH_VERSION_0_SECURE                     0x0
#define FUSE_BOOTROM_PATCH_VERSION_0_DUAL                       0x0
#define FUSE_BOOTROM_PATCH_VERSION_0_SCR                        0
#define FUSE_BOOTROM_PATCH_VERSION_0_WORD_COUNT                         0x1
#define FUSE_BOOTROM_PATCH_VERSION_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_BOOTROM_PATCH_VERSION_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define FUSE_BOOTROM_PATCH_VERSION_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_BOOTROM_PATCH_VERSION_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_BOOTROM_PATCH_VERSION_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define FUSE_BOOTROM_PATCH_VERSION_0_WRITE_MASK                         _MK_MASK_CONST(0xff)
#define FUSE_BOOTROM_PATCH_VERSION_0_BOOTROM_PATCH_VERSION_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_BOOTROM_PATCH_VERSION_0_BOOTROM_PATCH_VERSION_FIELD                        _MK_FIELD_CONST(0xff, FUSE_BOOTROM_PATCH_VERSION_0_BOOTROM_PATCH_VERSION_SHIFT)
#define FUSE_BOOTROM_PATCH_VERSION_0_BOOTROM_PATCH_VERSION_RANGE                        7:0
#define FUSE_BOOTROM_PATCH_VERSION_0_BOOTROM_PATCH_VERSION_WOFFSET                      0x0
#define FUSE_BOOTROM_PATCH_VERSION_0_BOOTROM_PATCH_VERSION_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_BOOTROM_PATCH_VERSION_0_BOOTROM_PATCH_VERSION_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define FUSE_BOOTROM_PATCH_VERSION_0_BOOTROM_PATCH_VERSION_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_BOOTROM_PATCH_VERSION_0_BOOTROM_PATCH_VERSION_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_BOOTROM_PATCH_VERSION_0_BOOTROM_PATCH_VERSION_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_BOOTROM_PATCH_VERSION_0_BOOTROM_PATCH_VERSION_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_OPT_SFK_ACC_DIS_0
#define FUSE_OPT_SFK_ACC_DIS_0                  _MK_ADDR_CONST(0x4ac)
#define FUSE_OPT_SFK_ACC_DIS_0_SECURE                   0x0
#define FUSE_OPT_SFK_ACC_DIS_0_DUAL                     0x0
#define FUSE_OPT_SFK_ACC_DIS_0_SCR                      0
#define FUSE_OPT_SFK_ACC_DIS_0_WORD_COUNT                       0x1
#define FUSE_OPT_SFK_ACC_DIS_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define FUSE_OPT_SFK_ACC_DIS_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_OPT_SFK_ACC_DIS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_SFK_ACC_DIS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_SFK_ACC_DIS_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_OPT_SFK_ACC_DIS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_SFK_ACC_DIS_0_OPT_SFK_ACC_DIS_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_SFK_ACC_DIS_0_OPT_SFK_ACC_DIS_FIELD                    _MK_FIELD_CONST(0x1, FUSE_OPT_SFK_ACC_DIS_0_OPT_SFK_ACC_DIS_SHIFT)
#define FUSE_OPT_SFK_ACC_DIS_0_OPT_SFK_ACC_DIS_RANGE                    0:0
#define FUSE_OPT_SFK_ACC_DIS_0_OPT_SFK_ACC_DIS_WOFFSET                  0x0
#define FUSE_OPT_SFK_ACC_DIS_0_OPT_SFK_ACC_DIS_DEFAULT                  _MK_MASK_CONST(0x1)
#define FUSE_OPT_SFK_ACC_DIS_0_OPT_SFK_ACC_DIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_OPT_SFK_ACC_DIS_0_OPT_SFK_ACC_DIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_SFK_ACC_DIS_0_OPT_SFK_ACC_DIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_SFK_ACC_DIS_0_OPT_SFK_ACC_DIS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_SFK_ACC_DIS_0_OPT_SFK_ACC_DIS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_PDK_ACC_DIS_0
#define FUSE_OPT_PDK_ACC_DIS_0                  _MK_ADDR_CONST(0x4b0)
#define FUSE_OPT_PDK_ACC_DIS_0_SECURE                   0x0
#define FUSE_OPT_PDK_ACC_DIS_0_DUAL                     0x0
#define FUSE_OPT_PDK_ACC_DIS_0_SCR                      0
#define FUSE_OPT_PDK_ACC_DIS_0_WORD_COUNT                       0x1
#define FUSE_OPT_PDK_ACC_DIS_0_RESET_VAL                        _MK_MASK_CONST(0x1)
#define FUSE_OPT_PDK_ACC_DIS_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_OPT_PDK_ACC_DIS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_PDK_ACC_DIS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PDK_ACC_DIS_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_OPT_PDK_ACC_DIS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_PDK_ACC_DIS_0_OPT_PDK_ACC_DIS_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_PDK_ACC_DIS_0_OPT_PDK_ACC_DIS_FIELD                    _MK_FIELD_CONST(0x1, FUSE_OPT_PDK_ACC_DIS_0_OPT_PDK_ACC_DIS_SHIFT)
#define FUSE_OPT_PDK_ACC_DIS_0_OPT_PDK_ACC_DIS_RANGE                    0:0
#define FUSE_OPT_PDK_ACC_DIS_0_OPT_PDK_ACC_DIS_WOFFSET                  0x0
#define FUSE_OPT_PDK_ACC_DIS_0_OPT_PDK_ACC_DIS_DEFAULT                  _MK_MASK_CONST(0x1)
#define FUSE_OPT_PDK_ACC_DIS_0_OPT_PDK_ACC_DIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_OPT_PDK_ACC_DIS_0_OPT_PDK_ACC_DIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_PDK_ACC_DIS_0_OPT_PDK_ACC_DIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PDK_ACC_DIS_0_OPT_PDK_ACC_DIS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_PDK_ACC_DIS_0_OPT_PDK_ACC_DIS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_INVALID_BITS_ATE_0
#define FUSE_OPT_INVALID_BITS_ATE_0                     _MK_ADDR_CONST(0x4b4)
#define FUSE_OPT_INVALID_BITS_ATE_0_SECURE                      0x0
#define FUSE_OPT_INVALID_BITS_ATE_0_DUAL                        0x0
#define FUSE_OPT_INVALID_BITS_ATE_0_SCR                         0
#define FUSE_OPT_INVALID_BITS_ATE_0_WORD_COUNT                  0x1
#define FUSE_OPT_INVALID_BITS_ATE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_INVALID_BITS_ATE_0_RESET_MASK                  _MK_MASK_CONST(0xffff)
#define FUSE_OPT_INVALID_BITS_ATE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_INVALID_BITS_ATE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_INVALID_BITS_ATE_0_READ_MASK                   _MK_MASK_CONST(0xffff)
#define FUSE_OPT_INVALID_BITS_ATE_0_WRITE_MASK                  _MK_MASK_CONST(0xffff)
#define FUSE_OPT_INVALID_BITS_ATE_0_OPT_INVALID_BITS_ATE_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_OPT_INVALID_BITS_ATE_0_OPT_INVALID_BITS_ATE_FIELD                  _MK_FIELD_CONST(0xffff, FUSE_OPT_INVALID_BITS_ATE_0_OPT_INVALID_BITS_ATE_SHIFT)
#define FUSE_OPT_INVALID_BITS_ATE_0_OPT_INVALID_BITS_ATE_RANGE                  15:0
#define FUSE_OPT_INVALID_BITS_ATE_0_OPT_INVALID_BITS_ATE_WOFFSET                        0x0
#define FUSE_OPT_INVALID_BITS_ATE_0_OPT_INVALID_BITS_ATE_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_INVALID_BITS_ATE_0_OPT_INVALID_BITS_ATE_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
#define FUSE_OPT_INVALID_BITS_ATE_0_OPT_INVALID_BITS_ATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_INVALID_BITS_ATE_0_OPT_INVALID_BITS_ATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_INVALID_BITS_ATE_0_OPT_INVALID_BITS_ATE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_INVALID_BITS_ATE_0_OPT_INVALID_BITS_ATE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_MB1_NV_REV_0
#define FUSE_MB1_NV_REV_0                       _MK_ADDR_CONST(0x4b8)
#define FUSE_MB1_NV_REV_0_SECURE                        0x0
#define FUSE_MB1_NV_REV_0_DUAL                  0x0
#define FUSE_MB1_NV_REV_0_SCR                   0
#define FUSE_MB1_NV_REV_0_WORD_COUNT                    0x1
#define FUSE_MB1_NV_REV_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_MB1_NV_REV_0_RESET_MASK                    _MK_MASK_CONST(0x7f)
#define FUSE_MB1_NV_REV_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_MB1_NV_REV_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_MB1_NV_REV_0_READ_MASK                     _MK_MASK_CONST(0x7f)
#define FUSE_MB1_NV_REV_0_WRITE_MASK                    _MK_MASK_CONST(0x7f)
#define FUSE_MB1_NV_REV_0_MB1_NV_REV_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_MB1_NV_REV_0_MB1_NV_REV_FIELD                      _MK_FIELD_CONST(0x7f, FUSE_MB1_NV_REV_0_MB1_NV_REV_SHIFT)
#define FUSE_MB1_NV_REV_0_MB1_NV_REV_RANGE                      6:0
#define FUSE_MB1_NV_REV_0_MB1_NV_REV_WOFFSET                    0x0
#define FUSE_MB1_NV_REV_0_MB1_NV_REV_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_MB1_NV_REV_0_MB1_NV_REV_DEFAULT_MASK                       _MK_MASK_CONST(0x7f)
#define FUSE_MB1_NV_REV_0_MB1_NV_REV_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_MB1_NV_REV_0_MB1_NV_REV_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_MB1_NV_REV_0_MB1_NV_REV_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_MB1_NV_REV_0_MB1_NV_REV_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_0
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_0                     _MK_ADDR_CONST(0x4bc)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_0_SECURE                      0x0
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_0_DUAL                        0x0
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_0_SCR                         0
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_0_WORD_COUNT                  0x1
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_FIELD                  _MK_FIELD_CONST(0xffffffff, FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_SHIFT)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_RANGE                  31:0
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_WOFFSET                        0x0
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_AGING_SENSOR_VERSION_0
#define FUSE_AGING_SENSOR_VERSION_0                     _MK_ADDR_CONST(0x4c0)
#define FUSE_AGING_SENSOR_VERSION_0_SECURE                      0x0
#define FUSE_AGING_SENSOR_VERSION_0_DUAL                        0x0
#define FUSE_AGING_SENSOR_VERSION_0_SCR                         0
#define FUSE_AGING_SENSOR_VERSION_0_WORD_COUNT                  0x1
#define FUSE_AGING_SENSOR_VERSION_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_AGING_SENSOR_VERSION_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define FUSE_AGING_SENSOR_VERSION_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_AGING_SENSOR_VERSION_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_AGING_SENSOR_VERSION_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define FUSE_AGING_SENSOR_VERSION_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
#define FUSE_AGING_SENSOR_VERSION_0_AGING_SENSOR_VERSION_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_AGING_SENSOR_VERSION_0_AGING_SENSOR_VERSION_FIELD                  _MK_FIELD_CONST(0x3, FUSE_AGING_SENSOR_VERSION_0_AGING_SENSOR_VERSION_SHIFT)
#define FUSE_AGING_SENSOR_VERSION_0_AGING_SENSOR_VERSION_RANGE                  1:0
#define FUSE_AGING_SENSOR_VERSION_0_AGING_SENSOR_VERSION_WOFFSET                        0x0
#define FUSE_AGING_SENSOR_VERSION_0_AGING_SENSOR_VERSION_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_AGING_SENSOR_VERSION_0_AGING_SENSOR_VERSION_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define FUSE_AGING_SENSOR_VERSION_0_AGING_SENSOR_VERSION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_AGING_SENSOR_VERSION_0_AGING_SENSOR_VERSION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_AGING_SENSOR_VERSION_0_AGING_SENSOR_VERSION_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_AGING_SENSOR_VERSION_0_AGING_SENSOR_VERSION_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPEEDO_IDDQ_VERSION_0
#define FUSE_SPEEDO_IDDQ_VERSION_0                      _MK_ADDR_CONST(0x4c4)
#define FUSE_SPEEDO_IDDQ_VERSION_0_SECURE                       0x0
#define FUSE_SPEEDO_IDDQ_VERSION_0_DUAL                         0x0
#define FUSE_SPEEDO_IDDQ_VERSION_0_SCR                  0
#define FUSE_SPEEDO_IDDQ_VERSION_0_WORD_COUNT                   0x1
#define FUSE_SPEEDO_IDDQ_VERSION_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_SPEEDO_IDDQ_VERSION_0_RESET_MASK                   _MK_MASK_CONST(0x7)
#define FUSE_SPEEDO_IDDQ_VERSION_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_SPEEDO_IDDQ_VERSION_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_SPEEDO_IDDQ_VERSION_0_READ_MASK                    _MK_MASK_CONST(0x7)
#define FUSE_SPEEDO_IDDQ_VERSION_0_WRITE_MASK                   _MK_MASK_CONST(0x7)
#define FUSE_SPEEDO_IDDQ_VERSION_0_SPEEDO_IDDQ_VERSION_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_SPEEDO_IDDQ_VERSION_0_SPEEDO_IDDQ_VERSION_FIELD                    _MK_FIELD_CONST(0x7, FUSE_SPEEDO_IDDQ_VERSION_0_SPEEDO_IDDQ_VERSION_SHIFT)
#define FUSE_SPEEDO_IDDQ_VERSION_0_SPEEDO_IDDQ_VERSION_RANGE                    2:0
#define FUSE_SPEEDO_IDDQ_VERSION_0_SPEEDO_IDDQ_VERSION_WOFFSET                  0x0
#define FUSE_SPEEDO_IDDQ_VERSION_0_SPEEDO_IDDQ_VERSION_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_SPEEDO_IDDQ_VERSION_0_SPEEDO_IDDQ_VERSION_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define FUSE_SPEEDO_IDDQ_VERSION_0_SPEEDO_IDDQ_VERSION_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_SPEEDO_IDDQ_VERSION_0_SPEEDO_IDDQ_VERSION_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPEEDO_IDDQ_VERSION_0_SPEEDO_IDDQ_VERSION_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_SPEEDO_IDDQ_VERSION_0_SPEEDO_IDDQ_VERSION_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_FORCE_DEBUG_WITH_TEST_KEYS_0
#define FUSE_FORCE_DEBUG_WITH_TEST_KEYS_0                       _MK_ADDR_CONST(0x4c8)
#define FUSE_FORCE_DEBUG_WITH_TEST_KEYS_0_SECURE                        0x0
#define FUSE_FORCE_DEBUG_WITH_TEST_KEYS_0_DUAL                  0x0
#define FUSE_FORCE_DEBUG_WITH_TEST_KEYS_0_SCR                   0
#define FUSE_FORCE_DEBUG_WITH_TEST_KEYS_0_WORD_COUNT                    0x1
#define FUSE_FORCE_DEBUG_WITH_TEST_KEYS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_FORCE_DEBUG_WITH_TEST_KEYS_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_FORCE_DEBUG_WITH_TEST_KEYS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_FORCE_DEBUG_WITH_TEST_KEYS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_FORCE_DEBUG_WITH_TEST_KEYS_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_FORCE_DEBUG_WITH_TEST_KEYS_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_FORCE_DEBUG_WITH_TEST_KEYS_0_FORCE_DEBUG_WITH_TEST_KEYS_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_FORCE_DEBUG_WITH_TEST_KEYS_0_FORCE_DEBUG_WITH_TEST_KEYS_FIELD                      _MK_FIELD_CONST(0x1, FUSE_FORCE_DEBUG_WITH_TEST_KEYS_0_FORCE_DEBUG_WITH_TEST_KEYS_SHIFT)
#define FUSE_FORCE_DEBUG_WITH_TEST_KEYS_0_FORCE_DEBUG_WITH_TEST_KEYS_RANGE                      0:0
#define FUSE_FORCE_DEBUG_WITH_TEST_KEYS_0_FORCE_DEBUG_WITH_TEST_KEYS_WOFFSET                    0x0
#define FUSE_FORCE_DEBUG_WITH_TEST_KEYS_0_FORCE_DEBUG_WITH_TEST_KEYS_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_FORCE_DEBUG_WITH_TEST_KEYS_0_FORCE_DEBUG_WITH_TEST_KEYS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_FORCE_DEBUG_WITH_TEST_KEYS_0_FORCE_DEBUG_WITH_TEST_KEYS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_FORCE_DEBUG_WITH_TEST_KEYS_0_FORCE_DEBUG_WITH_TEST_KEYS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_FORCE_DEBUG_WITH_TEST_KEYS_0_FORCE_DEBUG_WITH_TEST_KEYS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_FORCE_DEBUG_WITH_TEST_KEYS_0_FORCE_DEBUG_WITH_TEST_KEYS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_0
#define FUSE_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_0                        _MK_ADDR_CONST(0x4cc)
#define FUSE_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_0_SECURE                         0x0
#define FUSE_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_0_DUAL                   0x0
#define FUSE_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_0_SCR                    0
#define FUSE_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_0_WORD_COUNT                     0x1
#define FUSE_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_0_RESET_MASK                     _MK_MASK_CONST(0x7)
#define FUSE_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_0_READ_MASK                      _MK_MASK_CONST(0x7)
#define FUSE_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_0_WRITE_MASK                     _MK_MASK_CONST(0x7)
#define FUSE_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_0_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_0_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_FIELD                        _MK_FIELD_CONST(0x7, FUSE_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_0_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_SHIFT)
#define FUSE_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_0_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_RANGE                        2:0
#define FUSE_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_0_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_WOFFSET                      0x0
#define FUSE_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_0_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_0_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define FUSE_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_0_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_0_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_0_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_0_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Reserved address 0x4d0

// Reserved address 0x4d4

// Register FUSE_OPT_ISP_DISABLE_0
#define FUSE_OPT_ISP_DISABLE_0                  _MK_ADDR_CONST(0x4d8)
#define FUSE_OPT_ISP_DISABLE_0_SECURE                   0x0
#define FUSE_OPT_ISP_DISABLE_0_DUAL                     0x0
#define FUSE_OPT_ISP_DISABLE_0_SCR                      0
#define FUSE_OPT_ISP_DISABLE_0_WORD_COUNT                       0x1
#define FUSE_OPT_ISP_DISABLE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_ISP_DISABLE_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_OPT_ISP_DISABLE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_ISP_DISABLE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_ISP_DISABLE_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_OPT_ISP_DISABLE_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_OPT_ISP_DISABLE_0_OPT_ISP_DISABLE_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_ISP_DISABLE_0_OPT_ISP_DISABLE_FIELD                    _MK_FIELD_CONST(0x1, FUSE_OPT_ISP_DISABLE_0_OPT_ISP_DISABLE_SHIFT)
#define FUSE_OPT_ISP_DISABLE_0_OPT_ISP_DISABLE_RANGE                    0:0
#define FUSE_OPT_ISP_DISABLE_0_OPT_ISP_DISABLE_WOFFSET                  0x0
#define FUSE_OPT_ISP_DISABLE_0_OPT_ISP_DISABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_ISP_DISABLE_0_OPT_ISP_DISABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_OPT_ISP_DISABLE_0_OPT_ISP_DISABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_ISP_DISABLE_0_OPT_ISP_DISABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_ISP_DISABLE_0_OPT_ISP_DISABLE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_ISP_DISABLE_0_OPT_ISP_DISABLE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_ISP_DISABLE_CP_0
#define FUSE_OPT_ISP_DISABLE_CP_0                       _MK_ADDR_CONST(0x4dc)
#define FUSE_OPT_ISP_DISABLE_CP_0_SECURE                        0x0
#define FUSE_OPT_ISP_DISABLE_CP_0_DUAL                  0x0
#define FUSE_OPT_ISP_DISABLE_CP_0_SCR                   0
#define FUSE_OPT_ISP_DISABLE_CP_0_WORD_COUNT                    0x1
#define FUSE_OPT_ISP_DISABLE_CP_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_ISP_DISABLE_CP_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_OPT_ISP_DISABLE_CP_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_ISP_DISABLE_CP_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_ISP_DISABLE_CP_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_OPT_ISP_DISABLE_CP_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_OPT_ISP_DISABLE_CP_0_OPT_ISP_DISABLE_CP_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_ISP_DISABLE_CP_0_OPT_ISP_DISABLE_CP_FIELD                      _MK_FIELD_CONST(0x1, FUSE_OPT_ISP_DISABLE_CP_0_OPT_ISP_DISABLE_CP_SHIFT)
#define FUSE_OPT_ISP_DISABLE_CP_0_OPT_ISP_DISABLE_CP_RANGE                      0:0
#define FUSE_OPT_ISP_DISABLE_CP_0_OPT_ISP_DISABLE_CP_WOFFSET                    0x0
#define FUSE_OPT_ISP_DISABLE_CP_0_OPT_ISP_DISABLE_CP_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_ISP_DISABLE_CP_0_OPT_ISP_DISABLE_CP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_OPT_ISP_DISABLE_CP_0_OPT_ISP_DISABLE_CP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_ISP_DISABLE_CP_0_OPT_ISP_DISABLE_CP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_ISP_DISABLE_CP_0_OPT_ISP_DISABLE_CP_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_ISP_DISABLE_CP_0_OPT_ISP_DISABLE_CP_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_NVENC_DISABLE_0
#define FUSE_OPT_NVENC_DISABLE_0                        _MK_ADDR_CONST(0x4e0)
#define FUSE_OPT_NVENC_DISABLE_0_SECURE                         0x0
#define FUSE_OPT_NVENC_DISABLE_0_DUAL                   0x0
#define FUSE_OPT_NVENC_DISABLE_0_SCR                    0
#define FUSE_OPT_NVENC_DISABLE_0_WORD_COUNT                     0x1
#define FUSE_OPT_NVENC_DISABLE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVENC_DISABLE_0_RESET_MASK                     _MK_MASK_CONST(0x3)
#define FUSE_OPT_NVENC_DISABLE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVENC_DISABLE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVENC_DISABLE_0_READ_MASK                      _MK_MASK_CONST(0x3)
#define FUSE_OPT_NVENC_DISABLE_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
#define FUSE_OPT_NVENC_DISABLE_0_OPT_NVENC_DISABLE_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_OPT_NVENC_DISABLE_0_OPT_NVENC_DISABLE_FIELD                        _MK_FIELD_CONST(0x3, FUSE_OPT_NVENC_DISABLE_0_OPT_NVENC_DISABLE_SHIFT)
#define FUSE_OPT_NVENC_DISABLE_0_OPT_NVENC_DISABLE_RANGE                        1:0
#define FUSE_OPT_NVENC_DISABLE_0_OPT_NVENC_DISABLE_WOFFSET                      0x0
#define FUSE_OPT_NVENC_DISABLE_0_OPT_NVENC_DISABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVENC_DISABLE_0_OPT_NVENC_DISABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define FUSE_OPT_NVENC_DISABLE_0_OPT_NVENC_DISABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVENC_DISABLE_0_OPT_NVENC_DISABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVENC_DISABLE_0_OPT_NVENC_DISABLE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVENC_DISABLE_0_OPT_NVENC_DISABLE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_OPT_NVENC_DISABLE_CP_0
#define FUSE_OPT_NVENC_DISABLE_CP_0                     _MK_ADDR_CONST(0x4e4)
#define FUSE_OPT_NVENC_DISABLE_CP_0_SECURE                      0x0
#define FUSE_OPT_NVENC_DISABLE_CP_0_DUAL                        0x0
#define FUSE_OPT_NVENC_DISABLE_CP_0_SCR                         0
#define FUSE_OPT_NVENC_DISABLE_CP_0_WORD_COUNT                  0x1
#define FUSE_OPT_NVENC_DISABLE_CP_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVENC_DISABLE_CP_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define FUSE_OPT_NVENC_DISABLE_CP_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVENC_DISABLE_CP_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVENC_DISABLE_CP_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define FUSE_OPT_NVENC_DISABLE_CP_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
#define FUSE_OPT_NVENC_DISABLE_CP_0_OPT_NVENC_DISABLE_CP_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_OPT_NVENC_DISABLE_CP_0_OPT_NVENC_DISABLE_CP_FIELD                  _MK_FIELD_CONST(0x3, FUSE_OPT_NVENC_DISABLE_CP_0_OPT_NVENC_DISABLE_CP_SHIFT)
#define FUSE_OPT_NVENC_DISABLE_CP_0_OPT_NVENC_DISABLE_CP_RANGE                  1:0
#define FUSE_OPT_NVENC_DISABLE_CP_0_OPT_NVENC_DISABLE_CP_WOFFSET                        0x0
#define FUSE_OPT_NVENC_DISABLE_CP_0_OPT_NVENC_DISABLE_CP_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVENC_DISABLE_CP_0_OPT_NVENC_DISABLE_CP_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define FUSE_OPT_NVENC_DISABLE_CP_0_OPT_NVENC_DISABLE_CP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVENC_DISABLE_CP_0_OPT_NVENC_DISABLE_CP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVENC_DISABLE_CP_0_OPT_NVENC_DISABLE_CP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVENC_DISABLE_CP_0_OPT_NVENC_DISABLE_CP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_OPT_PVA_DISABLE_0
#define FUSE_OPT_PVA_DISABLE_0                  _MK_ADDR_CONST(0x4e8)
#define FUSE_OPT_PVA_DISABLE_0_SECURE                   0x0
#define FUSE_OPT_PVA_DISABLE_0_DUAL                     0x0
#define FUSE_OPT_PVA_DISABLE_0_SCR                      0
#define FUSE_OPT_PVA_DISABLE_0_WORD_COUNT                       0x1
#define FUSE_OPT_PVA_DISABLE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_PVA_DISABLE_0_RESET_MASK                       _MK_MASK_CONST(0x3)
#define FUSE_OPT_PVA_DISABLE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_PVA_DISABLE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PVA_DISABLE_0_READ_MASK                        _MK_MASK_CONST(0x3)
#define FUSE_OPT_PVA_DISABLE_0_WRITE_MASK                       _MK_MASK_CONST(0x3)
#define FUSE_OPT_PVA_DISABLE_0_OPT_PVA_DISABLE_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_PVA_DISABLE_0_OPT_PVA_DISABLE_FIELD                    _MK_FIELD_CONST(0x3, FUSE_OPT_PVA_DISABLE_0_OPT_PVA_DISABLE_SHIFT)
#define FUSE_OPT_PVA_DISABLE_0_OPT_PVA_DISABLE_RANGE                    1:0
#define FUSE_OPT_PVA_DISABLE_0_OPT_PVA_DISABLE_WOFFSET                  0x0
#define FUSE_OPT_PVA_DISABLE_0_OPT_PVA_DISABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PVA_DISABLE_0_OPT_PVA_DISABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define FUSE_OPT_PVA_DISABLE_0_OPT_PVA_DISABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_PVA_DISABLE_0_OPT_PVA_DISABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PVA_DISABLE_0_OPT_PVA_DISABLE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_PVA_DISABLE_0_OPT_PVA_DISABLE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_PVA_DISABLE_CP_0
#define FUSE_OPT_PVA_DISABLE_CP_0                       _MK_ADDR_CONST(0x4ec)
#define FUSE_OPT_PVA_DISABLE_CP_0_SECURE                        0x0
#define FUSE_OPT_PVA_DISABLE_CP_0_DUAL                  0x0
#define FUSE_OPT_PVA_DISABLE_CP_0_SCR                   0
#define FUSE_OPT_PVA_DISABLE_CP_0_WORD_COUNT                    0x1
#define FUSE_OPT_PVA_DISABLE_CP_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_PVA_DISABLE_CP_0_RESET_MASK                    _MK_MASK_CONST(0x3)
#define FUSE_OPT_PVA_DISABLE_CP_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_PVA_DISABLE_CP_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_PVA_DISABLE_CP_0_READ_MASK                     _MK_MASK_CONST(0x3)
#define FUSE_OPT_PVA_DISABLE_CP_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
#define FUSE_OPT_PVA_DISABLE_CP_0_OPT_PVA_DISABLE_CP_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_PVA_DISABLE_CP_0_OPT_PVA_DISABLE_CP_FIELD                      _MK_FIELD_CONST(0x3, FUSE_OPT_PVA_DISABLE_CP_0_OPT_PVA_DISABLE_CP_SHIFT)
#define FUSE_OPT_PVA_DISABLE_CP_0_OPT_PVA_DISABLE_CP_RANGE                      1:0
#define FUSE_OPT_PVA_DISABLE_CP_0_OPT_PVA_DISABLE_CP_WOFFSET                    0x0
#define FUSE_OPT_PVA_DISABLE_CP_0_OPT_PVA_DISABLE_CP_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_PVA_DISABLE_CP_0_OPT_PVA_DISABLE_CP_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define FUSE_OPT_PVA_DISABLE_CP_0_OPT_PVA_DISABLE_CP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_PVA_DISABLE_CP_0_OPT_PVA_DISABLE_CP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_PVA_DISABLE_CP_0_OPT_PVA_DISABLE_CP_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PVA_DISABLE_CP_0_OPT_PVA_DISABLE_CP_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_DLA_DISABLE_0
#define FUSE_OPT_DLA_DISABLE_0                  _MK_ADDR_CONST(0x4f0)
#define FUSE_OPT_DLA_DISABLE_0_SECURE                   0x0
#define FUSE_OPT_DLA_DISABLE_0_DUAL                     0x0
#define FUSE_OPT_DLA_DISABLE_0_SCR                      0
#define FUSE_OPT_DLA_DISABLE_0_WORD_COUNT                       0x1
#define FUSE_OPT_DLA_DISABLE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_DLA_DISABLE_0_RESET_MASK                       _MK_MASK_CONST(0x3)
#define FUSE_OPT_DLA_DISABLE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_DLA_DISABLE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_DLA_DISABLE_0_READ_MASK                        _MK_MASK_CONST(0x3)
#define FUSE_OPT_DLA_DISABLE_0_WRITE_MASK                       _MK_MASK_CONST(0x3)
#define FUSE_OPT_DLA_DISABLE_0_OPT_DLA_DISABLE_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_DLA_DISABLE_0_OPT_DLA_DISABLE_FIELD                    _MK_FIELD_CONST(0x3, FUSE_OPT_DLA_DISABLE_0_OPT_DLA_DISABLE_SHIFT)
#define FUSE_OPT_DLA_DISABLE_0_OPT_DLA_DISABLE_RANGE                    1:0
#define FUSE_OPT_DLA_DISABLE_0_OPT_DLA_DISABLE_WOFFSET                  0x0
#define FUSE_OPT_DLA_DISABLE_0_OPT_DLA_DISABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_DLA_DISABLE_0_OPT_DLA_DISABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define FUSE_OPT_DLA_DISABLE_0_OPT_DLA_DISABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_DLA_DISABLE_0_OPT_DLA_DISABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_DLA_DISABLE_0_OPT_DLA_DISABLE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_DLA_DISABLE_0_OPT_DLA_DISABLE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_DLA_DISABLE_CP_0
#define FUSE_OPT_DLA_DISABLE_CP_0                       _MK_ADDR_CONST(0x4f4)
#define FUSE_OPT_DLA_DISABLE_CP_0_SECURE                        0x0
#define FUSE_OPT_DLA_DISABLE_CP_0_DUAL                  0x0
#define FUSE_OPT_DLA_DISABLE_CP_0_SCR                   0
#define FUSE_OPT_DLA_DISABLE_CP_0_WORD_COUNT                    0x1
#define FUSE_OPT_DLA_DISABLE_CP_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_DLA_DISABLE_CP_0_RESET_MASK                    _MK_MASK_CONST(0x3)
#define FUSE_OPT_DLA_DISABLE_CP_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_DLA_DISABLE_CP_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_DLA_DISABLE_CP_0_READ_MASK                     _MK_MASK_CONST(0x3)
#define FUSE_OPT_DLA_DISABLE_CP_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
#define FUSE_OPT_DLA_DISABLE_CP_0_OPT_DLA_DISABLE_CP_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_DLA_DISABLE_CP_0_OPT_DLA_DISABLE_CP_FIELD                      _MK_FIELD_CONST(0x3, FUSE_OPT_DLA_DISABLE_CP_0_OPT_DLA_DISABLE_CP_SHIFT)
#define FUSE_OPT_DLA_DISABLE_CP_0_OPT_DLA_DISABLE_CP_RANGE                      1:0
#define FUSE_OPT_DLA_DISABLE_CP_0_OPT_DLA_DISABLE_CP_WOFFSET                    0x0
#define FUSE_OPT_DLA_DISABLE_CP_0_OPT_DLA_DISABLE_CP_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_DLA_DISABLE_CP_0_OPT_DLA_DISABLE_CP_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define FUSE_OPT_DLA_DISABLE_CP_0_OPT_DLA_DISABLE_CP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_DLA_DISABLE_CP_0_OPT_DLA_DISABLE_CP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_DLA_DISABLE_CP_0_OPT_DLA_DISABLE_CP_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_DLA_DISABLE_CP_0_OPT_DLA_DISABLE_CP_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_CV_DISABLE_0
#define FUSE_OPT_CV_DISABLE_0                   _MK_ADDR_CONST(0x4f8)
#define FUSE_OPT_CV_DISABLE_0_SECURE                    0x0
#define FUSE_OPT_CV_DISABLE_0_DUAL                      0x0
#define FUSE_OPT_CV_DISABLE_0_SCR                       0
#define FUSE_OPT_CV_DISABLE_0_WORD_COUNT                        0x1
#define FUSE_OPT_CV_DISABLE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_CV_DISABLE_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_OPT_CV_DISABLE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_CV_DISABLE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_CV_DISABLE_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define FUSE_OPT_CV_DISABLE_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_OPT_CV_DISABLE_0_OPT_CV_DISABLE_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_CV_DISABLE_0_OPT_CV_DISABLE_FIELD                      _MK_FIELD_CONST(0x1, FUSE_OPT_CV_DISABLE_0_OPT_CV_DISABLE_SHIFT)
#define FUSE_OPT_CV_DISABLE_0_OPT_CV_DISABLE_RANGE                      0:0
#define FUSE_OPT_CV_DISABLE_0_OPT_CV_DISABLE_WOFFSET                    0x0
#define FUSE_OPT_CV_DISABLE_0_OPT_CV_DISABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_CV_DISABLE_0_OPT_CV_DISABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_OPT_CV_DISABLE_0_OPT_CV_DISABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_CV_DISABLE_0_OPT_CV_DISABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_CV_DISABLE_0_OPT_CV_DISABLE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_CV_DISABLE_0_OPT_CV_DISABLE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_CV_DISABLE_CP_0
#define FUSE_OPT_CV_DISABLE_CP_0                        _MK_ADDR_CONST(0x4fc)
#define FUSE_OPT_CV_DISABLE_CP_0_SECURE                         0x0
#define FUSE_OPT_CV_DISABLE_CP_0_DUAL                   0x0
#define FUSE_OPT_CV_DISABLE_CP_0_SCR                    0
#define FUSE_OPT_CV_DISABLE_CP_0_WORD_COUNT                     0x1
#define FUSE_OPT_CV_DISABLE_CP_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_CV_DISABLE_CP_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_OPT_CV_DISABLE_CP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_CV_DISABLE_CP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_CV_DISABLE_CP_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_OPT_CV_DISABLE_CP_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_OPT_CV_DISABLE_CP_0_OPT_CV_DISABLE_CP_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_OPT_CV_DISABLE_CP_0_OPT_CV_DISABLE_CP_FIELD                        _MK_FIELD_CONST(0x1, FUSE_OPT_CV_DISABLE_CP_0_OPT_CV_DISABLE_CP_SHIFT)
#define FUSE_OPT_CV_DISABLE_CP_0_OPT_CV_DISABLE_CP_RANGE                        0:0
#define FUSE_OPT_CV_DISABLE_CP_0_OPT_CV_DISABLE_CP_WOFFSET                      0x0
#define FUSE_OPT_CV_DISABLE_CP_0_OPT_CV_DISABLE_CP_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_CV_DISABLE_CP_0_OPT_CV_DISABLE_CP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define FUSE_OPT_CV_DISABLE_CP_0_OPT_CV_DISABLE_CP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_CV_DISABLE_CP_0_OPT_CV_DISABLE_CP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_CV_DISABLE_CP_0_OPT_CV_DISABLE_CP_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_CV_DISABLE_CP_0_OPT_CV_DISABLE_CP_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_PDK2_0_0
#define FUSE_PDK2_0_0                   _MK_ADDR_CONST(0x500)
#define FUSE_PDK2_0_0_SECURE                    0x0
#define FUSE_PDK2_0_0_DUAL                      0x0
#define FUSE_PDK2_0_0_SCR                       0
#define FUSE_PDK2_0_0_WORD_COUNT                        0x1
#define FUSE_PDK2_0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_PDK2_0_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK2_0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_PDK2_0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_PDK2_0_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK2_0_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK2_0_0_PDK2_0_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_PDK2_0_0_PDK2_0_FIELD                      _MK_FIELD_CONST(0xffffffff, FUSE_PDK2_0_0_PDK2_0_SHIFT)
#define FUSE_PDK2_0_0_PDK2_0_RANGE                      31:0
#define FUSE_PDK2_0_0_PDK2_0_WOFFSET                    0x0
#define FUSE_PDK2_0_0_PDK2_0_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_PDK2_0_0_PDK2_0_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK2_0_0_PDK2_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_PDK2_0_0_PDK2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_PDK2_0_0_PDK2_0_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_PDK2_0_0_PDK2_0_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_PDK2_1_0
#define FUSE_PDK2_1_0                   _MK_ADDR_CONST(0x504)
#define FUSE_PDK2_1_0_SECURE                    0x0
#define FUSE_PDK2_1_0_DUAL                      0x0
#define FUSE_PDK2_1_0_SCR                       0
#define FUSE_PDK2_1_0_WORD_COUNT                        0x1
#define FUSE_PDK2_1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_PDK2_1_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK2_1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_PDK2_1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_PDK2_1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK2_1_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK2_1_0_PDK2_1_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_PDK2_1_0_PDK2_1_FIELD                      _MK_FIELD_CONST(0xffffffff, FUSE_PDK2_1_0_PDK2_1_SHIFT)
#define FUSE_PDK2_1_0_PDK2_1_RANGE                      31:0
#define FUSE_PDK2_1_0_PDK2_1_WOFFSET                    0x0
#define FUSE_PDK2_1_0_PDK2_1_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_PDK2_1_0_PDK2_1_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK2_1_0_PDK2_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_PDK2_1_0_PDK2_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_PDK2_1_0_PDK2_1_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_PDK2_1_0_PDK2_1_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_PDK2_2_0
#define FUSE_PDK2_2_0                   _MK_ADDR_CONST(0x508)
#define FUSE_PDK2_2_0_SECURE                    0x0
#define FUSE_PDK2_2_0_DUAL                      0x0
#define FUSE_PDK2_2_0_SCR                       0
#define FUSE_PDK2_2_0_WORD_COUNT                        0x1
#define FUSE_PDK2_2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_PDK2_2_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK2_2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_PDK2_2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_PDK2_2_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK2_2_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK2_2_0_PDK2_2_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_PDK2_2_0_PDK2_2_FIELD                      _MK_FIELD_CONST(0xffffffff, FUSE_PDK2_2_0_PDK2_2_SHIFT)
#define FUSE_PDK2_2_0_PDK2_2_RANGE                      31:0
#define FUSE_PDK2_2_0_PDK2_2_WOFFSET                    0x0
#define FUSE_PDK2_2_0_PDK2_2_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_PDK2_2_0_PDK2_2_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK2_2_0_PDK2_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_PDK2_2_0_PDK2_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_PDK2_2_0_PDK2_2_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_PDK2_2_0_PDK2_2_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_PDK2_3_0
#define FUSE_PDK2_3_0                   _MK_ADDR_CONST(0x50c)
#define FUSE_PDK2_3_0_SECURE                    0x0
#define FUSE_PDK2_3_0_DUAL                      0x0
#define FUSE_PDK2_3_0_SCR                       0
#define FUSE_PDK2_3_0_WORD_COUNT                        0x1
#define FUSE_PDK2_3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_PDK2_3_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK2_3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_PDK2_3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_PDK2_3_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK2_3_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK2_3_0_PDK2_3_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_PDK2_3_0_PDK2_3_FIELD                      _MK_FIELD_CONST(0xffffffff, FUSE_PDK2_3_0_PDK2_3_SHIFT)
#define FUSE_PDK2_3_0_PDK2_3_RANGE                      31:0
#define FUSE_PDK2_3_0_PDK2_3_WOFFSET                    0x0
#define FUSE_PDK2_3_0_PDK2_3_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_PDK2_3_0_PDK2_3_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_PDK2_3_0_PDK2_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_PDK2_3_0_PDK2_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_PDK2_3_0_PDK2_3_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_PDK2_3_0_PDK2_3_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_PRIV_SFK2_0_0
#define FUSE_OPT_PRIV_SFK2_0_0                  _MK_ADDR_CONST(0x510)
#define FUSE_OPT_PRIV_SFK2_0_0_SECURE                   0x0
#define FUSE_OPT_PRIV_SFK2_0_0_DUAL                     0x0
#define FUSE_OPT_PRIV_SFK2_0_0_SCR                      0
#define FUSE_OPT_PRIV_SFK2_0_0_WORD_COUNT                       0x1
#define FUSE_OPT_PRIV_SFK2_0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK2_0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK2_0_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK2_0_0_OPT_PRIV_SFK2_0_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_PRIV_SFK2_0_0_OPT_PRIV_SFK2_0_FIELD                    _MK_FIELD_CONST(0xffffffff, FUSE_OPT_PRIV_SFK2_0_0_OPT_PRIV_SFK2_0_SHIFT)
#define FUSE_OPT_PRIV_SFK2_0_0_OPT_PRIV_SFK2_0_RANGE                    31:0
#define FUSE_OPT_PRIV_SFK2_0_0_OPT_PRIV_SFK2_0_WOFFSET                  0x0
#define FUSE_OPT_PRIV_SFK2_0_0_OPT_PRIV_SFK2_0_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_0_0_OPT_PRIV_SFK2_0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK2_0_0_OPT_PRIV_SFK2_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_0_0_OPT_PRIV_SFK2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_0_0_OPT_PRIV_SFK2_0_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_0_0_OPT_PRIV_SFK2_0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_PRIV_SFK2_1_0
#define FUSE_OPT_PRIV_SFK2_1_0                  _MK_ADDR_CONST(0x514)
#define FUSE_OPT_PRIV_SFK2_1_0_SECURE                   0x0
#define FUSE_OPT_PRIV_SFK2_1_0_DUAL                     0x0
#define FUSE_OPT_PRIV_SFK2_1_0_SCR                      0
#define FUSE_OPT_PRIV_SFK2_1_0_WORD_COUNT                       0x1
#define FUSE_OPT_PRIV_SFK2_1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_1_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK2_1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_1_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK2_1_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK2_1_0_OPT_PRIV_SFK2_1_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_PRIV_SFK2_1_0_OPT_PRIV_SFK2_1_FIELD                    _MK_FIELD_CONST(0xffffffff, FUSE_OPT_PRIV_SFK2_1_0_OPT_PRIV_SFK2_1_SHIFT)
#define FUSE_OPT_PRIV_SFK2_1_0_OPT_PRIV_SFK2_1_RANGE                    31:0
#define FUSE_OPT_PRIV_SFK2_1_0_OPT_PRIV_SFK2_1_WOFFSET                  0x0
#define FUSE_OPT_PRIV_SFK2_1_0_OPT_PRIV_SFK2_1_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_1_0_OPT_PRIV_SFK2_1_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK2_1_0_OPT_PRIV_SFK2_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_1_0_OPT_PRIV_SFK2_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_1_0_OPT_PRIV_SFK2_1_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_1_0_OPT_PRIV_SFK2_1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_PRIV_SFK2_2_0
#define FUSE_OPT_PRIV_SFK2_2_0                  _MK_ADDR_CONST(0x518)
#define FUSE_OPT_PRIV_SFK2_2_0_SECURE                   0x0
#define FUSE_OPT_PRIV_SFK2_2_0_DUAL                     0x0
#define FUSE_OPT_PRIV_SFK2_2_0_SCR                      0
#define FUSE_OPT_PRIV_SFK2_2_0_WORD_COUNT                       0x1
#define FUSE_OPT_PRIV_SFK2_2_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_2_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK2_2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_2_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK2_2_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK2_2_0_OPT_PRIV_SFK2_2_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_PRIV_SFK2_2_0_OPT_PRIV_SFK2_2_FIELD                    _MK_FIELD_CONST(0xffffffff, FUSE_OPT_PRIV_SFK2_2_0_OPT_PRIV_SFK2_2_SHIFT)
#define FUSE_OPT_PRIV_SFK2_2_0_OPT_PRIV_SFK2_2_RANGE                    31:0
#define FUSE_OPT_PRIV_SFK2_2_0_OPT_PRIV_SFK2_2_WOFFSET                  0x0
#define FUSE_OPT_PRIV_SFK2_2_0_OPT_PRIV_SFK2_2_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_2_0_OPT_PRIV_SFK2_2_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK2_2_0_OPT_PRIV_SFK2_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_2_0_OPT_PRIV_SFK2_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_2_0_OPT_PRIV_SFK2_2_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_2_0_OPT_PRIV_SFK2_2_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_PRIV_SFK2_3_0
#define FUSE_OPT_PRIV_SFK2_3_0                  _MK_ADDR_CONST(0x51c)
#define FUSE_OPT_PRIV_SFK2_3_0_SECURE                   0x0
#define FUSE_OPT_PRIV_SFK2_3_0_DUAL                     0x0
#define FUSE_OPT_PRIV_SFK2_3_0_SCR                      0
#define FUSE_OPT_PRIV_SFK2_3_0_WORD_COUNT                       0x1
#define FUSE_OPT_PRIV_SFK2_3_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_3_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK2_3_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_3_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_3_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK2_3_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK2_3_0_OPT_PRIV_SFK2_3_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_PRIV_SFK2_3_0_OPT_PRIV_SFK2_3_FIELD                    _MK_FIELD_CONST(0xffffffff, FUSE_OPT_PRIV_SFK2_3_0_OPT_PRIV_SFK2_3_SHIFT)
#define FUSE_OPT_PRIV_SFK2_3_0_OPT_PRIV_SFK2_3_RANGE                    31:0
#define FUSE_OPT_PRIV_SFK2_3_0_OPT_PRIV_SFK2_3_WOFFSET                  0x0
#define FUSE_OPT_PRIV_SFK2_3_0_OPT_PRIV_SFK2_3_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_3_0_OPT_PRIV_SFK2_3_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_OPT_PRIV_SFK2_3_0_OPT_PRIV_SFK2_3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_3_0_OPT_PRIV_SFK2_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_3_0_OPT_PRIV_SFK2_3_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_PRIV_SFK2_3_0_OPT_PRIV_SFK2_3_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_RESERVED_ODM8_0
#define FUSE_RESERVED_ODM8_0                    _MK_ADDR_CONST(0x520)
#define FUSE_RESERVED_ODM8_0_SECURE                     0x0
#define FUSE_RESERVED_ODM8_0_DUAL                       0x0
#define FUSE_RESERVED_ODM8_0_SCR                        0
#define FUSE_RESERVED_ODM8_0_WORD_COUNT                         0x1
#define FUSE_RESERVED_ODM8_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM8_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM8_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM8_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM8_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM8_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM8_0_RESERVED_ODM8_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_RESERVED_ODM8_0_RESERVED_ODM8_FIELD                        _MK_FIELD_CONST(0xffffffff, FUSE_RESERVED_ODM8_0_RESERVED_ODM8_SHIFT)
#define FUSE_RESERVED_ODM8_0_RESERVED_ODM8_RANGE                        31:0
#define FUSE_RESERVED_ODM8_0_RESERVED_ODM8_WOFFSET                      0x0
#define FUSE_RESERVED_ODM8_0_RESERVED_ODM8_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM8_0_RESERVED_ODM8_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM8_0_RESERVED_ODM8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM8_0_RESERVED_ODM8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM8_0_RESERVED_ODM8_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM8_0_RESERVED_ODM8_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_RESERVED_ODM9_0
#define FUSE_RESERVED_ODM9_0                    _MK_ADDR_CONST(0x524)
#define FUSE_RESERVED_ODM9_0_SECURE                     0x0
#define FUSE_RESERVED_ODM9_0_DUAL                       0x0
#define FUSE_RESERVED_ODM9_0_SCR                        0
#define FUSE_RESERVED_ODM9_0_WORD_COUNT                         0x1
#define FUSE_RESERVED_ODM9_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM9_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM9_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM9_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM9_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM9_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM9_0_RESERVED_ODM9_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_RESERVED_ODM9_0_RESERVED_ODM9_FIELD                        _MK_FIELD_CONST(0xffffffff, FUSE_RESERVED_ODM9_0_RESERVED_ODM9_SHIFT)
#define FUSE_RESERVED_ODM9_0_RESERVED_ODM9_RANGE                        31:0
#define FUSE_RESERVED_ODM9_0_RESERVED_ODM9_WOFFSET                      0x0
#define FUSE_RESERVED_ODM9_0_RESERVED_ODM9_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM9_0_RESERVED_ODM9_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM9_0_RESERVED_ODM9_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM9_0_RESERVED_ODM9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM9_0_RESERVED_ODM9_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM9_0_RESERVED_ODM9_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_RESERVED_ODM10_0
#define FUSE_RESERVED_ODM10_0                   _MK_ADDR_CONST(0x528)
#define FUSE_RESERVED_ODM10_0_SECURE                    0x0
#define FUSE_RESERVED_ODM10_0_DUAL                      0x0
#define FUSE_RESERVED_ODM10_0_SCR                       0
#define FUSE_RESERVED_ODM10_0_WORD_COUNT                        0x1
#define FUSE_RESERVED_ODM10_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM10_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM10_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM10_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM10_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM10_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM10_0_RESERVED_ODM10_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_RESERVED_ODM10_0_RESERVED_ODM10_FIELD                      _MK_FIELD_CONST(0xffffffff, FUSE_RESERVED_ODM10_0_RESERVED_ODM10_SHIFT)
#define FUSE_RESERVED_ODM10_0_RESERVED_ODM10_RANGE                      31:0
#define FUSE_RESERVED_ODM10_0_RESERVED_ODM10_WOFFSET                    0x0
#define FUSE_RESERVED_ODM10_0_RESERVED_ODM10_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM10_0_RESERVED_ODM10_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM10_0_RESERVED_ODM10_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM10_0_RESERVED_ODM10_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM10_0_RESERVED_ODM10_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM10_0_RESERVED_ODM10_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_RESERVED_ODM11_0
#define FUSE_RESERVED_ODM11_0                   _MK_ADDR_CONST(0x52c)
#define FUSE_RESERVED_ODM11_0_SECURE                    0x0
#define FUSE_RESERVED_ODM11_0_DUAL                      0x0
#define FUSE_RESERVED_ODM11_0_SCR                       0
#define FUSE_RESERVED_ODM11_0_WORD_COUNT                        0x1
#define FUSE_RESERVED_ODM11_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM11_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM11_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM11_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM11_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM11_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM11_0_RESERVED_ODM11_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_RESERVED_ODM11_0_RESERVED_ODM11_FIELD                      _MK_FIELD_CONST(0xffffffff, FUSE_RESERVED_ODM11_0_RESERVED_ODM11_SHIFT)
#define FUSE_RESERVED_ODM11_0_RESERVED_ODM11_RANGE                      31:0
#define FUSE_RESERVED_ODM11_0_RESERVED_ODM11_WOFFSET                    0x0
#define FUSE_RESERVED_ODM11_0_RESERVED_ODM11_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM11_0_RESERVED_ODM11_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_ODM11_0_RESERVED_ODM11_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM11_0_RESERVED_ODM11_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM11_0_RESERVED_ODM11_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_ODM11_0_RESERVED_ODM11_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_0
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_0                     _MK_ADDR_CONST(0x530)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_0_SECURE                      0x0
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_0_DUAL                        0x0
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_0_SCR                         0
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_0_WORD_COUNT                  0x1
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_FIELD                  _MK_FIELD_CONST(0xffffffff, FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_SHIFT)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_RANGE                  31:0
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_WOFFSET                        0x0
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_0
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_0                     _MK_ADDR_CONST(0x534)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_0_SECURE                      0x0
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_0_DUAL                        0x0
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_0_SCR                         0
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_0_WORD_COUNT                  0x1
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_FIELD                  _MK_FIELD_CONST(0xffffffff, FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_SHIFT)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_RANGE                  31:0
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_WOFFSET                        0x0
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_0_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_LOCK_PROD_RESTRICTED_FLAG_0
#define FUSE_LOCK_PROD_RESTRICTED_FLAG_0                        _MK_ADDR_CONST(0x538)
#define FUSE_LOCK_PROD_RESTRICTED_FLAG_0_SECURE                         0x0
#define FUSE_LOCK_PROD_RESTRICTED_FLAG_0_DUAL                   0x0
#define FUSE_LOCK_PROD_RESTRICTED_FLAG_0_SCR                    0
#define FUSE_LOCK_PROD_RESTRICTED_FLAG_0_WORD_COUNT                     0x1
#define FUSE_LOCK_PROD_RESTRICTED_FLAG_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_LOCK_PROD_RESTRICTED_FLAG_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_LOCK_PROD_RESTRICTED_FLAG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_LOCK_PROD_RESTRICTED_FLAG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_LOCK_PROD_RESTRICTED_FLAG_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_LOCK_PROD_RESTRICTED_FLAG_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_LOCK_PROD_RESTRICTED_FLAG_0_LOCK_PROD_RESTRICTED_FLAG_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_LOCK_PROD_RESTRICTED_FLAG_0_LOCK_PROD_RESTRICTED_FLAG_FIELD                        _MK_FIELD_CONST(0x1, FUSE_LOCK_PROD_RESTRICTED_FLAG_0_LOCK_PROD_RESTRICTED_FLAG_SHIFT)
#define FUSE_LOCK_PROD_RESTRICTED_FLAG_0_LOCK_PROD_RESTRICTED_FLAG_RANGE                        0:0
#define FUSE_LOCK_PROD_RESTRICTED_FLAG_0_LOCK_PROD_RESTRICTED_FLAG_WOFFSET                      0x0
#define FUSE_LOCK_PROD_RESTRICTED_FLAG_0_LOCK_PROD_RESTRICTED_FLAG_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_LOCK_PROD_RESTRICTED_FLAG_0_LOCK_PROD_RESTRICTED_FLAG_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define FUSE_LOCK_PROD_RESTRICTED_FLAG_0_LOCK_PROD_RESTRICTED_FLAG_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_LOCK_PROD_RESTRICTED_FLAG_0_LOCK_PROD_RESTRICTED_FLAG_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_LOCK_PROD_RESTRICTED_FLAG_0_LOCK_PROD_RESTRICTED_FLAG_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_LOCK_PROD_RESTRICTED_FLAG_0_LOCK_PROD_RESTRICTED_FLAG_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_LOCK_PROD_DISALLOWED_FLAG_0
#define FUSE_LOCK_PROD_DISALLOWED_FLAG_0                        _MK_ADDR_CONST(0x53c)
#define FUSE_LOCK_PROD_DISALLOWED_FLAG_0_SECURE                         0x0
#define FUSE_LOCK_PROD_DISALLOWED_FLAG_0_DUAL                   0x0
#define FUSE_LOCK_PROD_DISALLOWED_FLAG_0_SCR                    0
#define FUSE_LOCK_PROD_DISALLOWED_FLAG_0_WORD_COUNT                     0x1
#define FUSE_LOCK_PROD_DISALLOWED_FLAG_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_LOCK_PROD_DISALLOWED_FLAG_0_RESET_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_LOCK_PROD_DISALLOWED_FLAG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_LOCK_PROD_DISALLOWED_FLAG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_LOCK_PROD_DISALLOWED_FLAG_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_LOCK_PROD_DISALLOWED_FLAG_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_LOCK_PROD_DISALLOWED_FLAG_0_LOCK_PROD_DISALLOWED_FLAG_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_LOCK_PROD_DISALLOWED_FLAG_0_LOCK_PROD_DISALLOWED_FLAG_FIELD                        _MK_FIELD_CONST(0x1, FUSE_LOCK_PROD_DISALLOWED_FLAG_0_LOCK_PROD_DISALLOWED_FLAG_SHIFT)
#define FUSE_LOCK_PROD_DISALLOWED_FLAG_0_LOCK_PROD_DISALLOWED_FLAG_RANGE                        0:0
#define FUSE_LOCK_PROD_DISALLOWED_FLAG_0_LOCK_PROD_DISALLOWED_FLAG_WOFFSET                      0x0
#define FUSE_LOCK_PROD_DISALLOWED_FLAG_0_LOCK_PROD_DISALLOWED_FLAG_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_LOCK_PROD_DISALLOWED_FLAG_0_LOCK_PROD_DISALLOWED_FLAG_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define FUSE_LOCK_PROD_DISALLOWED_FLAG_0_LOCK_PROD_DISALLOWED_FLAG_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_LOCK_PROD_DISALLOWED_FLAG_0_LOCK_PROD_DISALLOWED_FLAG_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_LOCK_PROD_DISALLOWED_FLAG_0_LOCK_PROD_DISALLOWED_FLAG_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_LOCK_PROD_DISALLOWED_FLAG_0_LOCK_PROD_DISALLOWED_FLAG_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_FUSE_INTEGRITY_CHECK_ENABLE_0
#define FUSE_FUSE_INTEGRITY_CHECK_ENABLE_0                      _MK_ADDR_CONST(0x540)
#define FUSE_FUSE_INTEGRITY_CHECK_ENABLE_0_SECURE                       0x0
#define FUSE_FUSE_INTEGRITY_CHECK_ENABLE_0_DUAL                         0x0
#define FUSE_FUSE_INTEGRITY_CHECK_ENABLE_0_SCR                  0
#define FUSE_FUSE_INTEGRITY_CHECK_ENABLE_0_WORD_COUNT                   0x1
#define FUSE_FUSE_INTEGRITY_CHECK_ENABLE_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_FUSE_INTEGRITY_CHECK_ENABLE_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_FUSE_INTEGRITY_CHECK_ENABLE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_FUSE_INTEGRITY_CHECK_ENABLE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_FUSE_INTEGRITY_CHECK_ENABLE_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_FUSE_INTEGRITY_CHECK_ENABLE_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_FUSE_INTEGRITY_CHECK_ENABLE_0_FUSE_INTEGRITY_CHECK_ENABLE_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_FUSE_INTEGRITY_CHECK_ENABLE_0_FUSE_INTEGRITY_CHECK_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, FUSE_FUSE_INTEGRITY_CHECK_ENABLE_0_FUSE_INTEGRITY_CHECK_ENABLE_SHIFT)
#define FUSE_FUSE_INTEGRITY_CHECK_ENABLE_0_FUSE_INTEGRITY_CHECK_ENABLE_RANGE                    0:0
#define FUSE_FUSE_INTEGRITY_CHECK_ENABLE_0_FUSE_INTEGRITY_CHECK_ENABLE_WOFFSET                  0x0
#define FUSE_FUSE_INTEGRITY_CHECK_ENABLE_0_FUSE_INTEGRITY_CHECK_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_FUSE_INTEGRITY_CHECK_ENABLE_0_FUSE_INTEGRITY_CHECK_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_FUSE_INTEGRITY_CHECK_ENABLE_0_FUSE_INTEGRITY_CHECK_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_FUSE_INTEGRITY_CHECK_ENABLE_0_FUSE_INTEGRITY_CHECK_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_FUSE_INTEGRITY_CHECK_ENABLE_0_FUSE_INTEGRITY_CHECK_ENABLE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_FUSE_INTEGRITY_CHECK_ENABLE_0_FUSE_INTEGRITY_CHECK_ENABLE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_TSENSOR11_CALIB_0
#define FUSE_TSENSOR11_CALIB_0                  _MK_ADDR_CONST(0x544)
#define FUSE_TSENSOR11_CALIB_0_SECURE                   0x0
#define FUSE_TSENSOR11_CALIB_0_DUAL                     0x0
#define FUSE_TSENSOR11_CALIB_0_SCR                      0
#define FUSE_TSENSOR11_CALIB_0_WORD_COUNT                       0x1
#define FUSE_TSENSOR11_CALIB_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR11_CALIB_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR11_CALIB_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR11_CALIB_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR11_CALIB_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR11_CALIB_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR11_CALIB_0_TSENSOR11_CALIB_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_TSENSOR11_CALIB_0_TSENSOR11_CALIB_FIELD                    _MK_FIELD_CONST(0xffffffff, FUSE_TSENSOR11_CALIB_0_TSENSOR11_CALIB_SHIFT)
#define FUSE_TSENSOR11_CALIB_0_TSENSOR11_CALIB_RANGE                    31:0
#define FUSE_TSENSOR11_CALIB_0_TSENSOR11_CALIB_WOFFSET                  0x0
#define FUSE_TSENSOR11_CALIB_0_TSENSOR11_CALIB_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR11_CALIB_0_TSENSOR11_CALIB_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR11_CALIB_0_TSENSOR11_CALIB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR11_CALIB_0_TSENSOR11_CALIB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR11_CALIB_0_TSENSOR11_CALIB_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR11_CALIB_0_TSENSOR11_CALIB_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_TSENSOR12_CALIB_0
#define FUSE_TSENSOR12_CALIB_0                  _MK_ADDR_CONST(0x548)
#define FUSE_TSENSOR12_CALIB_0_SECURE                   0x0
#define FUSE_TSENSOR12_CALIB_0_DUAL                     0x0
#define FUSE_TSENSOR12_CALIB_0_SCR                      0
#define FUSE_TSENSOR12_CALIB_0_WORD_COUNT                       0x1
#define FUSE_TSENSOR12_CALIB_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR12_CALIB_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR12_CALIB_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR12_CALIB_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR12_CALIB_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR12_CALIB_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR12_CALIB_0_TSENSOR12_CALIB_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_TSENSOR12_CALIB_0_TSENSOR12_CALIB_FIELD                    _MK_FIELD_CONST(0xffffffff, FUSE_TSENSOR12_CALIB_0_TSENSOR12_CALIB_SHIFT)
#define FUSE_TSENSOR12_CALIB_0_TSENSOR12_CALIB_RANGE                    31:0
#define FUSE_TSENSOR12_CALIB_0_TSENSOR12_CALIB_WOFFSET                  0x0
#define FUSE_TSENSOR12_CALIB_0_TSENSOR12_CALIB_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR12_CALIB_0_TSENSOR12_CALIB_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR12_CALIB_0_TSENSOR12_CALIB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR12_CALIB_0_TSENSOR12_CALIB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR12_CALIB_0_TSENSOR12_CALIB_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR12_CALIB_0_TSENSOR12_CALIB_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Reserved address 0x54c

// Reserved address 0x550

// Reserved address 0x554

// Reserved address 0x558

// Register FUSE_TSENSOR17_CALIB_0
#define FUSE_TSENSOR17_CALIB_0                  _MK_ADDR_CONST(0x55c)
#define FUSE_TSENSOR17_CALIB_0_SECURE                   0x0
#define FUSE_TSENSOR17_CALIB_0_DUAL                     0x0
#define FUSE_TSENSOR17_CALIB_0_SCR                      0
#define FUSE_TSENSOR17_CALIB_0_WORD_COUNT                       0x1
#define FUSE_TSENSOR17_CALIB_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR17_CALIB_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR17_CALIB_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR17_CALIB_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR17_CALIB_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR17_CALIB_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR17_CALIB_0_TSENSOR17_CALIB_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_TSENSOR17_CALIB_0_TSENSOR17_CALIB_FIELD                    _MK_FIELD_CONST(0xffffffff, FUSE_TSENSOR17_CALIB_0_TSENSOR17_CALIB_SHIFT)
#define FUSE_TSENSOR17_CALIB_0_TSENSOR17_CALIB_RANGE                    31:0
#define FUSE_TSENSOR17_CALIB_0_TSENSOR17_CALIB_WOFFSET                  0x0
#define FUSE_TSENSOR17_CALIB_0_TSENSOR17_CALIB_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR17_CALIB_0_TSENSOR17_CALIB_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_TSENSOR17_CALIB_0_TSENSOR17_CALIB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR17_CALIB_0_TSENSOR17_CALIB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR17_CALIB_0_TSENSOR17_CALIB_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_TSENSOR17_CALIB_0_TSENSOR17_CALIB_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_FLW0_0
#define FUSE_FLW0_0                     _MK_ADDR_CONST(0x560)
#define FUSE_FLW0_0_SECURE                      0x0
#define FUSE_FLW0_0_DUAL                        0x0
#define FUSE_FLW0_0_SCR                         0
#define FUSE_FLW0_0_WORD_COUNT                  0x1
#define FUSE_FLW0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_FLW0_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_FLW0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_FLW0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_FLW0_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_FLW0_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_FLW0_0_FLW0_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_FLW0_0_FLW0_FIELD                  _MK_FIELD_CONST(0x1, FUSE_FLW0_0_FLW0_SHIFT)
#define FUSE_FLW0_0_FLW0_RANGE                  0:0
#define FUSE_FLW0_0_FLW0_WOFFSET                        0x0
#define FUSE_FLW0_0_FLW0_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_FLW0_0_FLW0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_FLW0_0_FLW0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_FLW0_0_FLW0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_FLW0_0_FLW0_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_FLW0_0_FLW0_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_FLW1_0
#define FUSE_FLW1_0                     _MK_ADDR_CONST(0x564)
#define FUSE_FLW1_0_SECURE                      0x0
#define FUSE_FLW1_0_DUAL                        0x0
#define FUSE_FLW1_0_SCR                         0
#define FUSE_FLW1_0_WORD_COUNT                  0x1
#define FUSE_FLW1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_FLW1_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_FLW1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_FLW1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_FLW1_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_FLW1_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_FLW1_0_FLW1_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_FLW1_0_FLW1_FIELD                  _MK_FIELD_CONST(0x1, FUSE_FLW1_0_FLW1_SHIFT)
#define FUSE_FLW1_0_FLW1_RANGE                  0:0
#define FUSE_FLW1_0_FLW1_WOFFSET                        0x0
#define FUSE_FLW1_0_FLW1_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_FLW1_0_FLW1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_FLW1_0_FLW1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_FLW1_0_FLW1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_FLW1_0_FLW1_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_FLW1_0_FLW1_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_FLW2_0
#define FUSE_FLW2_0                     _MK_ADDR_CONST(0x568)
#define FUSE_FLW2_0_SECURE                      0x0
#define FUSE_FLW2_0_DUAL                        0x0
#define FUSE_FLW2_0_SCR                         0
#define FUSE_FLW2_0_WORD_COUNT                  0x1
#define FUSE_FLW2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_FLW2_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_FLW2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_FLW2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_FLW2_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_FLW2_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_FLW2_0_FLW2_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_FLW2_0_FLW2_FIELD                  _MK_FIELD_CONST(0x1, FUSE_FLW2_0_FLW2_SHIFT)
#define FUSE_FLW2_0_FLW2_RANGE                  0:0
#define FUSE_FLW2_0_FLW2_WOFFSET                        0x0
#define FUSE_FLW2_0_FLW2_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_FLW2_0_FLW2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_FLW2_0_FLW2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_FLW2_0_FLW2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_FLW2_0_FLW2_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_FLW2_0_FLW2_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_FLW3_0
#define FUSE_FLW3_0                     _MK_ADDR_CONST(0x56c)
#define FUSE_FLW3_0_SECURE                      0x0
#define FUSE_FLW3_0_DUAL                        0x0
#define FUSE_FLW3_0_SCR                         0
#define FUSE_FLW3_0_WORD_COUNT                  0x1
#define FUSE_FLW3_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_FLW3_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_FLW3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_FLW3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_FLW3_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_FLW3_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_FLW3_0_FLW3_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_FLW3_0_FLW3_FIELD                  _MK_FIELD_CONST(0x1, FUSE_FLW3_0_FLW3_SHIFT)
#define FUSE_FLW3_0_FLW3_RANGE                  0:0
#define FUSE_FLW3_0_FLW3_WOFFSET                        0x0
#define FUSE_FLW3_0_FLW3_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_FLW3_0_FLW3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_FLW3_0_FLW3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_FLW3_0_FLW3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_FLW3_0_FLW3_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_FLW3_0_FLW3_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_BPMP_DUMMY_KEY_READ_ENABLE_0
#define FUSE_BPMP_DUMMY_KEY_READ_ENABLE_0                       _MK_ADDR_CONST(0x570)
#define FUSE_BPMP_DUMMY_KEY_READ_ENABLE_0_SECURE                        0x0
#define FUSE_BPMP_DUMMY_KEY_READ_ENABLE_0_DUAL                  0x0
#define FUSE_BPMP_DUMMY_KEY_READ_ENABLE_0_SCR                   0
#define FUSE_BPMP_DUMMY_KEY_READ_ENABLE_0_WORD_COUNT                    0x1
#define FUSE_BPMP_DUMMY_KEY_READ_ENABLE_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define FUSE_BPMP_DUMMY_KEY_READ_ENABLE_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_BPMP_DUMMY_KEY_READ_ENABLE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_BPMP_DUMMY_KEY_READ_ENABLE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_BPMP_DUMMY_KEY_READ_ENABLE_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_BPMP_DUMMY_KEY_READ_ENABLE_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_BPMP_DUMMY_KEY_READ_ENABLE_0_BPMP_DUMMY_KEY_READ_ENABLE_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_BPMP_DUMMY_KEY_READ_ENABLE_0_BPMP_DUMMY_KEY_READ_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, FUSE_BPMP_DUMMY_KEY_READ_ENABLE_0_BPMP_DUMMY_KEY_READ_ENABLE_SHIFT)
#define FUSE_BPMP_DUMMY_KEY_READ_ENABLE_0_BPMP_DUMMY_KEY_READ_ENABLE_RANGE                      0:0
#define FUSE_BPMP_DUMMY_KEY_READ_ENABLE_0_BPMP_DUMMY_KEY_READ_ENABLE_WOFFSET                    0x0
#define FUSE_BPMP_DUMMY_KEY_READ_ENABLE_0_BPMP_DUMMY_KEY_READ_ENABLE_DEFAULT                    _MK_MASK_CONST(0x1)
#define FUSE_BPMP_DUMMY_KEY_READ_ENABLE_0_BPMP_DUMMY_KEY_READ_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_BPMP_DUMMY_KEY_READ_ENABLE_0_BPMP_DUMMY_KEY_READ_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_BPMP_DUMMY_KEY_READ_ENABLE_0_BPMP_DUMMY_KEY_READ_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_BPMP_DUMMY_KEY_READ_ENABLE_0_BPMP_DUMMY_KEY_READ_ENABLE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_BPMP_DUMMY_KEY_READ_ENABLE_0_BPMP_DUMMY_KEY_READ_ENABLE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_VREFRO_CALIB_0
#define FUSE_VREFRO_CALIB_0                     _MK_ADDR_CONST(0x574)
#define FUSE_VREFRO_CALIB_0_SECURE                      0x0
#define FUSE_VREFRO_CALIB_0_DUAL                        0x0
#define FUSE_VREFRO_CALIB_0_SCR                         0
#define FUSE_VREFRO_CALIB_0_WORD_COUNT                  0x1
#define FUSE_VREFRO_CALIB_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_VREFRO_CALIB_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define FUSE_VREFRO_CALIB_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_VREFRO_CALIB_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_VREFRO_CALIB_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define FUSE_VREFRO_CALIB_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
#define FUSE_VREFRO_CALIB_0_VREFRO_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_VREFRO_CALIB_0_VREFRO_CALIB_FIELD                  _MK_FIELD_CONST(0x3f, FUSE_VREFRO_CALIB_0_VREFRO_CALIB_SHIFT)
#define FUSE_VREFRO_CALIB_0_VREFRO_CALIB_RANGE                  5:0
#define FUSE_VREFRO_CALIB_0_VREFRO_CALIB_WOFFSET                        0x0
#define FUSE_VREFRO_CALIB_0_VREFRO_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_VREFRO_CALIB_0_VREFRO_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
#define FUSE_VREFRO_CALIB_0_VREFRO_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_VREFRO_CALIB_0_VREFRO_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_VREFRO_CALIB_0_VREFRO_CALIB_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_VREFRO_CALIB_0_VREFRO_CALIB_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_BOOT_NV_INFO_0
#define FUSE_BOOT_NV_INFO_0                     _MK_ADDR_CONST(0x578)
#define FUSE_BOOT_NV_INFO_0_SECURE                      0x0
#define FUSE_BOOT_NV_INFO_0_DUAL                        0x0
#define FUSE_BOOT_NV_INFO_0_SCR                         0
#define FUSE_BOOT_NV_INFO_0_WORD_COUNT                  0x1
#define FUSE_BOOT_NV_INFO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_BOOT_NV_INFO_0_RESET_MASK                  _MK_MASK_CONST(0xffff)
#define FUSE_BOOT_NV_INFO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_BOOT_NV_INFO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_BOOT_NV_INFO_0_READ_MASK                   _MK_MASK_CONST(0xffff)
#define FUSE_BOOT_NV_INFO_0_WRITE_MASK                  _MK_MASK_CONST(0xffff)
#define FUSE_BOOT_NV_INFO_0_BOOT_NV_INFO_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_BOOT_NV_INFO_0_BOOT_NV_INFO_FIELD                  _MK_FIELD_CONST(0xffff, FUSE_BOOT_NV_INFO_0_BOOT_NV_INFO_SHIFT)
#define FUSE_BOOT_NV_INFO_0_BOOT_NV_INFO_RANGE                  15:0
#define FUSE_BOOT_NV_INFO_0_BOOT_NV_INFO_WOFFSET                        0x0
#define FUSE_BOOT_NV_INFO_0_BOOT_NV_INFO_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_BOOT_NV_INFO_0_BOOT_NV_INFO_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
#define FUSE_BOOT_NV_INFO_0_BOOT_NV_INFO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_BOOT_NV_INFO_0_BOOT_NV_INFO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_BOOT_NV_INFO_0_BOOT_NV_INFO_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_BOOT_NV_INFO_0_BOOT_NV_INFO_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_OPT_RAM_SVOP_DP_PO4SVT_0
#define FUSE_OPT_RAM_SVOP_DP_PO4SVT_0                   _MK_ADDR_CONST(0x57c)
#define FUSE_OPT_RAM_SVOP_DP_PO4SVT_0_SECURE                    0x0
#define FUSE_OPT_RAM_SVOP_DP_PO4SVT_0_DUAL                      0x0
#define FUSE_OPT_RAM_SVOP_DP_PO4SVT_0_SCR                       0
#define FUSE_OPT_RAM_SVOP_DP_PO4SVT_0_WORD_COUNT                        0x1
#define FUSE_OPT_RAM_SVOP_DP_PO4SVT_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_DP_PO4SVT_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define FUSE_OPT_RAM_SVOP_DP_PO4SVT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_DP_PO4SVT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_DP_PO4SVT_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define FUSE_OPT_RAM_SVOP_DP_PO4SVT_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define FUSE_OPT_RAM_SVOP_DP_PO4SVT_0_OPT_RAM_SVOP_DP_PO4SVT_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_RAM_SVOP_DP_PO4SVT_0_OPT_RAM_SVOP_DP_PO4SVT_FIELD                      _MK_FIELD_CONST(0x3, FUSE_OPT_RAM_SVOP_DP_PO4SVT_0_OPT_RAM_SVOP_DP_PO4SVT_SHIFT)
#define FUSE_OPT_RAM_SVOP_DP_PO4SVT_0_OPT_RAM_SVOP_DP_PO4SVT_RANGE                      1:0
#define FUSE_OPT_RAM_SVOP_DP_PO4SVT_0_OPT_RAM_SVOP_DP_PO4SVT_WOFFSET                    0x0
#define FUSE_OPT_RAM_SVOP_DP_PO4SVT_0_OPT_RAM_SVOP_DP_PO4SVT_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_DP_PO4SVT_0_OPT_RAM_SVOP_DP_PO4SVT_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define FUSE_OPT_RAM_SVOP_DP_PO4SVT_0_OPT_RAM_SVOP_DP_PO4SVT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_DP_PO4SVT_0_OPT_RAM_SVOP_DP_PO4SVT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_DP_PO4SVT_0_OPT_RAM_SVOP_DP_PO4SVT_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_DP_PO4SVT_0_OPT_RAM_SVOP_DP_PO4SVT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_RAM_SVOP_PDP_PO4SVT_0
#define FUSE_OPT_RAM_SVOP_PDP_PO4SVT_0                  _MK_ADDR_CONST(0x580)
#define FUSE_OPT_RAM_SVOP_PDP_PO4SVT_0_SECURE                   0x0
#define FUSE_OPT_RAM_SVOP_PDP_PO4SVT_0_DUAL                     0x0
#define FUSE_OPT_RAM_SVOP_PDP_PO4SVT_0_SCR                      0
#define FUSE_OPT_RAM_SVOP_PDP_PO4SVT_0_WORD_COUNT                       0x1
#define FUSE_OPT_RAM_SVOP_PDP_PO4SVT_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_PDP_PO4SVT_0_RESET_MASK                       _MK_MASK_CONST(0xff)
#define FUSE_OPT_RAM_SVOP_PDP_PO4SVT_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_PDP_PO4SVT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_PDP_PO4SVT_0_READ_MASK                        _MK_MASK_CONST(0xff)
#define FUSE_OPT_RAM_SVOP_PDP_PO4SVT_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
#define FUSE_OPT_RAM_SVOP_PDP_PO4SVT_0_OPT_RAM_SVOP_PDP_PO4SVT_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_RAM_SVOP_PDP_PO4SVT_0_OPT_RAM_SVOP_PDP_PO4SVT_FIELD                    _MK_FIELD_CONST(0xff, FUSE_OPT_RAM_SVOP_PDP_PO4SVT_0_OPT_RAM_SVOP_PDP_PO4SVT_SHIFT)
#define FUSE_OPT_RAM_SVOP_PDP_PO4SVT_0_OPT_RAM_SVOP_PDP_PO4SVT_RANGE                    7:0
#define FUSE_OPT_RAM_SVOP_PDP_PO4SVT_0_OPT_RAM_SVOP_PDP_PO4SVT_WOFFSET                  0x0
#define FUSE_OPT_RAM_SVOP_PDP_PO4SVT_0_OPT_RAM_SVOP_PDP_PO4SVT_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_PDP_PO4SVT_0_OPT_RAM_SVOP_PDP_PO4SVT_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define FUSE_OPT_RAM_SVOP_PDP_PO4SVT_0_OPT_RAM_SVOP_PDP_PO4SVT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_PDP_PO4SVT_0_OPT_RAM_SVOP_PDP_PO4SVT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_PDP_PO4SVT_0_OPT_RAM_SVOP_PDP_PO4SVT_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_PDP_PO4SVT_0_OPT_RAM_SVOP_PDP_PO4SVT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_RAM_SVOP_SP_PO4SVT_0
#define FUSE_OPT_RAM_SVOP_SP_PO4SVT_0                   _MK_ADDR_CONST(0x584)
#define FUSE_OPT_RAM_SVOP_SP_PO4SVT_0_SECURE                    0x0
#define FUSE_OPT_RAM_SVOP_SP_PO4SVT_0_DUAL                      0x0
#define FUSE_OPT_RAM_SVOP_SP_PO4SVT_0_SCR                       0
#define FUSE_OPT_RAM_SVOP_SP_PO4SVT_0_WORD_COUNT                        0x1
#define FUSE_OPT_RAM_SVOP_SP_PO4SVT_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SP_PO4SVT_0_RESET_MASK                        _MK_MASK_CONST(0x7)
#define FUSE_OPT_RAM_SVOP_SP_PO4SVT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SP_PO4SVT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SP_PO4SVT_0_READ_MASK                         _MK_MASK_CONST(0x7)
#define FUSE_OPT_RAM_SVOP_SP_PO4SVT_0_WRITE_MASK                        _MK_MASK_CONST(0x7)
#define FUSE_OPT_RAM_SVOP_SP_PO4SVT_0_OPT_RAM_SVOP_SP_PO4SVT_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_RAM_SVOP_SP_PO4SVT_0_OPT_RAM_SVOP_SP_PO4SVT_FIELD                      _MK_FIELD_CONST(0x7, FUSE_OPT_RAM_SVOP_SP_PO4SVT_0_OPT_RAM_SVOP_SP_PO4SVT_SHIFT)
#define FUSE_OPT_RAM_SVOP_SP_PO4SVT_0_OPT_RAM_SVOP_SP_PO4SVT_RANGE                      2:0
#define FUSE_OPT_RAM_SVOP_SP_PO4SVT_0_OPT_RAM_SVOP_SP_PO4SVT_WOFFSET                    0x0
#define FUSE_OPT_RAM_SVOP_SP_PO4SVT_0_OPT_RAM_SVOP_SP_PO4SVT_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SP_PO4SVT_0_OPT_RAM_SVOP_SP_PO4SVT_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define FUSE_OPT_RAM_SVOP_SP_PO4SVT_0_OPT_RAM_SVOP_SP_PO4SVT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SP_PO4SVT_0_OPT_RAM_SVOP_SP_PO4SVT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SP_PO4SVT_0_OPT_RAM_SVOP_SP_PO4SVT_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SP_PO4SVT_0_OPT_RAM_SVOP_SP_PO4SVT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_RAM_SVOP_SMPDP_PO4SVT_0
#define FUSE_OPT_RAM_SVOP_SMPDP_PO4SVT_0                        _MK_ADDR_CONST(0x588)
#define FUSE_OPT_RAM_SVOP_SMPDP_PO4SVT_0_SECURE                         0x0
#define FUSE_OPT_RAM_SVOP_SMPDP_PO4SVT_0_DUAL                   0x0
#define FUSE_OPT_RAM_SVOP_SMPDP_PO4SVT_0_SCR                    0
#define FUSE_OPT_RAM_SVOP_SMPDP_PO4SVT_0_WORD_COUNT                     0x1
#define FUSE_OPT_RAM_SVOP_SMPDP_PO4SVT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SMPDP_PO4SVT_0_RESET_MASK                     _MK_MASK_CONST(0xff)
#define FUSE_OPT_RAM_SVOP_SMPDP_PO4SVT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SMPDP_PO4SVT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SMPDP_PO4SVT_0_READ_MASK                      _MK_MASK_CONST(0xff)
#define FUSE_OPT_RAM_SVOP_SMPDP_PO4SVT_0_WRITE_MASK                     _MK_MASK_CONST(0xff)
#define FUSE_OPT_RAM_SVOP_SMPDP_PO4SVT_0_OPT_RAM_SVOP_SMPDP_PO4SVT_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_OPT_RAM_SVOP_SMPDP_PO4SVT_0_OPT_RAM_SVOP_SMPDP_PO4SVT_FIELD                        _MK_FIELD_CONST(0xff, FUSE_OPT_RAM_SVOP_SMPDP_PO4SVT_0_OPT_RAM_SVOP_SMPDP_PO4SVT_SHIFT)
#define FUSE_OPT_RAM_SVOP_SMPDP_PO4SVT_0_OPT_RAM_SVOP_SMPDP_PO4SVT_RANGE                        7:0
#define FUSE_OPT_RAM_SVOP_SMPDP_PO4SVT_0_OPT_RAM_SVOP_SMPDP_PO4SVT_WOFFSET                      0x0
#define FUSE_OPT_RAM_SVOP_SMPDP_PO4SVT_0_OPT_RAM_SVOP_SMPDP_PO4SVT_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SMPDP_PO4SVT_0_OPT_RAM_SVOP_SMPDP_PO4SVT_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define FUSE_OPT_RAM_SVOP_SMPDP_PO4SVT_0_OPT_RAM_SVOP_SMPDP_PO4SVT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SMPDP_PO4SVT_0_OPT_RAM_SVOP_SMPDP_PO4SVT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SMPDP_PO4SVT_0_OPT_RAM_SVOP_SMPDP_PO4SVT_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SMPDP_PO4SVT_0_OPT_RAM_SVOP_SMPDP_PO4SVT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_OPT_RAM_SVOP_SP_PO4HVT_0
#define FUSE_OPT_RAM_SVOP_SP_PO4HVT_0                   _MK_ADDR_CONST(0x58c)
#define FUSE_OPT_RAM_SVOP_SP_PO4HVT_0_SECURE                    0x0
#define FUSE_OPT_RAM_SVOP_SP_PO4HVT_0_DUAL                      0x0
#define FUSE_OPT_RAM_SVOP_SP_PO4HVT_0_SCR                       0
#define FUSE_OPT_RAM_SVOP_SP_PO4HVT_0_WORD_COUNT                        0x1
#define FUSE_OPT_RAM_SVOP_SP_PO4HVT_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SP_PO4HVT_0_RESET_MASK                        _MK_MASK_CONST(0x7)
#define FUSE_OPT_RAM_SVOP_SP_PO4HVT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SP_PO4HVT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SP_PO4HVT_0_READ_MASK                         _MK_MASK_CONST(0x7)
#define FUSE_OPT_RAM_SVOP_SP_PO4HVT_0_WRITE_MASK                        _MK_MASK_CONST(0x7)
#define FUSE_OPT_RAM_SVOP_SP_PO4HVT_0_OPT_RAM_SVOP_SP_PO4HVT_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_RAM_SVOP_SP_PO4HVT_0_OPT_RAM_SVOP_SP_PO4HVT_FIELD                      _MK_FIELD_CONST(0x7, FUSE_OPT_RAM_SVOP_SP_PO4HVT_0_OPT_RAM_SVOP_SP_PO4HVT_SHIFT)
#define FUSE_OPT_RAM_SVOP_SP_PO4HVT_0_OPT_RAM_SVOP_SP_PO4HVT_RANGE                      2:0
#define FUSE_OPT_RAM_SVOP_SP_PO4HVT_0_OPT_RAM_SVOP_SP_PO4HVT_WOFFSET                    0x0
#define FUSE_OPT_RAM_SVOP_SP_PO4HVT_0_OPT_RAM_SVOP_SP_PO4HVT_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SP_PO4HVT_0_OPT_RAM_SVOP_SP_PO4HVT_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define FUSE_OPT_RAM_SVOP_SP_PO4HVT_0_OPT_RAM_SVOP_SP_PO4HVT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SP_PO4HVT_0_OPT_RAM_SVOP_SP_PO4HVT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SP_PO4HVT_0_OPT_RAM_SVOP_SP_PO4HVT_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SP_PO4HVT_0_OPT_RAM_SVOP_SP_PO4HVT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_FUSE_UCODE_HULK_REV_0
#define FUSE_OPT_FUSE_UCODE_HULK_REV_0                  _MK_ADDR_CONST(0x594)
#define FUSE_OPT_FUSE_UCODE_HULK_REV_0_SECURE                   0x0
#define FUSE_OPT_FUSE_UCODE_HULK_REV_0_DUAL                     0x0
#define FUSE_OPT_FUSE_UCODE_HULK_REV_0_SCR                      0
#define FUSE_OPT_FUSE_UCODE_HULK_REV_0_WORD_COUNT                       0x1
#define FUSE_OPT_FUSE_UCODE_HULK_REV_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_HULK_REV_0_RESET_MASK                       _MK_MASK_CONST(0x7)
#define FUSE_OPT_FUSE_UCODE_HULK_REV_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_HULK_REV_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_HULK_REV_0_READ_MASK                        _MK_MASK_CONST(0x7)
#define FUSE_OPT_FUSE_UCODE_HULK_REV_0_WRITE_MASK                       _MK_MASK_CONST(0x7)
#define FUSE_OPT_FUSE_UCODE_HULK_REV_0_OPT_FUSE_UCODE_HULK_REV_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_FUSE_UCODE_HULK_REV_0_OPT_FUSE_UCODE_HULK_REV_FIELD                    _MK_FIELD_CONST(0x7, FUSE_OPT_FUSE_UCODE_HULK_REV_0_OPT_FUSE_UCODE_HULK_REV_SHIFT)
#define FUSE_OPT_FUSE_UCODE_HULK_REV_0_OPT_FUSE_UCODE_HULK_REV_RANGE                    2:0
#define FUSE_OPT_FUSE_UCODE_HULK_REV_0_OPT_FUSE_UCODE_HULK_REV_WOFFSET                  0x0
#define FUSE_OPT_FUSE_UCODE_HULK_REV_0_OPT_FUSE_UCODE_HULK_REV_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_HULK_REV_0_OPT_FUSE_UCODE_HULK_REV_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define FUSE_OPT_FUSE_UCODE_HULK_REV_0_OPT_FUSE_UCODE_HULK_REV_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_HULK_REV_0_OPT_FUSE_UCODE_HULK_REV_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_HULK_REV_0_OPT_FUSE_UCODE_HULK_REV_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_HULK_REV_0_OPT_FUSE_UCODE_HULK_REV_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_FUSE_UCODE_UDE_REV_0
#define FUSE_OPT_FUSE_UCODE_UDE_REV_0                   _MK_ADDR_CONST(0x598)
#define FUSE_OPT_FUSE_UCODE_UDE_REV_0_SECURE                    0x0
#define FUSE_OPT_FUSE_UCODE_UDE_REV_0_DUAL                      0x0
#define FUSE_OPT_FUSE_UCODE_UDE_REV_0_SCR                       0
#define FUSE_OPT_FUSE_UCODE_UDE_REV_0_WORD_COUNT                        0x1
#define FUSE_OPT_FUSE_UCODE_UDE_REV_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_UDE_REV_0_RESET_MASK                        _MK_MASK_CONST(0x7)
#define FUSE_OPT_FUSE_UCODE_UDE_REV_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_UDE_REV_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_UDE_REV_0_READ_MASK                         _MK_MASK_CONST(0x7)
#define FUSE_OPT_FUSE_UCODE_UDE_REV_0_WRITE_MASK                        _MK_MASK_CONST(0x7)
#define FUSE_OPT_FUSE_UCODE_UDE_REV_0_OPT_FUSE_UCODE_UDE_REV_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_FUSE_UCODE_UDE_REV_0_OPT_FUSE_UCODE_UDE_REV_FIELD                      _MK_FIELD_CONST(0x7, FUSE_OPT_FUSE_UCODE_UDE_REV_0_OPT_FUSE_UCODE_UDE_REV_SHIFT)
#define FUSE_OPT_FUSE_UCODE_UDE_REV_0_OPT_FUSE_UCODE_UDE_REV_RANGE                      2:0
#define FUSE_OPT_FUSE_UCODE_UDE_REV_0_OPT_FUSE_UCODE_UDE_REV_WOFFSET                    0x0
#define FUSE_OPT_FUSE_UCODE_UDE_REV_0_OPT_FUSE_UCODE_UDE_REV_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_UDE_REV_0_OPT_FUSE_UCODE_UDE_REV_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define FUSE_OPT_FUSE_UCODE_UDE_REV_0_OPT_FUSE_UCODE_UDE_REV_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_UDE_REV_0_OPT_FUSE_UCODE_UDE_REV_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_UDE_REV_0_OPT_FUSE_UCODE_UDE_REV_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_UDE_REV_0_OPT_FUSE_UCODE_UDE_REV_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_0
#define FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_0                       _MK_ADDR_CONST(0x59c)
#define FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_0_SECURE                        0x0
#define FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_0_DUAL                  0x0
#define FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_0_SCR                   0
#define FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_0_WORD_COUNT                    0x1
#define FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_0_RESET_VAL                     _MK_MASK_CONST(0x1)
#define FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_0_RESET_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_0_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_0_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_FIELD                      _MK_FIELD_CONST(0x1, FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_0_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_SHIFT)
#define FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_0_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_RANGE                      0:0
#define FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_0_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_WOFFSET                    0x0
#define FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_0_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_DEFAULT                    _MK_MASK_CONST(0x1)
#define FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_0_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_0_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_0_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_0_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_0_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_FUSE_UCODE_CTXSW_REV_0
#define FUSE_OPT_FUSE_UCODE_CTXSW_REV_0                 _MK_ADDR_CONST(0x5a0)
#define FUSE_OPT_FUSE_UCODE_CTXSW_REV_0_SECURE                  0x0
#define FUSE_OPT_FUSE_UCODE_CTXSW_REV_0_DUAL                    0x0
#define FUSE_OPT_FUSE_UCODE_CTXSW_REV_0_SCR                     0
#define FUSE_OPT_FUSE_UCODE_CTXSW_REV_0_WORD_COUNT                      0x1
#define FUSE_OPT_FUSE_UCODE_CTXSW_REV_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_CTXSW_REV_0_RESET_MASK                      _MK_MASK_CONST(0x7)
#define FUSE_OPT_FUSE_UCODE_CTXSW_REV_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_CTXSW_REV_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_CTXSW_REV_0_READ_MASK                       _MK_MASK_CONST(0x7)
#define FUSE_OPT_FUSE_UCODE_CTXSW_REV_0_WRITE_MASK                      _MK_MASK_CONST(0x7)
#define FUSE_OPT_FUSE_UCODE_CTXSW_REV_0_OPT_FUSE_UCODE_CTXSW_REV_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_OPT_FUSE_UCODE_CTXSW_REV_0_OPT_FUSE_UCODE_CTXSW_REV_FIELD                  _MK_FIELD_CONST(0x7, FUSE_OPT_FUSE_UCODE_CTXSW_REV_0_OPT_FUSE_UCODE_CTXSW_REV_SHIFT)
#define FUSE_OPT_FUSE_UCODE_CTXSW_REV_0_OPT_FUSE_UCODE_CTXSW_REV_RANGE                  2:0
#define FUSE_OPT_FUSE_UCODE_CTXSW_REV_0_OPT_FUSE_UCODE_CTXSW_REV_WOFFSET                        0x0
#define FUSE_OPT_FUSE_UCODE_CTXSW_REV_0_OPT_FUSE_UCODE_CTXSW_REV_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_CTXSW_REV_0_OPT_FUSE_UCODE_CTXSW_REV_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define FUSE_OPT_FUSE_UCODE_CTXSW_REV_0_OPT_FUSE_UCODE_CTXSW_REV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_CTXSW_REV_0_OPT_FUSE_UCODE_CTXSW_REV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_CTXSW_REV_0_OPT_FUSE_UCODE_CTXSW_REV_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_CTXSW_REV_0_OPT_FUSE_UCODE_CTXSW_REV_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_OPT_ADC_CAL_INSTANCE4_DELTA_0
#define FUSE_OPT_ADC_CAL_INSTANCE4_DELTA_0                      _MK_ADDR_CONST(0x5a4)
#define FUSE_OPT_ADC_CAL_INSTANCE4_DELTA_0_SECURE                       0x0
#define FUSE_OPT_ADC_CAL_INSTANCE4_DELTA_0_DUAL                         0x0
#define FUSE_OPT_ADC_CAL_INSTANCE4_DELTA_0_SCR                  0
#define FUSE_OPT_ADC_CAL_INSTANCE4_DELTA_0_WORD_COUNT                   0x1
#define FUSE_OPT_ADC_CAL_INSTANCE4_DELTA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE4_DELTA_0_RESET_MASK                   _MK_MASK_CONST(0x7fffff)
#define FUSE_OPT_ADC_CAL_INSTANCE4_DELTA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE4_DELTA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE4_DELTA_0_READ_MASK                    _MK_MASK_CONST(0x7fffff)
#define FUSE_OPT_ADC_CAL_INSTANCE4_DELTA_0_WRITE_MASK                   _MK_MASK_CONST(0x7fffff)
#define FUSE_OPT_ADC_CAL_INSTANCE4_DELTA_0_OPT_ADC_CAL_INSTANCE4_DELTA_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_ADC_CAL_INSTANCE4_DELTA_0_OPT_ADC_CAL_INSTANCE4_DELTA_FIELD                    _MK_FIELD_CONST(0x7fffff, FUSE_OPT_ADC_CAL_INSTANCE4_DELTA_0_OPT_ADC_CAL_INSTANCE4_DELTA_SHIFT)
#define FUSE_OPT_ADC_CAL_INSTANCE4_DELTA_0_OPT_ADC_CAL_INSTANCE4_DELTA_RANGE                    22:0
#define FUSE_OPT_ADC_CAL_INSTANCE4_DELTA_0_OPT_ADC_CAL_INSTANCE4_DELTA_WOFFSET                  0x0
#define FUSE_OPT_ADC_CAL_INSTANCE4_DELTA_0_OPT_ADC_CAL_INSTANCE4_DELTA_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE4_DELTA_0_OPT_ADC_CAL_INSTANCE4_DELTA_DEFAULT_MASK                     _MK_MASK_CONST(0x7fffff)
#define FUSE_OPT_ADC_CAL_INSTANCE4_DELTA_0_OPT_ADC_CAL_INSTANCE4_DELTA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE4_DELTA_0_OPT_ADC_CAL_INSTANCE4_DELTA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE4_DELTA_0_OPT_ADC_CAL_INSTANCE4_DELTA_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_ADC_CAL_INSTANCE4_DELTA_0_OPT_ADC_CAL_INSTANCE4_DELTA_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_CUSTOMER_OPTIN_FUSE_0
#define FUSE_OPT_CUSTOMER_OPTIN_FUSE_0                  _MK_ADDR_CONST(0x5a8)
#define FUSE_OPT_CUSTOMER_OPTIN_FUSE_0_SECURE                   0x0
#define FUSE_OPT_CUSTOMER_OPTIN_FUSE_0_DUAL                     0x0
#define FUSE_OPT_CUSTOMER_OPTIN_FUSE_0_SCR                      0
#define FUSE_OPT_CUSTOMER_OPTIN_FUSE_0_WORD_COUNT                       0x1
#define FUSE_OPT_CUSTOMER_OPTIN_FUSE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_CUSTOMER_OPTIN_FUSE_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_OPT_CUSTOMER_OPTIN_FUSE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_CUSTOMER_OPTIN_FUSE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_CUSTOMER_OPTIN_FUSE_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_OPT_CUSTOMER_OPTIN_FUSE_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_OPT_CUSTOMER_OPTIN_FUSE_0_OPT_CUSTOMER_OPTIN_FUSE_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_CUSTOMER_OPTIN_FUSE_0_OPT_CUSTOMER_OPTIN_FUSE_FIELD                    _MK_FIELD_CONST(0x1, FUSE_OPT_CUSTOMER_OPTIN_FUSE_0_OPT_CUSTOMER_OPTIN_FUSE_SHIFT)
#define FUSE_OPT_CUSTOMER_OPTIN_FUSE_0_OPT_CUSTOMER_OPTIN_FUSE_RANGE                    0:0
#define FUSE_OPT_CUSTOMER_OPTIN_FUSE_0_OPT_CUSTOMER_OPTIN_FUSE_WOFFSET                  0x0
#define FUSE_OPT_CUSTOMER_OPTIN_FUSE_0_OPT_CUSTOMER_OPTIN_FUSE_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_CUSTOMER_OPTIN_FUSE_0_OPT_CUSTOMER_OPTIN_FUSE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_OPT_CUSTOMER_OPTIN_FUSE_0_OPT_CUSTOMER_OPTIN_FUSE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_CUSTOMER_OPTIN_FUSE_0_OPT_CUSTOMER_OPTIN_FUSE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_CUSTOMER_OPTIN_FUSE_0_OPT_CUSTOMER_OPTIN_FUSE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_CUSTOMER_OPTIN_FUSE_0_OPT_CUSTOMER_OPTIN_FUSE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_RESERVED_FUSELESS_0
#define FUSE_RESERVED_FUSELESS_0                        _MK_ADDR_CONST(0x5ac)
#define FUSE_RESERVED_FUSELESS_0_SECURE                         0x0
#define FUSE_RESERVED_FUSELESS_0_DUAL                   0x0
#define FUSE_RESERVED_FUSELESS_0_SCR                    0
#define FUSE_RESERVED_FUSELESS_0_WORD_COUNT                     0x1
#define FUSE_RESERVED_FUSELESS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_FUSELESS_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_FUSELESS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_FUSELESS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_FUSELESS_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_FUSELESS_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_FUSELESS_0_RESERVED_FUSELESS_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_RESERVED_FUSELESS_0_RESERVED_FUSELESS_FIELD                        _MK_FIELD_CONST(0xffffffff, FUSE_RESERVED_FUSELESS_0_RESERVED_FUSELESS_SHIFT)
#define FUSE_RESERVED_FUSELESS_0_RESERVED_FUSELESS_RANGE                        31:0
#define FUSE_RESERVED_FUSELESS_0_RESERVED_FUSELESS_WOFFSET                      0x0
#define FUSE_RESERVED_FUSELESS_0_RESERVED_FUSELESS_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_FUSELESS_0_RESERVED_FUSELESS_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define FUSE_RESERVED_FUSELESS_0_RESERVED_FUSELESS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_FUSELESS_0_RESERVED_FUSELESS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_FUSELESS_0_RESERVED_FUSELESS_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_RESERVED_FUSELESS_0_RESERVED_FUSELESS_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_IP_DISABLE_0
#define FUSE_IP_DISABLE_0                       _MK_ADDR_CONST(0x5b0)
#define FUSE_IP_DISABLE_0_SECURE                        0x0
#define FUSE_IP_DISABLE_0_DUAL                  0x0
#define FUSE_IP_DISABLE_0_SCR                   0
#define FUSE_IP_DISABLE_0_WORD_COUNT                    0x1
#define FUSE_IP_DISABLE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_IP_DISABLE_0_RESET_MASK                    _MK_MASK_CONST(0x3f)
#define FUSE_IP_DISABLE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_IP_DISABLE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define FUSE_IP_DISABLE_0_READ_MASK                     _MK_MASK_CONST(0x3f)
#define FUSE_IP_DISABLE_0_WRITE_MASK                    _MK_MASK_CONST(0x3f)
#define FUSE_IP_DISABLE_0_IP_DISABLE_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_IP_DISABLE_0_IP_DISABLE_FIELD                      _MK_FIELD_CONST(0x3f, FUSE_IP_DISABLE_0_IP_DISABLE_SHIFT)
#define FUSE_IP_DISABLE_0_IP_DISABLE_RANGE                      5:0
#define FUSE_IP_DISABLE_0_IP_DISABLE_WOFFSET                    0x0
#define FUSE_IP_DISABLE_0_IP_DISABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_IP_DISABLE_0_IP_DISABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
#define FUSE_IP_DISABLE_0_IP_DISABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_IP_DISABLE_0_IP_DISABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_IP_DISABLE_0_IP_DISABLE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_IP_DISABLE_0_IP_DISABLE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_ASYNC_L1ARST_ENABLE_0
#define FUSE_OPT_ASYNC_L1ARST_ENABLE_0                  _MK_ADDR_CONST(0x5b4)
#define FUSE_OPT_ASYNC_L1ARST_ENABLE_0_SECURE                   0x0
#define FUSE_OPT_ASYNC_L1ARST_ENABLE_0_DUAL                     0x0
#define FUSE_OPT_ASYNC_L1ARST_ENABLE_0_SCR                      0
#define FUSE_OPT_ASYNC_L1ARST_ENABLE_0_WORD_COUNT                       0x1
#define FUSE_OPT_ASYNC_L1ARST_ENABLE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_ASYNC_L1ARST_ENABLE_0_RESET_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_OPT_ASYNC_L1ARST_ENABLE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_ASYNC_L1ARST_ENABLE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_ASYNC_L1ARST_ENABLE_0_READ_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_OPT_ASYNC_L1ARST_ENABLE_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_OPT_ASYNC_L1ARST_ENABLE_0_OPT_ASYNC_L1ARST_ENABLE_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_ASYNC_L1ARST_ENABLE_0_OPT_ASYNC_L1ARST_ENABLE_FIELD                    _MK_FIELD_CONST(0x1, FUSE_OPT_ASYNC_L1ARST_ENABLE_0_OPT_ASYNC_L1ARST_ENABLE_SHIFT)
#define FUSE_OPT_ASYNC_L1ARST_ENABLE_0_OPT_ASYNC_L1ARST_ENABLE_RANGE                    0:0
#define FUSE_OPT_ASYNC_L1ARST_ENABLE_0_OPT_ASYNC_L1ARST_ENABLE_WOFFSET                  0x0
#define FUSE_OPT_ASYNC_L1ARST_ENABLE_0_OPT_ASYNC_L1ARST_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_ASYNC_L1ARST_ENABLE_0_OPT_ASYNC_L1ARST_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_OPT_ASYNC_L1ARST_ENABLE_0_OPT_ASYNC_L1ARST_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_ASYNC_L1ARST_ENABLE_0_OPT_ASYNC_L1ARST_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_ASYNC_L1ARST_ENABLE_0_OPT_ASYNC_L1ARST_ENABLE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_ASYNC_L1ARST_ENABLE_0_OPT_ASYNC_L1ARST_ENABLE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_ASYNC_L0RST_ENABLE_0
#define FUSE_OPT_ASYNC_L0RST_ENABLE_0                   _MK_ADDR_CONST(0x5b8)
#define FUSE_OPT_ASYNC_L0RST_ENABLE_0_SECURE                    0x0
#define FUSE_OPT_ASYNC_L0RST_ENABLE_0_DUAL                      0x0
#define FUSE_OPT_ASYNC_L0RST_ENABLE_0_SCR                       0
#define FUSE_OPT_ASYNC_L0RST_ENABLE_0_WORD_COUNT                        0x1
#define FUSE_OPT_ASYNC_L0RST_ENABLE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_ASYNC_L0RST_ENABLE_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_OPT_ASYNC_L0RST_ENABLE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_ASYNC_L0RST_ENABLE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_ASYNC_L0RST_ENABLE_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define FUSE_OPT_ASYNC_L0RST_ENABLE_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_OPT_ASYNC_L0RST_ENABLE_0_OPT_ASYNC_L0RST_ENABLE_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_ASYNC_L0RST_ENABLE_0_OPT_ASYNC_L0RST_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, FUSE_OPT_ASYNC_L0RST_ENABLE_0_OPT_ASYNC_L0RST_ENABLE_SHIFT)
#define FUSE_OPT_ASYNC_L0RST_ENABLE_0_OPT_ASYNC_L0RST_ENABLE_RANGE                      0:0
#define FUSE_OPT_ASYNC_L0RST_ENABLE_0_OPT_ASYNC_L0RST_ENABLE_WOFFSET                    0x0
#define FUSE_OPT_ASYNC_L0RST_ENABLE_0_OPT_ASYNC_L0RST_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_ASYNC_L0RST_ENABLE_0_OPT_ASYNC_L0RST_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_OPT_ASYNC_L0RST_ENABLE_0_OPT_ASYNC_L0RST_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_ASYNC_L0RST_ENABLE_0_OPT_ASYNC_L0RST_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_ASYNC_L0RST_ENABLE_0_OPT_ASYNC_L0RST_ENABLE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_ASYNC_L0RST_ENABLE_0_OPT_ASYNC_L0RST_ENABLE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_0
#define FUSE_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_0                 _MK_ADDR_CONST(0x5bc)
#define FUSE_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_0_SECURE                  0x0
#define FUSE_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_0_DUAL                    0x0
#define FUSE_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_0_SCR                     0
#define FUSE_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_0_WORD_COUNT                      0x1
#define FUSE_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_0_RESET_VAL                       _MK_MASK_CONST(0x1)
#define FUSE_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_0_RESET_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_0_READ_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
#define FUSE_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_0_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_0_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_FIELD                  _MK_FIELD_CONST(0x1, FUSE_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_0_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_SHIFT)
#define FUSE_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_0_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_RANGE                  0:0
#define FUSE_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_0_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_WOFFSET                        0x0
#define FUSE_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_0_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_DEFAULT                        _MK_MASK_CONST(0x1)
#define FUSE_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_0_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_0_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_0_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_0_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_0_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_OPT_IST_DISABLE_JTAG_FILLER_0
#define FUSE_OPT_IST_DISABLE_JTAG_FILLER_0                      _MK_ADDR_CONST(0x5c0)
#define FUSE_OPT_IST_DISABLE_JTAG_FILLER_0_SECURE                       0x0
#define FUSE_OPT_IST_DISABLE_JTAG_FILLER_0_DUAL                         0x0
#define FUSE_OPT_IST_DISABLE_JTAG_FILLER_0_SCR                  0
#define FUSE_OPT_IST_DISABLE_JTAG_FILLER_0_WORD_COUNT                   0x1
#define FUSE_OPT_IST_DISABLE_JTAG_FILLER_0_RESET_VAL                    _MK_MASK_CONST(0x1)
#define FUSE_OPT_IST_DISABLE_JTAG_FILLER_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_OPT_IST_DISABLE_JTAG_FILLER_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_IST_DISABLE_JTAG_FILLER_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_IST_DISABLE_JTAG_FILLER_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_OPT_IST_DISABLE_JTAG_FILLER_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_OPT_IST_DISABLE_JTAG_FILLER_0_OPT_IST_DISABLE_JTAG_FILLER_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_IST_DISABLE_JTAG_FILLER_0_OPT_IST_DISABLE_JTAG_FILLER_FIELD                    _MK_FIELD_CONST(0x1, FUSE_OPT_IST_DISABLE_JTAG_FILLER_0_OPT_IST_DISABLE_JTAG_FILLER_SHIFT)
#define FUSE_OPT_IST_DISABLE_JTAG_FILLER_0_OPT_IST_DISABLE_JTAG_FILLER_RANGE                    0:0
#define FUSE_OPT_IST_DISABLE_JTAG_FILLER_0_OPT_IST_DISABLE_JTAG_FILLER_WOFFSET                  0x0
#define FUSE_OPT_IST_DISABLE_JTAG_FILLER_0_OPT_IST_DISABLE_JTAG_FILLER_DEFAULT                  _MK_MASK_CONST(0x1)
#define FUSE_OPT_IST_DISABLE_JTAG_FILLER_0_OPT_IST_DISABLE_JTAG_FILLER_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_OPT_IST_DISABLE_JTAG_FILLER_0_OPT_IST_DISABLE_JTAG_FILLER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_IST_DISABLE_JTAG_FILLER_0_OPT_IST_DISABLE_JTAG_FILLER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_IST_DISABLE_JTAG_FILLER_0_OPT_IST_DISABLE_JTAG_FILLER_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_IST_DISABLE_JTAG_FILLER_0_OPT_IST_DISABLE_JTAG_FILLER_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_0
#define FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_0                   _MK_ADDR_CONST(0x5c4)
#define FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_0_SECURE                    0x0
#define FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_0_DUAL                      0x0
#define FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_0_SCR                       0
#define FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_0_WORD_COUNT                        0x1
#define FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_0_RESET_VAL                         _MK_MASK_CONST(0x1)
#define FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_0_RESET_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_0_READ_MASK                         _MK_MASK_CONST(0x1)
#define FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
#define FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_0_OPT_IST_DISABLE_DEBUG_FEATURES_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_0_OPT_IST_DISABLE_DEBUG_FEATURES_FIELD                      _MK_FIELD_CONST(0x1, FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_0_OPT_IST_DISABLE_DEBUG_FEATURES_SHIFT)
#define FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_0_OPT_IST_DISABLE_DEBUG_FEATURES_RANGE                      0:0
#define FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_0_OPT_IST_DISABLE_DEBUG_FEATURES_WOFFSET                    0x0
#define FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_0_OPT_IST_DISABLE_DEBUG_FEATURES_DEFAULT                    _MK_MASK_CONST(0x1)
#define FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_0_OPT_IST_DISABLE_DEBUG_FEATURES_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_0_OPT_IST_DISABLE_DEBUG_FEATURES_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_0_OPT_IST_DISABLE_DEBUG_FEATURES_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_0_OPT_IST_DISABLE_DEBUG_FEATURES_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_0_OPT_IST_DISABLE_DEBUG_FEATURES_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE_0
#define FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE_0                 _MK_ADDR_CONST(0x5cc)
#define FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE_0_SECURE                  0x0
#define FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE_0_DUAL                    0x0
#define FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE_0_SCR                     0
#define FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE_0_WORD_COUNT                      0x1
#define FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE_0_RESET_MASK                      _MK_MASK_CONST(0xff)
#define FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE_0_READ_MASK                       _MK_MASK_CONST(0xff)
#define FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
#define FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE_0_OPT_SECURE_NVLINK_MASK_WR_SECURE_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE_0_OPT_SECURE_NVLINK_MASK_WR_SECURE_FIELD                  _MK_FIELD_CONST(0xff, FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE_0_OPT_SECURE_NVLINK_MASK_WR_SECURE_SHIFT)
#define FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE_0_OPT_SECURE_NVLINK_MASK_WR_SECURE_RANGE                  7:0
#define FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE_0_OPT_SECURE_NVLINK_MASK_WR_SECURE_WOFFSET                        0x0
#define FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE_0_OPT_SECURE_NVLINK_MASK_WR_SECURE_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE_0_OPT_SECURE_NVLINK_MASK_WR_SECURE_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE_0_OPT_SECURE_NVLINK_MASK_WR_SECURE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE_0_OPT_SECURE_NVLINK_MASK_WR_SECURE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE_0_OPT_SECURE_NVLINK_MASK_WR_SECURE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE_0_OPT_SECURE_NVLINK_MASK_WR_SECURE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_0
#define FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_0                    _MK_ADDR_CONST(0x5d0)
#define FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_0_SECURE                     0x0
#define FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_0_DUAL                       0x0
#define FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_0_SCR                        0
#define FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_0_WORD_COUNT                         0x1
#define FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_0_RESET_MASK                         _MK_MASK_CONST(0x1)
#define FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_0_READ_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
#define FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_0_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_0_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_FIELD                        _MK_FIELD_CONST(0x1, FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_0_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_SHIFT)
#define FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_0_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_RANGE                        0:0
#define FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_0_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_WOFFSET                      0x0
#define FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_0_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_0_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_0_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_0_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_0_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_0_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_OPT_FUSE_UCODE_MINION_REV_0
#define FUSE_OPT_FUSE_UCODE_MINION_REV_0                        _MK_ADDR_CONST(0x5d4)
#define FUSE_OPT_FUSE_UCODE_MINION_REV_0_SECURE                         0x0
#define FUSE_OPT_FUSE_UCODE_MINION_REV_0_DUAL                   0x0
#define FUSE_OPT_FUSE_UCODE_MINION_REV_0_SCR                    0
#define FUSE_OPT_FUSE_UCODE_MINION_REV_0_WORD_COUNT                     0x1
#define FUSE_OPT_FUSE_UCODE_MINION_REV_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_MINION_REV_0_RESET_MASK                     _MK_MASK_CONST(0x7)
#define FUSE_OPT_FUSE_UCODE_MINION_REV_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_MINION_REV_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_MINION_REV_0_READ_MASK                      _MK_MASK_CONST(0x7)
#define FUSE_OPT_FUSE_UCODE_MINION_REV_0_WRITE_MASK                     _MK_MASK_CONST(0x7)
#define FUSE_OPT_FUSE_UCODE_MINION_REV_0_OPT_FUSE_UCODE_MINION_REV_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_OPT_FUSE_UCODE_MINION_REV_0_OPT_FUSE_UCODE_MINION_REV_FIELD                        _MK_FIELD_CONST(0x7, FUSE_OPT_FUSE_UCODE_MINION_REV_0_OPT_FUSE_UCODE_MINION_REV_SHIFT)
#define FUSE_OPT_FUSE_UCODE_MINION_REV_0_OPT_FUSE_UCODE_MINION_REV_RANGE                        2:0
#define FUSE_OPT_FUSE_UCODE_MINION_REV_0_OPT_FUSE_UCODE_MINION_REV_WOFFSET                      0x0
#define FUSE_OPT_FUSE_UCODE_MINION_REV_0_OPT_FUSE_UCODE_MINION_REV_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_MINION_REV_0_OPT_FUSE_UCODE_MINION_REV_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define FUSE_OPT_FUSE_UCODE_MINION_REV_0_OPT_FUSE_UCODE_MINION_REV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_MINION_REV_0_OPT_FUSE_UCODE_MINION_REV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_MINION_REV_0_OPT_FUSE_UCODE_MINION_REV_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_FUSE_UCODE_MINION_REV_0_OPT_FUSE_UCODE_MINION_REV_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_OPT_SECURE_MINION_DEBUG_DIS_0
#define FUSE_OPT_SECURE_MINION_DEBUG_DIS_0                      _MK_ADDR_CONST(0x5d8)
#define FUSE_OPT_SECURE_MINION_DEBUG_DIS_0_SECURE                       0x0
#define FUSE_OPT_SECURE_MINION_DEBUG_DIS_0_DUAL                         0x0
#define FUSE_OPT_SECURE_MINION_DEBUG_DIS_0_SCR                  0
#define FUSE_OPT_SECURE_MINION_DEBUG_DIS_0_WORD_COUNT                   0x1
#define FUSE_OPT_SECURE_MINION_DEBUG_DIS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_MINION_DEBUG_DIS_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_OPT_SECURE_MINION_DEBUG_DIS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_MINION_DEBUG_DIS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_MINION_DEBUG_DIS_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_OPT_SECURE_MINION_DEBUG_DIS_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_OPT_SECURE_MINION_DEBUG_DIS_0_OPT_SECURE_MINION_DEBUG_DIS_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_SECURE_MINION_DEBUG_DIS_0_OPT_SECURE_MINION_DEBUG_DIS_FIELD                    _MK_FIELD_CONST(0x1, FUSE_OPT_SECURE_MINION_DEBUG_DIS_0_OPT_SECURE_MINION_DEBUG_DIS_SHIFT)
#define FUSE_OPT_SECURE_MINION_DEBUG_DIS_0_OPT_SECURE_MINION_DEBUG_DIS_RANGE                    0:0
#define FUSE_OPT_SECURE_MINION_DEBUG_DIS_0_OPT_SECURE_MINION_DEBUG_DIS_WOFFSET                  0x0
#define FUSE_OPT_SECURE_MINION_DEBUG_DIS_0_OPT_SECURE_MINION_DEBUG_DIS_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_MINION_DEBUG_DIS_0_OPT_SECURE_MINION_DEBUG_DIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_OPT_SECURE_MINION_DEBUG_DIS_0_OPT_SECURE_MINION_DEBUG_DIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_MINION_DEBUG_DIS_0_OPT_SECURE_MINION_DEBUG_DIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_MINION_DEBUG_DIS_0_OPT_SECURE_MINION_DEBUG_DIS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_SECURE_MINION_DEBUG_DIS_0_OPT_SECURE_MINION_DEBUG_DIS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_RAM_SVOP_DP_SVT_0
#define FUSE_OPT_RAM_SVOP_DP_SVT_0                      _MK_ADDR_CONST(0x5dc)
#define FUSE_OPT_RAM_SVOP_DP_SVT_0_SECURE                       0x0
#define FUSE_OPT_RAM_SVOP_DP_SVT_0_DUAL                         0x0
#define FUSE_OPT_RAM_SVOP_DP_SVT_0_SCR                  0
#define FUSE_OPT_RAM_SVOP_DP_SVT_0_WORD_COUNT                   0x1
#define FUSE_OPT_RAM_SVOP_DP_SVT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_DP_SVT_0_RESET_MASK                   _MK_MASK_CONST(0x3)
#define FUSE_OPT_RAM_SVOP_DP_SVT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_DP_SVT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_DP_SVT_0_READ_MASK                    _MK_MASK_CONST(0x3)
#define FUSE_OPT_RAM_SVOP_DP_SVT_0_WRITE_MASK                   _MK_MASK_CONST(0x3)
#define FUSE_OPT_RAM_SVOP_DP_SVT_0_OPT_RAM_SVOP_DP_SVT_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_RAM_SVOP_DP_SVT_0_OPT_RAM_SVOP_DP_SVT_FIELD                    _MK_FIELD_CONST(0x3, FUSE_OPT_RAM_SVOP_DP_SVT_0_OPT_RAM_SVOP_DP_SVT_SHIFT)
#define FUSE_OPT_RAM_SVOP_DP_SVT_0_OPT_RAM_SVOP_DP_SVT_RANGE                    1:0
#define FUSE_OPT_RAM_SVOP_DP_SVT_0_OPT_RAM_SVOP_DP_SVT_WOFFSET                  0x0
#define FUSE_OPT_RAM_SVOP_DP_SVT_0_OPT_RAM_SVOP_DP_SVT_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_DP_SVT_0_OPT_RAM_SVOP_DP_SVT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define FUSE_OPT_RAM_SVOP_DP_SVT_0_OPT_RAM_SVOP_DP_SVT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_DP_SVT_0_OPT_RAM_SVOP_DP_SVT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_DP_SVT_0_OPT_RAM_SVOP_DP_SVT_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_DP_SVT_0_OPT_RAM_SVOP_DP_SVT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_RAM_SVOP_SP_SVT_0
#define FUSE_OPT_RAM_SVOP_SP_SVT_0                      _MK_ADDR_CONST(0x5e0)
#define FUSE_OPT_RAM_SVOP_SP_SVT_0_SECURE                       0x0
#define FUSE_OPT_RAM_SVOP_SP_SVT_0_DUAL                         0x0
#define FUSE_OPT_RAM_SVOP_SP_SVT_0_SCR                  0
#define FUSE_OPT_RAM_SVOP_SP_SVT_0_WORD_COUNT                   0x1
#define FUSE_OPT_RAM_SVOP_SP_SVT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SP_SVT_0_RESET_MASK                   _MK_MASK_CONST(0x7)
#define FUSE_OPT_RAM_SVOP_SP_SVT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SP_SVT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SP_SVT_0_READ_MASK                    _MK_MASK_CONST(0x7)
#define FUSE_OPT_RAM_SVOP_SP_SVT_0_WRITE_MASK                   _MK_MASK_CONST(0x7)
#define FUSE_OPT_RAM_SVOP_SP_SVT_0_OPT_RAM_SVOP_SP_SVT_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_OPT_RAM_SVOP_SP_SVT_0_OPT_RAM_SVOP_SP_SVT_FIELD                    _MK_FIELD_CONST(0x7, FUSE_OPT_RAM_SVOP_SP_SVT_0_OPT_RAM_SVOP_SP_SVT_SHIFT)
#define FUSE_OPT_RAM_SVOP_SP_SVT_0_OPT_RAM_SVOP_SP_SVT_RANGE                    2:0
#define FUSE_OPT_RAM_SVOP_SP_SVT_0_OPT_RAM_SVOP_SP_SVT_WOFFSET                  0x0
#define FUSE_OPT_RAM_SVOP_SP_SVT_0_OPT_RAM_SVOP_SP_SVT_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SP_SVT_0_OPT_RAM_SVOP_SP_SVT_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define FUSE_OPT_RAM_SVOP_SP_SVT_0_OPT_RAM_SVOP_SP_SVT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SP_SVT_0_OPT_RAM_SVOP_SP_SVT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SP_SVT_0_OPT_RAM_SVOP_SP_SVT_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_SP_SVT_0_OPT_RAM_SVOP_SP_SVT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_RAM_SVOP_PDP_SVT_0
#define FUSE_OPT_RAM_SVOP_PDP_SVT_0                     _MK_ADDR_CONST(0x5e4)
#define FUSE_OPT_RAM_SVOP_PDP_SVT_0_SECURE                      0x0
#define FUSE_OPT_RAM_SVOP_PDP_SVT_0_DUAL                        0x0
#define FUSE_OPT_RAM_SVOP_PDP_SVT_0_SCR                         0
#define FUSE_OPT_RAM_SVOP_PDP_SVT_0_WORD_COUNT                  0x1
#define FUSE_OPT_RAM_SVOP_PDP_SVT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_PDP_SVT_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define FUSE_OPT_RAM_SVOP_PDP_SVT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_PDP_SVT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_PDP_SVT_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define FUSE_OPT_RAM_SVOP_PDP_SVT_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define FUSE_OPT_RAM_SVOP_PDP_SVT_0_OPT_RAM_SVOP_PDP_SVT_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_OPT_RAM_SVOP_PDP_SVT_0_OPT_RAM_SVOP_PDP_SVT_FIELD                  _MK_FIELD_CONST(0xff, FUSE_OPT_RAM_SVOP_PDP_SVT_0_OPT_RAM_SVOP_PDP_SVT_SHIFT)
#define FUSE_OPT_RAM_SVOP_PDP_SVT_0_OPT_RAM_SVOP_PDP_SVT_RANGE                  7:0
#define FUSE_OPT_RAM_SVOP_PDP_SVT_0_OPT_RAM_SVOP_PDP_SVT_WOFFSET                        0x0
#define FUSE_OPT_RAM_SVOP_PDP_SVT_0_OPT_RAM_SVOP_PDP_SVT_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_PDP_SVT_0_OPT_RAM_SVOP_PDP_SVT_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define FUSE_OPT_RAM_SVOP_PDP_SVT_0_OPT_RAM_SVOP_PDP_SVT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_PDP_SVT_0_OPT_RAM_SVOP_PDP_SVT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_PDP_SVT_0_OPT_RAM_SVOP_PDP_SVT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_SVOP_PDP_SVT_0_OPT_RAM_SVOP_PDP_SVT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_OPT_ROM_SVOP_HVT_0
#define FUSE_OPT_ROM_SVOP_HVT_0                 _MK_ADDR_CONST(0x5e8)
#define FUSE_OPT_ROM_SVOP_HVT_0_SECURE                  0x0
#define FUSE_OPT_ROM_SVOP_HVT_0_DUAL                    0x0
#define FUSE_OPT_ROM_SVOP_HVT_0_SCR                     0
#define FUSE_OPT_ROM_SVOP_HVT_0_WORD_COUNT                      0x1
#define FUSE_OPT_ROM_SVOP_HVT_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_OPT_ROM_SVOP_HVT_0_RESET_MASK                      _MK_MASK_CONST(0x3)
#define FUSE_OPT_ROM_SVOP_HVT_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_ROM_SVOP_HVT_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_ROM_SVOP_HVT_0_READ_MASK                       _MK_MASK_CONST(0x3)
#define FUSE_OPT_ROM_SVOP_HVT_0_WRITE_MASK                      _MK_MASK_CONST(0x3)
#define FUSE_OPT_ROM_SVOP_HVT_0_OPT_ROM_SVOP_HVT_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_OPT_ROM_SVOP_HVT_0_OPT_ROM_SVOP_HVT_FIELD                  _MK_FIELD_CONST(0x3, FUSE_OPT_ROM_SVOP_HVT_0_OPT_ROM_SVOP_HVT_SHIFT)
#define FUSE_OPT_ROM_SVOP_HVT_0_OPT_ROM_SVOP_HVT_RANGE                  1:0
#define FUSE_OPT_ROM_SVOP_HVT_0_OPT_ROM_SVOP_HVT_WOFFSET                        0x0
#define FUSE_OPT_ROM_SVOP_HVT_0_OPT_ROM_SVOP_HVT_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_ROM_SVOP_HVT_0_OPT_ROM_SVOP_HVT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define FUSE_OPT_ROM_SVOP_HVT_0_OPT_ROM_SVOP_HVT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_ROM_SVOP_HVT_0_OPT_ROM_SVOP_HVT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_ROM_SVOP_HVT_0_OPT_ROM_SVOP_HVT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_ROM_SVOP_HVT_0_OPT_ROM_SVOP_HVT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_FALCON_UCODE_NV_REV_0
#define FUSE_FALCON_UCODE_NV_REV_0                      _MK_ADDR_CONST(0x5ec)
#define FUSE_FALCON_UCODE_NV_REV_0_SECURE                       0x0
#define FUSE_FALCON_UCODE_NV_REV_0_DUAL                         0x0
#define FUSE_FALCON_UCODE_NV_REV_0_SCR                  0
#define FUSE_FALCON_UCODE_NV_REV_0_WORD_COUNT                   0x1
#define FUSE_FALCON_UCODE_NV_REV_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_FALCON_UCODE_NV_REV_0_RESET_MASK                   _MK_MASK_CONST(0x7f)
#define FUSE_FALCON_UCODE_NV_REV_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_FALCON_UCODE_NV_REV_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_FALCON_UCODE_NV_REV_0_READ_MASK                    _MK_MASK_CONST(0x7f)
#define FUSE_FALCON_UCODE_NV_REV_0_WRITE_MASK                   _MK_MASK_CONST(0x7f)
#define FUSE_FALCON_UCODE_NV_REV_0_FALCON_UCODE_NV_REV_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_FALCON_UCODE_NV_REV_0_FALCON_UCODE_NV_REV_FIELD                    _MK_FIELD_CONST(0x7f, FUSE_FALCON_UCODE_NV_REV_0_FALCON_UCODE_NV_REV_SHIFT)
#define FUSE_FALCON_UCODE_NV_REV_0_FALCON_UCODE_NV_REV_RANGE                    6:0
#define FUSE_FALCON_UCODE_NV_REV_0_FALCON_UCODE_NV_REV_WOFFSET                  0x0
#define FUSE_FALCON_UCODE_NV_REV_0_FALCON_UCODE_NV_REV_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_FALCON_UCODE_NV_REV_0_FALCON_UCODE_NV_REV_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
#define FUSE_FALCON_UCODE_NV_REV_0_FALCON_UCODE_NV_REV_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_FALCON_UCODE_NV_REV_0_FALCON_UCODE_NV_REV_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_FALCON_UCODE_NV_REV_0_FALCON_UCODE_NV_REV_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_FALCON_UCODE_NV_REV_0_FALCON_UCODE_NV_REV_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_OPT_NVDEC_DISABLE_0
#define FUSE_OPT_NVDEC_DISABLE_0                        _MK_ADDR_CONST(0x5f0)
#define FUSE_OPT_NVDEC_DISABLE_0_SECURE                         0x0
#define FUSE_OPT_NVDEC_DISABLE_0_DUAL                   0x0
#define FUSE_OPT_NVDEC_DISABLE_0_SCR                    0
#define FUSE_OPT_NVDEC_DISABLE_0_WORD_COUNT                     0x1
#define FUSE_OPT_NVDEC_DISABLE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVDEC_DISABLE_0_RESET_MASK                     _MK_MASK_CONST(0x3)
#define FUSE_OPT_NVDEC_DISABLE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVDEC_DISABLE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVDEC_DISABLE_0_READ_MASK                      _MK_MASK_CONST(0x3)
#define FUSE_OPT_NVDEC_DISABLE_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
#define FUSE_OPT_NVDEC_DISABLE_0_OPT_NVDEC_DISABLE_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_OPT_NVDEC_DISABLE_0_OPT_NVDEC_DISABLE_FIELD                        _MK_FIELD_CONST(0x3, FUSE_OPT_NVDEC_DISABLE_0_OPT_NVDEC_DISABLE_SHIFT)
#define FUSE_OPT_NVDEC_DISABLE_0_OPT_NVDEC_DISABLE_RANGE                        1:0
#define FUSE_OPT_NVDEC_DISABLE_0_OPT_NVDEC_DISABLE_WOFFSET                      0x0
#define FUSE_OPT_NVDEC_DISABLE_0_OPT_NVDEC_DISABLE_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVDEC_DISABLE_0_OPT_NVDEC_DISABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define FUSE_OPT_NVDEC_DISABLE_0_OPT_NVDEC_DISABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVDEC_DISABLE_0_OPT_NVDEC_DISABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVDEC_DISABLE_0_OPT_NVDEC_DISABLE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVDEC_DISABLE_0_OPT_NVDEC_DISABLE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_OPT_NVDEC_DISABLE_CP_0
#define FUSE_OPT_NVDEC_DISABLE_CP_0                     _MK_ADDR_CONST(0x5f4)
#define FUSE_OPT_NVDEC_DISABLE_CP_0_SECURE                      0x0
#define FUSE_OPT_NVDEC_DISABLE_CP_0_DUAL                        0x0
#define FUSE_OPT_NVDEC_DISABLE_CP_0_SCR                         0
#define FUSE_OPT_NVDEC_DISABLE_CP_0_WORD_COUNT                  0x1
#define FUSE_OPT_NVDEC_DISABLE_CP_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVDEC_DISABLE_CP_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define FUSE_OPT_NVDEC_DISABLE_CP_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVDEC_DISABLE_CP_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVDEC_DISABLE_CP_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define FUSE_OPT_NVDEC_DISABLE_CP_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
#define FUSE_OPT_NVDEC_DISABLE_CP_0_OPT_NVDEC_DISABLE_CP_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_OPT_NVDEC_DISABLE_CP_0_OPT_NVDEC_DISABLE_CP_FIELD                  _MK_FIELD_CONST(0x3, FUSE_OPT_NVDEC_DISABLE_CP_0_OPT_NVDEC_DISABLE_CP_SHIFT)
#define FUSE_OPT_NVDEC_DISABLE_CP_0_OPT_NVDEC_DISABLE_CP_RANGE                  1:0
#define FUSE_OPT_NVDEC_DISABLE_CP_0_OPT_NVDEC_DISABLE_CP_WOFFSET                        0x0
#define FUSE_OPT_NVDEC_DISABLE_CP_0_OPT_NVDEC_DISABLE_CP_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVDEC_DISABLE_CP_0_OPT_NVDEC_DISABLE_CP_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define FUSE_OPT_NVDEC_DISABLE_CP_0_OPT_NVDEC_DISABLE_CP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVDEC_DISABLE_CP_0_OPT_NVDEC_DISABLE_CP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVDEC_DISABLE_CP_0_OPT_NVDEC_DISABLE_CP_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_NVDEC_DISABLE_CP_0_OPT_NVDEC_DISABLE_CP_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_OPT_RAM_FOP_CCPLEX_6D_0
#define FUSE_OPT_RAM_FOP_CCPLEX_6D_0                    _MK_ADDR_CONST(0x5f8)
#define FUSE_OPT_RAM_FOP_CCPLEX_6D_0_SECURE                     0x0
#define FUSE_OPT_RAM_FOP_CCPLEX_6D_0_DUAL                       0x0
#define FUSE_OPT_RAM_FOP_CCPLEX_6D_0_SCR                        0
#define FUSE_OPT_RAM_FOP_CCPLEX_6D_0_WORD_COUNT                         0x1
#define FUSE_OPT_RAM_FOP_CCPLEX_6D_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CCPLEX_6D_0_RESET_MASK                         _MK_MASK_CONST(0x7)
#define FUSE_OPT_RAM_FOP_CCPLEX_6D_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CCPLEX_6D_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CCPLEX_6D_0_READ_MASK                  _MK_MASK_CONST(0x7)
#define FUSE_OPT_RAM_FOP_CCPLEX_6D_0_WRITE_MASK                         _MK_MASK_CONST(0x7)
#define FUSE_OPT_RAM_FOP_CCPLEX_6D_0_OPT_RAM_FOP_CCPLEX_6D_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_OPT_RAM_FOP_CCPLEX_6D_0_OPT_RAM_FOP_CCPLEX_6D_FIELD                        _MK_FIELD_CONST(0x7, FUSE_OPT_RAM_FOP_CCPLEX_6D_0_OPT_RAM_FOP_CCPLEX_6D_SHIFT)
#define FUSE_OPT_RAM_FOP_CCPLEX_6D_0_OPT_RAM_FOP_CCPLEX_6D_RANGE                        2:0
#define FUSE_OPT_RAM_FOP_CCPLEX_6D_0_OPT_RAM_FOP_CCPLEX_6D_WOFFSET                      0x0
#define FUSE_OPT_RAM_FOP_CCPLEX_6D_0_OPT_RAM_FOP_CCPLEX_6D_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CCPLEX_6D_0_OPT_RAM_FOP_CCPLEX_6D_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define FUSE_OPT_RAM_FOP_CCPLEX_6D_0_OPT_RAM_FOP_CCPLEX_6D_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CCPLEX_6D_0_OPT_RAM_FOP_CCPLEX_6D_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CCPLEX_6D_0_OPT_RAM_FOP_CCPLEX_6D_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CCPLEX_6D_0_OPT_RAM_FOP_CCPLEX_6D_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_OPT_RAM_FOP_CCPLEX_L2_0
#define FUSE_OPT_RAM_FOP_CCPLEX_L2_0                    _MK_ADDR_CONST(0x5fc)
#define FUSE_OPT_RAM_FOP_CCPLEX_L2_0_SECURE                     0x0
#define FUSE_OPT_RAM_FOP_CCPLEX_L2_0_DUAL                       0x0
#define FUSE_OPT_RAM_FOP_CCPLEX_L2_0_SCR                        0
#define FUSE_OPT_RAM_FOP_CCPLEX_L2_0_WORD_COUNT                         0x1
#define FUSE_OPT_RAM_FOP_CCPLEX_L2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CCPLEX_L2_0_RESET_MASK                         _MK_MASK_CONST(0x7)
#define FUSE_OPT_RAM_FOP_CCPLEX_L2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CCPLEX_L2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CCPLEX_L2_0_READ_MASK                  _MK_MASK_CONST(0x7)
#define FUSE_OPT_RAM_FOP_CCPLEX_L2_0_WRITE_MASK                         _MK_MASK_CONST(0x7)
#define FUSE_OPT_RAM_FOP_CCPLEX_L2_0_OPT_RAM_FOP_CCPLEX_L2_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_OPT_RAM_FOP_CCPLEX_L2_0_OPT_RAM_FOP_CCPLEX_L2_FIELD                        _MK_FIELD_CONST(0x7, FUSE_OPT_RAM_FOP_CCPLEX_L2_0_OPT_RAM_FOP_CCPLEX_L2_SHIFT)
#define FUSE_OPT_RAM_FOP_CCPLEX_L2_0_OPT_RAM_FOP_CCPLEX_L2_RANGE                        2:0
#define FUSE_OPT_RAM_FOP_CCPLEX_L2_0_OPT_RAM_FOP_CCPLEX_L2_WOFFSET                      0x0
#define FUSE_OPT_RAM_FOP_CCPLEX_L2_0_OPT_RAM_FOP_CCPLEX_L2_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CCPLEX_L2_0_OPT_RAM_FOP_CCPLEX_L2_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define FUSE_OPT_RAM_FOP_CCPLEX_L2_0_OPT_RAM_FOP_CCPLEX_L2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CCPLEX_L2_0_OPT_RAM_FOP_CCPLEX_L2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CCPLEX_L2_0_OPT_RAM_FOP_CCPLEX_L2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CCPLEX_L2_0_OPT_RAM_FOP_CCPLEX_L2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_OPT_RAM_FOP_CCPLEX_L3D_0
#define FUSE_OPT_RAM_FOP_CCPLEX_L3D_0                   _MK_ADDR_CONST(0x600)
#define FUSE_OPT_RAM_FOP_CCPLEX_L3D_0_SECURE                    0x0
#define FUSE_OPT_RAM_FOP_CCPLEX_L3D_0_DUAL                      0x0
#define FUSE_OPT_RAM_FOP_CCPLEX_L3D_0_SCR                       0
#define FUSE_OPT_RAM_FOP_CCPLEX_L3D_0_WORD_COUNT                        0x1
#define FUSE_OPT_RAM_FOP_CCPLEX_L3D_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CCPLEX_L3D_0_RESET_MASK                        _MK_MASK_CONST(0xff)
#define FUSE_OPT_RAM_FOP_CCPLEX_L3D_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CCPLEX_L3D_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CCPLEX_L3D_0_READ_MASK                         _MK_MASK_CONST(0xff)
#define FUSE_OPT_RAM_FOP_CCPLEX_L3D_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
#define FUSE_OPT_RAM_FOP_CCPLEX_L3D_0_OPT_RAM_FOP_CCPLEX_L3D_SHIFT                      _MK_SHIFT_CONST(0)
#define FUSE_OPT_RAM_FOP_CCPLEX_L3D_0_OPT_RAM_FOP_CCPLEX_L3D_FIELD                      _MK_FIELD_CONST(0xff, FUSE_OPT_RAM_FOP_CCPLEX_L3D_0_OPT_RAM_FOP_CCPLEX_L3D_SHIFT)
#define FUSE_OPT_RAM_FOP_CCPLEX_L3D_0_OPT_RAM_FOP_CCPLEX_L3D_RANGE                      7:0
#define FUSE_OPT_RAM_FOP_CCPLEX_L3D_0_OPT_RAM_FOP_CCPLEX_L3D_WOFFSET                    0x0
#define FUSE_OPT_RAM_FOP_CCPLEX_L3D_0_OPT_RAM_FOP_CCPLEX_L3D_DEFAULT                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CCPLEX_L3D_0_OPT_RAM_FOP_CCPLEX_L3D_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define FUSE_OPT_RAM_FOP_CCPLEX_L3D_0_OPT_RAM_FOP_CCPLEX_L3D_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CCPLEX_L3D_0_OPT_RAM_FOP_CCPLEX_L3D_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CCPLEX_L3D_0_OPT_RAM_FOP_CCPLEX_L3D_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CCPLEX_L3D_0_OPT_RAM_FOP_CCPLEX_L3D_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

// Register FUSE_OPT_RAM_FOP_CV_CVSRAM_0
#define FUSE_OPT_RAM_FOP_CV_CVSRAM_0                    _MK_ADDR_CONST(0x604)
#define FUSE_OPT_RAM_FOP_CV_CVSRAM_0_SECURE                     0x0
#define FUSE_OPT_RAM_FOP_CV_CVSRAM_0_DUAL                       0x0
#define FUSE_OPT_RAM_FOP_CV_CVSRAM_0_SCR                        0
#define FUSE_OPT_RAM_FOP_CV_CVSRAM_0_WORD_COUNT                         0x1
#define FUSE_OPT_RAM_FOP_CV_CVSRAM_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CV_CVSRAM_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define FUSE_OPT_RAM_FOP_CV_CVSRAM_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CV_CVSRAM_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CV_CVSRAM_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define FUSE_OPT_RAM_FOP_CV_CVSRAM_0_WRITE_MASK                         _MK_MASK_CONST(0xff)
#define FUSE_OPT_RAM_FOP_CV_CVSRAM_0_OPT_RAM_FOP_CV_CVSRAM_SHIFT                        _MK_SHIFT_CONST(0)
#define FUSE_OPT_RAM_FOP_CV_CVSRAM_0_OPT_RAM_FOP_CV_CVSRAM_FIELD                        _MK_FIELD_CONST(0xff, FUSE_OPT_RAM_FOP_CV_CVSRAM_0_OPT_RAM_FOP_CV_CVSRAM_SHIFT)
#define FUSE_OPT_RAM_FOP_CV_CVSRAM_0_OPT_RAM_FOP_CV_CVSRAM_RANGE                        7:0
#define FUSE_OPT_RAM_FOP_CV_CVSRAM_0_OPT_RAM_FOP_CV_CVSRAM_WOFFSET                      0x0
#define FUSE_OPT_RAM_FOP_CV_CVSRAM_0_OPT_RAM_FOP_CV_CVSRAM_DEFAULT                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CV_CVSRAM_0_OPT_RAM_FOP_CV_CVSRAM_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define FUSE_OPT_RAM_FOP_CV_CVSRAM_0_OPT_RAM_FOP_CV_CVSRAM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CV_CVSRAM_0_OPT_RAM_FOP_CV_CVSRAM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CV_CVSRAM_0_OPT_RAM_FOP_CV_CVSRAM_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define FUSE_OPT_RAM_FOP_CV_CVSRAM_0_OPT_RAM_FOP_CV_CVSRAM_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

// Register FUSE_USB3_RCM_CALIB2_0
#define FUSE_USB3_RCM_CALIB2_0                  _MK_ADDR_CONST(0x608)
#define FUSE_USB3_RCM_CALIB2_0_SECURE                   0x0
#define FUSE_USB3_RCM_CALIB2_0_DUAL                     0x0
#define FUSE_USB3_RCM_CALIB2_0_SCR                      0
#define FUSE_USB3_RCM_CALIB2_0_WORD_COUNT                       0x1
#define FUSE_USB3_RCM_CALIB2_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define FUSE_USB3_RCM_CALIB2_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define FUSE_USB3_RCM_CALIB2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_USB3_RCM_CALIB2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_USB3_RCM_CALIB2_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define FUSE_USB3_RCM_CALIB2_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define FUSE_USB3_RCM_CALIB2_0_USB3_RCM_CALIB2_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_USB3_RCM_CALIB2_0_USB3_RCM_CALIB2_FIELD                    _MK_FIELD_CONST(0xffff, FUSE_USB3_RCM_CALIB2_0_USB3_RCM_CALIB2_SHIFT)
#define FUSE_USB3_RCM_CALIB2_0_USB3_RCM_CALIB2_RANGE                    15:0
#define FUSE_USB3_RCM_CALIB2_0_USB3_RCM_CALIB2_WOFFSET                  0x0
#define FUSE_USB3_RCM_CALIB2_0_USB3_RCM_CALIB2_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_USB3_RCM_CALIB2_0_USB3_RCM_CALIB2_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define FUSE_USB3_RCM_CALIB2_0_USB3_RCM_CALIB2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_USB3_RCM_CALIB2_0_USB3_RCM_CALIB2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_USB3_RCM_CALIB2_0_USB3_RCM_CALIB2_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_USB3_RCM_CALIB2_0_USB3_RCM_CALIB2_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_0_0
#define FUSE_SPARE_BIT_0_0                      _MK_ADDR_CONST(0x60c)
#define FUSE_SPARE_BIT_0_0_SECURE                       0x0
#define FUSE_SPARE_BIT_0_0_DUAL                         0x0
#define FUSE_SPARE_BIT_0_0_SCR                  0
#define FUSE_SPARE_BIT_0_0_WORD_COUNT                   0x1
#define FUSE_SPARE_BIT_0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_0_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_0_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_0_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_FIELD                    _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_0_0_SPARE_BIT_0_SHIFT)
#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_RANGE                    0:0
#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_WOFFSET                  0x0
#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_1_0
#define FUSE_SPARE_BIT_1_0                      _MK_ADDR_CONST(0x610)
#define FUSE_SPARE_BIT_1_0_SECURE                       0x0
#define FUSE_SPARE_BIT_1_0_DUAL                         0x0
#define FUSE_SPARE_BIT_1_0_SCR                  0
#define FUSE_SPARE_BIT_1_0_WORD_COUNT                   0x1
#define FUSE_SPARE_BIT_1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_1_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_1_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_1_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_FIELD                    _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_1_0_SPARE_BIT_1_SHIFT)
#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_RANGE                    0:0
#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_WOFFSET                  0x0
#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_2_0
#define FUSE_SPARE_BIT_2_0                      _MK_ADDR_CONST(0x614)
#define FUSE_SPARE_BIT_2_0_SECURE                       0x0
#define FUSE_SPARE_BIT_2_0_DUAL                         0x0
#define FUSE_SPARE_BIT_2_0_SCR                  0
#define FUSE_SPARE_BIT_2_0_WORD_COUNT                   0x1
#define FUSE_SPARE_BIT_2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_2_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_2_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_2_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_FIELD                    _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_2_0_SPARE_BIT_2_SHIFT)
#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_RANGE                    0:0
#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_WOFFSET                  0x0
#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_3_0
#define FUSE_SPARE_BIT_3_0                      _MK_ADDR_CONST(0x618)
#define FUSE_SPARE_BIT_3_0_SECURE                       0x0
#define FUSE_SPARE_BIT_3_0_DUAL                         0x0
#define FUSE_SPARE_BIT_3_0_SCR                  0
#define FUSE_SPARE_BIT_3_0_WORD_COUNT                   0x1
#define FUSE_SPARE_BIT_3_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_3_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_3_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_3_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_FIELD                    _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_3_0_SPARE_BIT_3_SHIFT)
#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_RANGE                    0:0
#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_WOFFSET                  0x0
#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_4_0
#define FUSE_SPARE_BIT_4_0                      _MK_ADDR_CONST(0x61c)
#define FUSE_SPARE_BIT_4_0_SECURE                       0x0
#define FUSE_SPARE_BIT_4_0_DUAL                         0x0
#define FUSE_SPARE_BIT_4_0_SCR                  0
#define FUSE_SPARE_BIT_4_0_WORD_COUNT                   0x1
#define FUSE_SPARE_BIT_4_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_4_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_4_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_4_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_4_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_4_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_FIELD                    _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_4_0_SPARE_BIT_4_SHIFT)
#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_RANGE                    0:0
#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_WOFFSET                  0x0
#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_5_0
#define FUSE_SPARE_BIT_5_0                      _MK_ADDR_CONST(0x620)
#define FUSE_SPARE_BIT_5_0_SECURE                       0x0
#define FUSE_SPARE_BIT_5_0_DUAL                         0x0
#define FUSE_SPARE_BIT_5_0_SCR                  0
#define FUSE_SPARE_BIT_5_0_WORD_COUNT                   0x1
#define FUSE_SPARE_BIT_5_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_5_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_5_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_5_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_5_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_5_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_FIELD                    _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_5_0_SPARE_BIT_5_SHIFT)
#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_RANGE                    0:0
#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_WOFFSET                  0x0
#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_6_0
#define FUSE_SPARE_BIT_6_0                      _MK_ADDR_CONST(0x624)
#define FUSE_SPARE_BIT_6_0_SECURE                       0x0
#define FUSE_SPARE_BIT_6_0_DUAL                         0x0
#define FUSE_SPARE_BIT_6_0_SCR                  0
#define FUSE_SPARE_BIT_6_0_WORD_COUNT                   0x1
#define FUSE_SPARE_BIT_6_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_6_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_6_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_6_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_6_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_6_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_FIELD                    _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_6_0_SPARE_BIT_6_SHIFT)
#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_RANGE                    0:0
#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_WOFFSET                  0x0
#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_7_0
#define FUSE_SPARE_BIT_7_0                      _MK_ADDR_CONST(0x628)
#define FUSE_SPARE_BIT_7_0_SECURE                       0x0
#define FUSE_SPARE_BIT_7_0_DUAL                         0x0
#define FUSE_SPARE_BIT_7_0_SCR                  0
#define FUSE_SPARE_BIT_7_0_WORD_COUNT                   0x1
#define FUSE_SPARE_BIT_7_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_7_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_7_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_7_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_7_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_7_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_FIELD                    _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_7_0_SPARE_BIT_7_SHIFT)
#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_RANGE                    0:0
#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_WOFFSET                  0x0
#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_8_0
#define FUSE_SPARE_BIT_8_0                      _MK_ADDR_CONST(0x62c)
#define FUSE_SPARE_BIT_8_0_SECURE                       0x0
#define FUSE_SPARE_BIT_8_0_DUAL                         0x0
#define FUSE_SPARE_BIT_8_0_SCR                  0
#define FUSE_SPARE_BIT_8_0_WORD_COUNT                   0x1
#define FUSE_SPARE_BIT_8_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_8_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_8_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_8_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_8_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_8_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_FIELD                    _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_8_0_SPARE_BIT_8_SHIFT)
#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_RANGE                    0:0
#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_WOFFSET                  0x0
#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_9_0
#define FUSE_SPARE_BIT_9_0                      _MK_ADDR_CONST(0x630)
#define FUSE_SPARE_BIT_9_0_SECURE                       0x0
#define FUSE_SPARE_BIT_9_0_DUAL                         0x0
#define FUSE_SPARE_BIT_9_0_SCR                  0
#define FUSE_SPARE_BIT_9_0_WORD_COUNT                   0x1
#define FUSE_SPARE_BIT_9_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_9_0_RESET_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_9_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_9_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_9_0_READ_MASK                    _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_9_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_SHIFT                    _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_FIELD                    _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_9_0_SPARE_BIT_9_SHIFT)
#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_RANGE                    0:0
#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_WOFFSET                  0x0
#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_DEFAULT                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_10_0
#define FUSE_SPARE_BIT_10_0                     _MK_ADDR_CONST(0x634)
#define FUSE_SPARE_BIT_10_0_SECURE                      0x0
#define FUSE_SPARE_BIT_10_0_DUAL                        0x0
#define FUSE_SPARE_BIT_10_0_SCR                         0
#define FUSE_SPARE_BIT_10_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_10_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_10_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_10_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_10_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_10_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_10_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_10_0_SPARE_BIT_10_SHIFT)
#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_RANGE                  0:0
#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_WOFFSET                        0x0
#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_11_0
#define FUSE_SPARE_BIT_11_0                     _MK_ADDR_CONST(0x638)
#define FUSE_SPARE_BIT_11_0_SECURE                      0x0
#define FUSE_SPARE_BIT_11_0_DUAL                        0x0
#define FUSE_SPARE_BIT_11_0_SCR                         0
#define FUSE_SPARE_BIT_11_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_11_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_11_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_11_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_11_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_11_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_11_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_11_0_SPARE_BIT_11_SHIFT)
#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_RANGE                  0:0
#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_WOFFSET                        0x0
#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_12_0
#define FUSE_SPARE_BIT_12_0                     _MK_ADDR_CONST(0x63c)
#define FUSE_SPARE_BIT_12_0_SECURE                      0x0
#define FUSE_SPARE_BIT_12_0_DUAL                        0x0
#define FUSE_SPARE_BIT_12_0_SCR                         0
#define FUSE_SPARE_BIT_12_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_12_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_12_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_12_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_12_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_12_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_12_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_12_0_SPARE_BIT_12_SHIFT)
#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_RANGE                  0:0
#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_WOFFSET                        0x0
#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_13_0
#define FUSE_SPARE_BIT_13_0                     _MK_ADDR_CONST(0x640)
#define FUSE_SPARE_BIT_13_0_SECURE                      0x0
#define FUSE_SPARE_BIT_13_0_DUAL                        0x0
#define FUSE_SPARE_BIT_13_0_SCR                         0
#define FUSE_SPARE_BIT_13_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_13_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_13_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_13_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_13_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_13_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_13_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_13_0_SPARE_BIT_13_SHIFT)
#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_RANGE                  0:0
#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_WOFFSET                        0x0
#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_14_0
#define FUSE_SPARE_BIT_14_0                     _MK_ADDR_CONST(0x644)
#define FUSE_SPARE_BIT_14_0_SECURE                      0x0
#define FUSE_SPARE_BIT_14_0_DUAL                        0x0
#define FUSE_SPARE_BIT_14_0_SCR                         0
#define FUSE_SPARE_BIT_14_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_14_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_14_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_14_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_14_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_14_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_14_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_14_0_SPARE_BIT_14_SHIFT)
#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_RANGE                  0:0
#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_WOFFSET                        0x0
#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_15_0
#define FUSE_SPARE_BIT_15_0                     _MK_ADDR_CONST(0x648)
#define FUSE_SPARE_BIT_15_0_SECURE                      0x0
#define FUSE_SPARE_BIT_15_0_DUAL                        0x0
#define FUSE_SPARE_BIT_15_0_SCR                         0
#define FUSE_SPARE_BIT_15_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_15_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_15_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_15_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_15_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_15_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_15_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_15_0_SPARE_BIT_15_SHIFT)
#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_RANGE                  0:0
#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_WOFFSET                        0x0
#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_16_0
#define FUSE_SPARE_BIT_16_0                     _MK_ADDR_CONST(0x64c)
#define FUSE_SPARE_BIT_16_0_SECURE                      0x0
#define FUSE_SPARE_BIT_16_0_DUAL                        0x0
#define FUSE_SPARE_BIT_16_0_SCR                         0
#define FUSE_SPARE_BIT_16_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_16_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_16_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_16_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_16_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_16_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_16_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_16_0_SPARE_BIT_16_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_16_0_SPARE_BIT_16_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_16_0_SPARE_BIT_16_SHIFT)
#define FUSE_SPARE_BIT_16_0_SPARE_BIT_16_RANGE                  0:0
#define FUSE_SPARE_BIT_16_0_SPARE_BIT_16_WOFFSET                        0x0
#define FUSE_SPARE_BIT_16_0_SPARE_BIT_16_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_16_0_SPARE_BIT_16_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_16_0_SPARE_BIT_16_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_16_0_SPARE_BIT_16_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_16_0_SPARE_BIT_16_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_16_0_SPARE_BIT_16_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_17_0
#define FUSE_SPARE_BIT_17_0                     _MK_ADDR_CONST(0x650)
#define FUSE_SPARE_BIT_17_0_SECURE                      0x0
#define FUSE_SPARE_BIT_17_0_DUAL                        0x0
#define FUSE_SPARE_BIT_17_0_SCR                         0
#define FUSE_SPARE_BIT_17_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_17_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_17_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_17_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_17_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_17_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_17_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_17_0_SPARE_BIT_17_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_17_0_SPARE_BIT_17_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_17_0_SPARE_BIT_17_SHIFT)
#define FUSE_SPARE_BIT_17_0_SPARE_BIT_17_RANGE                  0:0
#define FUSE_SPARE_BIT_17_0_SPARE_BIT_17_WOFFSET                        0x0
#define FUSE_SPARE_BIT_17_0_SPARE_BIT_17_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_17_0_SPARE_BIT_17_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_17_0_SPARE_BIT_17_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_17_0_SPARE_BIT_17_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_17_0_SPARE_BIT_17_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_17_0_SPARE_BIT_17_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_18_0
#define FUSE_SPARE_BIT_18_0                     _MK_ADDR_CONST(0x654)
#define FUSE_SPARE_BIT_18_0_SECURE                      0x0
#define FUSE_SPARE_BIT_18_0_DUAL                        0x0
#define FUSE_SPARE_BIT_18_0_SCR                         0
#define FUSE_SPARE_BIT_18_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_18_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_18_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_18_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_18_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_18_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_18_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_18_0_SPARE_BIT_18_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_18_0_SPARE_BIT_18_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_18_0_SPARE_BIT_18_SHIFT)
#define FUSE_SPARE_BIT_18_0_SPARE_BIT_18_RANGE                  0:0
#define FUSE_SPARE_BIT_18_0_SPARE_BIT_18_WOFFSET                        0x0
#define FUSE_SPARE_BIT_18_0_SPARE_BIT_18_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_18_0_SPARE_BIT_18_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_18_0_SPARE_BIT_18_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_18_0_SPARE_BIT_18_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_18_0_SPARE_BIT_18_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_18_0_SPARE_BIT_18_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_19_0
#define FUSE_SPARE_BIT_19_0                     _MK_ADDR_CONST(0x658)
#define FUSE_SPARE_BIT_19_0_SECURE                      0x0
#define FUSE_SPARE_BIT_19_0_DUAL                        0x0
#define FUSE_SPARE_BIT_19_0_SCR                         0
#define FUSE_SPARE_BIT_19_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_19_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_19_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_19_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_19_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_19_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_19_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_19_0_SPARE_BIT_19_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_19_0_SPARE_BIT_19_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_19_0_SPARE_BIT_19_SHIFT)
#define FUSE_SPARE_BIT_19_0_SPARE_BIT_19_RANGE                  0:0
#define FUSE_SPARE_BIT_19_0_SPARE_BIT_19_WOFFSET                        0x0
#define FUSE_SPARE_BIT_19_0_SPARE_BIT_19_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_19_0_SPARE_BIT_19_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_19_0_SPARE_BIT_19_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_19_0_SPARE_BIT_19_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_19_0_SPARE_BIT_19_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_19_0_SPARE_BIT_19_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_20_0
#define FUSE_SPARE_BIT_20_0                     _MK_ADDR_CONST(0x65c)
#define FUSE_SPARE_BIT_20_0_SECURE                      0x0
#define FUSE_SPARE_BIT_20_0_DUAL                        0x0
#define FUSE_SPARE_BIT_20_0_SCR                         0
#define FUSE_SPARE_BIT_20_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_20_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_20_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_20_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_20_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_20_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_20_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_20_0_SPARE_BIT_20_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_20_0_SPARE_BIT_20_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_20_0_SPARE_BIT_20_SHIFT)
#define FUSE_SPARE_BIT_20_0_SPARE_BIT_20_RANGE                  0:0
#define FUSE_SPARE_BIT_20_0_SPARE_BIT_20_WOFFSET                        0x0
#define FUSE_SPARE_BIT_20_0_SPARE_BIT_20_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_20_0_SPARE_BIT_20_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_20_0_SPARE_BIT_20_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_20_0_SPARE_BIT_20_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_20_0_SPARE_BIT_20_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_20_0_SPARE_BIT_20_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_21_0
#define FUSE_SPARE_BIT_21_0                     _MK_ADDR_CONST(0x660)
#define FUSE_SPARE_BIT_21_0_SECURE                      0x0
#define FUSE_SPARE_BIT_21_0_DUAL                        0x0
#define FUSE_SPARE_BIT_21_0_SCR                         0
#define FUSE_SPARE_BIT_21_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_21_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_21_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_21_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_21_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_21_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_21_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_21_0_SPARE_BIT_21_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_21_0_SPARE_BIT_21_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_21_0_SPARE_BIT_21_SHIFT)
#define FUSE_SPARE_BIT_21_0_SPARE_BIT_21_RANGE                  0:0
#define FUSE_SPARE_BIT_21_0_SPARE_BIT_21_WOFFSET                        0x0
#define FUSE_SPARE_BIT_21_0_SPARE_BIT_21_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_21_0_SPARE_BIT_21_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_21_0_SPARE_BIT_21_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_21_0_SPARE_BIT_21_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_21_0_SPARE_BIT_21_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_21_0_SPARE_BIT_21_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_22_0
#define FUSE_SPARE_BIT_22_0                     _MK_ADDR_CONST(0x664)
#define FUSE_SPARE_BIT_22_0_SECURE                      0x0
#define FUSE_SPARE_BIT_22_0_DUAL                        0x0
#define FUSE_SPARE_BIT_22_0_SCR                         0
#define FUSE_SPARE_BIT_22_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_22_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_22_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_22_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_22_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_22_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_22_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_22_0_SPARE_BIT_22_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_22_0_SPARE_BIT_22_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_22_0_SPARE_BIT_22_SHIFT)
#define FUSE_SPARE_BIT_22_0_SPARE_BIT_22_RANGE                  0:0
#define FUSE_SPARE_BIT_22_0_SPARE_BIT_22_WOFFSET                        0x0
#define FUSE_SPARE_BIT_22_0_SPARE_BIT_22_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_22_0_SPARE_BIT_22_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_22_0_SPARE_BIT_22_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_22_0_SPARE_BIT_22_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_22_0_SPARE_BIT_22_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_22_0_SPARE_BIT_22_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_23_0
#define FUSE_SPARE_BIT_23_0                     _MK_ADDR_CONST(0x668)
#define FUSE_SPARE_BIT_23_0_SECURE                      0x0
#define FUSE_SPARE_BIT_23_0_DUAL                        0x0
#define FUSE_SPARE_BIT_23_0_SCR                         0
#define FUSE_SPARE_BIT_23_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_23_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_23_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_23_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_23_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_23_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_23_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_23_0_SPARE_BIT_23_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_23_0_SPARE_BIT_23_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_23_0_SPARE_BIT_23_SHIFT)
#define FUSE_SPARE_BIT_23_0_SPARE_BIT_23_RANGE                  0:0
#define FUSE_SPARE_BIT_23_0_SPARE_BIT_23_WOFFSET                        0x0
#define FUSE_SPARE_BIT_23_0_SPARE_BIT_23_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_23_0_SPARE_BIT_23_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_23_0_SPARE_BIT_23_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_23_0_SPARE_BIT_23_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_23_0_SPARE_BIT_23_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_23_0_SPARE_BIT_23_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_24_0
#define FUSE_SPARE_BIT_24_0                     _MK_ADDR_CONST(0x66c)
#define FUSE_SPARE_BIT_24_0_SECURE                      0x0
#define FUSE_SPARE_BIT_24_0_DUAL                        0x0
#define FUSE_SPARE_BIT_24_0_SCR                         0
#define FUSE_SPARE_BIT_24_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_24_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_24_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_24_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_24_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_24_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_24_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_24_0_SPARE_BIT_24_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_24_0_SPARE_BIT_24_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_24_0_SPARE_BIT_24_SHIFT)
#define FUSE_SPARE_BIT_24_0_SPARE_BIT_24_RANGE                  0:0
#define FUSE_SPARE_BIT_24_0_SPARE_BIT_24_WOFFSET                        0x0
#define FUSE_SPARE_BIT_24_0_SPARE_BIT_24_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_24_0_SPARE_BIT_24_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_24_0_SPARE_BIT_24_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_24_0_SPARE_BIT_24_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_24_0_SPARE_BIT_24_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_24_0_SPARE_BIT_24_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_25_0
#define FUSE_SPARE_BIT_25_0                     _MK_ADDR_CONST(0x670)
#define FUSE_SPARE_BIT_25_0_SECURE                      0x0
#define FUSE_SPARE_BIT_25_0_DUAL                        0x0
#define FUSE_SPARE_BIT_25_0_SCR                         0
#define FUSE_SPARE_BIT_25_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_25_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_25_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_25_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_25_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_25_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_25_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_25_0_SPARE_BIT_25_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_25_0_SPARE_BIT_25_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_25_0_SPARE_BIT_25_SHIFT)
#define FUSE_SPARE_BIT_25_0_SPARE_BIT_25_RANGE                  0:0
#define FUSE_SPARE_BIT_25_0_SPARE_BIT_25_WOFFSET                        0x0
#define FUSE_SPARE_BIT_25_0_SPARE_BIT_25_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_25_0_SPARE_BIT_25_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_25_0_SPARE_BIT_25_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_25_0_SPARE_BIT_25_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_25_0_SPARE_BIT_25_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_25_0_SPARE_BIT_25_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_26_0
#define FUSE_SPARE_BIT_26_0                     _MK_ADDR_CONST(0x674)
#define FUSE_SPARE_BIT_26_0_SECURE                      0x0
#define FUSE_SPARE_BIT_26_0_DUAL                        0x0
#define FUSE_SPARE_BIT_26_0_SCR                         0
#define FUSE_SPARE_BIT_26_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_26_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_26_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_26_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_26_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_26_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_26_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_26_0_SPARE_BIT_26_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_26_0_SPARE_BIT_26_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_26_0_SPARE_BIT_26_SHIFT)
#define FUSE_SPARE_BIT_26_0_SPARE_BIT_26_RANGE                  0:0
#define FUSE_SPARE_BIT_26_0_SPARE_BIT_26_WOFFSET                        0x0
#define FUSE_SPARE_BIT_26_0_SPARE_BIT_26_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_26_0_SPARE_BIT_26_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_26_0_SPARE_BIT_26_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_26_0_SPARE_BIT_26_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_26_0_SPARE_BIT_26_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_26_0_SPARE_BIT_26_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_27_0
#define FUSE_SPARE_BIT_27_0                     _MK_ADDR_CONST(0x678)
#define FUSE_SPARE_BIT_27_0_SECURE                      0x0
#define FUSE_SPARE_BIT_27_0_DUAL                        0x0
#define FUSE_SPARE_BIT_27_0_SCR                         0
#define FUSE_SPARE_BIT_27_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_27_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_27_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_27_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_27_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_27_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_27_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_27_0_SPARE_BIT_27_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_27_0_SPARE_BIT_27_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_27_0_SPARE_BIT_27_SHIFT)
#define FUSE_SPARE_BIT_27_0_SPARE_BIT_27_RANGE                  0:0
#define FUSE_SPARE_BIT_27_0_SPARE_BIT_27_WOFFSET                        0x0
#define FUSE_SPARE_BIT_27_0_SPARE_BIT_27_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_27_0_SPARE_BIT_27_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_27_0_SPARE_BIT_27_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_27_0_SPARE_BIT_27_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_27_0_SPARE_BIT_27_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_27_0_SPARE_BIT_27_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_28_0
#define FUSE_SPARE_BIT_28_0                     _MK_ADDR_CONST(0x67c)
#define FUSE_SPARE_BIT_28_0_SECURE                      0x0
#define FUSE_SPARE_BIT_28_0_DUAL                        0x0
#define FUSE_SPARE_BIT_28_0_SCR                         0
#define FUSE_SPARE_BIT_28_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_28_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_28_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_28_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_28_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_28_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_28_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_28_0_SPARE_BIT_28_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_28_0_SPARE_BIT_28_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_28_0_SPARE_BIT_28_SHIFT)
#define FUSE_SPARE_BIT_28_0_SPARE_BIT_28_RANGE                  0:0
#define FUSE_SPARE_BIT_28_0_SPARE_BIT_28_WOFFSET                        0x0
#define FUSE_SPARE_BIT_28_0_SPARE_BIT_28_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_28_0_SPARE_BIT_28_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_28_0_SPARE_BIT_28_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_28_0_SPARE_BIT_28_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_28_0_SPARE_BIT_28_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_28_0_SPARE_BIT_28_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_29_0
#define FUSE_SPARE_BIT_29_0                     _MK_ADDR_CONST(0x680)
#define FUSE_SPARE_BIT_29_0_SECURE                      0x0
#define FUSE_SPARE_BIT_29_0_DUAL                        0x0
#define FUSE_SPARE_BIT_29_0_SCR                         0
#define FUSE_SPARE_BIT_29_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_29_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_29_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_29_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_29_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_29_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_29_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_29_0_SPARE_BIT_29_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_29_0_SPARE_BIT_29_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_29_0_SPARE_BIT_29_SHIFT)
#define FUSE_SPARE_BIT_29_0_SPARE_BIT_29_RANGE                  0:0
#define FUSE_SPARE_BIT_29_0_SPARE_BIT_29_WOFFSET                        0x0
#define FUSE_SPARE_BIT_29_0_SPARE_BIT_29_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_29_0_SPARE_BIT_29_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_29_0_SPARE_BIT_29_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_29_0_SPARE_BIT_29_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_29_0_SPARE_BIT_29_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_29_0_SPARE_BIT_29_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_30_0
#define FUSE_SPARE_BIT_30_0                     _MK_ADDR_CONST(0x684)
#define FUSE_SPARE_BIT_30_0_SECURE                      0x0
#define FUSE_SPARE_BIT_30_0_DUAL                        0x0
#define FUSE_SPARE_BIT_30_0_SCR                         0
#define FUSE_SPARE_BIT_30_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_30_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_30_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_30_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_30_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_30_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_30_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_30_0_SPARE_BIT_30_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_30_0_SPARE_BIT_30_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_30_0_SPARE_BIT_30_SHIFT)
#define FUSE_SPARE_BIT_30_0_SPARE_BIT_30_RANGE                  0:0
#define FUSE_SPARE_BIT_30_0_SPARE_BIT_30_WOFFSET                        0x0
#define FUSE_SPARE_BIT_30_0_SPARE_BIT_30_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_30_0_SPARE_BIT_30_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_30_0_SPARE_BIT_30_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_30_0_SPARE_BIT_30_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_30_0_SPARE_BIT_30_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_30_0_SPARE_BIT_30_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_31_0
#define FUSE_SPARE_BIT_31_0                     _MK_ADDR_CONST(0x688)
#define FUSE_SPARE_BIT_31_0_SECURE                      0x0
#define FUSE_SPARE_BIT_31_0_DUAL                        0x0
#define FUSE_SPARE_BIT_31_0_SCR                         0
#define FUSE_SPARE_BIT_31_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_31_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_31_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_31_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_31_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_31_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_31_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_31_0_SPARE_BIT_31_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_31_0_SPARE_BIT_31_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_31_0_SPARE_BIT_31_SHIFT)
#define FUSE_SPARE_BIT_31_0_SPARE_BIT_31_RANGE                  0:0
#define FUSE_SPARE_BIT_31_0_SPARE_BIT_31_WOFFSET                        0x0
#define FUSE_SPARE_BIT_31_0_SPARE_BIT_31_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_31_0_SPARE_BIT_31_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_31_0_SPARE_BIT_31_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_31_0_SPARE_BIT_31_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_31_0_SPARE_BIT_31_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_31_0_SPARE_BIT_31_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_32_0
#define FUSE_SPARE_BIT_32_0                     _MK_ADDR_CONST(0x68c)
#define FUSE_SPARE_BIT_32_0_SECURE                      0x0
#define FUSE_SPARE_BIT_32_0_DUAL                        0x0
#define FUSE_SPARE_BIT_32_0_SCR                         0
#define FUSE_SPARE_BIT_32_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_32_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_32_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_32_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_32_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_32_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_32_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_32_0_SPARE_BIT_32_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_32_0_SPARE_BIT_32_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_32_0_SPARE_BIT_32_SHIFT)
#define FUSE_SPARE_BIT_32_0_SPARE_BIT_32_RANGE                  0:0
#define FUSE_SPARE_BIT_32_0_SPARE_BIT_32_WOFFSET                        0x0
#define FUSE_SPARE_BIT_32_0_SPARE_BIT_32_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_32_0_SPARE_BIT_32_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_32_0_SPARE_BIT_32_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_32_0_SPARE_BIT_32_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_32_0_SPARE_BIT_32_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_32_0_SPARE_BIT_32_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_33_0
#define FUSE_SPARE_BIT_33_0                     _MK_ADDR_CONST(0x690)
#define FUSE_SPARE_BIT_33_0_SECURE                      0x0
#define FUSE_SPARE_BIT_33_0_DUAL                        0x0
#define FUSE_SPARE_BIT_33_0_SCR                         0
#define FUSE_SPARE_BIT_33_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_33_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_33_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_33_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_33_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_33_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_33_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_33_0_SPARE_BIT_33_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_33_0_SPARE_BIT_33_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_33_0_SPARE_BIT_33_SHIFT)
#define FUSE_SPARE_BIT_33_0_SPARE_BIT_33_RANGE                  0:0
#define FUSE_SPARE_BIT_33_0_SPARE_BIT_33_WOFFSET                        0x0
#define FUSE_SPARE_BIT_33_0_SPARE_BIT_33_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_33_0_SPARE_BIT_33_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_33_0_SPARE_BIT_33_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_33_0_SPARE_BIT_33_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_33_0_SPARE_BIT_33_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_33_0_SPARE_BIT_33_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_34_0
#define FUSE_SPARE_BIT_34_0                     _MK_ADDR_CONST(0x694)
#define FUSE_SPARE_BIT_34_0_SECURE                      0x0
#define FUSE_SPARE_BIT_34_0_DUAL                        0x0
#define FUSE_SPARE_BIT_34_0_SCR                         0
#define FUSE_SPARE_BIT_34_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_34_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_34_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_34_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_34_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_34_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_34_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_34_0_SPARE_BIT_34_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_34_0_SPARE_BIT_34_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_34_0_SPARE_BIT_34_SHIFT)
#define FUSE_SPARE_BIT_34_0_SPARE_BIT_34_RANGE                  0:0
#define FUSE_SPARE_BIT_34_0_SPARE_BIT_34_WOFFSET                        0x0
#define FUSE_SPARE_BIT_34_0_SPARE_BIT_34_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_34_0_SPARE_BIT_34_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_34_0_SPARE_BIT_34_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_34_0_SPARE_BIT_34_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_34_0_SPARE_BIT_34_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_34_0_SPARE_BIT_34_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_35_0
#define FUSE_SPARE_BIT_35_0                     _MK_ADDR_CONST(0x698)
#define FUSE_SPARE_BIT_35_0_SECURE                      0x0
#define FUSE_SPARE_BIT_35_0_DUAL                        0x0
#define FUSE_SPARE_BIT_35_0_SCR                         0
#define FUSE_SPARE_BIT_35_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_35_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_35_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_35_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_35_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_35_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_35_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_35_0_SPARE_BIT_35_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_35_0_SPARE_BIT_35_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_35_0_SPARE_BIT_35_SHIFT)
#define FUSE_SPARE_BIT_35_0_SPARE_BIT_35_RANGE                  0:0
#define FUSE_SPARE_BIT_35_0_SPARE_BIT_35_WOFFSET                        0x0
#define FUSE_SPARE_BIT_35_0_SPARE_BIT_35_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_35_0_SPARE_BIT_35_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_35_0_SPARE_BIT_35_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_35_0_SPARE_BIT_35_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_35_0_SPARE_BIT_35_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_35_0_SPARE_BIT_35_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_36_0
#define FUSE_SPARE_BIT_36_0                     _MK_ADDR_CONST(0x69c)
#define FUSE_SPARE_BIT_36_0_SECURE                      0x0
#define FUSE_SPARE_BIT_36_0_DUAL                        0x0
#define FUSE_SPARE_BIT_36_0_SCR                         0
#define FUSE_SPARE_BIT_36_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_36_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_36_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_36_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_36_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_36_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_36_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_36_0_SPARE_BIT_36_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_36_0_SPARE_BIT_36_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_36_0_SPARE_BIT_36_SHIFT)
#define FUSE_SPARE_BIT_36_0_SPARE_BIT_36_RANGE                  0:0
#define FUSE_SPARE_BIT_36_0_SPARE_BIT_36_WOFFSET                        0x0
#define FUSE_SPARE_BIT_36_0_SPARE_BIT_36_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_36_0_SPARE_BIT_36_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_36_0_SPARE_BIT_36_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_36_0_SPARE_BIT_36_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_36_0_SPARE_BIT_36_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_36_0_SPARE_BIT_36_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_37_0
#define FUSE_SPARE_BIT_37_0                     _MK_ADDR_CONST(0x6a0)
#define FUSE_SPARE_BIT_37_0_SECURE                      0x0
#define FUSE_SPARE_BIT_37_0_DUAL                        0x0
#define FUSE_SPARE_BIT_37_0_SCR                         0
#define FUSE_SPARE_BIT_37_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_37_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_37_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_37_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_37_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_37_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_37_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_37_0_SPARE_BIT_37_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_37_0_SPARE_BIT_37_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_37_0_SPARE_BIT_37_SHIFT)
#define FUSE_SPARE_BIT_37_0_SPARE_BIT_37_RANGE                  0:0
#define FUSE_SPARE_BIT_37_0_SPARE_BIT_37_WOFFSET                        0x0
#define FUSE_SPARE_BIT_37_0_SPARE_BIT_37_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_37_0_SPARE_BIT_37_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_37_0_SPARE_BIT_37_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_37_0_SPARE_BIT_37_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_37_0_SPARE_BIT_37_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_37_0_SPARE_BIT_37_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_38_0
#define FUSE_SPARE_BIT_38_0                     _MK_ADDR_CONST(0x6a4)
#define FUSE_SPARE_BIT_38_0_SECURE                      0x0
#define FUSE_SPARE_BIT_38_0_DUAL                        0x0
#define FUSE_SPARE_BIT_38_0_SCR                         0
#define FUSE_SPARE_BIT_38_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_38_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_38_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_38_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_38_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_38_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_38_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_38_0_SPARE_BIT_38_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_38_0_SPARE_BIT_38_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_38_0_SPARE_BIT_38_SHIFT)
#define FUSE_SPARE_BIT_38_0_SPARE_BIT_38_RANGE                  0:0
#define FUSE_SPARE_BIT_38_0_SPARE_BIT_38_WOFFSET                        0x0
#define FUSE_SPARE_BIT_38_0_SPARE_BIT_38_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_38_0_SPARE_BIT_38_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_38_0_SPARE_BIT_38_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_38_0_SPARE_BIT_38_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_38_0_SPARE_BIT_38_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_38_0_SPARE_BIT_38_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_39_0
#define FUSE_SPARE_BIT_39_0                     _MK_ADDR_CONST(0x6a8)
#define FUSE_SPARE_BIT_39_0_SECURE                      0x0
#define FUSE_SPARE_BIT_39_0_DUAL                        0x0
#define FUSE_SPARE_BIT_39_0_SCR                         0
#define FUSE_SPARE_BIT_39_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_39_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_39_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_39_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_39_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_39_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_39_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_39_0_SPARE_BIT_39_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_39_0_SPARE_BIT_39_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_39_0_SPARE_BIT_39_SHIFT)
#define FUSE_SPARE_BIT_39_0_SPARE_BIT_39_RANGE                  0:0
#define FUSE_SPARE_BIT_39_0_SPARE_BIT_39_WOFFSET                        0x0
#define FUSE_SPARE_BIT_39_0_SPARE_BIT_39_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_39_0_SPARE_BIT_39_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_39_0_SPARE_BIT_39_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_39_0_SPARE_BIT_39_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_39_0_SPARE_BIT_39_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_39_0_SPARE_BIT_39_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_40_0
#define FUSE_SPARE_BIT_40_0                     _MK_ADDR_CONST(0x6ac)
#define FUSE_SPARE_BIT_40_0_SECURE                      0x0
#define FUSE_SPARE_BIT_40_0_DUAL                        0x0
#define FUSE_SPARE_BIT_40_0_SCR                         0
#define FUSE_SPARE_BIT_40_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_40_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_40_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_40_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_40_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_40_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_40_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_40_0_SPARE_BIT_40_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_40_0_SPARE_BIT_40_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_40_0_SPARE_BIT_40_SHIFT)
#define FUSE_SPARE_BIT_40_0_SPARE_BIT_40_RANGE                  0:0
#define FUSE_SPARE_BIT_40_0_SPARE_BIT_40_WOFFSET                        0x0
#define FUSE_SPARE_BIT_40_0_SPARE_BIT_40_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_40_0_SPARE_BIT_40_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_40_0_SPARE_BIT_40_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_40_0_SPARE_BIT_40_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_40_0_SPARE_BIT_40_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_40_0_SPARE_BIT_40_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_41_0
#define FUSE_SPARE_BIT_41_0                     _MK_ADDR_CONST(0x6b0)
#define FUSE_SPARE_BIT_41_0_SECURE                      0x0
#define FUSE_SPARE_BIT_41_0_DUAL                        0x0
#define FUSE_SPARE_BIT_41_0_SCR                         0
#define FUSE_SPARE_BIT_41_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_41_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_41_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_41_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_41_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_41_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_41_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_41_0_SPARE_BIT_41_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_41_0_SPARE_BIT_41_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_41_0_SPARE_BIT_41_SHIFT)
#define FUSE_SPARE_BIT_41_0_SPARE_BIT_41_RANGE                  0:0
#define FUSE_SPARE_BIT_41_0_SPARE_BIT_41_WOFFSET                        0x0
#define FUSE_SPARE_BIT_41_0_SPARE_BIT_41_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_41_0_SPARE_BIT_41_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_41_0_SPARE_BIT_41_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_41_0_SPARE_BIT_41_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_41_0_SPARE_BIT_41_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_41_0_SPARE_BIT_41_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_42_0
#define FUSE_SPARE_BIT_42_0                     _MK_ADDR_CONST(0x6b4)
#define FUSE_SPARE_BIT_42_0_SECURE                      0x0
#define FUSE_SPARE_BIT_42_0_DUAL                        0x0
#define FUSE_SPARE_BIT_42_0_SCR                         0
#define FUSE_SPARE_BIT_42_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_42_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_42_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_42_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_42_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_42_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_42_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_42_0_SPARE_BIT_42_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_42_0_SPARE_BIT_42_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_42_0_SPARE_BIT_42_SHIFT)
#define FUSE_SPARE_BIT_42_0_SPARE_BIT_42_RANGE                  0:0
#define FUSE_SPARE_BIT_42_0_SPARE_BIT_42_WOFFSET                        0x0
#define FUSE_SPARE_BIT_42_0_SPARE_BIT_42_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_42_0_SPARE_BIT_42_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_42_0_SPARE_BIT_42_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_42_0_SPARE_BIT_42_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_42_0_SPARE_BIT_42_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_42_0_SPARE_BIT_42_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_43_0
#define FUSE_SPARE_BIT_43_0                     _MK_ADDR_CONST(0x6b8)
#define FUSE_SPARE_BIT_43_0_SECURE                      0x0
#define FUSE_SPARE_BIT_43_0_DUAL                        0x0
#define FUSE_SPARE_BIT_43_0_SCR                         0
#define FUSE_SPARE_BIT_43_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_43_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_43_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_43_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_43_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_43_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_43_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_43_0_SPARE_BIT_43_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_43_0_SPARE_BIT_43_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_43_0_SPARE_BIT_43_SHIFT)
#define FUSE_SPARE_BIT_43_0_SPARE_BIT_43_RANGE                  0:0
#define FUSE_SPARE_BIT_43_0_SPARE_BIT_43_WOFFSET                        0x0
#define FUSE_SPARE_BIT_43_0_SPARE_BIT_43_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_43_0_SPARE_BIT_43_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_43_0_SPARE_BIT_43_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_43_0_SPARE_BIT_43_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_43_0_SPARE_BIT_43_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_43_0_SPARE_BIT_43_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_44_0
#define FUSE_SPARE_BIT_44_0                     _MK_ADDR_CONST(0x6bc)
#define FUSE_SPARE_BIT_44_0_SECURE                      0x0
#define FUSE_SPARE_BIT_44_0_DUAL                        0x0
#define FUSE_SPARE_BIT_44_0_SCR                         0
#define FUSE_SPARE_BIT_44_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_44_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_44_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_44_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_44_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_44_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_44_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_44_0_SPARE_BIT_44_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_44_0_SPARE_BIT_44_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_44_0_SPARE_BIT_44_SHIFT)
#define FUSE_SPARE_BIT_44_0_SPARE_BIT_44_RANGE                  0:0
#define FUSE_SPARE_BIT_44_0_SPARE_BIT_44_WOFFSET                        0x0
#define FUSE_SPARE_BIT_44_0_SPARE_BIT_44_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_44_0_SPARE_BIT_44_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_44_0_SPARE_BIT_44_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_44_0_SPARE_BIT_44_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_44_0_SPARE_BIT_44_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_44_0_SPARE_BIT_44_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_45_0
#define FUSE_SPARE_BIT_45_0                     _MK_ADDR_CONST(0x6c0)
#define FUSE_SPARE_BIT_45_0_SECURE                      0x0
#define FUSE_SPARE_BIT_45_0_DUAL                        0x0
#define FUSE_SPARE_BIT_45_0_SCR                         0
#define FUSE_SPARE_BIT_45_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_45_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_45_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_45_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_45_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_45_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_45_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_45_0_SPARE_BIT_45_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_45_0_SPARE_BIT_45_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_45_0_SPARE_BIT_45_SHIFT)
#define FUSE_SPARE_BIT_45_0_SPARE_BIT_45_RANGE                  0:0
#define FUSE_SPARE_BIT_45_0_SPARE_BIT_45_WOFFSET                        0x0
#define FUSE_SPARE_BIT_45_0_SPARE_BIT_45_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_45_0_SPARE_BIT_45_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_45_0_SPARE_BIT_45_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_45_0_SPARE_BIT_45_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_45_0_SPARE_BIT_45_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_45_0_SPARE_BIT_45_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_46_0
#define FUSE_SPARE_BIT_46_0                     _MK_ADDR_CONST(0x6c4)
#define FUSE_SPARE_BIT_46_0_SECURE                      0x0
#define FUSE_SPARE_BIT_46_0_DUAL                        0x0
#define FUSE_SPARE_BIT_46_0_SCR                         0
#define FUSE_SPARE_BIT_46_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_46_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_46_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_46_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_46_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_46_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_46_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_46_0_SPARE_BIT_46_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_46_0_SPARE_BIT_46_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_46_0_SPARE_BIT_46_SHIFT)
#define FUSE_SPARE_BIT_46_0_SPARE_BIT_46_RANGE                  0:0
#define FUSE_SPARE_BIT_46_0_SPARE_BIT_46_WOFFSET                        0x0
#define FUSE_SPARE_BIT_46_0_SPARE_BIT_46_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_46_0_SPARE_BIT_46_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_46_0_SPARE_BIT_46_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_46_0_SPARE_BIT_46_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_46_0_SPARE_BIT_46_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_46_0_SPARE_BIT_46_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_47_0
#define FUSE_SPARE_BIT_47_0                     _MK_ADDR_CONST(0x6c8)
#define FUSE_SPARE_BIT_47_0_SECURE                      0x0
#define FUSE_SPARE_BIT_47_0_DUAL                        0x0
#define FUSE_SPARE_BIT_47_0_SCR                         0
#define FUSE_SPARE_BIT_47_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_47_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_47_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_47_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_47_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_47_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_47_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_47_0_SPARE_BIT_47_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_47_0_SPARE_BIT_47_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_47_0_SPARE_BIT_47_SHIFT)
#define FUSE_SPARE_BIT_47_0_SPARE_BIT_47_RANGE                  0:0
#define FUSE_SPARE_BIT_47_0_SPARE_BIT_47_WOFFSET                        0x0
#define FUSE_SPARE_BIT_47_0_SPARE_BIT_47_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_47_0_SPARE_BIT_47_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_47_0_SPARE_BIT_47_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_47_0_SPARE_BIT_47_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_47_0_SPARE_BIT_47_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_47_0_SPARE_BIT_47_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_48_0
#define FUSE_SPARE_BIT_48_0                     _MK_ADDR_CONST(0x6cc)
#define FUSE_SPARE_BIT_48_0_SECURE                      0x0
#define FUSE_SPARE_BIT_48_0_DUAL                        0x0
#define FUSE_SPARE_BIT_48_0_SCR                         0
#define FUSE_SPARE_BIT_48_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_48_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_48_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_48_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_48_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_48_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_48_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_48_0_SPARE_BIT_48_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_48_0_SPARE_BIT_48_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_48_0_SPARE_BIT_48_SHIFT)
#define FUSE_SPARE_BIT_48_0_SPARE_BIT_48_RANGE                  0:0
#define FUSE_SPARE_BIT_48_0_SPARE_BIT_48_WOFFSET                        0x0
#define FUSE_SPARE_BIT_48_0_SPARE_BIT_48_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_48_0_SPARE_BIT_48_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_48_0_SPARE_BIT_48_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_48_0_SPARE_BIT_48_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_48_0_SPARE_BIT_48_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_48_0_SPARE_BIT_48_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_49_0
#define FUSE_SPARE_BIT_49_0                     _MK_ADDR_CONST(0x6d0)
#define FUSE_SPARE_BIT_49_0_SECURE                      0x0
#define FUSE_SPARE_BIT_49_0_DUAL                        0x0
#define FUSE_SPARE_BIT_49_0_SCR                         0
#define FUSE_SPARE_BIT_49_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_49_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_49_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_49_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_49_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_49_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_49_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_49_0_SPARE_BIT_49_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_49_0_SPARE_BIT_49_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_49_0_SPARE_BIT_49_SHIFT)
#define FUSE_SPARE_BIT_49_0_SPARE_BIT_49_RANGE                  0:0
#define FUSE_SPARE_BIT_49_0_SPARE_BIT_49_WOFFSET                        0x0
#define FUSE_SPARE_BIT_49_0_SPARE_BIT_49_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_49_0_SPARE_BIT_49_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_49_0_SPARE_BIT_49_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_49_0_SPARE_BIT_49_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_49_0_SPARE_BIT_49_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_49_0_SPARE_BIT_49_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_50_0
#define FUSE_SPARE_BIT_50_0                     _MK_ADDR_CONST(0x6d4)
#define FUSE_SPARE_BIT_50_0_SECURE                      0x0
#define FUSE_SPARE_BIT_50_0_DUAL                        0x0
#define FUSE_SPARE_BIT_50_0_SCR                         0
#define FUSE_SPARE_BIT_50_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_50_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_50_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_50_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_50_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_50_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_50_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_50_0_SPARE_BIT_50_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_50_0_SPARE_BIT_50_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_50_0_SPARE_BIT_50_SHIFT)
#define FUSE_SPARE_BIT_50_0_SPARE_BIT_50_RANGE                  0:0
#define FUSE_SPARE_BIT_50_0_SPARE_BIT_50_WOFFSET                        0x0
#define FUSE_SPARE_BIT_50_0_SPARE_BIT_50_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_50_0_SPARE_BIT_50_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_50_0_SPARE_BIT_50_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_50_0_SPARE_BIT_50_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_50_0_SPARE_BIT_50_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_50_0_SPARE_BIT_50_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_51_0
#define FUSE_SPARE_BIT_51_0                     _MK_ADDR_CONST(0x6d8)
#define FUSE_SPARE_BIT_51_0_SECURE                      0x0
#define FUSE_SPARE_BIT_51_0_DUAL                        0x0
#define FUSE_SPARE_BIT_51_0_SCR                         0
#define FUSE_SPARE_BIT_51_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_51_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_51_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_51_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_51_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_51_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_51_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_51_0_SPARE_BIT_51_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_51_0_SPARE_BIT_51_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_51_0_SPARE_BIT_51_SHIFT)
#define FUSE_SPARE_BIT_51_0_SPARE_BIT_51_RANGE                  0:0
#define FUSE_SPARE_BIT_51_0_SPARE_BIT_51_WOFFSET                        0x0
#define FUSE_SPARE_BIT_51_0_SPARE_BIT_51_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_51_0_SPARE_BIT_51_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_51_0_SPARE_BIT_51_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_51_0_SPARE_BIT_51_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_51_0_SPARE_BIT_51_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_51_0_SPARE_BIT_51_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_52_0
#define FUSE_SPARE_BIT_52_0                     _MK_ADDR_CONST(0x6dc)
#define FUSE_SPARE_BIT_52_0_SECURE                      0x0
#define FUSE_SPARE_BIT_52_0_DUAL                        0x0
#define FUSE_SPARE_BIT_52_0_SCR                         0
#define FUSE_SPARE_BIT_52_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_52_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_52_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_52_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_52_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_52_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_52_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_52_0_SPARE_BIT_52_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_52_0_SPARE_BIT_52_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_52_0_SPARE_BIT_52_SHIFT)
#define FUSE_SPARE_BIT_52_0_SPARE_BIT_52_RANGE                  0:0
#define FUSE_SPARE_BIT_52_0_SPARE_BIT_52_WOFFSET                        0x0
#define FUSE_SPARE_BIT_52_0_SPARE_BIT_52_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_52_0_SPARE_BIT_52_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_52_0_SPARE_BIT_52_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_52_0_SPARE_BIT_52_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_52_0_SPARE_BIT_52_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_52_0_SPARE_BIT_52_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_53_0
#define FUSE_SPARE_BIT_53_0                     _MK_ADDR_CONST(0x6e0)
#define FUSE_SPARE_BIT_53_0_SECURE                      0x0
#define FUSE_SPARE_BIT_53_0_DUAL                        0x0
#define FUSE_SPARE_BIT_53_0_SCR                         0
#define FUSE_SPARE_BIT_53_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_53_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_53_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_53_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_53_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_53_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_53_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_53_0_SPARE_BIT_53_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_53_0_SPARE_BIT_53_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_53_0_SPARE_BIT_53_SHIFT)
#define FUSE_SPARE_BIT_53_0_SPARE_BIT_53_RANGE                  0:0
#define FUSE_SPARE_BIT_53_0_SPARE_BIT_53_WOFFSET                        0x0
#define FUSE_SPARE_BIT_53_0_SPARE_BIT_53_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_53_0_SPARE_BIT_53_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_53_0_SPARE_BIT_53_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_53_0_SPARE_BIT_53_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_53_0_SPARE_BIT_53_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_53_0_SPARE_BIT_53_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_54_0
#define FUSE_SPARE_BIT_54_0                     _MK_ADDR_CONST(0x6e4)
#define FUSE_SPARE_BIT_54_0_SECURE                      0x0
#define FUSE_SPARE_BIT_54_0_DUAL                        0x0
#define FUSE_SPARE_BIT_54_0_SCR                         0
#define FUSE_SPARE_BIT_54_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_54_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_54_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_54_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_54_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_54_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_54_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_54_0_SPARE_BIT_54_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_54_0_SPARE_BIT_54_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_54_0_SPARE_BIT_54_SHIFT)
#define FUSE_SPARE_BIT_54_0_SPARE_BIT_54_RANGE                  0:0
#define FUSE_SPARE_BIT_54_0_SPARE_BIT_54_WOFFSET                        0x0
#define FUSE_SPARE_BIT_54_0_SPARE_BIT_54_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_54_0_SPARE_BIT_54_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_54_0_SPARE_BIT_54_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_54_0_SPARE_BIT_54_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_54_0_SPARE_BIT_54_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_54_0_SPARE_BIT_54_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_55_0
#define FUSE_SPARE_BIT_55_0                     _MK_ADDR_CONST(0x6e8)
#define FUSE_SPARE_BIT_55_0_SECURE                      0x0
#define FUSE_SPARE_BIT_55_0_DUAL                        0x0
#define FUSE_SPARE_BIT_55_0_SCR                         0
#define FUSE_SPARE_BIT_55_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_55_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_55_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_55_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_55_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_55_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_55_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_55_0_SPARE_BIT_55_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_55_0_SPARE_BIT_55_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_55_0_SPARE_BIT_55_SHIFT)
#define FUSE_SPARE_BIT_55_0_SPARE_BIT_55_RANGE                  0:0
#define FUSE_SPARE_BIT_55_0_SPARE_BIT_55_WOFFSET                        0x0
#define FUSE_SPARE_BIT_55_0_SPARE_BIT_55_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_55_0_SPARE_BIT_55_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_55_0_SPARE_BIT_55_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_55_0_SPARE_BIT_55_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_55_0_SPARE_BIT_55_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_55_0_SPARE_BIT_55_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_56_0
#define FUSE_SPARE_BIT_56_0                     _MK_ADDR_CONST(0x6ec)
#define FUSE_SPARE_BIT_56_0_SECURE                      0x0
#define FUSE_SPARE_BIT_56_0_DUAL                        0x0
#define FUSE_SPARE_BIT_56_0_SCR                         0
#define FUSE_SPARE_BIT_56_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_56_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_56_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_56_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_56_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_56_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_56_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_56_0_SPARE_BIT_56_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_56_0_SPARE_BIT_56_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_56_0_SPARE_BIT_56_SHIFT)
#define FUSE_SPARE_BIT_56_0_SPARE_BIT_56_RANGE                  0:0
#define FUSE_SPARE_BIT_56_0_SPARE_BIT_56_WOFFSET                        0x0
#define FUSE_SPARE_BIT_56_0_SPARE_BIT_56_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_56_0_SPARE_BIT_56_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_56_0_SPARE_BIT_56_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_56_0_SPARE_BIT_56_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_56_0_SPARE_BIT_56_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_56_0_SPARE_BIT_56_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_57_0
#define FUSE_SPARE_BIT_57_0                     _MK_ADDR_CONST(0x6f0)
#define FUSE_SPARE_BIT_57_0_SECURE                      0x0
#define FUSE_SPARE_BIT_57_0_DUAL                        0x0
#define FUSE_SPARE_BIT_57_0_SCR                         0
#define FUSE_SPARE_BIT_57_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_57_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_57_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_57_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_57_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_57_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_57_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_57_0_SPARE_BIT_57_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_57_0_SPARE_BIT_57_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_57_0_SPARE_BIT_57_SHIFT)
#define FUSE_SPARE_BIT_57_0_SPARE_BIT_57_RANGE                  0:0
#define FUSE_SPARE_BIT_57_0_SPARE_BIT_57_WOFFSET                        0x0
#define FUSE_SPARE_BIT_57_0_SPARE_BIT_57_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_57_0_SPARE_BIT_57_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_57_0_SPARE_BIT_57_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_57_0_SPARE_BIT_57_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_57_0_SPARE_BIT_57_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_57_0_SPARE_BIT_57_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_58_0
#define FUSE_SPARE_BIT_58_0                     _MK_ADDR_CONST(0x6f4)
#define FUSE_SPARE_BIT_58_0_SECURE                      0x0
#define FUSE_SPARE_BIT_58_0_DUAL                        0x0
#define FUSE_SPARE_BIT_58_0_SCR                         0
#define FUSE_SPARE_BIT_58_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_58_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_58_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_58_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_58_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_58_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_58_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_58_0_SPARE_BIT_58_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_58_0_SPARE_BIT_58_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_58_0_SPARE_BIT_58_SHIFT)
#define FUSE_SPARE_BIT_58_0_SPARE_BIT_58_RANGE                  0:0
#define FUSE_SPARE_BIT_58_0_SPARE_BIT_58_WOFFSET                        0x0
#define FUSE_SPARE_BIT_58_0_SPARE_BIT_58_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_58_0_SPARE_BIT_58_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_58_0_SPARE_BIT_58_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_58_0_SPARE_BIT_58_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_58_0_SPARE_BIT_58_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_58_0_SPARE_BIT_58_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_59_0
#define FUSE_SPARE_BIT_59_0                     _MK_ADDR_CONST(0x6f8)
#define FUSE_SPARE_BIT_59_0_SECURE                      0x0
#define FUSE_SPARE_BIT_59_0_DUAL                        0x0
#define FUSE_SPARE_BIT_59_0_SCR                         0
#define FUSE_SPARE_BIT_59_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_59_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_59_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_59_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_59_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_59_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_59_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_59_0_SPARE_BIT_59_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_59_0_SPARE_BIT_59_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_59_0_SPARE_BIT_59_SHIFT)
#define FUSE_SPARE_BIT_59_0_SPARE_BIT_59_RANGE                  0:0
#define FUSE_SPARE_BIT_59_0_SPARE_BIT_59_WOFFSET                        0x0
#define FUSE_SPARE_BIT_59_0_SPARE_BIT_59_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_59_0_SPARE_BIT_59_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_59_0_SPARE_BIT_59_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_59_0_SPARE_BIT_59_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_59_0_SPARE_BIT_59_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_59_0_SPARE_BIT_59_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_60_0
#define FUSE_SPARE_BIT_60_0                     _MK_ADDR_CONST(0x6fc)
#define FUSE_SPARE_BIT_60_0_SECURE                      0x0
#define FUSE_SPARE_BIT_60_0_DUAL                        0x0
#define FUSE_SPARE_BIT_60_0_SCR                         0
#define FUSE_SPARE_BIT_60_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_60_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_60_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_60_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_60_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_60_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_60_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_60_0_SPARE_BIT_60_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_60_0_SPARE_BIT_60_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_60_0_SPARE_BIT_60_SHIFT)
#define FUSE_SPARE_BIT_60_0_SPARE_BIT_60_RANGE                  0:0
#define FUSE_SPARE_BIT_60_0_SPARE_BIT_60_WOFFSET                        0x0
#define FUSE_SPARE_BIT_60_0_SPARE_BIT_60_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_60_0_SPARE_BIT_60_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_60_0_SPARE_BIT_60_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_60_0_SPARE_BIT_60_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_60_0_SPARE_BIT_60_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_60_0_SPARE_BIT_60_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_61_0
#define FUSE_SPARE_BIT_61_0                     _MK_ADDR_CONST(0x700)
#define FUSE_SPARE_BIT_61_0_SECURE                      0x0
#define FUSE_SPARE_BIT_61_0_DUAL                        0x0
#define FUSE_SPARE_BIT_61_0_SCR                         0
#define FUSE_SPARE_BIT_61_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_61_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_61_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_61_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_61_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_61_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_61_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_61_0_SPARE_BIT_61_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_61_0_SPARE_BIT_61_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_61_0_SPARE_BIT_61_SHIFT)
#define FUSE_SPARE_BIT_61_0_SPARE_BIT_61_RANGE                  0:0
#define FUSE_SPARE_BIT_61_0_SPARE_BIT_61_WOFFSET                        0x0
#define FUSE_SPARE_BIT_61_0_SPARE_BIT_61_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_61_0_SPARE_BIT_61_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_61_0_SPARE_BIT_61_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_61_0_SPARE_BIT_61_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_61_0_SPARE_BIT_61_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_61_0_SPARE_BIT_61_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_62_0
#define FUSE_SPARE_BIT_62_0                     _MK_ADDR_CONST(0x704)
#define FUSE_SPARE_BIT_62_0_SECURE                      0x0
#define FUSE_SPARE_BIT_62_0_DUAL                        0x0
#define FUSE_SPARE_BIT_62_0_SCR                         0
#define FUSE_SPARE_BIT_62_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_62_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_62_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_62_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_62_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_62_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_62_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_62_0_SPARE_BIT_62_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_62_0_SPARE_BIT_62_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_62_0_SPARE_BIT_62_SHIFT)
#define FUSE_SPARE_BIT_62_0_SPARE_BIT_62_RANGE                  0:0
#define FUSE_SPARE_BIT_62_0_SPARE_BIT_62_WOFFSET                        0x0
#define FUSE_SPARE_BIT_62_0_SPARE_BIT_62_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_62_0_SPARE_BIT_62_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_62_0_SPARE_BIT_62_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_62_0_SPARE_BIT_62_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_62_0_SPARE_BIT_62_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_62_0_SPARE_BIT_62_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_63_0
#define FUSE_SPARE_BIT_63_0                     _MK_ADDR_CONST(0x708)
#define FUSE_SPARE_BIT_63_0_SECURE                      0x0
#define FUSE_SPARE_BIT_63_0_DUAL                        0x0
#define FUSE_SPARE_BIT_63_0_SCR                         0
#define FUSE_SPARE_BIT_63_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_63_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_63_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_63_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_63_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_63_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_63_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_63_0_SPARE_BIT_63_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_63_0_SPARE_BIT_63_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_63_0_SPARE_BIT_63_SHIFT)
#define FUSE_SPARE_BIT_63_0_SPARE_BIT_63_RANGE                  0:0
#define FUSE_SPARE_BIT_63_0_SPARE_BIT_63_WOFFSET                        0x0
#define FUSE_SPARE_BIT_63_0_SPARE_BIT_63_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_63_0_SPARE_BIT_63_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_63_0_SPARE_BIT_63_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_63_0_SPARE_BIT_63_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_63_0_SPARE_BIT_63_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_63_0_SPARE_BIT_63_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_64_0
#define FUSE_SPARE_BIT_64_0                     _MK_ADDR_CONST(0x70c)
#define FUSE_SPARE_BIT_64_0_SECURE                      0x0
#define FUSE_SPARE_BIT_64_0_DUAL                        0x0
#define FUSE_SPARE_BIT_64_0_SCR                         0
#define FUSE_SPARE_BIT_64_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_64_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_64_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_64_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_64_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_64_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_64_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_64_0_SPARE_BIT_64_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_64_0_SPARE_BIT_64_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_64_0_SPARE_BIT_64_SHIFT)
#define FUSE_SPARE_BIT_64_0_SPARE_BIT_64_RANGE                  0:0
#define FUSE_SPARE_BIT_64_0_SPARE_BIT_64_WOFFSET                        0x0
#define FUSE_SPARE_BIT_64_0_SPARE_BIT_64_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_64_0_SPARE_BIT_64_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_64_0_SPARE_BIT_64_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_64_0_SPARE_BIT_64_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_64_0_SPARE_BIT_64_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_64_0_SPARE_BIT_64_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_65_0
#define FUSE_SPARE_BIT_65_0                     _MK_ADDR_CONST(0x710)
#define FUSE_SPARE_BIT_65_0_SECURE                      0x0
#define FUSE_SPARE_BIT_65_0_DUAL                        0x0
#define FUSE_SPARE_BIT_65_0_SCR                         0
#define FUSE_SPARE_BIT_65_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_65_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_65_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_65_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_65_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_65_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_65_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_65_0_SPARE_BIT_65_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_65_0_SPARE_BIT_65_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_65_0_SPARE_BIT_65_SHIFT)
#define FUSE_SPARE_BIT_65_0_SPARE_BIT_65_RANGE                  0:0
#define FUSE_SPARE_BIT_65_0_SPARE_BIT_65_WOFFSET                        0x0
#define FUSE_SPARE_BIT_65_0_SPARE_BIT_65_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_65_0_SPARE_BIT_65_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_65_0_SPARE_BIT_65_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_65_0_SPARE_BIT_65_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_65_0_SPARE_BIT_65_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_65_0_SPARE_BIT_65_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_66_0
#define FUSE_SPARE_BIT_66_0                     _MK_ADDR_CONST(0x714)
#define FUSE_SPARE_BIT_66_0_SECURE                      0x0
#define FUSE_SPARE_BIT_66_0_DUAL                        0x0
#define FUSE_SPARE_BIT_66_0_SCR                         0
#define FUSE_SPARE_BIT_66_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_66_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_66_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_66_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_66_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_66_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_66_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_66_0_SPARE_BIT_66_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_66_0_SPARE_BIT_66_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_66_0_SPARE_BIT_66_SHIFT)
#define FUSE_SPARE_BIT_66_0_SPARE_BIT_66_RANGE                  0:0
#define FUSE_SPARE_BIT_66_0_SPARE_BIT_66_WOFFSET                        0x0
#define FUSE_SPARE_BIT_66_0_SPARE_BIT_66_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_66_0_SPARE_BIT_66_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_66_0_SPARE_BIT_66_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_66_0_SPARE_BIT_66_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_66_0_SPARE_BIT_66_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_66_0_SPARE_BIT_66_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_67_0
#define FUSE_SPARE_BIT_67_0                     _MK_ADDR_CONST(0x718)
#define FUSE_SPARE_BIT_67_0_SECURE                      0x0
#define FUSE_SPARE_BIT_67_0_DUAL                        0x0
#define FUSE_SPARE_BIT_67_0_SCR                         0
#define FUSE_SPARE_BIT_67_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_67_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_67_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_67_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_67_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_67_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_67_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_67_0_SPARE_BIT_67_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_67_0_SPARE_BIT_67_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_67_0_SPARE_BIT_67_SHIFT)
#define FUSE_SPARE_BIT_67_0_SPARE_BIT_67_RANGE                  0:0
#define FUSE_SPARE_BIT_67_0_SPARE_BIT_67_WOFFSET                        0x0
#define FUSE_SPARE_BIT_67_0_SPARE_BIT_67_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_67_0_SPARE_BIT_67_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_67_0_SPARE_BIT_67_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_67_0_SPARE_BIT_67_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_67_0_SPARE_BIT_67_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_67_0_SPARE_BIT_67_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_68_0
#define FUSE_SPARE_BIT_68_0                     _MK_ADDR_CONST(0x71c)
#define FUSE_SPARE_BIT_68_0_SECURE                      0x0
#define FUSE_SPARE_BIT_68_0_DUAL                        0x0
#define FUSE_SPARE_BIT_68_0_SCR                         0
#define FUSE_SPARE_BIT_68_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_68_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_68_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_68_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_68_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_68_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_68_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_68_0_SPARE_BIT_68_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_68_0_SPARE_BIT_68_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_68_0_SPARE_BIT_68_SHIFT)
#define FUSE_SPARE_BIT_68_0_SPARE_BIT_68_RANGE                  0:0
#define FUSE_SPARE_BIT_68_0_SPARE_BIT_68_WOFFSET                        0x0
#define FUSE_SPARE_BIT_68_0_SPARE_BIT_68_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_68_0_SPARE_BIT_68_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_68_0_SPARE_BIT_68_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_68_0_SPARE_BIT_68_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_68_0_SPARE_BIT_68_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_68_0_SPARE_BIT_68_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_69_0
#define FUSE_SPARE_BIT_69_0                     _MK_ADDR_CONST(0x720)
#define FUSE_SPARE_BIT_69_0_SECURE                      0x0
#define FUSE_SPARE_BIT_69_0_DUAL                        0x0
#define FUSE_SPARE_BIT_69_0_SCR                         0
#define FUSE_SPARE_BIT_69_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_69_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_69_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_69_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_69_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_69_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_69_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_69_0_SPARE_BIT_69_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_69_0_SPARE_BIT_69_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_69_0_SPARE_BIT_69_SHIFT)
#define FUSE_SPARE_BIT_69_0_SPARE_BIT_69_RANGE                  0:0
#define FUSE_SPARE_BIT_69_0_SPARE_BIT_69_WOFFSET                        0x0
#define FUSE_SPARE_BIT_69_0_SPARE_BIT_69_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_69_0_SPARE_BIT_69_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_69_0_SPARE_BIT_69_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_69_0_SPARE_BIT_69_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_69_0_SPARE_BIT_69_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_69_0_SPARE_BIT_69_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_70_0
#define FUSE_SPARE_BIT_70_0                     _MK_ADDR_CONST(0x724)
#define FUSE_SPARE_BIT_70_0_SECURE                      0x0
#define FUSE_SPARE_BIT_70_0_DUAL                        0x0
#define FUSE_SPARE_BIT_70_0_SCR                         0
#define FUSE_SPARE_BIT_70_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_70_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_70_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_70_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_70_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_70_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_70_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_70_0_SPARE_BIT_70_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_70_0_SPARE_BIT_70_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_70_0_SPARE_BIT_70_SHIFT)
#define FUSE_SPARE_BIT_70_0_SPARE_BIT_70_RANGE                  0:0
#define FUSE_SPARE_BIT_70_0_SPARE_BIT_70_WOFFSET                        0x0
#define FUSE_SPARE_BIT_70_0_SPARE_BIT_70_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_70_0_SPARE_BIT_70_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_70_0_SPARE_BIT_70_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_70_0_SPARE_BIT_70_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_70_0_SPARE_BIT_70_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_70_0_SPARE_BIT_70_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_71_0
#define FUSE_SPARE_BIT_71_0                     _MK_ADDR_CONST(0x728)
#define FUSE_SPARE_BIT_71_0_SECURE                      0x0
#define FUSE_SPARE_BIT_71_0_DUAL                        0x0
#define FUSE_SPARE_BIT_71_0_SCR                         0
#define FUSE_SPARE_BIT_71_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_71_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_71_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_71_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_71_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_71_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_71_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_71_0_SPARE_BIT_71_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_71_0_SPARE_BIT_71_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_71_0_SPARE_BIT_71_SHIFT)
#define FUSE_SPARE_BIT_71_0_SPARE_BIT_71_RANGE                  0:0
#define FUSE_SPARE_BIT_71_0_SPARE_BIT_71_WOFFSET                        0x0
#define FUSE_SPARE_BIT_71_0_SPARE_BIT_71_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_71_0_SPARE_BIT_71_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_71_0_SPARE_BIT_71_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_71_0_SPARE_BIT_71_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_71_0_SPARE_BIT_71_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_71_0_SPARE_BIT_71_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_72_0
#define FUSE_SPARE_BIT_72_0                     _MK_ADDR_CONST(0x72c)
#define FUSE_SPARE_BIT_72_0_SECURE                      0x0
#define FUSE_SPARE_BIT_72_0_DUAL                        0x0
#define FUSE_SPARE_BIT_72_0_SCR                         0
#define FUSE_SPARE_BIT_72_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_72_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_72_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_72_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_72_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_72_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_72_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_72_0_SPARE_BIT_72_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_72_0_SPARE_BIT_72_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_72_0_SPARE_BIT_72_SHIFT)
#define FUSE_SPARE_BIT_72_0_SPARE_BIT_72_RANGE                  0:0
#define FUSE_SPARE_BIT_72_0_SPARE_BIT_72_WOFFSET                        0x0
#define FUSE_SPARE_BIT_72_0_SPARE_BIT_72_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_72_0_SPARE_BIT_72_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_72_0_SPARE_BIT_72_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_72_0_SPARE_BIT_72_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_72_0_SPARE_BIT_72_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_72_0_SPARE_BIT_72_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_73_0
#define FUSE_SPARE_BIT_73_0                     _MK_ADDR_CONST(0x730)
#define FUSE_SPARE_BIT_73_0_SECURE                      0x0
#define FUSE_SPARE_BIT_73_0_DUAL                        0x0
#define FUSE_SPARE_BIT_73_0_SCR                         0
#define FUSE_SPARE_BIT_73_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_73_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_73_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_73_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_73_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_73_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_73_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_73_0_SPARE_BIT_73_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_73_0_SPARE_BIT_73_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_73_0_SPARE_BIT_73_SHIFT)
#define FUSE_SPARE_BIT_73_0_SPARE_BIT_73_RANGE                  0:0
#define FUSE_SPARE_BIT_73_0_SPARE_BIT_73_WOFFSET                        0x0
#define FUSE_SPARE_BIT_73_0_SPARE_BIT_73_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_73_0_SPARE_BIT_73_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_73_0_SPARE_BIT_73_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_73_0_SPARE_BIT_73_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_73_0_SPARE_BIT_73_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_73_0_SPARE_BIT_73_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_74_0
#define FUSE_SPARE_BIT_74_0                     _MK_ADDR_CONST(0x734)
#define FUSE_SPARE_BIT_74_0_SECURE                      0x0
#define FUSE_SPARE_BIT_74_0_DUAL                        0x0
#define FUSE_SPARE_BIT_74_0_SCR                         0
#define FUSE_SPARE_BIT_74_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_74_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_74_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_74_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_74_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_74_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_74_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_74_0_SPARE_BIT_74_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_74_0_SPARE_BIT_74_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_74_0_SPARE_BIT_74_SHIFT)
#define FUSE_SPARE_BIT_74_0_SPARE_BIT_74_RANGE                  0:0
#define FUSE_SPARE_BIT_74_0_SPARE_BIT_74_WOFFSET                        0x0
#define FUSE_SPARE_BIT_74_0_SPARE_BIT_74_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_74_0_SPARE_BIT_74_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_74_0_SPARE_BIT_74_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_74_0_SPARE_BIT_74_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_74_0_SPARE_BIT_74_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_74_0_SPARE_BIT_74_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_75_0
#define FUSE_SPARE_BIT_75_0                     _MK_ADDR_CONST(0x738)
#define FUSE_SPARE_BIT_75_0_SECURE                      0x0
#define FUSE_SPARE_BIT_75_0_DUAL                        0x0
#define FUSE_SPARE_BIT_75_0_SCR                         0
#define FUSE_SPARE_BIT_75_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_75_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_75_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_75_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_75_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_75_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_75_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_75_0_SPARE_BIT_75_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_75_0_SPARE_BIT_75_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_75_0_SPARE_BIT_75_SHIFT)
#define FUSE_SPARE_BIT_75_0_SPARE_BIT_75_RANGE                  0:0
#define FUSE_SPARE_BIT_75_0_SPARE_BIT_75_WOFFSET                        0x0
#define FUSE_SPARE_BIT_75_0_SPARE_BIT_75_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_75_0_SPARE_BIT_75_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_75_0_SPARE_BIT_75_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_75_0_SPARE_BIT_75_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_75_0_SPARE_BIT_75_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_75_0_SPARE_BIT_75_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_76_0
#define FUSE_SPARE_BIT_76_0                     _MK_ADDR_CONST(0x73c)
#define FUSE_SPARE_BIT_76_0_SECURE                      0x0
#define FUSE_SPARE_BIT_76_0_DUAL                        0x0
#define FUSE_SPARE_BIT_76_0_SCR                         0
#define FUSE_SPARE_BIT_76_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_76_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_76_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_76_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_76_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_76_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_76_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_76_0_SPARE_BIT_76_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_76_0_SPARE_BIT_76_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_76_0_SPARE_BIT_76_SHIFT)
#define FUSE_SPARE_BIT_76_0_SPARE_BIT_76_RANGE                  0:0
#define FUSE_SPARE_BIT_76_0_SPARE_BIT_76_WOFFSET                        0x0
#define FUSE_SPARE_BIT_76_0_SPARE_BIT_76_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_76_0_SPARE_BIT_76_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_76_0_SPARE_BIT_76_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_76_0_SPARE_BIT_76_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_76_0_SPARE_BIT_76_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_76_0_SPARE_BIT_76_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_77_0
#define FUSE_SPARE_BIT_77_0                     _MK_ADDR_CONST(0x740)
#define FUSE_SPARE_BIT_77_0_SECURE                      0x0
#define FUSE_SPARE_BIT_77_0_DUAL                        0x0
#define FUSE_SPARE_BIT_77_0_SCR                         0
#define FUSE_SPARE_BIT_77_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_77_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_77_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_77_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_77_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_77_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_77_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_77_0_SPARE_BIT_77_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_77_0_SPARE_BIT_77_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_77_0_SPARE_BIT_77_SHIFT)
#define FUSE_SPARE_BIT_77_0_SPARE_BIT_77_RANGE                  0:0
#define FUSE_SPARE_BIT_77_0_SPARE_BIT_77_WOFFSET                        0x0
#define FUSE_SPARE_BIT_77_0_SPARE_BIT_77_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_77_0_SPARE_BIT_77_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_77_0_SPARE_BIT_77_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_77_0_SPARE_BIT_77_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_77_0_SPARE_BIT_77_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_77_0_SPARE_BIT_77_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_78_0
#define FUSE_SPARE_BIT_78_0                     _MK_ADDR_CONST(0x744)
#define FUSE_SPARE_BIT_78_0_SECURE                      0x0
#define FUSE_SPARE_BIT_78_0_DUAL                        0x0
#define FUSE_SPARE_BIT_78_0_SCR                         0
#define FUSE_SPARE_BIT_78_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_78_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_78_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_78_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_78_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_78_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_78_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_78_0_SPARE_BIT_78_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_78_0_SPARE_BIT_78_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_78_0_SPARE_BIT_78_SHIFT)
#define FUSE_SPARE_BIT_78_0_SPARE_BIT_78_RANGE                  0:0
#define FUSE_SPARE_BIT_78_0_SPARE_BIT_78_WOFFSET                        0x0
#define FUSE_SPARE_BIT_78_0_SPARE_BIT_78_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_78_0_SPARE_BIT_78_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_78_0_SPARE_BIT_78_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_78_0_SPARE_BIT_78_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_78_0_SPARE_BIT_78_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_78_0_SPARE_BIT_78_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_79_0
#define FUSE_SPARE_BIT_79_0                     _MK_ADDR_CONST(0x748)
#define FUSE_SPARE_BIT_79_0_SECURE                      0x0
#define FUSE_SPARE_BIT_79_0_DUAL                        0x0
#define FUSE_SPARE_BIT_79_0_SCR                         0
#define FUSE_SPARE_BIT_79_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_79_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_79_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_79_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_79_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_79_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_79_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_79_0_SPARE_BIT_79_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_79_0_SPARE_BIT_79_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_79_0_SPARE_BIT_79_SHIFT)
#define FUSE_SPARE_BIT_79_0_SPARE_BIT_79_RANGE                  0:0
#define FUSE_SPARE_BIT_79_0_SPARE_BIT_79_WOFFSET                        0x0
#define FUSE_SPARE_BIT_79_0_SPARE_BIT_79_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_79_0_SPARE_BIT_79_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_79_0_SPARE_BIT_79_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_79_0_SPARE_BIT_79_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_79_0_SPARE_BIT_79_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_79_0_SPARE_BIT_79_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_80_0
#define FUSE_SPARE_BIT_80_0                     _MK_ADDR_CONST(0x74c)
#define FUSE_SPARE_BIT_80_0_SECURE                      0x0
#define FUSE_SPARE_BIT_80_0_DUAL                        0x0
#define FUSE_SPARE_BIT_80_0_SCR                         0
#define FUSE_SPARE_BIT_80_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_80_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_80_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_80_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_80_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_80_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_80_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_80_0_SPARE_BIT_80_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_80_0_SPARE_BIT_80_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_80_0_SPARE_BIT_80_SHIFT)
#define FUSE_SPARE_BIT_80_0_SPARE_BIT_80_RANGE                  0:0
#define FUSE_SPARE_BIT_80_0_SPARE_BIT_80_WOFFSET                        0x0
#define FUSE_SPARE_BIT_80_0_SPARE_BIT_80_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_80_0_SPARE_BIT_80_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_80_0_SPARE_BIT_80_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_80_0_SPARE_BIT_80_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_80_0_SPARE_BIT_80_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_80_0_SPARE_BIT_80_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

// Register FUSE_SPARE_BIT_81_0
#define FUSE_SPARE_BIT_81_0                     _MK_ADDR_CONST(0x750)
#define FUSE_SPARE_BIT_81_0_SECURE                      0x0
#define FUSE_SPARE_BIT_81_0_DUAL                        0x0
#define FUSE_SPARE_BIT_81_0_SCR                         0
#define FUSE_SPARE_BIT_81_0_WORD_COUNT                  0x1
#define FUSE_SPARE_BIT_81_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_81_0_RESET_MASK                  _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_81_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_81_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_81_0_READ_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_81_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_81_0_SPARE_BIT_81_SHIFT                  _MK_SHIFT_CONST(0)
#define FUSE_SPARE_BIT_81_0_SPARE_BIT_81_FIELD                  _MK_FIELD_CONST(0x1, FUSE_SPARE_BIT_81_0_SPARE_BIT_81_SHIFT)
#define FUSE_SPARE_BIT_81_0_SPARE_BIT_81_RANGE                  0:0
#define FUSE_SPARE_BIT_81_0_SPARE_BIT_81_WOFFSET                        0x0
#define FUSE_SPARE_BIT_81_0_SPARE_BIT_81_DEFAULT                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_81_0_SPARE_BIT_81_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define FUSE_SPARE_BIT_81_0_SPARE_BIT_81_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_81_0_SPARE_BIT_81_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_81_0_SPARE_BIT_81_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define FUSE_SPARE_BIT_81_0_SPARE_BIT_81_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

//
// REGISTER LIST
//
#define LIST_ARFUSE_REGS(_op_) \
_op_(FUSE_FUSECTRL_0) \
_op_(FUSE_FUSEADDR_0) \
_op_(FUSE_FUSERDATA_0) \
_op_(FUSE_FUSEWDATA_0) \
_op_(FUSE_FUSETIME_RD1_0) \
_op_(FUSE_FUSETIME_RD2_0) \
_op_(FUSE_FUSETIME_PGM1_0) \
_op_(FUSE_FUSETIME_PGM2_0) \
_op_(FUSE_PRIV2INTFC_START_0) \
_op_(FUSE_FUSEBYPASS_0) \
_op_(FUSE_PRIVATEKEYDISABLE_0) \
_op_(FUSE_DISABLEREGPROGRAM_0) \
_op_(FUSE_WRITE_ACCESS_SW_0) \
_op_(FUSE_FUSETIME_RD3_0) \
_op_(FUSE_SPARE_ADDR_START_0) \
_op_(FUSE_CRC_STATUS_0) \
_op_(FUSE_CONTROL_WORD_STATUS_0) \
_op_(FUSE_PRIVATE_KEY0_NONZERO_0) \
_op_(FUSE_PRIVATE_KEY1_NONZERO_0) \
_op_(FUSE_PRIVATE_KEY2_NONZERO_0) \
_op_(FUSE_PRIVATE_KEY3_NONZERO_0) \
_op_(FUSE_H2_NONZERO_0) \
_op_(FUSE_RESHIFT_TRIGGER_CHAIN_3_0) \
_op_(FUSE_RESHIFT_STATUS_CHAIN_3_0) \
_op_(FUSE_RESHIFT_TRIGGER_CHAIN_4_0) \
_op_(FUSE_RESHIFT_STATUS_CHAIN_4_0) \
_op_(FUSE_RESHIFT_TRIGGER_CHAIN_5_0) \
_op_(FUSE_RESHIFT_STATUS_CHAIN_5_0) \
_op_(FUSE_RESHIFT_TRIGGER_CHAIN_6_0) \
_op_(FUSE_RESHIFT_STATUS_CHAIN_6_0) \
_op_(FUSE_RESHIFT_TRIGGER_CHAIN_7_0) \
_op_(FUSE_RESHIFT_STATUS_CHAIN_7_0) \
_op_(FUSE_RESHIFT_TRIGGER_CHAIN_8_0) \
_op_(FUSE_RESHIFT_STATUS_CHAIN_8_0) \
_op_(FUSE_PRODUCTION_MODE_0) \
_op_(FUSE_ODM_LOCK_0) \
_op_(FUSE_OPT_OPENGL_EN_0) \
_op_(FUSE_SKU_INFO_0) \
_op_(FUSE_CPU_SPEEDO_CALIB_0) \
_op_(FUSE_CPU1_HT_IDDQ_CALIB_0) \
_op_(FUSE_OPT_FT_REV_0) \
_op_(FUSE_CV_SPEEDO_CALIB_0) \
_op_(FUSE_GPU_SPEEDO_CALIB_0) \
_op_(FUSE_SOC_SPEEDO_CALIB_0) \
_op_(FUSE_RESERVED_0_SPEEDO_CALIB_0) \
_op_(FUSE_RESERVED_1_SPEEDO_CALIB_0) \
_op_(FUSE_SOC_HT_IDDQ_CALIB_0) \
_op_(FUSE_RESERVED_PRODUCTION_0) \
_op_(FUSE_HDMI_LANE0_CALIB_0) \
_op_(FUSE_HDMI_LANE1_CALIB_0) \
_op_(FUSE_HDMI_LANE2_CALIB_0) \
_op_(FUSE_HDMI_LANE3_CALIB_0) \
_op_(FUSE_PUBLIC_KEY0_0) \
_op_(FUSE_PUBLIC_KEY1_0) \
_op_(FUSE_PUBLIC_KEY2_0) \
_op_(FUSE_PUBLIC_KEY3_0) \
_op_(FUSE_PUBLIC_KEY4_0) \
_op_(FUSE_PUBLIC_KEY5_0) \
_op_(FUSE_PUBLIC_KEY6_0) \
_op_(FUSE_PUBLIC_KEY7_0) \
_op_(FUSE_OPT_CP_REV_0) \
_op_(FUSE_OPT_PFG_0) \
_op_(FUSE_SECURITY_MODE_0) \
_op_(FUSE_PRIVATE_KEY0_0) \
_op_(FUSE_PRIVATE_KEY1_0) \
_op_(FUSE_PRIVATE_KEY2_0) \
_op_(FUSE_PRIVATE_KEY3_0) \
_op_(FUSE_ARM_JTAG_DIS_0) \
_op_(FUSE_BOOT_DEVICE_INFO_0) \
_op_(FUSE_RESERVED_SW_0) \
_op_(FUSE_OPT_VP9_DISABLE_0) \
_op_(FUSE_RESERVED_ODM0_0) \
_op_(FUSE_RESERVED_ODM1_0) \
_op_(FUSE_RESERVED_ODM2_0) \
_op_(FUSE_RESERVED_ODM3_0) \
_op_(FUSE_RESERVED_ODM4_0) \
_op_(FUSE_RESERVED_ODM5_0) \
_op_(FUSE_RESERVED_ODM6_0) \
_op_(FUSE_RESERVED_ODM7_0) \
_op_(FUSE_USB_CALIB_0) \
_op_(FUSE_SKU_DIRECT_CONFIG_0) \
_op_(FUSE_KFUSE_PRIVKEY_CTRL_0) \
_op_(FUSE_PACKAGE_INFO_0) \
_op_(FUSE_OPT_VENDOR_CODE_0) \
_op_(FUSE_OPT_FAB_CODE_0) \
_op_(FUSE_OPT_LOT_CODE_0_0) \
_op_(FUSE_OPT_LOT_CODE_1_0) \
_op_(FUSE_OPT_WAFER_ID_0) \
_op_(FUSE_OPT_X_COORDINATE_0) \
_op_(FUSE_OPT_Y_COORDINATE_0) \
_op_(FUSE_OPT_OPS_RESERVED_0) \
_op_(FUSE_SATA_MPHY_ODM_CALIB_0) \
_op_(FUSE_GPU_HT_IDDQ_CALIB_0) \
_op_(FUSE_CLOCK_BONDOUT0_0) \
_op_(FUSE_CLOCK_BONDOUT1_0) \
_op_(FUSE_OPT_SAMPLE_TYPE_0) \
_op_(FUSE_OPT_SUBREVISION_0) \
_op_(FUSE_OPT_SW_RESERVED_0_0) \
_op_(FUSE_OPT_SW_RESERVED_1_0) \
_op_(FUSE_TSENSOR4_CALIB_0) \
_op_(FUSE_TSENSOR5_CALIB_0) \
_op_(FUSE_TSENSOR6_CALIB_0) \
_op_(FUSE_TSENSOR7_CALIB_0) \
_op_(FUSE_OPT_PRIV_SEC_EN_0) \
_op_(FUSE_BOOT_SECURITY_INFO_0) \
_op_(FUSE_FUSE2TSEC_DEBUG_DISABLE_0) \
_op_(FUSE_TSENSOR_COMMON_T1_0) \
_op_(FUSE_OPT_CP_BIN_0) \
_op_(FUSE_OPT_GPU_DISABLE_0) \
_op_(FUSE_OPT_FT_DONE_0) \
_op_(FUSE_OPT_DONE_MAP_0) \
_op_(FUSE_ODM_INFO_0) \
_op_(FUSE_ARM_CRYPT_DE_FEATURE_0) \
_op_(FUSE_CCPLEX_UCODE_MISC_0) \
_op_(FUSE_CCPLEX_DFD_ACCESS_DISABLE_0) \
_op_(FUSE_WOA_SKU_FLAG_0) \
_op_(FUSE_ECO_RESERVE_1_0) \
_op_(FUSE_GCPLEX_CONFIG_FUSE_0) \
_op_(FUSE_PRODUCTION_MONTH_0) \
_op_(FUSE_RAM_REPAIR_INDICATOR_0) \
_op_(FUSE_TSENSOR8_CALIB_0) \
_op_(FUSE_VMIN_CALIBRATION_0) \
_op_(FUSE_AGING_SENSOR_CALIBRATION_0) \
_op_(FUSE_DEBUG_AUTHENTICATION_0) \
_op_(FUSE_OPT_GPU_DISABLE_CP_0) \
_op_(FUSE_SPARE_ENDIS_0) \
_op_(FUSE_ECO_RESERVE_0_0) \
_op_(FUSE_USB3_RCM_CALIB0_0) \
_op_(FUSE_USB3_RCM_CALIB1_0) \
_op_(FUSE_OPT_TPC_DISABLE_0) \
_op_(FUSE_OPT_TPC_DISABLE_CP_0) \
_op_(FUSE_OPT_CCPLEX_CORE_DISABLE_0) \
_op_(FUSE_OPT_CCPLEX_CORE_DISABLE_CP_0) \
_op_(FUSE_TSENSOR9_CALIB_0) \
_op_(FUSE_TSENSOR10_CALIB_0) \
_op_(FUSE_USB_CALIB_EXT_0) \
_op_(FUSE_HYPERVOLTAGING_0) \
_op_(FUSE_OPT_ECC_EN_0) \
_op_(FUSE_TSENSOR_COMMON_T2_0) \
_op_(FUSE_TSENSOR_COMMON_T3_0) \
_op_(FUSE_CCPLEX_UCODE_NV_REV_0) \
_op_(FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET3_0) \
_op_(FUSE_CCPLEX_DFD_AUTH_REQD_0) \
_op_(FUSE_VMIN_SENSOR_CALIBRATION_0) \
_op_(FUSE_OPT_CCPLEX_L2S_DISABLE_0) \
_op_(FUSE_OPT_CCPLEX_L2S_DISABLE_CP_0) \
_op_(FUSE_EK0_0) \
_op_(FUSE_EK1_0) \
_op_(FUSE_EK2_0) \
_op_(FUSE_EK3_0) \
_op_(FUSE_EK4_0) \
_op_(FUSE_EK5_0) \
_op_(FUSE_EK6_0) \
_op_(FUSE_EK7_0) \
_op_(FUSE_PDK0_0) \
_op_(FUSE_PDK1_0) \
_op_(FUSE_PDK2_0) \
_op_(FUSE_PDK3_0) \
_op_(FUSE_KEK00_0) \
_op_(FUSE_KEK01_0) \
_op_(FUSE_KEK02_0) \
_op_(FUSE_KEK03_0) \
_op_(FUSE_KEK10_0) \
_op_(FUSE_KEK11_0) \
_op_(FUSE_KEK12_0) \
_op_(FUSE_KEK13_0) \
_op_(FUSE_KEK20_0) \
_op_(FUSE_KEK21_0) \
_op_(FUSE_KEK22_0) \
_op_(FUSE_KEK23_0) \
_op_(FUSE_OPT_PRIV_SFK_0_0) \
_op_(FUSE_OPT_PRIV_SFK_1_0) \
_op_(FUSE_OPT_PRIV_SFK_2_0) \
_op_(FUSE_OPT_PRIV_SFK_3_0) \
_op_(FUSE_PDI0_0) \
_op_(FUSE_PDI1_0) \
_op_(FUSE_ODMID0_0) \
_op_(FUSE_ODMID1_0) \
_op_(FUSE_H0_0) \
_op_(FUSE_H1_0) \
_op_(FUSE_H2_0) \
_op_(FUSE_H3_0) \
_op_(FUSE_OPT_SECURE_SCC_DIS_0) \
_op_(FUSE_OPT_ADC_CAL_FUSE_REV_0) \
_op_(FUSE_OPT_ADC_CAL_INSTANCE0_0) \
_op_(FUSE_OPT_ADC_CAL_INSTANCE1_DELTA_0) \
_op_(FUSE_OPT_ADC_CAL_INSTANCE2_DELTA_0) \
_op_(FUSE_OPT_ADC_CAL_INSTANCE3_DELTA_0) \
_op_(FUSE_BPMP_CONFIG_0) \
_op_(FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_0) \
_op_(FUSE_OPT_FUSE_UCODE_ACR_HS_REV_0) \
_op_(FUSE_OPT_FUSE_UCODE_NVDEC_REV_0) \
_op_(FUSE_VCM_REVISION_0) \
_op_(FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_0) \
_op_(FUSE_CV_LT_IDDQ_CALIB_0) \
_op_(FUSE_CPU0_HT_IDDQ_CALIB_0) \
_op_(FUSE_RESERVED_IDDQ_CALIB_0) \
_op_(FUSE_CV_HT_IDDQ_CALIB_0) \
_op_(FUSE_CPU1_LT_IDDQ_CALIB_0) \
_op_(FUSE_CPU0_LT_IDDQ_CALIB_0) \
_op_(FUSE_SOC_LT_IDDQ_CALIB_0) \
_op_(FUSE_GPU_LT_IDDQ_CALIB_0) \
_op_(FUSE_OPT_INTERNAL_SKU_0) \
_op_(FUSE_FUSE2NVDEC_DEBUG_DISABLE_0) \
_op_(FUSE_SATA_NV_CALIB_0) \
_op_(FUSE_MPHY_NV_CALIB_0) \
_op_(FUSE_BOOTROM_PATCH_VERSION_0) \
_op_(FUSE_OPT_SFK_ACC_DIS_0) \
_op_(FUSE_OPT_PDK_ACC_DIS_0) \
_op_(FUSE_OPT_INVALID_BITS_ATE_0) \
_op_(FUSE_MB1_NV_REV_0) \
_op_(FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET2_0) \
_op_(FUSE_AGING_SENSOR_VERSION_0) \
_op_(FUSE_SPEEDO_IDDQ_VERSION_0) \
_op_(FUSE_FORCE_DEBUG_WITH_TEST_KEYS_0) \
_op_(FUSE_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_0) \
_op_(FUSE_OPT_ISP_DISABLE_0) \
_op_(FUSE_OPT_ISP_DISABLE_CP_0) \
_op_(FUSE_OPT_NVENC_DISABLE_0) \
_op_(FUSE_OPT_NVENC_DISABLE_CP_0) \
_op_(FUSE_OPT_PVA_DISABLE_0) \
_op_(FUSE_OPT_PVA_DISABLE_CP_0) \
_op_(FUSE_OPT_DLA_DISABLE_0) \
_op_(FUSE_OPT_DLA_DISABLE_CP_0) \
_op_(FUSE_OPT_CV_DISABLE_0) \
_op_(FUSE_OPT_CV_DISABLE_CP_0) \
_op_(FUSE_PDK2_0_0) \
_op_(FUSE_PDK2_1_0) \
_op_(FUSE_PDK2_2_0) \
_op_(FUSE_PDK2_3_0) \
_op_(FUSE_OPT_PRIV_SFK2_0_0) \
_op_(FUSE_OPT_PRIV_SFK2_1_0) \
_op_(FUSE_OPT_PRIV_SFK2_2_0) \
_op_(FUSE_OPT_PRIV_SFK2_3_0) \
_op_(FUSE_RESERVED_ODM8_0) \
_op_(FUSE_RESERVED_ODM9_0) \
_op_(FUSE_RESERVED_ODM10_0) \
_op_(FUSE_RESERVED_ODM11_0) \
_op_(FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET0_0) \
_op_(FUSE_CCPLEX_UCODE_MB1_FALCON_UCODE_FIELD_RATCHET1_0) \
_op_(FUSE_LOCK_PROD_RESTRICTED_FLAG_0) \
_op_(FUSE_LOCK_PROD_DISALLOWED_FLAG_0) \
_op_(FUSE_FUSE_INTEGRITY_CHECK_ENABLE_0) \
_op_(FUSE_TSENSOR11_CALIB_0) \
_op_(FUSE_TSENSOR12_CALIB_0) \
_op_(FUSE_TSENSOR17_CALIB_0) \
_op_(FUSE_FLW0_0) \
_op_(FUSE_FLW1_0) \
_op_(FUSE_FLW2_0) \
_op_(FUSE_FLW3_0) \
_op_(FUSE_BPMP_DUMMY_KEY_READ_ENABLE_0) \
_op_(FUSE_VREFRO_CALIB_0) \
_op_(FUSE_BOOT_NV_INFO_0) \
_op_(FUSE_OPT_RAM_SVOP_DP_PO4SVT_0) \
_op_(FUSE_OPT_RAM_SVOP_PDP_PO4SVT_0) \
_op_(FUSE_OPT_RAM_SVOP_SP_PO4SVT_0) \
_op_(FUSE_OPT_RAM_SVOP_SMPDP_PO4SVT_0) \
_op_(FUSE_OPT_RAM_SVOP_SP_PO4HVT_0) \
_op_(FUSE_OPT_FUSE_UCODE_HULK_REV_0) \
_op_(FUSE_OPT_FUSE_UCODE_UDE_REV_0) \
_op_(FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_0) \
_op_(FUSE_OPT_FUSE_UCODE_CTXSW_REV_0) \
_op_(FUSE_OPT_ADC_CAL_INSTANCE4_DELTA_0) \
_op_(FUSE_OPT_CUSTOMER_OPTIN_FUSE_0) \
_op_(FUSE_RESERVED_FUSELESS_0) \
_op_(FUSE_IP_DISABLE_0) \
_op_(FUSE_OPT_ASYNC_L1ARST_ENABLE_0) \
_op_(FUSE_OPT_ASYNC_L0RST_ENABLE_0) \
_op_(FUSE_OPT_IST_UCODE_JTAG_DATA_OVERRIDE_0) \
_op_(FUSE_OPT_IST_DISABLE_JTAG_FILLER_0) \
_op_(FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_0) \
_op_(FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE_0) \
_op_(FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_0) \
_op_(FUSE_OPT_FUSE_UCODE_MINION_REV_0) \
_op_(FUSE_OPT_SECURE_MINION_DEBUG_DIS_0) \
_op_(FUSE_OPT_RAM_SVOP_DP_SVT_0) \
_op_(FUSE_OPT_RAM_SVOP_SP_SVT_0) \
_op_(FUSE_OPT_RAM_SVOP_PDP_SVT_0) \
_op_(FUSE_OPT_ROM_SVOP_HVT_0) \
_op_(FUSE_FALCON_UCODE_NV_REV_0) \
_op_(FUSE_OPT_NVDEC_DISABLE_0) \
_op_(FUSE_OPT_NVDEC_DISABLE_CP_0) \
_op_(FUSE_OPT_RAM_FOP_CCPLEX_6D_0) \
_op_(FUSE_OPT_RAM_FOP_CCPLEX_L2_0) \
_op_(FUSE_OPT_RAM_FOP_CCPLEX_L3D_0) \
_op_(FUSE_OPT_RAM_FOP_CV_CVSRAM_0) \
_op_(FUSE_USB3_RCM_CALIB2_0) \
_op_(FUSE_SPARE_BIT_0_0) \
_op_(FUSE_SPARE_BIT_1_0) \
_op_(FUSE_SPARE_BIT_2_0) \
_op_(FUSE_SPARE_BIT_3_0) \
_op_(FUSE_SPARE_BIT_4_0) \
_op_(FUSE_SPARE_BIT_5_0) \
_op_(FUSE_SPARE_BIT_6_0) \
_op_(FUSE_SPARE_BIT_7_0) \
_op_(FUSE_SPARE_BIT_8_0) \
_op_(FUSE_SPARE_BIT_9_0) \
_op_(FUSE_SPARE_BIT_10_0) \
_op_(FUSE_SPARE_BIT_11_0) \
_op_(FUSE_SPARE_BIT_12_0) \
_op_(FUSE_SPARE_BIT_13_0) \
_op_(FUSE_SPARE_BIT_14_0) \
_op_(FUSE_SPARE_BIT_15_0) \
_op_(FUSE_SPARE_BIT_16_0) \
_op_(FUSE_SPARE_BIT_17_0) \
_op_(FUSE_SPARE_BIT_18_0) \
_op_(FUSE_SPARE_BIT_19_0) \
_op_(FUSE_SPARE_BIT_20_0) \
_op_(FUSE_SPARE_BIT_21_0) \
_op_(FUSE_SPARE_BIT_22_0) \
_op_(FUSE_SPARE_BIT_23_0) \
_op_(FUSE_SPARE_BIT_24_0) \
_op_(FUSE_SPARE_BIT_25_0) \
_op_(FUSE_SPARE_BIT_26_0) \
_op_(FUSE_SPARE_BIT_27_0) \
_op_(FUSE_SPARE_BIT_28_0) \
_op_(FUSE_SPARE_BIT_29_0) \
_op_(FUSE_SPARE_BIT_30_0) \
_op_(FUSE_SPARE_BIT_31_0) \
_op_(FUSE_SPARE_BIT_32_0) \
_op_(FUSE_SPARE_BIT_33_0) \
_op_(FUSE_SPARE_BIT_34_0) \
_op_(FUSE_SPARE_BIT_35_0) \
_op_(FUSE_SPARE_BIT_36_0) \
_op_(FUSE_SPARE_BIT_37_0) \
_op_(FUSE_SPARE_BIT_38_0) \
_op_(FUSE_SPARE_BIT_39_0) \
_op_(FUSE_SPARE_BIT_40_0) \
_op_(FUSE_SPARE_BIT_41_0) \
_op_(FUSE_SPARE_BIT_42_0) \
_op_(FUSE_SPARE_BIT_43_0) \
_op_(FUSE_SPARE_BIT_44_0) \
_op_(FUSE_SPARE_BIT_45_0) \
_op_(FUSE_SPARE_BIT_46_0) \
_op_(FUSE_SPARE_BIT_47_0) \
_op_(FUSE_SPARE_BIT_48_0) \
_op_(FUSE_SPARE_BIT_49_0) \
_op_(FUSE_SPARE_BIT_50_0) \
_op_(FUSE_SPARE_BIT_51_0) \
_op_(FUSE_SPARE_BIT_52_0) \
_op_(FUSE_SPARE_BIT_53_0) \
_op_(FUSE_SPARE_BIT_54_0) \
_op_(FUSE_SPARE_BIT_55_0) \
_op_(FUSE_SPARE_BIT_56_0) \
_op_(FUSE_SPARE_BIT_57_0) \
_op_(FUSE_SPARE_BIT_58_0) \
_op_(FUSE_SPARE_BIT_59_0) \
_op_(FUSE_SPARE_BIT_60_0) \
_op_(FUSE_SPARE_BIT_61_0) \
_op_(FUSE_SPARE_BIT_62_0) \
_op_(FUSE_SPARE_BIT_63_0) \
_op_(FUSE_SPARE_BIT_64_0) \
_op_(FUSE_SPARE_BIT_65_0) \
_op_(FUSE_SPARE_BIT_66_0) \
_op_(FUSE_SPARE_BIT_67_0) \
_op_(FUSE_SPARE_BIT_68_0) \
_op_(FUSE_SPARE_BIT_69_0) \
_op_(FUSE_SPARE_BIT_70_0) \
_op_(FUSE_SPARE_BIT_71_0) \
_op_(FUSE_SPARE_BIT_72_0) \
_op_(FUSE_SPARE_BIT_73_0) \
_op_(FUSE_SPARE_BIT_74_0) \
_op_(FUSE_SPARE_BIT_75_0) \
_op_(FUSE_SPARE_BIT_76_0) \
_op_(FUSE_SPARE_BIT_77_0) \
_op_(FUSE_SPARE_BIT_78_0) \
_op_(FUSE_SPARE_BIT_79_0) \
_op_(FUSE_SPARE_BIT_80_0) \
_op_(FUSE_SPARE_BIT_81_0)

//
// ADDRESS SPACES
//

#define BASE_ADDRESS_FUSE       0x00000000

//
// ARFUSE REGISTER BANKS
//

#define FUSE0_FIRST_REG 0x0000 // FUSE_FUSECTRL_0
#define FUSE0_LAST_REG 0x0030 // FUSE_WRITE_ACCESS_SW_0
#define FUSE1_FIRST_REG 0x004c // FUSE_FUSETIME_RD3_0
#define FUSE1_LAST_REG 0x004c // FUSE_FUSETIME_RD3_0
#define FUSE2_FIRST_REG 0x0060 // FUSE_SPARE_ADDR_START_0
#define FUSE2_LAST_REG 0x0060 // FUSE_SPARE_ADDR_START_0
#define FUSE3_FIRST_REG 0x0068 // FUSE_CRC_STATUS_0
#define FUSE3_LAST_REG 0x006c // FUSE_CONTROL_WORD_STATUS_0
#define FUSE4_FIRST_REG 0x0080 // FUSE_PRIVATE_KEY0_NONZERO_0
#define FUSE4_LAST_REG 0x0090 // FUSE_H2_NONZERO_0
#define FUSE5_FIRST_REG 0x00a0 // FUSE_RESHIFT_TRIGGER_CHAIN_3_0
#define FUSE5_LAST_REG 0x00cc // FUSE_RESHIFT_STATUS_CHAIN_8_0
#define FUSE6_FIRST_REG 0x0100 // FUSE_PRODUCTION_MODE_0
#define FUSE6_LAST_REG 0x0118 // FUSE_CPU1_HT_IDDQ_CALIB_0
#define FUSE7_FIRST_REG 0x0128 // FUSE_OPT_FT_REV_0
#define FUSE7_LAST_REG 0x0140 // FUSE_SOC_HT_IDDQ_CALIB_0
#define FUSE8_LAST_REG 0x015c // FUSE_HDMI_LANE3_CALIB_0
#define FUSE9_FIRST_REG 0x0164 // FUSE_PUBLIC_KEY0_0
#define FUSE9_LAST_REG 0x0180 // FUSE_PUBLIC_KEY7_0
#define FUSE10_FIRST_REG 0x0190 // FUSE_OPT_CP_REV_0
#define FUSE10_LAST_REG 0x0194 // FUSE_OPT_PFG_0
#define FUSE11_FIRST_REG 0x01a0 // FUSE_SECURITY_MODE_0
#define FUSE11_LAST_REG 0x01b0 // FUSE_PRIVATE_KEY3_0
#define FUSE12_FIRST_REG 0x01b8 // FUSE_ARM_JTAG_DIS_0
#define FUSE12_LAST_REG 0x0228 // FUSE_GPU_HT_IDDQ_CALIB_0
#define FUSE13_FIRST_REG 0x0230 // FUSE_CLOCK_BONDOUT0_0
#define FUSE13_LAST_REG 0x0234 // FUSE_CLOCK_BONDOUT1_0
#define FUSE14_FIRST_REG 0x0244 // FUSE_OPT_SAMPLE_TYPE_0
#define FUSE14_LAST_REG 0x0268 // FUSE_BOOT_SECURITY_INFO_0
#define FUSE15_FIRST_REG 0x027c // FUSE_FUSE2TSEC_DEBUG_DISABLE_0
#define FUSE15_LAST_REG 0x0290 // FUSE_OPT_DONE_MAP_0
#define FUSE16_LAST_REG 0x029c // FUSE_ODM_INFO_0
#define FUSE17_FIRST_REG 0x02a8 // FUSE_ARM_CRYPT_DE_FEATURE_0
#define FUSE17_LAST_REG 0x02ac // FUSE_CCPLEX_UCODE_MISC_0
#define FUSE18_FIRST_REG 0x02bc // FUSE_CCPLEX_DFD_ACCESS_DISABLE_0
#define FUSE18_LAST_REG 0x02d4 // FUSE_TSENSOR8_CALIB_0
#define FUSE19_FIRST_REG 0x02dc // FUSE_VMIN_CALIBRATION_0
#define FUSE19_LAST_REG 0x02f8 // FUSE_ECO_RESERVE_0_0
#define FUSE20_FIRST_REG 0x0304 // FUSE_USB3_RCM_CALIB0_0
#define FUSE20_LAST_REG 0x0320 // FUSE_TSENSOR10_CALIB_0
#define FUSE21_FIRST_REG 0x0350 // FUSE_USB_CALIB_EXT_0
#define FUSE21_LAST_REG 0x036c // FUSE_CCPLEX_DFD_AUTH_REQD_0
#define FUSE22_FIRST_REG 0x0374 // FUSE_VMIN_SENSOR_CALIBRATION_0
#define FUSE22_LAST_REG 0x037c // FUSE_OPT_CCPLEX_L2S_DISABLE_CP_0
#define FUSE23_FIRST_REG 0x0390 // FUSE_EK0_0
#define FUSE23_LAST_REG 0x040c // FUSE_ODMID1_0
#define FUSE24_FIRST_REG 0x0434 // FUSE_H0_0
#define FUSE24_LAST_REG 0x04a0 // FUSE_MPHY_NV_CALIB_0
#define FUSE25_FIRST_REG 0x04a8 // FUSE_BOOTROM_PATCH_VERSION_0
#define FUSE25_LAST_REG 0x04cc // FUSE_OPT_SECURE_IN_SYSTEM_BIST_CONTROL_0
#define FUSE26_FIRST_REG 0x04d8 // FUSE_OPT_ISP_DISABLE_0
#define FUSE26_LAST_REG 0x0548 // FUSE_TSENSOR12_CALIB_0
#define FUSE27_FIRST_REG 0x055c // FUSE_TSENSOR17_CALIB_0
#define FUSE27_LAST_REG 0x0750 // FUSE_SPARE_BIT_81_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif
#ifndef _MK_FIELD_CONST
  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
#endif

#endif // ifndef ___ARFUSE_H_INC_
