//
// Copyright (c) 2018 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ___ARSDMMCAB_H_INC_
#define ___ARSDMMCAB_H_INC_
#define NV_MOBILE_ARSDMMCAB_H_UNIT_OF_OFFSET 1B


// Register SDMMCAB_SYSTEM_ADDRESS_0
#define SDMMCAB_SYSTEM_ADDRESS_0                        _MK_ADDR_CONST(0x0)
#define SDMMCAB_SYSTEM_ADDRESS_0_SECURE                         0x0
#define SDMMCAB_SYSTEM_ADDRESS_0_DUAL                   0x0
#define SDMMCAB_SYSTEM_ADDRESS_0_SCR                    0
#define SDMMCAB_SYSTEM_ADDRESS_0_WORD_COUNT                     0x1
#define SDMMCAB_SYSTEM_ADDRESS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define SDMMCAB_SYSTEM_ADDRESS_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_SYSTEM_ADDRESS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SDMMCAB_SYSTEM_ADDRESS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_SYSTEM_ADDRESS_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_SYSTEM_ADDRESS_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_SYSTEM_ADDRESS_0_ADDRESS_SHIFT                  _MK_SHIFT_CONST(0)
#define SDMMCAB_SYSTEM_ADDRESS_0_ADDRESS_FIELD                  _MK_FIELD_CONST(0xffffffff, SDMMCAB_SYSTEM_ADDRESS_0_ADDRESS_SHIFT)
#define SDMMCAB_SYSTEM_ADDRESS_0_ADDRESS_RANGE                  31:0
#define SDMMCAB_SYSTEM_ADDRESS_0_ADDRESS_WOFFSET                        0x0
#define SDMMCAB_SYSTEM_ADDRESS_0_ADDRESS_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_SYSTEM_ADDRESS_0_ADDRESS_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_SYSTEM_ADDRESS_0_ADDRESS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_SYSTEM_ADDRESS_0_ADDRESS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_SYSTEM_ADDRESS_0_ADDRESS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_SYSTEM_ADDRESS_0_ADDRESS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0                        _MK_ADDR_CONST(0x4)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_SECURE                         0x0
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_DUAL                   0x0
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_SCR                    0
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_WORD_COUNT                     0x1
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_RESET_MASK                     _MK_MASK_CONST(0xffff7fff)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_READ_MASK                      _MK_MASK_CONST(0xffff7fff)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_WRITE_MASK                     _MK_MASK_CONST(0xffff7fff)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_BLOCKS_COUNT_SHIFT                     _MK_SHIFT_CONST(16)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_BLOCKS_COUNT_FIELD                     _MK_FIELD_CONST(0xffff, SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_BLOCKS_COUNT_SHIFT)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_BLOCKS_COUNT_RANGE                     31:16
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_BLOCKS_COUNT_WOFFSET                   0x0
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_BLOCKS_COUNT_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_BLOCKS_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_BLOCKS_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_BLOCKS_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_BLOCKS_COUNT_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_BLOCKS_COUNT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_SHIFT                     _MK_SHIFT_CONST(12)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_FIELD                     _MK_FIELD_CONST(0x7, SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_SHIFT)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_RANGE                     14:12
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_WOFFSET                   0x0
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DMA4K                     _MK_ENUM_CONST(0)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DMA8K                     _MK_ENUM_CONST(1)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DMA16K                    _MK_ENUM_CONST(2)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DMA32K                    _MK_ENUM_CONST(3)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DMA64K                    _MK_ENUM_CONST(4)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DMA128K                   _MK_ENUM_CONST(5)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DMA256K                   _MK_ENUM_CONST(6)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DMA512K                   _MK_ENUM_CONST(7)

#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_11_0_SHIFT                     _MK_SHIFT_CONST(0)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_11_0_FIELD                     _MK_FIELD_CONST(0xfff, SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_11_0_SHIFT)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_11_0_RANGE                     11:0
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_11_0_WOFFSET                   0x0
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_11_0_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_11_0_DEFAULT_MASK                      _MK_MASK_CONST(0xfff)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_11_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_11_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_11_0_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_11_0_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_11_0__PROD                     _MK_ENUM_CONST(512)


// Register SDMMCAB_ARGUMENT_0
#define SDMMCAB_ARGUMENT_0                      _MK_ADDR_CONST(0x8)
#define SDMMCAB_ARGUMENT_0_SECURE                       0x0
#define SDMMCAB_ARGUMENT_0_DUAL                         0x0
#define SDMMCAB_ARGUMENT_0_SCR                  0
#define SDMMCAB_ARGUMENT_0_WORD_COUNT                   0x1
#define SDMMCAB_ARGUMENT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SDMMCAB_ARGUMENT_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_ARGUMENT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SDMMCAB_ARGUMENT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_ARGUMENT_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_ARGUMENT_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_ARGUMENT_0_COMMAND_ARGUMENT_SHIFT                       _MK_SHIFT_CONST(0)
#define SDMMCAB_ARGUMENT_0_COMMAND_ARGUMENT_FIELD                       _MK_FIELD_CONST(0xffffffff, SDMMCAB_ARGUMENT_0_COMMAND_ARGUMENT_SHIFT)
#define SDMMCAB_ARGUMENT_0_COMMAND_ARGUMENT_RANGE                       31:0
#define SDMMCAB_ARGUMENT_0_COMMAND_ARGUMENT_WOFFSET                     0x0
#define SDMMCAB_ARGUMENT_0_COMMAND_ARGUMENT_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_ARGUMENT_0_COMMAND_ARGUMENT_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_ARGUMENT_0_COMMAND_ARGUMENT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_ARGUMENT_0_COMMAND_ARGUMENT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_ARGUMENT_0_COMMAND_ARGUMENT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_ARGUMENT_0_COMMAND_ARGUMENT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register SDMMCAB_CMD_XFER_MODE_0
#define SDMMCAB_CMD_XFER_MODE_0                 _MK_ADDR_CONST(0xc)
#define SDMMCAB_CMD_XFER_MODE_0_SECURE                  0x0
#define SDMMCAB_CMD_XFER_MODE_0_DUAL                    0x0
#define SDMMCAB_CMD_XFER_MODE_0_SCR                     0
#define SDMMCAB_CMD_XFER_MODE_0_WORD_COUNT                      0x1
#define SDMMCAB_CMD_XFER_MODE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_RESET_MASK                      _MK_MASK_CONST(0x3fff01ff)
#define SDMMCAB_CMD_XFER_MODE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_READ_MASK                       _MK_MASK_CONST(0x3fff01ff)
#define SDMMCAB_CMD_XFER_MODE_0_WRITE_MASK                      _MK_MASK_CONST(0x3fff01ff)
#define SDMMCAB_CMD_XFER_MODE_0_COMMAND_INDEX_SHIFT                     _MK_SHIFT_CONST(24)
#define SDMMCAB_CMD_XFER_MODE_0_COMMAND_INDEX_FIELD                     _MK_FIELD_CONST(0x3f, SDMMCAB_CMD_XFER_MODE_0_COMMAND_INDEX_SHIFT)
#define SDMMCAB_CMD_XFER_MODE_0_COMMAND_INDEX_RANGE                     29:24
#define SDMMCAB_CMD_XFER_MODE_0_COMMAND_INDEX_WOFFSET                   0x0
#define SDMMCAB_CMD_XFER_MODE_0_COMMAND_INDEX_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_COMMAND_INDEX_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
#define SDMMCAB_CMD_XFER_MODE_0_COMMAND_INDEX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_COMMAND_INDEX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_COMMAND_INDEX_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_COMMAND_INDEX_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SDMMCAB_CMD_XFER_MODE_0_COMMAND_TYPE_SHIFT                      _MK_SHIFT_CONST(22)
#define SDMMCAB_CMD_XFER_MODE_0_COMMAND_TYPE_FIELD                      _MK_FIELD_CONST(0x3, SDMMCAB_CMD_XFER_MODE_0_COMMAND_TYPE_SHIFT)
#define SDMMCAB_CMD_XFER_MODE_0_COMMAND_TYPE_RANGE                      23:22
#define SDMMCAB_CMD_XFER_MODE_0_COMMAND_TYPE_WOFFSET                    0x0
#define SDMMCAB_CMD_XFER_MODE_0_COMMAND_TYPE_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_COMMAND_TYPE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define SDMMCAB_CMD_XFER_MODE_0_COMMAND_TYPE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_COMMAND_TYPE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_COMMAND_TYPE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_COMMAND_TYPE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_CMD_XFER_MODE_0_COMMAND_TYPE_NORMAL                     _MK_ENUM_CONST(0)
#define SDMMCAB_CMD_XFER_MODE_0_COMMAND_TYPE_SUSPEND                    _MK_ENUM_CONST(1)
#define SDMMCAB_CMD_XFER_MODE_0_COMMAND_TYPE_RESUME                     _MK_ENUM_CONST(2)
#define SDMMCAB_CMD_XFER_MODE_0_COMMAND_TYPE_ABORT                      _MK_ENUM_CONST(3)

#define SDMMCAB_CMD_XFER_MODE_0_DATA_PRESENT_SELECT_SHIFT                       _MK_SHIFT_CONST(21)
#define SDMMCAB_CMD_XFER_MODE_0_DATA_PRESENT_SELECT_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_CMD_XFER_MODE_0_DATA_PRESENT_SELECT_SHIFT)
#define SDMMCAB_CMD_XFER_MODE_0_DATA_PRESENT_SELECT_RANGE                       21:21
#define SDMMCAB_CMD_XFER_MODE_0_DATA_PRESENT_SELECT_WOFFSET                     0x0
#define SDMMCAB_CMD_XFER_MODE_0_DATA_PRESENT_SELECT_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_DATA_PRESENT_SELECT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_CMD_XFER_MODE_0_DATA_PRESENT_SELECT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_DATA_PRESENT_SELECT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_DATA_PRESENT_SELECT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_DATA_PRESENT_SELECT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_CMD_XFER_MODE_0_DATA_PRESENT_SELECT_NO_DATA_TRANSFER                    _MK_ENUM_CONST(0)
#define SDMMCAB_CMD_XFER_MODE_0_DATA_PRESENT_SELECT_DATA_TRANSFER                       _MK_ENUM_CONST(1)

#define SDMMCAB_CMD_XFER_MODE_0_CMD_INDEX_CHECK_EN_SHIFT                        _MK_SHIFT_CONST(20)
#define SDMMCAB_CMD_XFER_MODE_0_CMD_INDEX_CHECK_EN_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_CMD_XFER_MODE_0_CMD_INDEX_CHECK_EN_SHIFT)
#define SDMMCAB_CMD_XFER_MODE_0_CMD_INDEX_CHECK_EN_RANGE                        20:20
#define SDMMCAB_CMD_XFER_MODE_0_CMD_INDEX_CHECK_EN_WOFFSET                      0x0
#define SDMMCAB_CMD_XFER_MODE_0_CMD_INDEX_CHECK_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_CMD_INDEX_CHECK_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_CMD_XFER_MODE_0_CMD_INDEX_CHECK_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_CMD_INDEX_CHECK_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_CMD_INDEX_CHECK_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_CMD_INDEX_CHECK_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_CMD_XFER_MODE_0_CMD_INDEX_CHECK_EN_DISABLE                      _MK_ENUM_CONST(0)
#define SDMMCAB_CMD_XFER_MODE_0_CMD_INDEX_CHECK_EN_ENABLE                       _MK_ENUM_CONST(1)

#define SDMMCAB_CMD_XFER_MODE_0_CMD_CRC_CHECK_EN_SHIFT                  _MK_SHIFT_CONST(19)
#define SDMMCAB_CMD_XFER_MODE_0_CMD_CRC_CHECK_EN_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_CMD_XFER_MODE_0_CMD_CRC_CHECK_EN_SHIFT)
#define SDMMCAB_CMD_XFER_MODE_0_CMD_CRC_CHECK_EN_RANGE                  19:19
#define SDMMCAB_CMD_XFER_MODE_0_CMD_CRC_CHECK_EN_WOFFSET                        0x0
#define SDMMCAB_CMD_XFER_MODE_0_CMD_CRC_CHECK_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_CMD_CRC_CHECK_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_CMD_XFER_MODE_0_CMD_CRC_CHECK_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_CMD_CRC_CHECK_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_CMD_CRC_CHECK_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_CMD_CRC_CHECK_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_CMD_XFER_MODE_0_CMD_CRC_CHECK_EN_DISABLE                        _MK_ENUM_CONST(0)
#define SDMMCAB_CMD_XFER_MODE_0_CMD_CRC_CHECK_EN_ENABLE                 _MK_ENUM_CONST(1)

#define SDMMCAB_CMD_XFER_MODE_0_SUB_CMD_FLAG_SHIFT                      _MK_SHIFT_CONST(18)
#define SDMMCAB_CMD_XFER_MODE_0_SUB_CMD_FLAG_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_CMD_XFER_MODE_0_SUB_CMD_FLAG_SHIFT)
#define SDMMCAB_CMD_XFER_MODE_0_SUB_CMD_FLAG_RANGE                      18:18
#define SDMMCAB_CMD_XFER_MODE_0_SUB_CMD_FLAG_WOFFSET                    0x0
#define SDMMCAB_CMD_XFER_MODE_0_SUB_CMD_FLAG_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_SUB_CMD_FLAG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_CMD_XFER_MODE_0_SUB_CMD_FLAG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_SUB_CMD_FLAG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_SUB_CMD_FLAG_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_SUB_CMD_FLAG_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_CMD_XFER_MODE_0_SUB_CMD_FLAG_MAIN_CMD                   _MK_ENUM_CONST(0)
#define SDMMCAB_CMD_XFER_MODE_0_SUB_CMD_FLAG_SUB_CMD                    _MK_ENUM_CONST(1)

#define SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_SELECT_SHIFT                  _MK_SHIFT_CONST(16)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_SELECT_FIELD                  _MK_FIELD_CONST(0x3, SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_SELECT_SHIFT)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_SELECT_RANGE                  17:16
#define SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_SELECT_WOFFSET                        0x0
#define SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_SELECT_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_SELECT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_SELECT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_SELECT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_SELECT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_SELECT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_SELECT_NO_RESPONSE                    _MK_ENUM_CONST(0)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_SELECT_RESP_LENGTH_136                        _MK_ENUM_CONST(1)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_SELECT_RESP_LENGTH_48                 _MK_ENUM_CONST(2)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_SELECT_RESP_LENGTH_48BUSY                     _MK_ENUM_CONST(3)

#define SDMMCAB_CMD_XFER_MODE_0_RESP_INT_DIS_SHIFT                      _MK_SHIFT_CONST(8)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_INT_DIS_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_CMD_XFER_MODE_0_RESP_INT_DIS_SHIFT)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_INT_DIS_RANGE                      8:8
#define SDMMCAB_CMD_XFER_MODE_0_RESP_INT_DIS_WOFFSET                    0x0
#define SDMMCAB_CMD_XFER_MODE_0_RESP_INT_DIS_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_INT_DIS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_INT_DIS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_INT_DIS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_INT_DIS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_INT_DIS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_INT_DIS_ENABLE                     _MK_ENUM_CONST(0)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_INT_DIS_DISABLE                    _MK_ENUM_CONST(1)

#define SDMMCAB_CMD_XFER_MODE_0_RESP_ERR_CHK_EN_SHIFT                   _MK_SHIFT_CONST(7)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_ERR_CHK_EN_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_CMD_XFER_MODE_0_RESP_ERR_CHK_EN_SHIFT)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_ERR_CHK_EN_RANGE                   7:7
#define SDMMCAB_CMD_XFER_MODE_0_RESP_ERR_CHK_EN_WOFFSET                 0x0
#define SDMMCAB_CMD_XFER_MODE_0_RESP_ERR_CHK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_ERR_CHK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_ERR_CHK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_ERR_CHK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_ERR_CHK_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_ERR_CHK_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_ERR_CHK_EN_DISABLE                 _MK_ENUM_CONST(0)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_ERR_CHK_EN_ENABLE                  _MK_ENUM_CONST(1)

#define SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_SHIFT                 _MK_SHIFT_CONST(6)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_SHIFT)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_RANGE                 6:6
#define SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_WOFFSET                       0x0
#define SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_R1                    _MK_ENUM_CONST(0)
#define SDMMCAB_CMD_XFER_MODE_0_RESP_TYPE_R5                    _MK_ENUM_CONST(1)

#define SDMMCAB_CMD_XFER_MODE_0_MULTI_BLOCK_SELECT_SHIFT                        _MK_SHIFT_CONST(5)
#define SDMMCAB_CMD_XFER_MODE_0_MULTI_BLOCK_SELECT_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_CMD_XFER_MODE_0_MULTI_BLOCK_SELECT_SHIFT)
#define SDMMCAB_CMD_XFER_MODE_0_MULTI_BLOCK_SELECT_RANGE                        5:5
#define SDMMCAB_CMD_XFER_MODE_0_MULTI_BLOCK_SELECT_WOFFSET                      0x0
#define SDMMCAB_CMD_XFER_MODE_0_MULTI_BLOCK_SELECT_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_MULTI_BLOCK_SELECT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_CMD_XFER_MODE_0_MULTI_BLOCK_SELECT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_MULTI_BLOCK_SELECT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_MULTI_BLOCK_SELECT_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_MULTI_BLOCK_SELECT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_CMD_XFER_MODE_0_MULTI_BLOCK_SELECT_DISABLE                      _MK_ENUM_CONST(0)
#define SDMMCAB_CMD_XFER_MODE_0_MULTI_BLOCK_SELECT_ENABLE                       _MK_ENUM_CONST(1)

#define SDMMCAB_CMD_XFER_MODE_0_DATA_XFER_DIR_SEL_SHIFT                 _MK_SHIFT_CONST(4)
#define SDMMCAB_CMD_XFER_MODE_0_DATA_XFER_DIR_SEL_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_CMD_XFER_MODE_0_DATA_XFER_DIR_SEL_SHIFT)
#define SDMMCAB_CMD_XFER_MODE_0_DATA_XFER_DIR_SEL_RANGE                 4:4
#define SDMMCAB_CMD_XFER_MODE_0_DATA_XFER_DIR_SEL_WOFFSET                       0x0
#define SDMMCAB_CMD_XFER_MODE_0_DATA_XFER_DIR_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_DATA_XFER_DIR_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_CMD_XFER_MODE_0_DATA_XFER_DIR_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_DATA_XFER_DIR_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_DATA_XFER_DIR_SEL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_DATA_XFER_DIR_SEL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_CMD_XFER_MODE_0_DATA_XFER_DIR_SEL_WRITE                 _MK_ENUM_CONST(0)
#define SDMMCAB_CMD_XFER_MODE_0_DATA_XFER_DIR_SEL_READ                  _MK_ENUM_CONST(1)

#define SDMMCAB_CMD_XFER_MODE_0_AUTO_CMD12_EN_SHIFT                     _MK_SHIFT_CONST(2)
#define SDMMCAB_CMD_XFER_MODE_0_AUTO_CMD12_EN_FIELD                     _MK_FIELD_CONST(0x3, SDMMCAB_CMD_XFER_MODE_0_AUTO_CMD12_EN_SHIFT)
#define SDMMCAB_CMD_XFER_MODE_0_AUTO_CMD12_EN_RANGE                     3:2
#define SDMMCAB_CMD_XFER_MODE_0_AUTO_CMD12_EN_WOFFSET                   0x0
#define SDMMCAB_CMD_XFER_MODE_0_AUTO_CMD12_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_AUTO_CMD12_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define SDMMCAB_CMD_XFER_MODE_0_AUTO_CMD12_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_AUTO_CMD12_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_AUTO_CMD12_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_AUTO_CMD12_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_CMD_XFER_MODE_0_AUTO_CMD12_EN_DISABLE                   _MK_ENUM_CONST(0)
#define SDMMCAB_CMD_XFER_MODE_0_AUTO_CMD12_EN_CMD12                     _MK_ENUM_CONST(1)
#define SDMMCAB_CMD_XFER_MODE_0_AUTO_CMD12_EN_CMD23                     _MK_ENUM_CONST(2)
#define SDMMCAB_CMD_XFER_MODE_0_AUTO_CMD12_EN_AUTO_CMD_AUTO_SEL                 _MK_ENUM_CONST(3)

#define SDMMCAB_CMD_XFER_MODE_0_BLOCK_COUNT_EN_SHIFT                    _MK_SHIFT_CONST(1)
#define SDMMCAB_CMD_XFER_MODE_0_BLOCK_COUNT_EN_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_CMD_XFER_MODE_0_BLOCK_COUNT_EN_SHIFT)
#define SDMMCAB_CMD_XFER_MODE_0_BLOCK_COUNT_EN_RANGE                    1:1
#define SDMMCAB_CMD_XFER_MODE_0_BLOCK_COUNT_EN_WOFFSET                  0x0
#define SDMMCAB_CMD_XFER_MODE_0_BLOCK_COUNT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_BLOCK_COUNT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_CMD_XFER_MODE_0_BLOCK_COUNT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_BLOCK_COUNT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_BLOCK_COUNT_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_BLOCK_COUNT_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_CMD_XFER_MODE_0_BLOCK_COUNT_EN_DISABLE                  _MK_ENUM_CONST(0)
#define SDMMCAB_CMD_XFER_MODE_0_BLOCK_COUNT_EN_ENABLE                   _MK_ENUM_CONST(1)

#define SDMMCAB_CMD_XFER_MODE_0_DMA_EN_SHIFT                    _MK_SHIFT_CONST(0)
#define SDMMCAB_CMD_XFER_MODE_0_DMA_EN_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_CMD_XFER_MODE_0_DMA_EN_SHIFT)
#define SDMMCAB_CMD_XFER_MODE_0_DMA_EN_RANGE                    0:0
#define SDMMCAB_CMD_XFER_MODE_0_DMA_EN_WOFFSET                  0x0
#define SDMMCAB_CMD_XFER_MODE_0_DMA_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_DMA_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_CMD_XFER_MODE_0_DMA_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_DMA_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_DMA_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CMD_XFER_MODE_0_DMA_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_CMD_XFER_MODE_0_DMA_EN_DISABLE                  _MK_ENUM_CONST(0)
#define SDMMCAB_CMD_XFER_MODE_0_DMA_EN_ENABLE                   _MK_ENUM_CONST(1)


// Register SDMMCAB_RESPONSE_R0_R1_0
#define SDMMCAB_RESPONSE_R0_R1_0                        _MK_ADDR_CONST(0x10)
#define SDMMCAB_RESPONSE_R0_R1_0_SECURE                         0x0
#define SDMMCAB_RESPONSE_R0_R1_0_DUAL                   0x0
#define SDMMCAB_RESPONSE_R0_R1_0_SCR                    0
#define SDMMCAB_RESPONSE_R0_R1_0_WORD_COUNT                     0x1
#define SDMMCAB_RESPONSE_R0_R1_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R0_R1_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_RESPONSE_R0_R1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R0_R1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R0_R1_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_RESPONSE_R0_R1_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R0_R1_0_CMD_RESP_31_16_SHIFT                   _MK_SHIFT_CONST(16)
#define SDMMCAB_RESPONSE_R0_R1_0_CMD_RESP_31_16_FIELD                   _MK_FIELD_CONST(0xffff, SDMMCAB_RESPONSE_R0_R1_0_CMD_RESP_31_16_SHIFT)
#define SDMMCAB_RESPONSE_R0_R1_0_CMD_RESP_31_16_RANGE                   31:16
#define SDMMCAB_RESPONSE_R0_R1_0_CMD_RESP_31_16_WOFFSET                 0x0
#define SDMMCAB_RESPONSE_R0_R1_0_CMD_RESP_31_16_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R0_R1_0_CMD_RESP_31_16_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define SDMMCAB_RESPONSE_R0_R1_0_CMD_RESP_31_16_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R0_R1_0_CMD_RESP_31_16_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R0_R1_0_CMD_RESP_31_16_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R0_R1_0_CMD_RESP_31_16_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SDMMCAB_RESPONSE_R0_R1_0_CMD_RESP_15_0_SHIFT                    _MK_SHIFT_CONST(0)
#define SDMMCAB_RESPONSE_R0_R1_0_CMD_RESP_15_0_FIELD                    _MK_FIELD_CONST(0xffff, SDMMCAB_RESPONSE_R0_R1_0_CMD_RESP_15_0_SHIFT)
#define SDMMCAB_RESPONSE_R0_R1_0_CMD_RESP_15_0_RANGE                    15:0
#define SDMMCAB_RESPONSE_R0_R1_0_CMD_RESP_15_0_WOFFSET                  0x0
#define SDMMCAB_RESPONSE_R0_R1_0_CMD_RESP_15_0_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R0_R1_0_CMD_RESP_15_0_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define SDMMCAB_RESPONSE_R0_R1_0_CMD_RESP_15_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R0_R1_0_CMD_RESP_15_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R0_R1_0_CMD_RESP_15_0_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R0_R1_0_CMD_RESP_15_0_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register SDMMCAB_RESPONSE_R2_R3_0
#define SDMMCAB_RESPONSE_R2_R3_0                        _MK_ADDR_CONST(0x14)
#define SDMMCAB_RESPONSE_R2_R3_0_SECURE                         0x0
#define SDMMCAB_RESPONSE_R2_R3_0_DUAL                   0x0
#define SDMMCAB_RESPONSE_R2_R3_0_SCR                    0
#define SDMMCAB_RESPONSE_R2_R3_0_WORD_COUNT                     0x1
#define SDMMCAB_RESPONSE_R2_R3_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R2_R3_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_RESPONSE_R2_R3_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R2_R3_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R2_R3_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_RESPONSE_R2_R3_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R2_R3_0_CMD_RESP_63_48_SHIFT                   _MK_SHIFT_CONST(16)
#define SDMMCAB_RESPONSE_R2_R3_0_CMD_RESP_63_48_FIELD                   _MK_FIELD_CONST(0xffff, SDMMCAB_RESPONSE_R2_R3_0_CMD_RESP_63_48_SHIFT)
#define SDMMCAB_RESPONSE_R2_R3_0_CMD_RESP_63_48_RANGE                   31:16
#define SDMMCAB_RESPONSE_R2_R3_0_CMD_RESP_63_48_WOFFSET                 0x0
#define SDMMCAB_RESPONSE_R2_R3_0_CMD_RESP_63_48_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R2_R3_0_CMD_RESP_63_48_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define SDMMCAB_RESPONSE_R2_R3_0_CMD_RESP_63_48_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R2_R3_0_CMD_RESP_63_48_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R2_R3_0_CMD_RESP_63_48_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R2_R3_0_CMD_RESP_63_48_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SDMMCAB_RESPONSE_R2_R3_0_CMD_RESP_47_32_SHIFT                   _MK_SHIFT_CONST(0)
#define SDMMCAB_RESPONSE_R2_R3_0_CMD_RESP_47_32_FIELD                   _MK_FIELD_CONST(0xffff, SDMMCAB_RESPONSE_R2_R3_0_CMD_RESP_47_32_SHIFT)
#define SDMMCAB_RESPONSE_R2_R3_0_CMD_RESP_47_32_RANGE                   15:0
#define SDMMCAB_RESPONSE_R2_R3_0_CMD_RESP_47_32_WOFFSET                 0x0
#define SDMMCAB_RESPONSE_R2_R3_0_CMD_RESP_47_32_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R2_R3_0_CMD_RESP_47_32_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define SDMMCAB_RESPONSE_R2_R3_0_CMD_RESP_47_32_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R2_R3_0_CMD_RESP_47_32_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R2_R3_0_CMD_RESP_47_32_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R2_R3_0_CMD_RESP_47_32_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register SDMMCAB_RESPONSE_R4_R5_0
#define SDMMCAB_RESPONSE_R4_R5_0                        _MK_ADDR_CONST(0x18)
#define SDMMCAB_RESPONSE_R4_R5_0_SECURE                         0x0
#define SDMMCAB_RESPONSE_R4_R5_0_DUAL                   0x0
#define SDMMCAB_RESPONSE_R4_R5_0_SCR                    0
#define SDMMCAB_RESPONSE_R4_R5_0_WORD_COUNT                     0x1
#define SDMMCAB_RESPONSE_R4_R5_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R4_R5_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_RESPONSE_R4_R5_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R4_R5_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R4_R5_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_RESPONSE_R4_R5_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R4_R5_0_CMD_RESP_95_80_SHIFT                   _MK_SHIFT_CONST(16)
#define SDMMCAB_RESPONSE_R4_R5_0_CMD_RESP_95_80_FIELD                   _MK_FIELD_CONST(0xffff, SDMMCAB_RESPONSE_R4_R5_0_CMD_RESP_95_80_SHIFT)
#define SDMMCAB_RESPONSE_R4_R5_0_CMD_RESP_95_80_RANGE                   31:16
#define SDMMCAB_RESPONSE_R4_R5_0_CMD_RESP_95_80_WOFFSET                 0x0
#define SDMMCAB_RESPONSE_R4_R5_0_CMD_RESP_95_80_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R4_R5_0_CMD_RESP_95_80_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define SDMMCAB_RESPONSE_R4_R5_0_CMD_RESP_95_80_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R4_R5_0_CMD_RESP_95_80_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R4_R5_0_CMD_RESP_95_80_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R4_R5_0_CMD_RESP_95_80_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SDMMCAB_RESPONSE_R4_R5_0_CMD_RESP_79_64_SHIFT                   _MK_SHIFT_CONST(0)
#define SDMMCAB_RESPONSE_R4_R5_0_CMD_RESP_79_64_FIELD                   _MK_FIELD_CONST(0xffff, SDMMCAB_RESPONSE_R4_R5_0_CMD_RESP_79_64_SHIFT)
#define SDMMCAB_RESPONSE_R4_R5_0_CMD_RESP_79_64_RANGE                   15:0
#define SDMMCAB_RESPONSE_R4_R5_0_CMD_RESP_79_64_WOFFSET                 0x0
#define SDMMCAB_RESPONSE_R4_R5_0_CMD_RESP_79_64_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R4_R5_0_CMD_RESP_79_64_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define SDMMCAB_RESPONSE_R4_R5_0_CMD_RESP_79_64_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R4_R5_0_CMD_RESP_79_64_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R4_R5_0_CMD_RESP_79_64_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R4_R5_0_CMD_RESP_79_64_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register SDMMCAB_RESPONSE_R6_R7_0
#define SDMMCAB_RESPONSE_R6_R7_0                        _MK_ADDR_CONST(0x1c)
#define SDMMCAB_RESPONSE_R6_R7_0_SECURE                         0x0
#define SDMMCAB_RESPONSE_R6_R7_0_DUAL                   0x0
#define SDMMCAB_RESPONSE_R6_R7_0_SCR                    0
#define SDMMCAB_RESPONSE_R6_R7_0_WORD_COUNT                     0x1
#define SDMMCAB_RESPONSE_R6_R7_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R6_R7_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_RESPONSE_R6_R7_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R6_R7_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R6_R7_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_RESPONSE_R6_R7_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R6_R7_0_CMD_RESP_127_112_SHIFT                 _MK_SHIFT_CONST(16)
#define SDMMCAB_RESPONSE_R6_R7_0_CMD_RESP_127_112_FIELD                 _MK_FIELD_CONST(0xffff, SDMMCAB_RESPONSE_R6_R7_0_CMD_RESP_127_112_SHIFT)
#define SDMMCAB_RESPONSE_R6_R7_0_CMD_RESP_127_112_RANGE                 31:16
#define SDMMCAB_RESPONSE_R6_R7_0_CMD_RESP_127_112_WOFFSET                       0x0
#define SDMMCAB_RESPONSE_R6_R7_0_CMD_RESP_127_112_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R6_R7_0_CMD_RESP_127_112_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define SDMMCAB_RESPONSE_R6_R7_0_CMD_RESP_127_112_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R6_R7_0_CMD_RESP_127_112_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R6_R7_0_CMD_RESP_127_112_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R6_R7_0_CMD_RESP_127_112_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SDMMCAB_RESPONSE_R6_R7_0_CMD_RESP_111_96_SHIFT                  _MK_SHIFT_CONST(0)
#define SDMMCAB_RESPONSE_R6_R7_0_CMD_RESP_111_96_FIELD                  _MK_FIELD_CONST(0xffff, SDMMCAB_RESPONSE_R6_R7_0_CMD_RESP_111_96_SHIFT)
#define SDMMCAB_RESPONSE_R6_R7_0_CMD_RESP_111_96_RANGE                  15:0
#define SDMMCAB_RESPONSE_R6_R7_0_CMD_RESP_111_96_WOFFSET                        0x0
#define SDMMCAB_RESPONSE_R6_R7_0_CMD_RESP_111_96_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R6_R7_0_CMD_RESP_111_96_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
#define SDMMCAB_RESPONSE_R6_R7_0_CMD_RESP_111_96_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R6_R7_0_CMD_RESP_111_96_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R6_R7_0_CMD_RESP_111_96_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_RESPONSE_R6_R7_0_CMD_RESP_111_96_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register SDMMCAB_BUFFER_DATA_PORT_0
#define SDMMCAB_BUFFER_DATA_PORT_0                      _MK_ADDR_CONST(0x20)
#define SDMMCAB_BUFFER_DATA_PORT_0_SECURE                       0x0
#define SDMMCAB_BUFFER_DATA_PORT_0_DUAL                         0x0
#define SDMMCAB_BUFFER_DATA_PORT_0_SCR                  0
#define SDMMCAB_BUFFER_DATA_PORT_0_WORD_COUNT                   0x1
#define SDMMCAB_BUFFER_DATA_PORT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SDMMCAB_BUFFER_DATA_PORT_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_BUFFER_DATA_PORT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SDMMCAB_BUFFER_DATA_PORT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_BUFFER_DATA_PORT_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_BUFFER_DATA_PORT_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_BUFFER_DATA_PORT_0_BUFFER_DATA_SHIFT                    _MK_SHIFT_CONST(0)
#define SDMMCAB_BUFFER_DATA_PORT_0_BUFFER_DATA_FIELD                    _MK_FIELD_CONST(0xffffffff, SDMMCAB_BUFFER_DATA_PORT_0_BUFFER_DATA_SHIFT)
#define SDMMCAB_BUFFER_DATA_PORT_0_BUFFER_DATA_RANGE                    31:0
#define SDMMCAB_BUFFER_DATA_PORT_0_BUFFER_DATA_WOFFSET                  0x0
#define SDMMCAB_BUFFER_DATA_PORT_0_BUFFER_DATA_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_BUFFER_DATA_PORT_0_BUFFER_DATA_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_BUFFER_DATA_PORT_0_BUFFER_DATA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_BUFFER_DATA_PORT_0_BUFFER_DATA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_BUFFER_DATA_PORT_0_BUFFER_DATA_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_BUFFER_DATA_PORT_0_BUFFER_DATA_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register SDMMCAB_PRESENT_STATE_0
#define SDMMCAB_PRESENT_STATE_0                 _MK_ADDR_CONST(0x24)
#define SDMMCAB_PRESENT_STATE_0_SECURE                  0x0
#define SDMMCAB_PRESENT_STATE_0_DUAL                    0x0
#define SDMMCAB_PRESENT_STATE_0_SCR                     0
#define SDMMCAB_PRESENT_STATE_0_WORD_COUNT                      0x1
#define SDMMCAB_PRESENT_STATE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_RESET_MASK                      _MK_MASK_CONST(0x1bff0fff)
#define SDMMCAB_PRESENT_STATE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_READ_MASK                       _MK_MASK_CONST(0x1bff0fff)
#define SDMMCAB_PRESENT_STATE_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_SUB_CMD_STATUS_SHIFT                    _MK_SHIFT_CONST(28)
#define SDMMCAB_PRESENT_STATE_0_SUB_CMD_STATUS_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_PRESENT_STATE_0_SUB_CMD_STATUS_SHIFT)
#define SDMMCAB_PRESENT_STATE_0_SUB_CMD_STATUS_RANGE                    28:28
#define SDMMCAB_PRESENT_STATE_0_SUB_CMD_STATUS_WOFFSET                  0x0
#define SDMMCAB_PRESENT_STATE_0_SUB_CMD_STATUS_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_SUB_CMD_STATUS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_SUB_CMD_STATUS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_SUB_CMD_STATUS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_SUB_CMD_STATUS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_SUB_CMD_STATUS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SDMMCAB_PRESENT_STATE_0_CMD_NOT_ISSUED_BY_ERROR_SHIFT                   _MK_SHIFT_CONST(27)
#define SDMMCAB_PRESENT_STATE_0_CMD_NOT_ISSUED_BY_ERROR_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_PRESENT_STATE_0_CMD_NOT_ISSUED_BY_ERROR_SHIFT)
#define SDMMCAB_PRESENT_STATE_0_CMD_NOT_ISSUED_BY_ERROR_RANGE                   27:27
#define SDMMCAB_PRESENT_STATE_0_CMD_NOT_ISSUED_BY_ERROR_WOFFSET                 0x0
#define SDMMCAB_PRESENT_STATE_0_CMD_NOT_ISSUED_BY_ERROR_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CMD_NOT_ISSUED_BY_ERROR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_CMD_NOT_ISSUED_BY_ERROR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CMD_NOT_ISSUED_BY_ERROR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CMD_NOT_ISSUED_BY_ERROR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CMD_NOT_ISSUED_BY_ERROR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SDMMCAB_PRESENT_STATE_0_HOST_REG_VOLTAGE_STABLE_SHIFT                   _MK_SHIFT_CONST(25)
#define SDMMCAB_PRESENT_STATE_0_HOST_REG_VOLTAGE_STABLE_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_PRESENT_STATE_0_HOST_REG_VOLTAGE_STABLE_SHIFT)
#define SDMMCAB_PRESENT_STATE_0_HOST_REG_VOLTAGE_STABLE_RANGE                   25:25
#define SDMMCAB_PRESENT_STATE_0_HOST_REG_VOLTAGE_STABLE_WOFFSET                 0x0
#define SDMMCAB_PRESENT_STATE_0_HOST_REG_VOLTAGE_STABLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_HOST_REG_VOLTAGE_STABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_HOST_REG_VOLTAGE_STABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_HOST_REG_VOLTAGE_STABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_HOST_REG_VOLTAGE_STABLE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_HOST_REG_VOLTAGE_STABLE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SDMMCAB_PRESENT_STATE_0_CMD_LINE_LEVEL_SHIFT                    _MK_SHIFT_CONST(24)
#define SDMMCAB_PRESENT_STATE_0_CMD_LINE_LEVEL_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_PRESENT_STATE_0_CMD_LINE_LEVEL_SHIFT)
#define SDMMCAB_PRESENT_STATE_0_CMD_LINE_LEVEL_RANGE                    24:24
#define SDMMCAB_PRESENT_STATE_0_CMD_LINE_LEVEL_WOFFSET                  0x0
#define SDMMCAB_PRESENT_STATE_0_CMD_LINE_LEVEL_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CMD_LINE_LEVEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_CMD_LINE_LEVEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CMD_LINE_LEVEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CMD_LINE_LEVEL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CMD_LINE_LEVEL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_CMD_LINE_LEVEL_LOW                      _MK_ENUM_CONST(0)
#define SDMMCAB_PRESENT_STATE_0_CMD_LINE_LEVEL_HIGH                     _MK_ENUM_CONST(1)

#define SDMMCAB_PRESENT_STATE_0_DAT_3_0_LINE_LEVEL_SHIFT                        _MK_SHIFT_CONST(20)
#define SDMMCAB_PRESENT_STATE_0_DAT_3_0_LINE_LEVEL_FIELD                        _MK_FIELD_CONST(0xf, SDMMCAB_PRESENT_STATE_0_DAT_3_0_LINE_LEVEL_SHIFT)
#define SDMMCAB_PRESENT_STATE_0_DAT_3_0_LINE_LEVEL_RANGE                        23:20
#define SDMMCAB_PRESENT_STATE_0_DAT_3_0_LINE_LEVEL_WOFFSET                      0x0
#define SDMMCAB_PRESENT_STATE_0_DAT_3_0_LINE_LEVEL_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_DAT_3_0_LINE_LEVEL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define SDMMCAB_PRESENT_STATE_0_DAT_3_0_LINE_LEVEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_DAT_3_0_LINE_LEVEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_DAT_3_0_LINE_LEVEL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_DAT_3_0_LINE_LEVEL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SDMMCAB_PRESENT_STATE_0_WRITE_PROTECT_LEVEL_SHIFT                       _MK_SHIFT_CONST(19)
#define SDMMCAB_PRESENT_STATE_0_WRITE_PROTECT_LEVEL_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_PRESENT_STATE_0_WRITE_PROTECT_LEVEL_SHIFT)
#define SDMMCAB_PRESENT_STATE_0_WRITE_PROTECT_LEVEL_RANGE                       19:19
#define SDMMCAB_PRESENT_STATE_0_WRITE_PROTECT_LEVEL_WOFFSET                     0x0
#define SDMMCAB_PRESENT_STATE_0_WRITE_PROTECT_LEVEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_WRITE_PROTECT_LEVEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_WRITE_PROTECT_LEVEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_WRITE_PROTECT_LEVEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_WRITE_PROTECT_LEVEL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_WRITE_PROTECT_LEVEL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_WRITE_PROTECT_LEVEL_PROTECTED                   _MK_ENUM_CONST(0)
#define SDMMCAB_PRESENT_STATE_0_WRITE_PROTECT_LEVEL_ENABLED                     _MK_ENUM_CONST(1)
#define SDMMCAB_PRESENT_STATE_0_WRITE_PROTECT_LEVEL__PROD                       _MK_ENUM_CONST(1)

#define SDMMCAB_PRESENT_STATE_0_CARD_DETECT_PIN_LEVEL_SHIFT                     _MK_SHIFT_CONST(18)
#define SDMMCAB_PRESENT_STATE_0_CARD_DETECT_PIN_LEVEL_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_PRESENT_STATE_0_CARD_DETECT_PIN_LEVEL_SHIFT)
#define SDMMCAB_PRESENT_STATE_0_CARD_DETECT_PIN_LEVEL_RANGE                     18:18
#define SDMMCAB_PRESENT_STATE_0_CARD_DETECT_PIN_LEVEL_WOFFSET                   0x0
#define SDMMCAB_PRESENT_STATE_0_CARD_DETECT_PIN_LEVEL_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CARD_DETECT_PIN_LEVEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_CARD_DETECT_PIN_LEVEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CARD_DETECT_PIN_LEVEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CARD_DETECT_PIN_LEVEL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CARD_DETECT_PIN_LEVEL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_CARD_DETECT_PIN_LEVEL_NO_CARD                   _MK_ENUM_CONST(0)
#define SDMMCAB_PRESENT_STATE_0_CARD_DETECT_PIN_LEVEL_CARD                      _MK_ENUM_CONST(1)

#define SDMMCAB_PRESENT_STATE_0_CARD_STATE_STABLE_SHIFT                 _MK_SHIFT_CONST(17)
#define SDMMCAB_PRESENT_STATE_0_CARD_STATE_STABLE_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_PRESENT_STATE_0_CARD_STATE_STABLE_SHIFT)
#define SDMMCAB_PRESENT_STATE_0_CARD_STATE_STABLE_RANGE                 17:17
#define SDMMCAB_PRESENT_STATE_0_CARD_STATE_STABLE_WOFFSET                       0x0
#define SDMMCAB_PRESENT_STATE_0_CARD_STATE_STABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CARD_STATE_STABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_CARD_STATE_STABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CARD_STATE_STABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CARD_STATE_STABLE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CARD_STATE_STABLE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_CARD_STATE_STABLE_DEBOUNCE                      _MK_ENUM_CONST(0)
#define SDMMCAB_PRESENT_STATE_0_CARD_STATE_STABLE_INSERTED                      _MK_ENUM_CONST(1)
#define SDMMCAB_PRESENT_STATE_0_CARD_STATE_STABLE__PROD                 _MK_ENUM_CONST(1)

#define SDMMCAB_PRESENT_STATE_0_CARD_INSERTED_SHIFT                     _MK_SHIFT_CONST(16)
#define SDMMCAB_PRESENT_STATE_0_CARD_INSERTED_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_PRESENT_STATE_0_CARD_INSERTED_SHIFT)
#define SDMMCAB_PRESENT_STATE_0_CARD_INSERTED_RANGE                     16:16
#define SDMMCAB_PRESENT_STATE_0_CARD_INSERTED_WOFFSET                   0x0
#define SDMMCAB_PRESENT_STATE_0_CARD_INSERTED_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CARD_INSERTED_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_CARD_INSERTED_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CARD_INSERTED_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CARD_INSERTED_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CARD_INSERTED_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_CARD_INSERTED_DEBOUNCE                  _MK_ENUM_CONST(0)
#define SDMMCAB_PRESENT_STATE_0_CARD_INSERTED_INSERTED                  _MK_ENUM_CONST(1)
#define SDMMCAB_PRESENT_STATE_0_CARD_INSERTED__PROD                     _MK_ENUM_CONST(1)

#define SDMMCAB_PRESENT_STATE_0_BUFFER_READ_EN_SHIFT                    _MK_SHIFT_CONST(11)
#define SDMMCAB_PRESENT_STATE_0_BUFFER_READ_EN_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_PRESENT_STATE_0_BUFFER_READ_EN_SHIFT)
#define SDMMCAB_PRESENT_STATE_0_BUFFER_READ_EN_RANGE                    11:11
#define SDMMCAB_PRESENT_STATE_0_BUFFER_READ_EN_WOFFSET                  0x0
#define SDMMCAB_PRESENT_STATE_0_BUFFER_READ_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_BUFFER_READ_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_BUFFER_READ_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_BUFFER_READ_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_BUFFER_READ_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_BUFFER_READ_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_BUFFER_READ_EN_DISABLE                  _MK_ENUM_CONST(0)
#define SDMMCAB_PRESENT_STATE_0_BUFFER_READ_EN_ENABLE                   _MK_ENUM_CONST(1)

#define SDMMCAB_PRESENT_STATE_0_BUFFER_WRITE_EN_SHIFT                   _MK_SHIFT_CONST(10)
#define SDMMCAB_PRESENT_STATE_0_BUFFER_WRITE_EN_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_PRESENT_STATE_0_BUFFER_WRITE_EN_SHIFT)
#define SDMMCAB_PRESENT_STATE_0_BUFFER_WRITE_EN_RANGE                   10:10
#define SDMMCAB_PRESENT_STATE_0_BUFFER_WRITE_EN_WOFFSET                 0x0
#define SDMMCAB_PRESENT_STATE_0_BUFFER_WRITE_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_BUFFER_WRITE_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_BUFFER_WRITE_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_BUFFER_WRITE_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_BUFFER_WRITE_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_BUFFER_WRITE_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_BUFFER_WRITE_EN_DISABLE                 _MK_ENUM_CONST(0)
#define SDMMCAB_PRESENT_STATE_0_BUFFER_WRITE_EN_ENABLE                  _MK_ENUM_CONST(1)

#define SDMMCAB_PRESENT_STATE_0_READ_XFER_ACTIVE_SHIFT                  _MK_SHIFT_CONST(9)
#define SDMMCAB_PRESENT_STATE_0_READ_XFER_ACTIVE_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_PRESENT_STATE_0_READ_XFER_ACTIVE_SHIFT)
#define SDMMCAB_PRESENT_STATE_0_READ_XFER_ACTIVE_RANGE                  9:9
#define SDMMCAB_PRESENT_STATE_0_READ_XFER_ACTIVE_WOFFSET                        0x0
#define SDMMCAB_PRESENT_STATE_0_READ_XFER_ACTIVE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_READ_XFER_ACTIVE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_READ_XFER_ACTIVE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_READ_XFER_ACTIVE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_READ_XFER_ACTIVE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_READ_XFER_ACTIVE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_READ_XFER_ACTIVE_NO_DATA                        _MK_ENUM_CONST(0)
#define SDMMCAB_PRESENT_STATE_0_READ_XFER_ACTIVE_TRANSFERING                    _MK_ENUM_CONST(1)

#define SDMMCAB_PRESENT_STATE_0_WRITE_XFER_ACTIVE_SHIFT                 _MK_SHIFT_CONST(8)
#define SDMMCAB_PRESENT_STATE_0_WRITE_XFER_ACTIVE_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_PRESENT_STATE_0_WRITE_XFER_ACTIVE_SHIFT)
#define SDMMCAB_PRESENT_STATE_0_WRITE_XFER_ACTIVE_RANGE                 8:8
#define SDMMCAB_PRESENT_STATE_0_WRITE_XFER_ACTIVE_WOFFSET                       0x0
#define SDMMCAB_PRESENT_STATE_0_WRITE_XFER_ACTIVE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_WRITE_XFER_ACTIVE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_WRITE_XFER_ACTIVE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_WRITE_XFER_ACTIVE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_WRITE_XFER_ACTIVE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_WRITE_XFER_ACTIVE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_WRITE_XFER_ACTIVE_NO_DATA                       _MK_ENUM_CONST(0)
#define SDMMCAB_PRESENT_STATE_0_WRITE_XFER_ACTIVE_TRANSFERING                   _MK_ENUM_CONST(1)

#define SDMMCAB_PRESENT_STATE_0_DAT_7_4_LINE_LEVEL_SHIFT                        _MK_SHIFT_CONST(4)
#define SDMMCAB_PRESENT_STATE_0_DAT_7_4_LINE_LEVEL_FIELD                        _MK_FIELD_CONST(0xf, SDMMCAB_PRESENT_STATE_0_DAT_7_4_LINE_LEVEL_SHIFT)
#define SDMMCAB_PRESENT_STATE_0_DAT_7_4_LINE_LEVEL_RANGE                        7:4
#define SDMMCAB_PRESENT_STATE_0_DAT_7_4_LINE_LEVEL_WOFFSET                      0x0
#define SDMMCAB_PRESENT_STATE_0_DAT_7_4_LINE_LEVEL_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_DAT_7_4_LINE_LEVEL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define SDMMCAB_PRESENT_STATE_0_DAT_7_4_LINE_LEVEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_DAT_7_4_LINE_LEVEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_DAT_7_4_LINE_LEVEL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_DAT_7_4_LINE_LEVEL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SDMMCAB_PRESENT_STATE_0_RETUNING_REQUEST_SHIFT                  _MK_SHIFT_CONST(3)
#define SDMMCAB_PRESENT_STATE_0_RETUNING_REQUEST_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_PRESENT_STATE_0_RETUNING_REQUEST_SHIFT)
#define SDMMCAB_PRESENT_STATE_0_RETUNING_REQUEST_RANGE                  3:3
#define SDMMCAB_PRESENT_STATE_0_RETUNING_REQUEST_WOFFSET                        0x0
#define SDMMCAB_PRESENT_STATE_0_RETUNING_REQUEST_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_RETUNING_REQUEST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_RETUNING_REQUEST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_RETUNING_REQUEST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_RETUNING_REQUEST_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_RETUNING_REQUEST_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_RETUNING_REQUEST_NOT_REQUIRED                   _MK_ENUM_CONST(0)
#define SDMMCAB_PRESENT_STATE_0_RETUNING_REQUEST_REQUIRED                       _MK_ENUM_CONST(1)

#define SDMMCAB_PRESENT_STATE_0_DAT_LINE_ACTIVE_SHIFT                   _MK_SHIFT_CONST(2)
#define SDMMCAB_PRESENT_STATE_0_DAT_LINE_ACTIVE_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_PRESENT_STATE_0_DAT_LINE_ACTIVE_SHIFT)
#define SDMMCAB_PRESENT_STATE_0_DAT_LINE_ACTIVE_RANGE                   2:2
#define SDMMCAB_PRESENT_STATE_0_DAT_LINE_ACTIVE_WOFFSET                 0x0
#define SDMMCAB_PRESENT_STATE_0_DAT_LINE_ACTIVE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_DAT_LINE_ACTIVE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_DAT_LINE_ACTIVE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_DAT_LINE_ACTIVE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_DAT_LINE_ACTIVE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_DAT_LINE_ACTIVE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_DAT_LINE_ACTIVE_INACTIVE                        _MK_ENUM_CONST(0)
#define SDMMCAB_PRESENT_STATE_0_DAT_LINE_ACTIVE_ACTIVE                  _MK_ENUM_CONST(1)

#define SDMMCAB_PRESENT_STATE_0_CMD_INHIBIT_DAT_SHIFT                   _MK_SHIFT_CONST(1)
#define SDMMCAB_PRESENT_STATE_0_CMD_INHIBIT_DAT_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_PRESENT_STATE_0_CMD_INHIBIT_DAT_SHIFT)
#define SDMMCAB_PRESENT_STATE_0_CMD_INHIBIT_DAT_RANGE                   1:1
#define SDMMCAB_PRESENT_STATE_0_CMD_INHIBIT_DAT_WOFFSET                 0x0
#define SDMMCAB_PRESENT_STATE_0_CMD_INHIBIT_DAT_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CMD_INHIBIT_DAT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_CMD_INHIBIT_DAT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CMD_INHIBIT_DAT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CMD_INHIBIT_DAT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CMD_INHIBIT_DAT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_CMD_INHIBIT_DAT_INACTIVE                        _MK_ENUM_CONST(0)
#define SDMMCAB_PRESENT_STATE_0_CMD_INHIBIT_DAT_ACTIVE                  _MK_ENUM_CONST(1)

#define SDMMCAB_PRESENT_STATE_0_CMD_INHIBIT_CMD_SHIFT                   _MK_SHIFT_CONST(0)
#define SDMMCAB_PRESENT_STATE_0_CMD_INHIBIT_CMD_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_PRESENT_STATE_0_CMD_INHIBIT_CMD_SHIFT)
#define SDMMCAB_PRESENT_STATE_0_CMD_INHIBIT_CMD_RANGE                   0:0
#define SDMMCAB_PRESENT_STATE_0_CMD_INHIBIT_CMD_WOFFSET                 0x0
#define SDMMCAB_PRESENT_STATE_0_CMD_INHIBIT_CMD_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CMD_INHIBIT_CMD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_CMD_INHIBIT_CMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CMD_INHIBIT_CMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CMD_INHIBIT_CMD_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESENT_STATE_0_CMD_INHIBIT_CMD_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESENT_STATE_0_CMD_INHIBIT_CMD_INACTIVE                        _MK_ENUM_CONST(0)
#define SDMMCAB_PRESENT_STATE_0_CMD_INHIBIT_CMD_ACTIVE                  _MK_ENUM_CONST(1)


// Register SDMMCAB_POWER_CONTROL_HOST_0
#define SDMMCAB_POWER_CONTROL_HOST_0                    _MK_ADDR_CONST(0x28)
#define SDMMCAB_POWER_CONTROL_HOST_0_SECURE                     0x0
#define SDMMCAB_POWER_CONTROL_HOST_0_DUAL                       0x0
#define SDMMCAB_POWER_CONTROL_HOST_0_SCR                        0
#define SDMMCAB_POWER_CONTROL_HOST_0_WORD_COUNT                         0x1
#define SDMMCAB_POWER_CONTROL_HOST_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_RESET_MASK                         _MK_MASK_CONST(0x70f0fff)
#define SDMMCAB_POWER_CONTROL_HOST_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_READ_MASK                  _MK_MASK_CONST(0x70f0fff)
#define SDMMCAB_POWER_CONTROL_HOST_0_WRITE_MASK                         _MK_MASK_CONST(0x70f0fff)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_REMOVAL_SHIFT                       _MK_SHIFT_CONST(26)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_REMOVAL_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_REMOVAL_SHIFT)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_REMOVAL_RANGE                       26:26
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_REMOVAL_WOFFSET                     0x0
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_REMOVAL_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_REMOVAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_REMOVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_REMOVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_REMOVAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_REMOVAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_REMOVAL_DISABLE                     _MK_ENUM_CONST(0)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_REMOVAL_ENABLE                      _MK_ENUM_CONST(1)

#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INSERTION_SHIFT                     _MK_SHIFT_CONST(25)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INSERTION_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INSERTION_SHIFT)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INSERTION_RANGE                     25:25
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INSERTION_WOFFSET                   0x0
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INSERTION_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INSERTION_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INSERTION_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INSERTION_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INSERTION_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INSERTION_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INSERTION_DISABLE                   _MK_ENUM_CONST(0)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INSERTION_ENABLE                    _MK_ENUM_CONST(1)

#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INTERRUPT_SHIFT                     _MK_SHIFT_CONST(24)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INTERRUPT_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INTERRUPT_SHIFT)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INTERRUPT_RANGE                     24:24
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INTERRUPT_WOFFSET                   0x0
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INTERRUPT_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INTERRUPT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INTERRUPT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INTERRUPT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INTERRUPT_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INTERRUPT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INTERRUPT_DISABLE                   _MK_ENUM_CONST(0)
#define SDMMCAB_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INTERRUPT_ENABLE                    _MK_ENUM_CONST(1)

#define SDMMCAB_POWER_CONTROL_HOST_0_INTERRUPT_AT_BLOCK_GAP_SHIFT                       _MK_SHIFT_CONST(19)
#define SDMMCAB_POWER_CONTROL_HOST_0_INTERRUPT_AT_BLOCK_GAP_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_POWER_CONTROL_HOST_0_INTERRUPT_AT_BLOCK_GAP_SHIFT)
#define SDMMCAB_POWER_CONTROL_HOST_0_INTERRUPT_AT_BLOCK_GAP_RANGE                       19:19
#define SDMMCAB_POWER_CONTROL_HOST_0_INTERRUPT_AT_BLOCK_GAP_WOFFSET                     0x0
#define SDMMCAB_POWER_CONTROL_HOST_0_INTERRUPT_AT_BLOCK_GAP_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_INTERRUPT_AT_BLOCK_GAP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_INTERRUPT_AT_BLOCK_GAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_INTERRUPT_AT_BLOCK_GAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_INTERRUPT_AT_BLOCK_GAP_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_INTERRUPT_AT_BLOCK_GAP_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_INTERRUPT_AT_BLOCK_GAP_DISABLE                     _MK_ENUM_CONST(0)
#define SDMMCAB_POWER_CONTROL_HOST_0_INTERRUPT_AT_BLOCK_GAP_ENABLE                      _MK_ENUM_CONST(1)

#define SDMMCAB_POWER_CONTROL_HOST_0_READ_WAIT_CONTROL_SHIFT                    _MK_SHIFT_CONST(18)
#define SDMMCAB_POWER_CONTROL_HOST_0_READ_WAIT_CONTROL_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_POWER_CONTROL_HOST_0_READ_WAIT_CONTROL_SHIFT)
#define SDMMCAB_POWER_CONTROL_HOST_0_READ_WAIT_CONTROL_RANGE                    18:18
#define SDMMCAB_POWER_CONTROL_HOST_0_READ_WAIT_CONTROL_WOFFSET                  0x0
#define SDMMCAB_POWER_CONTROL_HOST_0_READ_WAIT_CONTROL_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_READ_WAIT_CONTROL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_READ_WAIT_CONTROL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_READ_WAIT_CONTROL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_READ_WAIT_CONTROL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_READ_WAIT_CONTROL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_READ_WAIT_CONTROL_DISABLE                  _MK_ENUM_CONST(0)
#define SDMMCAB_POWER_CONTROL_HOST_0_READ_WAIT_CONTROL_ENABLE                   _MK_ENUM_CONST(1)

#define SDMMCAB_POWER_CONTROL_HOST_0_CONTINUE_REQUEST_SHIFT                     _MK_SHIFT_CONST(17)
#define SDMMCAB_POWER_CONTROL_HOST_0_CONTINUE_REQUEST_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_POWER_CONTROL_HOST_0_CONTINUE_REQUEST_SHIFT)
#define SDMMCAB_POWER_CONTROL_HOST_0_CONTINUE_REQUEST_RANGE                     17:17
#define SDMMCAB_POWER_CONTROL_HOST_0_CONTINUE_REQUEST_WOFFSET                   0x0
#define SDMMCAB_POWER_CONTROL_HOST_0_CONTINUE_REQUEST_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_CONTINUE_REQUEST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_CONTINUE_REQUEST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_CONTINUE_REQUEST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_CONTINUE_REQUEST_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_CONTINUE_REQUEST_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_CONTINUE_REQUEST_IGNORED                   _MK_ENUM_CONST(0)
#define SDMMCAB_POWER_CONTROL_HOST_0_CONTINUE_REQUEST_RESTART                   _MK_ENUM_CONST(1)

#define SDMMCAB_POWER_CONTROL_HOST_0_STOP_AT_BLOCK_GAP_REQUEST_SHIFT                    _MK_SHIFT_CONST(16)
#define SDMMCAB_POWER_CONTROL_HOST_0_STOP_AT_BLOCK_GAP_REQUEST_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_POWER_CONTROL_HOST_0_STOP_AT_BLOCK_GAP_REQUEST_SHIFT)
#define SDMMCAB_POWER_CONTROL_HOST_0_STOP_AT_BLOCK_GAP_REQUEST_RANGE                    16:16
#define SDMMCAB_POWER_CONTROL_HOST_0_STOP_AT_BLOCK_GAP_REQUEST_WOFFSET                  0x0
#define SDMMCAB_POWER_CONTROL_HOST_0_STOP_AT_BLOCK_GAP_REQUEST_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_STOP_AT_BLOCK_GAP_REQUEST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_STOP_AT_BLOCK_GAP_REQUEST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_STOP_AT_BLOCK_GAP_REQUEST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_STOP_AT_BLOCK_GAP_REQUEST_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_STOP_AT_BLOCK_GAP_REQUEST_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_STOP_AT_BLOCK_GAP_REQUEST_TRANSFER                 _MK_ENUM_CONST(0)
#define SDMMCAB_POWER_CONTROL_HOST_0_STOP_AT_BLOCK_GAP_REQUEST_STOP                     _MK_ENUM_CONST(1)

#define SDMMCAB_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_SHIFT                        _MK_SHIFT_CONST(9)
#define SDMMCAB_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_FIELD                        _MK_FIELD_CONST(0x7, SDMMCAB_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_SHIFT)
#define SDMMCAB_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_RANGE                        11:9
#define SDMMCAB_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_WOFFSET                      0x0
#define SDMMCAB_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define SDMMCAB_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_V1_8                 _MK_ENUM_CONST(5)
#define SDMMCAB_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_V3_0                 _MK_ENUM_CONST(6)
#define SDMMCAB_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_V3_3                 _MK_ENUM_CONST(7)

#define SDMMCAB_POWER_CONTROL_HOST_0_SD_BUS_POWER_SHIFT                 _MK_SHIFT_CONST(8)
#define SDMMCAB_POWER_CONTROL_HOST_0_SD_BUS_POWER_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_POWER_CONTROL_HOST_0_SD_BUS_POWER_SHIFT)
#define SDMMCAB_POWER_CONTROL_HOST_0_SD_BUS_POWER_RANGE                 8:8
#define SDMMCAB_POWER_CONTROL_HOST_0_SD_BUS_POWER_WOFFSET                       0x0
#define SDMMCAB_POWER_CONTROL_HOST_0_SD_BUS_POWER_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_SD_BUS_POWER_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_SD_BUS_POWER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_SD_BUS_POWER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_SD_BUS_POWER_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_SD_BUS_POWER_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_SD_BUS_POWER_POWER_OFF                     _MK_ENUM_CONST(0)
#define SDMMCAB_POWER_CONTROL_HOST_0_SD_BUS_POWER_POWER_ON                      _MK_ENUM_CONST(1)

#define SDMMCAB_POWER_CONTROL_HOST_0_CARD_DETECT_SIGNAL_DETECT_SHIFT                    _MK_SHIFT_CONST(7)
#define SDMMCAB_POWER_CONTROL_HOST_0_CARD_DETECT_SIGNAL_DETECT_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_POWER_CONTROL_HOST_0_CARD_DETECT_SIGNAL_DETECT_SHIFT)
#define SDMMCAB_POWER_CONTROL_HOST_0_CARD_DETECT_SIGNAL_DETECT_RANGE                    7:7
#define SDMMCAB_POWER_CONTROL_HOST_0_CARD_DETECT_SIGNAL_DETECT_WOFFSET                  0x0
#define SDMMCAB_POWER_CONTROL_HOST_0_CARD_DETECT_SIGNAL_DETECT_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_CARD_DETECT_SIGNAL_DETECT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_CARD_DETECT_SIGNAL_DETECT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_CARD_DETECT_SIGNAL_DETECT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_CARD_DETECT_SIGNAL_DETECT_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_CARD_DETECT_SIGNAL_DETECT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_CARD_DETECT_SIGNAL_DETECT_SDCD                     _MK_ENUM_CONST(0)
#define SDMMCAB_POWER_CONTROL_HOST_0_CARD_DETECT_SIGNAL_DETECT_CARD_DTECT_TST_LVL                       _MK_ENUM_CONST(1)

#define SDMMCAB_POWER_CONTROL_HOST_0_CARD_DETECT_TEST_LVL_SHIFT                 _MK_SHIFT_CONST(6)
#define SDMMCAB_POWER_CONTROL_HOST_0_CARD_DETECT_TEST_LVL_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_POWER_CONTROL_HOST_0_CARD_DETECT_TEST_LVL_SHIFT)
#define SDMMCAB_POWER_CONTROL_HOST_0_CARD_DETECT_TEST_LVL_RANGE                 6:6
#define SDMMCAB_POWER_CONTROL_HOST_0_CARD_DETECT_TEST_LVL_WOFFSET                       0x0
#define SDMMCAB_POWER_CONTROL_HOST_0_CARD_DETECT_TEST_LVL_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_CARD_DETECT_TEST_LVL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_CARD_DETECT_TEST_LVL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_CARD_DETECT_TEST_LVL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_CARD_DETECT_TEST_LVL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_CARD_DETECT_TEST_LVL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_CARD_DETECT_TEST_LVL_NO_CARD                       _MK_ENUM_CONST(0)
#define SDMMCAB_POWER_CONTROL_HOST_0_CARD_DETECT_TEST_LVL_CARD_INSERTED                 _MK_ENUM_CONST(1)

#define SDMMCAB_POWER_CONTROL_HOST_0_EXTENDED_DATA_TRANSFER_WIDTH_SHIFT                 _MK_SHIFT_CONST(5)
#define SDMMCAB_POWER_CONTROL_HOST_0_EXTENDED_DATA_TRANSFER_WIDTH_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_POWER_CONTROL_HOST_0_EXTENDED_DATA_TRANSFER_WIDTH_SHIFT)
#define SDMMCAB_POWER_CONTROL_HOST_0_EXTENDED_DATA_TRANSFER_WIDTH_RANGE                 5:5
#define SDMMCAB_POWER_CONTROL_HOST_0_EXTENDED_DATA_TRANSFER_WIDTH_WOFFSET                       0x0
#define SDMMCAB_POWER_CONTROL_HOST_0_EXTENDED_DATA_TRANSFER_WIDTH_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_EXTENDED_DATA_TRANSFER_WIDTH_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_EXTENDED_DATA_TRANSFER_WIDTH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_EXTENDED_DATA_TRANSFER_WIDTH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_EXTENDED_DATA_TRANSFER_WIDTH_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_EXTENDED_DATA_TRANSFER_WIDTH_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_EXTENDED_DATA_TRANSFER_WIDTH_NOBIT_8                       _MK_ENUM_CONST(0)
#define SDMMCAB_POWER_CONTROL_HOST_0_EXTENDED_DATA_TRANSFER_WIDTH_BIT_8                 _MK_ENUM_CONST(1)
#define SDMMCAB_POWER_CONTROL_HOST_0_EXTENDED_DATA_TRANSFER_WIDTH__PROD                 _MK_ENUM_CONST(1)

#define SDMMCAB_POWER_CONTROL_HOST_0_DMA_SELECT_SHIFT                   _MK_SHIFT_CONST(3)
#define SDMMCAB_POWER_CONTROL_HOST_0_DMA_SELECT_FIELD                   _MK_FIELD_CONST(0x3, SDMMCAB_POWER_CONTROL_HOST_0_DMA_SELECT_SHIFT)
#define SDMMCAB_POWER_CONTROL_HOST_0_DMA_SELECT_RANGE                   4:3
#define SDMMCAB_POWER_CONTROL_HOST_0_DMA_SELECT_WOFFSET                 0x0
#define SDMMCAB_POWER_CONTROL_HOST_0_DMA_SELECT_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_DMA_SELECT_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define SDMMCAB_POWER_CONTROL_HOST_0_DMA_SELECT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_DMA_SELECT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_DMA_SELECT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_DMA_SELECT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_DMA_SELECT_SDMA                    _MK_ENUM_CONST(0)
#define SDMMCAB_POWER_CONTROL_HOST_0_DMA_SELECT_RSVD                    _MK_ENUM_CONST(1)
#define SDMMCAB_POWER_CONTROL_HOST_0_DMA_SELECT_ADMA2                   _MK_ENUM_CONST(2)
#define SDMMCAB_POWER_CONTROL_HOST_0_DMA_SELECT_ADMA3_CQE                       _MK_ENUM_CONST(3)

#define SDMMCAB_POWER_CONTROL_HOST_0_HIGH_SPEED_EN_SHIFT                        _MK_SHIFT_CONST(2)
#define SDMMCAB_POWER_CONTROL_HOST_0_HIGH_SPEED_EN_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_POWER_CONTROL_HOST_0_HIGH_SPEED_EN_SHIFT)
#define SDMMCAB_POWER_CONTROL_HOST_0_HIGH_SPEED_EN_RANGE                        2:2
#define SDMMCAB_POWER_CONTROL_HOST_0_HIGH_SPEED_EN_WOFFSET                      0x0
#define SDMMCAB_POWER_CONTROL_HOST_0_HIGH_SPEED_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_HIGH_SPEED_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_HIGH_SPEED_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_HIGH_SPEED_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_HIGH_SPEED_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_HIGH_SPEED_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_HIGH_SPEED_EN_NORMAL_SPEED                 _MK_ENUM_CONST(0)
#define SDMMCAB_POWER_CONTROL_HOST_0_HIGH_SPEED_EN_HIGH_SPEED                   _MK_ENUM_CONST(1)

#define SDMMCAB_POWER_CONTROL_HOST_0_DATA_XFER_WIDTH_SHIFT                      _MK_SHIFT_CONST(1)
#define SDMMCAB_POWER_CONTROL_HOST_0_DATA_XFER_WIDTH_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_POWER_CONTROL_HOST_0_DATA_XFER_WIDTH_SHIFT)
#define SDMMCAB_POWER_CONTROL_HOST_0_DATA_XFER_WIDTH_RANGE                      1:1
#define SDMMCAB_POWER_CONTROL_HOST_0_DATA_XFER_WIDTH_WOFFSET                    0x0
#define SDMMCAB_POWER_CONTROL_HOST_0_DATA_XFER_WIDTH_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_DATA_XFER_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_DATA_XFER_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_DATA_XFER_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_DATA_XFER_WIDTH_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_DATA_XFER_WIDTH_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_DATA_XFER_WIDTH_BIT_1                      _MK_ENUM_CONST(0)
#define SDMMCAB_POWER_CONTROL_HOST_0_DATA_XFER_WIDTH_BIT_4                      _MK_ENUM_CONST(1)

#define SDMMCAB_POWER_CONTROL_HOST_0_LED_CONTROL_SHIFT                  _MK_SHIFT_CONST(0)
#define SDMMCAB_POWER_CONTROL_HOST_0_LED_CONTROL_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_POWER_CONTROL_HOST_0_LED_CONTROL_SHIFT)
#define SDMMCAB_POWER_CONTROL_HOST_0_LED_CONTROL_RANGE                  0:0
#define SDMMCAB_POWER_CONTROL_HOST_0_LED_CONTROL_WOFFSET                        0x0
#define SDMMCAB_POWER_CONTROL_HOST_0_LED_CONTROL_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_LED_CONTROL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_LED_CONTROL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_LED_CONTROL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_LED_CONTROL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_POWER_CONTROL_HOST_0_LED_CONTROL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_POWER_CONTROL_HOST_0_LED_CONTROL_OFF                    _MK_ENUM_CONST(0)
#define SDMMCAB_POWER_CONTROL_HOST_0_LED_CONTROL_ON                     _MK_ENUM_CONST(1)


// Register SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0                   _MK_ADDR_CONST(0x2c)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SECURE                    0x0
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_DUAL                      0x0
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SCR                       0
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_WORD_COUNT                        0x1
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_RESET_MASK                        _MK_MASK_CONST(0x70fffef)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_READ_MASK                         _MK_MASK_CONST(0x70fffef)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_WRITE_MASK                        _MK_MASK_CONST(0x70fffed)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_DAT_LINE_SHIFT                       _MK_SHIFT_CONST(26)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_DAT_LINE_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_DAT_LINE_SHIFT)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_DAT_LINE_RANGE                       26:26
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_DAT_LINE_WOFFSET                     0x0
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_DAT_LINE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_DAT_LINE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_DAT_LINE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_DAT_LINE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_DAT_LINE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_DAT_LINE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_DAT_LINE_WORK                        _MK_ENUM_CONST(0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_DAT_LINE_RESETED                     _MK_ENUM_CONST(1)

#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_CMD_LINE_SHIFT                       _MK_SHIFT_CONST(25)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_CMD_LINE_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_CMD_LINE_SHIFT)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_CMD_LINE_RANGE                       25:25
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_CMD_LINE_WOFFSET                     0x0
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_CMD_LINE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_CMD_LINE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_CMD_LINE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_CMD_LINE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_CMD_LINE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_CMD_LINE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_CMD_LINE_WORK                        _MK_ENUM_CONST(0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_CMD_LINE_RESETED                     _MK_ENUM_CONST(1)

#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_ALL_SHIFT                    _MK_SHIFT_CONST(24)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_ALL_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_ALL_SHIFT)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_ALL_RANGE                    24:24
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_ALL_WOFFSET                  0x0
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_ALL_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_ALL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_ALL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_ALL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_ALL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_ALL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_ALL_WORK                     _MK_ENUM_CONST(0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_ALL_RESETED                  _MK_ENUM_CONST(1)

#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_DATA_TIMEOUT_COUNTER_VALUE_SHIFT                  _MK_SHIFT_CONST(16)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_DATA_TIMEOUT_COUNTER_VALUE_FIELD                  _MK_FIELD_CONST(0xf, SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_DATA_TIMEOUT_COUNTER_VALUE_SHIFT)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_DATA_TIMEOUT_COUNTER_VALUE_RANGE                  19:16
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_DATA_TIMEOUT_COUNTER_VALUE_WOFFSET                        0x0
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_DATA_TIMEOUT_COUNTER_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_DATA_TIMEOUT_COUNTER_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_DATA_TIMEOUT_COUNTER_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_DATA_TIMEOUT_COUNTER_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_DATA_TIMEOUT_COUNTER_VALUE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_DATA_TIMEOUT_COUNTER_VALUE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_SHIFT                       _MK_SHIFT_CONST(8)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_FIELD                       _MK_FIELD_CONST(0xff, SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_SHIFT)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_RANGE                       15:8
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_WOFFSET                     0x0
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_DIV256                      _MK_ENUM_CONST(128)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_DIV128                      _MK_ENUM_CONST(64)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_DIV64                       _MK_ENUM_CONST(32)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_DIV32                       _MK_ENUM_CONST(16)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_DIV16                       _MK_ENUM_CONST(8)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_DIV8                        _MK_ENUM_CONST(4)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_DIV4                        _MK_ENUM_CONST(2)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_DIV2                        _MK_ENUM_CONST(1)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_BASE                        _MK_ENUM_CONST(0)

#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_UPPER_SDCLK_FREQUENCYSELECT_SHIFT                 _MK_SHIFT_CONST(6)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_UPPER_SDCLK_FREQUENCYSELECT_FIELD                 _MK_FIELD_CONST(0x3, SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_UPPER_SDCLK_FREQUENCYSELECT_SHIFT)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_UPPER_SDCLK_FREQUENCYSELECT_RANGE                 7:6
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_UPPER_SDCLK_FREQUENCYSELECT_WOFFSET                       0x0
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_UPPER_SDCLK_FREQUENCYSELECT_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_UPPER_SDCLK_FREQUENCYSELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_UPPER_SDCLK_FREQUENCYSELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_UPPER_SDCLK_FREQUENCYSELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_UPPER_SDCLK_FREQUENCYSELECT_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_UPPER_SDCLK_FREQUENCYSELECT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_CLOCK_GENERATOR_SELECT_SHIFT                      _MK_SHIFT_CONST(5)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_CLOCK_GENERATOR_SELECT_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_CLOCK_GENERATOR_SELECT_SHIFT)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_CLOCK_GENERATOR_SELECT_RANGE                      5:5
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_CLOCK_GENERATOR_SELECT_WOFFSET                    0x0
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_CLOCK_GENERATOR_SELECT_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_CLOCK_GENERATOR_SELECT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_CLOCK_GENERATOR_SELECT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_CLOCK_GENERATOR_SELECT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_CLOCK_GENERATOR_SELECT_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_CLOCK_GENERATOR_SELECT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_PLL_EN_SHIFT                      _MK_SHIFT_CONST(3)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_PLL_EN_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_PLL_EN_SHIFT)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_PLL_EN_RANGE                      3:3
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_PLL_EN_WOFFSET                    0x0
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_PLL_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_PLL_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_PLL_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_PLL_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_PLL_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_PLL_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SD_CLOCK_EN_SHIFT                 _MK_SHIFT_CONST(2)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SD_CLOCK_EN_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SD_CLOCK_EN_SHIFT)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SD_CLOCK_EN_RANGE                 2:2
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SD_CLOCK_EN_WOFFSET                       0x0
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SD_CLOCK_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SD_CLOCK_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SD_CLOCK_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SD_CLOCK_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SD_CLOCK_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SD_CLOCK_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SD_CLOCK_EN_DISABLE                       _MK_ENUM_CONST(0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SD_CLOCK_EN_ENABLE                        _MK_ENUM_CONST(1)

#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_STABLE_SHIFT                       _MK_SHIFT_CONST(1)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_STABLE_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_STABLE_SHIFT)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_STABLE_RANGE                       1:1
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_STABLE_WOFFSET                     0x0
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_STABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_STABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_STABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_STABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_STABLE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_STABLE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_STABLE_NOT_READY                   _MK_ENUM_CONST(0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_STABLE_READY                       _MK_ENUM_CONST(1)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_STABLE__PROD                       _MK_ENUM_CONST(1)

#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_EN_SHIFT                   _MK_SHIFT_CONST(0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_EN_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_EN_SHIFT)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_EN_RANGE                   0:0
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_EN_WOFFSET                 0x0
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_EN_STOP                    _MK_ENUM_CONST(0)
#define SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_EN_OSCILLATE                       _MK_ENUM_CONST(1)


// Register SDMMCAB_INTERRUPT_STATUS_0
#define SDMMCAB_INTERRUPT_STATUS_0                      _MK_ADDR_CONST(0x30)
#define SDMMCAB_INTERRUPT_STATUS_0_SECURE                       0x0
#define SDMMCAB_INTERRUPT_STATUS_0_DUAL                         0x0
#define SDMMCAB_INTERRUPT_STATUS_0_SCR                  0
#define SDMMCAB_INTERRUPT_STATUS_0_WORD_COUNT                   0x1
#define SDMMCAB_INTERRUPT_STATUS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_RESET_MASK                   _MK_MASK_CONST(0xfffff1ff)
#define SDMMCAB_INTERRUPT_STATUS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_READ_MASK                    _MK_MASK_CONST(0xfffff1ff)
#define SDMMCAB_INTERRUPT_STATUS_0_WRITE_MASK                   _MK_MASK_CONST(0xffff40ff)
#define SDMMCAB_INTERRUPT_STATUS_0_VEND_SPEC_ERR_SHIFT                  _MK_SHIFT_CONST(30)
#define SDMMCAB_INTERRUPT_STATUS_0_VEND_SPEC_ERR_FIELD                  _MK_FIELD_CONST(0x3, SDMMCAB_INTERRUPT_STATUS_0_VEND_SPEC_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_VEND_SPEC_ERR_RANGE                  31:30
#define SDMMCAB_INTERRUPT_STATUS_0_VEND_SPEC_ERR_WOFFSET                        0x0
#define SDMMCAB_INTERRUPT_STATUS_0_VEND_SPEC_ERR_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_VEND_SPEC_ERR_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define SDMMCAB_INTERRUPT_STATUS_0_VEND_SPEC_ERR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_VEND_SPEC_ERR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_VEND_SPEC_ERR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_VEND_SPEC_ERR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_VEND_SPEC_ERR_DISABLE                        _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_VEND_SPEC_ERR_ENABLE                 _MK_ENUM_CONST(3)

#define SDMMCAB_INTERRUPT_STATUS_0_SPI_ERR_SHIFT                        _MK_SHIFT_CONST(29)
#define SDMMCAB_INTERRUPT_STATUS_0_SPI_ERR_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_0_SPI_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_SPI_ERR_RANGE                        29:29
#define SDMMCAB_INTERRUPT_STATUS_0_SPI_ERR_WOFFSET                      0x0
#define SDMMCAB_INTERRUPT_STATUS_0_SPI_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_SPI_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_SPI_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_SPI_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_SPI_ERR_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_SPI_ERR_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_SPI_ERR_NO_ERR                       _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_SPI_ERR_ERR                  _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_0_TARGET_RESP_ERROR_SHIFT                      _MK_SHIFT_CONST(28)
#define SDMMCAB_INTERRUPT_STATUS_0_TARGET_RESP_ERROR_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_0_TARGET_RESP_ERROR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_TARGET_RESP_ERROR_RANGE                      28:28
#define SDMMCAB_INTERRUPT_STATUS_0_TARGET_RESP_ERROR_WOFFSET                    0x0
#define SDMMCAB_INTERRUPT_STATUS_0_TARGET_RESP_ERROR_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_TARGET_RESP_ERROR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_TARGET_RESP_ERROR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_TARGET_RESP_ERROR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_TARGET_RESP_ERROR_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_TARGET_RESP_ERROR_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_TARGET_RESP_ERROR_NO_ERROR                   _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_TARGET_RESP_ERROR_ERROR                      _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_0_RESP_ERR_SHIFT                       _MK_SHIFT_CONST(27)
#define SDMMCAB_INTERRUPT_STATUS_0_RESP_ERR_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_0_RESP_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_RESP_ERR_RANGE                       27:27
#define SDMMCAB_INTERRUPT_STATUS_0_RESP_ERR_WOFFSET                     0x0
#define SDMMCAB_INTERRUPT_STATUS_0_RESP_ERR_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_RESP_ERR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_RESP_ERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_RESP_ERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_RESP_ERR_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_RESP_ERR_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_RESP_ERR_NO_ERR                      _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_RESP_ERR_ERR                 _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_0_TUNING_ERR_SHIFT                     _MK_SHIFT_CONST(26)
#define SDMMCAB_INTERRUPT_STATUS_0_TUNING_ERR_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_0_TUNING_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_TUNING_ERR_RANGE                     26:26
#define SDMMCAB_INTERRUPT_STATUS_0_TUNING_ERR_WOFFSET                   0x0
#define SDMMCAB_INTERRUPT_STATUS_0_TUNING_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_TUNING_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_TUNING_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_TUNING_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_TUNING_ERR_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_TUNING_ERR_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_TUNING_ERR_NO_ERR                    _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_TUNING_ERR_ERR                       _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_0_ADMA_ERR_SHIFT                       _MK_SHIFT_CONST(25)
#define SDMMCAB_INTERRUPT_STATUS_0_ADMA_ERR_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_0_ADMA_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_ADMA_ERR_RANGE                       25:25
#define SDMMCAB_INTERRUPT_STATUS_0_ADMA_ERR_WOFFSET                     0x0
#define SDMMCAB_INTERRUPT_STATUS_0_ADMA_ERR_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_ADMA_ERR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_ADMA_ERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_ADMA_ERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_ADMA_ERR_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_ADMA_ERR_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_ADMA_ERR_NO_ERR                      _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_ADMA_ERR_ERR                 _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_0_AUTO_CMD12_ERR_SHIFT                 _MK_SHIFT_CONST(24)
#define SDMMCAB_INTERRUPT_STATUS_0_AUTO_CMD12_ERR_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_0_AUTO_CMD12_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_AUTO_CMD12_ERR_RANGE                 24:24
#define SDMMCAB_INTERRUPT_STATUS_0_AUTO_CMD12_ERR_WOFFSET                       0x0
#define SDMMCAB_INTERRUPT_STATUS_0_AUTO_CMD12_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_AUTO_CMD12_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_AUTO_CMD12_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_AUTO_CMD12_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_AUTO_CMD12_ERR_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_AUTO_CMD12_ERR_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_AUTO_CMD12_ERR_NO_ERR                        _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_AUTO_CMD12_ERR_ERR                   _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_0_CURRENT_LIMIT_ERR_SHIFT                      _MK_SHIFT_CONST(23)
#define SDMMCAB_INTERRUPT_STATUS_0_CURRENT_LIMIT_ERR_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_0_CURRENT_LIMIT_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_CURRENT_LIMIT_ERR_RANGE                      23:23
#define SDMMCAB_INTERRUPT_STATUS_0_CURRENT_LIMIT_ERR_WOFFSET                    0x0
#define SDMMCAB_INTERRUPT_STATUS_0_CURRENT_LIMIT_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_CURRENT_LIMIT_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_CURRENT_LIMIT_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_CURRENT_LIMIT_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_CURRENT_LIMIT_ERR_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_CURRENT_LIMIT_ERR_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_CURRENT_LIMIT_ERR_NO_ERR                     _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_CURRENT_LIMIT_ERR_POWER_FAIL                 _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_0_DATA_END_BIT_ERR_SHIFT                       _MK_SHIFT_CONST(22)
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_END_BIT_ERR_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_0_DATA_END_BIT_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_END_BIT_ERR_RANGE                       22:22
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_END_BIT_ERR_WOFFSET                     0x0
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_END_BIT_ERR_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_END_BIT_ERR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_END_BIT_ERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_END_BIT_ERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_END_BIT_ERR_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_END_BIT_ERR_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_END_BIT_ERR_NO_ERR                      _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_END_BIT_ERR_ERR                 _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_0_DATA_CRC_ERR_SHIFT                   _MK_SHIFT_CONST(21)
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_CRC_ERR_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_0_DATA_CRC_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_CRC_ERR_RANGE                   21:21
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_CRC_ERR_WOFFSET                 0x0
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_CRC_ERR_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_CRC_ERR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_CRC_ERR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_CRC_ERR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_CRC_ERR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_CRC_ERR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_CRC_ERR_NO_ERR                  _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_CRC_ERR_ERR                     _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_0_DATA_TIMEOUT_ERR_SHIFT                       _MK_SHIFT_CONST(20)
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_TIMEOUT_ERR_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_0_DATA_TIMEOUT_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_TIMEOUT_ERR_RANGE                       20:20
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_TIMEOUT_ERR_WOFFSET                     0x0
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_TIMEOUT_ERR_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_TIMEOUT_ERR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_TIMEOUT_ERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_TIMEOUT_ERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_TIMEOUT_ERR_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_TIMEOUT_ERR_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_TIMEOUT_ERR_NO_ERR                      _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_DATA_TIMEOUT_ERR_TIMEOUT                     _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_SHIFT                      _MK_SHIFT_CONST(19)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_RANGE                      19:19
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_WOFFSET                    0x0
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_NO_ERR                     _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_ERR                        _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_SHIFT                    _MK_SHIFT_CONST(18)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_RANGE                    18:18
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_WOFFSET                  0x0
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_NO_ERR                   _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_END_BIT_ERR_GENERATED                    _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_SHIFT                        _MK_SHIFT_CONST(17)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_RANGE                        17:17
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_WOFFSET                      0x0
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_NO_ERR                       _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_CRC_ERR_GENERATED                    _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_SHIFT                    _MK_SHIFT_CONST(16)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_RANGE                    16:16
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_WOFFSET                  0x0
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_NO_ERR                   _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_TIMEOUT                  _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_0_ERR_INTERRUPT_SHIFT                  _MK_SHIFT_CONST(15)
#define SDMMCAB_INTERRUPT_STATUS_0_ERR_INTERRUPT_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_0_ERR_INTERRUPT_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_ERR_INTERRUPT_RANGE                  15:15
#define SDMMCAB_INTERRUPT_STATUS_0_ERR_INTERRUPT_WOFFSET                        0x0
#define SDMMCAB_INTERRUPT_STATUS_0_ERR_INTERRUPT_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_ERR_INTERRUPT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_ERR_INTERRUPT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_ERR_INTERRUPT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_ERR_INTERRUPT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_ERR_INTERRUPT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_ERR_INTERRUPT_NO_ERR                 _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_ERR_INTERRUPT_ERR                    _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_0_CQE_INTR_SHIFT                       _MK_SHIFT_CONST(14)
#define SDMMCAB_INTERRUPT_STATUS_0_CQE_INTR_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_0_CQE_INTR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_CQE_INTR_RANGE                       14:14
#define SDMMCAB_INTERRUPT_STATUS_0_CQE_INTR_WOFFSET                     0x0
#define SDMMCAB_INTERRUPT_STATUS_0_CQE_INTR_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_CQE_INTR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_CQE_INTR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_CQE_INTR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_CQE_INTR_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_CQE_INTR_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_CQE_INTR_NO_INT                      _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_CQE_INTR_INT_GENERATED                       _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_0_FX_EVENT_SHIFT                       _MK_SHIFT_CONST(13)
#define SDMMCAB_INTERRUPT_STATUS_0_FX_EVENT_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_0_FX_EVENT_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_FX_EVENT_RANGE                       13:13
#define SDMMCAB_INTERRUPT_STATUS_0_FX_EVENT_WOFFSET                     0x0
#define SDMMCAB_INTERRUPT_STATUS_0_FX_EVENT_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_FX_EVENT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_FX_EVENT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_FX_EVENT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_FX_EVENT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_FX_EVENT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_FX_EVENT_NO_EVENT                    _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_FX_EVENT_FX_EVENT_DETECTED                   _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_0_RETUNING_EVENT_SHIFT                 _MK_SHIFT_CONST(12)
#define SDMMCAB_INTERRUPT_STATUS_0_RETUNING_EVENT_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_0_RETUNING_EVENT_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_RETUNING_EVENT_RANGE                 12:12
#define SDMMCAB_INTERRUPT_STATUS_0_RETUNING_EVENT_WOFFSET                       0x0
#define SDMMCAB_INTERRUPT_STATUS_0_RETUNING_EVENT_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_RETUNING_EVENT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_RETUNING_EVENT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_RETUNING_EVENT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_RETUNING_EVENT_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_RETUNING_EVENT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_RETUNING_EVENT_NO_INT                        _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_RETUNING_EVENT_GEN_INT                       _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_0_CARD_INTERRUPT_SHIFT                 _MK_SHIFT_CONST(8)
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_INTERRUPT_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_0_CARD_INTERRUPT_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_INTERRUPT_RANGE                 8:8
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_INTERRUPT_WOFFSET                       0x0
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_INTERRUPT_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_INTERRUPT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_INTERRUPT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_INTERRUPT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_INTERRUPT_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_INTERRUPT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_INTERRUPT_NO_INT                        _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_INTERRUPT_GEN_INT                       _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_0_CARD_REMOVAL_SHIFT                   _MK_SHIFT_CONST(7)
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_REMOVAL_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_0_CARD_REMOVAL_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_REMOVAL_RANGE                   7:7
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_REMOVAL_WOFFSET                 0x0
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_REMOVAL_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_REMOVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_REMOVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_REMOVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_REMOVAL_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_REMOVAL_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_REMOVAL_NO_INT                  _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_REMOVAL_GEN_INT                 _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_0_CARD_INSERTION_SHIFT                 _MK_SHIFT_CONST(6)
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_INSERTION_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_0_CARD_INSERTION_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_INSERTION_RANGE                 6:6
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_INSERTION_WOFFSET                       0x0
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_INSERTION_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_INSERTION_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_INSERTION_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_INSERTION_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_INSERTION_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_INSERTION_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_INSERTION_NO_INT                        _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_CARD_INSERTION_GEN_INT                       _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_0_BUFFER_READ_READY_SHIFT                      _MK_SHIFT_CONST(5)
#define SDMMCAB_INTERRUPT_STATUS_0_BUFFER_READ_READY_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_0_BUFFER_READ_READY_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_BUFFER_READ_READY_RANGE                      5:5
#define SDMMCAB_INTERRUPT_STATUS_0_BUFFER_READ_READY_WOFFSET                    0x0
#define SDMMCAB_INTERRUPT_STATUS_0_BUFFER_READ_READY_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_BUFFER_READ_READY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_BUFFER_READ_READY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_BUFFER_READ_READY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_BUFFER_READ_READY_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_BUFFER_READ_READY_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_BUFFER_READ_READY_NO_INT                     _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_BUFFER_READ_READY_GEN_INT                    _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_0_BUFFER_WRITE_READY_SHIFT                     _MK_SHIFT_CONST(4)
#define SDMMCAB_INTERRUPT_STATUS_0_BUFFER_WRITE_READY_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_0_BUFFER_WRITE_READY_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_BUFFER_WRITE_READY_RANGE                     4:4
#define SDMMCAB_INTERRUPT_STATUS_0_BUFFER_WRITE_READY_WOFFSET                   0x0
#define SDMMCAB_INTERRUPT_STATUS_0_BUFFER_WRITE_READY_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_BUFFER_WRITE_READY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_BUFFER_WRITE_READY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_BUFFER_WRITE_READY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_BUFFER_WRITE_READY_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_BUFFER_WRITE_READY_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_BUFFER_WRITE_READY_NO_INT                    _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_BUFFER_WRITE_READY_GEN_INT                   _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_0_DMA_INTERRUPT_SHIFT                  _MK_SHIFT_CONST(3)
#define SDMMCAB_INTERRUPT_STATUS_0_DMA_INTERRUPT_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_0_DMA_INTERRUPT_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_DMA_INTERRUPT_RANGE                  3:3
#define SDMMCAB_INTERRUPT_STATUS_0_DMA_INTERRUPT_WOFFSET                        0x0
#define SDMMCAB_INTERRUPT_STATUS_0_DMA_INTERRUPT_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_DMA_INTERRUPT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_DMA_INTERRUPT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_DMA_INTERRUPT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_DMA_INTERRUPT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_DMA_INTERRUPT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_DMA_INTERRUPT_NO_INT                 _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_DMA_INTERRUPT_GEN_INT                        _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_0_BLOCK_GAP_EVENT_SHIFT                        _MK_SHIFT_CONST(2)
#define SDMMCAB_INTERRUPT_STATUS_0_BLOCK_GAP_EVENT_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_0_BLOCK_GAP_EVENT_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_BLOCK_GAP_EVENT_RANGE                        2:2
#define SDMMCAB_INTERRUPT_STATUS_0_BLOCK_GAP_EVENT_WOFFSET                      0x0
#define SDMMCAB_INTERRUPT_STATUS_0_BLOCK_GAP_EVENT_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_BLOCK_GAP_EVENT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_BLOCK_GAP_EVENT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_BLOCK_GAP_EVENT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_BLOCK_GAP_EVENT_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_BLOCK_GAP_EVENT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_BLOCK_GAP_EVENT_NO_INT                       _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_BLOCK_GAP_EVENT_GEN_INT                      _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_0_XFER_COMPLETE_SHIFT                  _MK_SHIFT_CONST(1)
#define SDMMCAB_INTERRUPT_STATUS_0_XFER_COMPLETE_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_0_XFER_COMPLETE_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_XFER_COMPLETE_RANGE                  1:1
#define SDMMCAB_INTERRUPT_STATUS_0_XFER_COMPLETE_WOFFSET                        0x0
#define SDMMCAB_INTERRUPT_STATUS_0_XFER_COMPLETE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_XFER_COMPLETE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_XFER_COMPLETE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_XFER_COMPLETE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_XFER_COMPLETE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_XFER_COMPLETE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_XFER_COMPLETE_NO_INT                 _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_XFER_COMPLETE_GEN_INT                        _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_0_CMD_COMPLETE_SHIFT                   _MK_SHIFT_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_CMD_COMPLETE_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_0_CMD_COMPLETE_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_0_CMD_COMPLETE_RANGE                   0:0
#define SDMMCAB_INTERRUPT_STATUS_0_CMD_COMPLETE_WOFFSET                 0x0
#define SDMMCAB_INTERRUPT_STATUS_0_CMD_COMPLETE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_CMD_COMPLETE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_CMD_COMPLETE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_CMD_COMPLETE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_CMD_COMPLETE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_0_CMD_COMPLETE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_0_CMD_COMPLETE_NO_INT                  _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_0_CMD_COMPLETE_GEN_INT                 _MK_ENUM_CONST(1)


// Register SDMMCAB_INTERRUPT_STATUS_ENABLE_0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0                       _MK_ADDR_CONST(0x34)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_SECURE                        0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DUAL                  0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_SCR                   0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_WORD_COUNT                    0x1
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RESET_MASK                    _MK_MASK_CONST(0xffff71ff)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_READ_MASK                     _MK_MASK_CONST(0xffff71ff)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_WRITE_MASK                    _MK_MASK_CONST(0xffff71ff)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_VENDOR_SPECIFIC_ERR_SHIFT                     _MK_SHIFT_CONST(30)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_VENDOR_SPECIFIC_ERR_FIELD                     _MK_FIELD_CONST(0x3, SDMMCAB_INTERRUPT_STATUS_ENABLE_0_VENDOR_SPECIFIC_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_VENDOR_SPECIFIC_ERR_RANGE                     31:30
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_VENDOR_SPECIFIC_ERR_WOFFSET                   0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_VENDOR_SPECIFIC_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_VENDOR_SPECIFIC_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_VENDOR_SPECIFIC_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_VENDOR_SPECIFIC_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_VENDOR_SPECIFIC_ERR_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_VENDOR_SPECIFIC_ERR_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_VENDOR_SPECIFIC_ERR_DISABLE                   _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_VENDOR_SPECIFIC_ERR_ENABLE                    _MK_ENUM_CONST(3)

#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_SPI_ERR_SHIFT                 _MK_SHIFT_CONST(29)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_SPI_ERR_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_ENABLE_0_SPI_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_SPI_ERR_RANGE                 29:29
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_SPI_ERR_WOFFSET                       0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_SPI_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_SPI_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_SPI_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_SPI_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_SPI_ERR_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_SPI_ERR_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_SPI_ERR_DISABLE                       _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_SPI_ERR_ENABLE                        _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TARGET_RESP_ERROR_SHIFT                       _MK_SHIFT_CONST(28)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TARGET_RESP_ERROR_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TARGET_RESP_ERROR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TARGET_RESP_ERROR_RANGE                       28:28
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TARGET_RESP_ERROR_WOFFSET                     0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TARGET_RESP_ERROR_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TARGET_RESP_ERROR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TARGET_RESP_ERROR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TARGET_RESP_ERROR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TARGET_RESP_ERROR_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TARGET_RESP_ERROR_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TARGET_RESP_ERROR_NO_ERROR                    _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TARGET_RESP_ERROR_ERROR                       _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RESP_ERROR_SHIFT                      _MK_SHIFT_CONST(27)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RESP_ERROR_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RESP_ERROR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RESP_ERROR_RANGE                      27:27
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RESP_ERROR_WOFFSET                    0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RESP_ERROR_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RESP_ERROR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RESP_ERROR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RESP_ERROR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RESP_ERROR_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RESP_ERROR_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RESP_ERROR_NO_ERROR                   _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RESP_ERROR_ERROR                      _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TUNING_ERR_SHIFT                      _MK_SHIFT_CONST(26)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TUNING_ERR_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TUNING_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TUNING_ERR_RANGE                      26:26
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TUNING_ERR_WOFFSET                    0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TUNING_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TUNING_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TUNING_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TUNING_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TUNING_ERR_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TUNING_ERR_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TUNING_ERR_DISABLE                    _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TUNING_ERR_ENABLE                     _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_ADMA_ERR_SHIFT                        _MK_SHIFT_CONST(25)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_ADMA_ERR_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_ENABLE_0_ADMA_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_ADMA_ERR_RANGE                        25:25
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_ADMA_ERR_WOFFSET                      0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_ADMA_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_ADMA_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_ADMA_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_ADMA_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_ADMA_ERR_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_ADMA_ERR_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_ADMA_ERR_DISABLE                      _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_ADMA_ERR_ENABLE                       _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_AUTO_CMD12_ERR_SHIFT                  _MK_SHIFT_CONST(24)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_AUTO_CMD12_ERR_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_ENABLE_0_AUTO_CMD12_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_AUTO_CMD12_ERR_RANGE                  24:24
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_AUTO_CMD12_ERR_WOFFSET                        0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_AUTO_CMD12_ERR_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_AUTO_CMD12_ERR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_AUTO_CMD12_ERR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_AUTO_CMD12_ERR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_AUTO_CMD12_ERR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_AUTO_CMD12_ERR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_AUTO_CMD12_ERR_DISABLE                        _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_AUTO_CMD12_ERR_ENABLE                 _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CURRENT_LIMIT_ERR_SHIFT                       _MK_SHIFT_CONST(23)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CURRENT_LIMIT_ERR_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CURRENT_LIMIT_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CURRENT_LIMIT_ERR_RANGE                       23:23
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CURRENT_LIMIT_ERR_WOFFSET                     0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CURRENT_LIMIT_ERR_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CURRENT_LIMIT_ERR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CURRENT_LIMIT_ERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CURRENT_LIMIT_ERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CURRENT_LIMIT_ERR_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CURRENT_LIMIT_ERR_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CURRENT_LIMIT_ERR_DISABLE                     _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CURRENT_LIMIT_ERR_ENABLE                      _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_END_BIT_ERR_SHIFT                        _MK_SHIFT_CONST(22)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_END_BIT_ERR_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_END_BIT_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_END_BIT_ERR_RANGE                        22:22
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_END_BIT_ERR_WOFFSET                      0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_END_BIT_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_END_BIT_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_END_BIT_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_END_BIT_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_END_BIT_ERR_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_END_BIT_ERR_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_END_BIT_ERR_DISABLE                      _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_END_BIT_ERR_ENABLE                       _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_CRC_ERR_SHIFT                    _MK_SHIFT_CONST(21)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_CRC_ERR_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_CRC_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_CRC_ERR_RANGE                    21:21
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_CRC_ERR_WOFFSET                  0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_CRC_ERR_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_CRC_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_CRC_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_CRC_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_CRC_ERR_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_CRC_ERR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_CRC_ERR_DISABLE                  _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_CRC_ERR_ENABLE                   _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_TIMEOUT_ERR_SHIFT                        _MK_SHIFT_CONST(20)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_TIMEOUT_ERR_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_TIMEOUT_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_TIMEOUT_ERR_RANGE                        20:20
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_TIMEOUT_ERR_WOFFSET                      0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_TIMEOUT_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_TIMEOUT_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_TIMEOUT_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_TIMEOUT_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_TIMEOUT_ERR_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_TIMEOUT_ERR_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_TIMEOUT_ERR_DISABLE                      _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DATA_TIMEOUT_ERR_ENABLE                       _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_INDEX_ERR_SHIFT                       _MK_SHIFT_CONST(19)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_INDEX_ERR_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_INDEX_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_INDEX_ERR_RANGE                       19:19
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_INDEX_ERR_WOFFSET                     0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_INDEX_ERR_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_INDEX_ERR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_INDEX_ERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_INDEX_ERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_INDEX_ERR_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_INDEX_ERR_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_INDEX_ERR_DISABLE                     _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_INDEX_ERR_ENABLE                      _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_END_BIT_ERR_SHIFT                     _MK_SHIFT_CONST(18)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_END_BIT_ERR_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_END_BIT_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_END_BIT_ERR_RANGE                     18:18
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_END_BIT_ERR_WOFFSET                   0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_END_BIT_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_END_BIT_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_END_BIT_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_END_BIT_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_END_BIT_ERR_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_END_BIT_ERR_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_END_BIT_ERR_DISABLE                   _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_END_BIT_ERR_ENABLE                    _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_CRC_ERR_SHIFT                 _MK_SHIFT_CONST(17)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_CRC_ERR_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_CRC_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_CRC_ERR_RANGE                 17:17
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_CRC_ERR_WOFFSET                       0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_CRC_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_CRC_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_CRC_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_CRC_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_CRC_ERR_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_CRC_ERR_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_CRC_ERR_DISABLE                       _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_CRC_ERR_ENABLE                        _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_TIMEOUT_ERR_SHIFT                     _MK_SHIFT_CONST(16)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_TIMEOUT_ERR_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_TIMEOUT_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_TIMEOUT_ERR_RANGE                     16:16
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_TIMEOUT_ERR_WOFFSET                   0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_TIMEOUT_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_TIMEOUT_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_TIMEOUT_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_TIMEOUT_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_TIMEOUT_ERR_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_TIMEOUT_ERR_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_TIMEOUT_ERR_DISABLE                   _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_TIMEOUT_ERR_ENABLE                    _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CQE_INTR_SHIFT                        _MK_SHIFT_CONST(14)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CQE_INTR_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CQE_INTR_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CQE_INTR_RANGE                        14:14
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CQE_INTR_WOFFSET                      0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CQE_INTR_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CQE_INTR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CQE_INTR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CQE_INTR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CQE_INTR_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CQE_INTR_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CQE_INTR_DISABLE                      _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CQE_INTR_ENABLE                       _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_FX_EVENT_SHIFT                        _MK_SHIFT_CONST(13)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_FX_EVENT_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_ENABLE_0_FX_EVENT_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_FX_EVENT_RANGE                        13:13
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_FX_EVENT_WOFFSET                      0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_FX_EVENT_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_FX_EVENT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_FX_EVENT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_FX_EVENT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_FX_EVENT_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_FX_EVENT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_FX_EVENT_DISABLE                      _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_FX_EVENT_ENABLE                       _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RETUNING_EVENT_SHIFT                  _MK_SHIFT_CONST(12)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RETUNING_EVENT_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RETUNING_EVENT_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RETUNING_EVENT_RANGE                  12:12
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RETUNING_EVENT_WOFFSET                        0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RETUNING_EVENT_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RETUNING_EVENT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RETUNING_EVENT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RETUNING_EVENT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RETUNING_EVENT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RETUNING_EVENT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RETUNING_EVENT_DISABLE                        _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_RETUNING_EVENT_ENABLE                 _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_INTERRUPT_SHIFT                  _MK_SHIFT_CONST(8)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_INTERRUPT_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_INTERRUPT_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_INTERRUPT_RANGE                  8:8
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_INTERRUPT_WOFFSET                        0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_INTERRUPT_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_INTERRUPT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_INTERRUPT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_INTERRUPT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_INTERRUPT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_INTERRUPT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_INTERRUPT_DISABLE                        _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_INTERRUPT_ENABLE                 _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_REMOVAL_SHIFT                    _MK_SHIFT_CONST(7)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_REMOVAL_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_REMOVAL_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_REMOVAL_RANGE                    7:7
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_REMOVAL_WOFFSET                  0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_REMOVAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_REMOVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_REMOVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_REMOVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_REMOVAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_REMOVAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_REMOVAL_DISABLE                  _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_REMOVAL_ENABLE                   _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_INSERTION_SHIFT                  _MK_SHIFT_CONST(6)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_INSERTION_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_INSERTION_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_INSERTION_RANGE                  6:6
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_INSERTION_WOFFSET                        0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_INSERTION_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_INSERTION_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_INSERTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_INSERTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_INSERTION_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_INSERTION_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_INSERTION_DISABLE                        _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_CARD_INSERTION_ENABLE                 _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BUFFER_READ_READY_SHIFT                       _MK_SHIFT_CONST(5)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BUFFER_READ_READY_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BUFFER_READ_READY_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BUFFER_READ_READY_RANGE                       5:5
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BUFFER_READ_READY_WOFFSET                     0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BUFFER_READ_READY_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BUFFER_READ_READY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BUFFER_READ_READY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BUFFER_READ_READY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BUFFER_READ_READY_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BUFFER_READ_READY_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BUFFER_READ_READY_DISABLE                     _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BUFFER_READ_READY_ENABLE                      _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BUFFER_WRITE_READY_SHIFT                      _MK_SHIFT_CONST(4)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BUFFER_WRITE_READY_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BUFFER_WRITE_READY_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BUFFER_WRITE_READY_RANGE                      4:4
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BUFFER_WRITE_READY_WOFFSET                    0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BUFFER_WRITE_READY_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BUFFER_WRITE_READY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BUFFER_WRITE_READY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BUFFER_WRITE_READY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BUFFER_WRITE_READY_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BUFFER_WRITE_READY_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BUFFER_WRITE_READY_DISABLE                    _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BUFFER_WRITE_READY_ENABLE                     _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DMA_INTERRUPT_SHIFT                   _MK_SHIFT_CONST(3)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DMA_INTERRUPT_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DMA_INTERRUPT_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DMA_INTERRUPT_RANGE                   3:3
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DMA_INTERRUPT_WOFFSET                 0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DMA_INTERRUPT_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DMA_INTERRUPT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DMA_INTERRUPT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DMA_INTERRUPT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DMA_INTERRUPT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DMA_INTERRUPT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DMA_INTERRUPT_DISABLE                 _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_DMA_INTERRUPT_ENABLE                  _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BLOCK_GAP_EVENT_SHIFT                 _MK_SHIFT_CONST(2)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BLOCK_GAP_EVENT_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BLOCK_GAP_EVENT_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BLOCK_GAP_EVENT_RANGE                 2:2
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BLOCK_GAP_EVENT_WOFFSET                       0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BLOCK_GAP_EVENT_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BLOCK_GAP_EVENT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BLOCK_GAP_EVENT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BLOCK_GAP_EVENT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BLOCK_GAP_EVENT_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BLOCK_GAP_EVENT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BLOCK_GAP_EVENT_DISABLE                       _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_BLOCK_GAP_EVENT_ENABLE                        _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TRANSFER_COMPLETE_SHIFT                       _MK_SHIFT_CONST(1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TRANSFER_COMPLETE_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TRANSFER_COMPLETE_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TRANSFER_COMPLETE_RANGE                       1:1
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TRANSFER_COMPLETE_WOFFSET                     0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TRANSFER_COMPLETE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TRANSFER_COMPLETE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TRANSFER_COMPLETE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TRANSFER_COMPLETE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TRANSFER_COMPLETE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TRANSFER_COMPLETE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TRANSFER_COMPLETE_DISABLE                     _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_TRANSFER_COMPLETE_ENABLE                      _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_COMPLETE_SHIFT                        _MK_SHIFT_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_COMPLETE_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_COMPLETE_SHIFT)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_COMPLETE_RANGE                        0:0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_COMPLETE_WOFFSET                      0x0
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_COMPLETE_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_COMPLETE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_COMPLETE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_COMPLETE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_COMPLETE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_COMPLETE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_COMPLETE_DISABLE                      _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_STATUS_ENABLE_0_COMMAND_COMPLETE_ENABLE                       _MK_ENUM_CONST(1)


// Register SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0                       _MK_ADDR_CONST(0x38)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_SECURE                        0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DUAL                  0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_SCR                   0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_WORD_COUNT                    0x1
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RESET_MASK                    _MK_MASK_CONST(0xffff71ff)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_READ_MASK                     _MK_MASK_CONST(0xffff71ff)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_WRITE_MASK                    _MK_MASK_CONST(0xffff71ff)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_VENDOR_SPECIFIC_ERR_SHIFT                     _MK_SHIFT_CONST(30)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_VENDOR_SPECIFIC_ERR_FIELD                     _MK_FIELD_CONST(0x3, SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_VENDOR_SPECIFIC_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_VENDOR_SPECIFIC_ERR_RANGE                     31:30
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_VENDOR_SPECIFIC_ERR_WOFFSET                   0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_VENDOR_SPECIFIC_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_VENDOR_SPECIFIC_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_VENDOR_SPECIFIC_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_VENDOR_SPECIFIC_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_VENDOR_SPECIFIC_ERR_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_VENDOR_SPECIFIC_ERR_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_VENDOR_SPECIFIC_ERR_DISABLE                   _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_VENDOR_SPECIFIC_ERR_ENABLE                    _MK_ENUM_CONST(3)

#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_SPI_ERR_SHIFT                 _MK_SHIFT_CONST(29)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_SPI_ERR_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_SPI_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_SPI_ERR_RANGE                 29:29
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_SPI_ERR_WOFFSET                       0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_SPI_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_SPI_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_SPI_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_SPI_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_SPI_ERR_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_SPI_ERR_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_SPI_ERR_DISABLE                       _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_SPI_ERR_ENABLE                        _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TARGET_RESP_ERROR_SHIFT                       _MK_SHIFT_CONST(28)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TARGET_RESP_ERROR_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TARGET_RESP_ERROR_SHIFT)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TARGET_RESP_ERROR_RANGE                       28:28
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TARGET_RESP_ERROR_WOFFSET                     0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TARGET_RESP_ERROR_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TARGET_RESP_ERROR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TARGET_RESP_ERROR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TARGET_RESP_ERROR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TARGET_RESP_ERROR_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TARGET_RESP_ERROR_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TARGET_RESP_ERROR_NO_ERROR                    _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TARGET_RESP_ERROR_ERROR                       _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RESP_ERROR_SHIFT                      _MK_SHIFT_CONST(27)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RESP_ERROR_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RESP_ERROR_SHIFT)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RESP_ERROR_RANGE                      27:27
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RESP_ERROR_WOFFSET                    0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RESP_ERROR_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RESP_ERROR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RESP_ERROR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RESP_ERROR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RESP_ERROR_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RESP_ERROR_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RESP_ERROR_DISABLE                    _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RESP_ERROR_ENABLE                     _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TUNING_ERR_SHIFT                      _MK_SHIFT_CONST(26)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TUNING_ERR_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TUNING_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TUNING_ERR_RANGE                      26:26
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TUNING_ERR_WOFFSET                    0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TUNING_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TUNING_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TUNING_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TUNING_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TUNING_ERR_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TUNING_ERR_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TUNING_ERR_DISABLE                    _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TUNING_ERR_ENABLE                     _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_ADMA_ERR_SHIFT                        _MK_SHIFT_CONST(25)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_ADMA_ERR_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_ADMA_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_ADMA_ERR_RANGE                        25:25
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_ADMA_ERR_WOFFSET                      0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_ADMA_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_ADMA_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_ADMA_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_ADMA_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_ADMA_ERR_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_ADMA_ERR_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_ADMA_ERR_DISABLE                      _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_ADMA_ERR_ENABLE                       _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_AUTO_CMD12_ERR_SHIFT                  _MK_SHIFT_CONST(24)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_AUTO_CMD12_ERR_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_AUTO_CMD12_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_AUTO_CMD12_ERR_RANGE                  24:24
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_AUTO_CMD12_ERR_WOFFSET                        0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_AUTO_CMD12_ERR_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_AUTO_CMD12_ERR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_AUTO_CMD12_ERR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_AUTO_CMD12_ERR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_AUTO_CMD12_ERR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_AUTO_CMD12_ERR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_AUTO_CMD12_ERR_DISABLE                        _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_AUTO_CMD12_ERR_ENABLE                 _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CURRENT_LIMIT_ERR_SHIFT                       _MK_SHIFT_CONST(23)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CURRENT_LIMIT_ERR_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CURRENT_LIMIT_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CURRENT_LIMIT_ERR_RANGE                       23:23
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CURRENT_LIMIT_ERR_WOFFSET                     0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CURRENT_LIMIT_ERR_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CURRENT_LIMIT_ERR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CURRENT_LIMIT_ERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CURRENT_LIMIT_ERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CURRENT_LIMIT_ERR_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CURRENT_LIMIT_ERR_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CURRENT_LIMIT_ERR_DISABLE                     _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CURRENT_LIMIT_ERR_ENABLE                      _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_END_BIT_ERR_SHIFT                        _MK_SHIFT_CONST(22)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_END_BIT_ERR_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_END_BIT_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_END_BIT_ERR_RANGE                        22:22
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_END_BIT_ERR_WOFFSET                      0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_END_BIT_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_END_BIT_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_END_BIT_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_END_BIT_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_END_BIT_ERR_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_END_BIT_ERR_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_END_BIT_ERR_DISABLE                      _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_END_BIT_ERR_ENABLE                       _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_CRC_ERR_SHIFT                    _MK_SHIFT_CONST(21)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_CRC_ERR_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_CRC_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_CRC_ERR_RANGE                    21:21
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_CRC_ERR_WOFFSET                  0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_CRC_ERR_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_CRC_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_CRC_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_CRC_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_CRC_ERR_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_CRC_ERR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_CRC_ERR_DISABLE                  _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_CRC_ERR_ENABLE                   _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_TIMEOUT_ERR_SHIFT                        _MK_SHIFT_CONST(20)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_TIMEOUT_ERR_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_TIMEOUT_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_TIMEOUT_ERR_RANGE                        20:20
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_TIMEOUT_ERR_WOFFSET                      0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_TIMEOUT_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_TIMEOUT_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_TIMEOUT_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_TIMEOUT_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_TIMEOUT_ERR_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_TIMEOUT_ERR_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_TIMEOUT_ERR_DISABLE                      _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DATA_TIMEOUT_ERR_ENABLE                       _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_INDEX_ERR_SHIFT                       _MK_SHIFT_CONST(19)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_INDEX_ERR_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_INDEX_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_INDEX_ERR_RANGE                       19:19
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_INDEX_ERR_WOFFSET                     0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_INDEX_ERR_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_INDEX_ERR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_INDEX_ERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_INDEX_ERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_INDEX_ERR_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_INDEX_ERR_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_INDEX_ERR_DISABLE                     _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_INDEX_ERR_ENABLE                      _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_END_BIT_ERR_SHIFT                     _MK_SHIFT_CONST(18)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_END_BIT_ERR_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_END_BIT_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_END_BIT_ERR_RANGE                     18:18
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_END_BIT_ERR_WOFFSET                   0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_END_BIT_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_END_BIT_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_END_BIT_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_END_BIT_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_END_BIT_ERR_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_END_BIT_ERR_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_END_BIT_ERR_DISABLE                   _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_END_BIT_ERR_ENABLE                    _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_CRC_ERR_SHIFT                 _MK_SHIFT_CONST(17)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_CRC_ERR_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_CRC_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_CRC_ERR_RANGE                 17:17
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_CRC_ERR_WOFFSET                       0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_CRC_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_CRC_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_CRC_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_CRC_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_CRC_ERR_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_CRC_ERR_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_CRC_ERR_DISABLE                       _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_CRC_ERR_ENABLE                        _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_TIMEOUT_ERR_SHIFT                     _MK_SHIFT_CONST(16)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_TIMEOUT_ERR_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_TIMEOUT_ERR_SHIFT)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_TIMEOUT_ERR_RANGE                     16:16
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_TIMEOUT_ERR_WOFFSET                   0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_TIMEOUT_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_TIMEOUT_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_TIMEOUT_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_TIMEOUT_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_TIMEOUT_ERR_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_TIMEOUT_ERR_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_TIMEOUT_ERR_DISABLE                   _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_TIMEOUT_ERR_ENABLE                    _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CQE_INTR_SHIFT                        _MK_SHIFT_CONST(14)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CQE_INTR_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CQE_INTR_SHIFT)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CQE_INTR_RANGE                        14:14
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CQE_INTR_WOFFSET                      0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CQE_INTR_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CQE_INTR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CQE_INTR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CQE_INTR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CQE_INTR_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CQE_INTR_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CQE_INTR_DISABLE                      _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CQE_INTR_ENABLE                       _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_FX_EVENT_SHIFT                        _MK_SHIFT_CONST(13)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_FX_EVENT_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_FX_EVENT_SHIFT)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_FX_EVENT_RANGE                        13:13
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_FX_EVENT_WOFFSET                      0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_FX_EVENT_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_FX_EVENT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_FX_EVENT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_FX_EVENT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_FX_EVENT_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_FX_EVENT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_FX_EVENT_DISABLE                      _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_FX_EVENT_ENABLE                       _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RETUNING_EVENT_SHIFT                  _MK_SHIFT_CONST(12)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RETUNING_EVENT_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RETUNING_EVENT_SHIFT)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RETUNING_EVENT_RANGE                  12:12
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RETUNING_EVENT_WOFFSET                        0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RETUNING_EVENT_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RETUNING_EVENT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RETUNING_EVENT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RETUNING_EVENT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RETUNING_EVENT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RETUNING_EVENT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RETUNING_EVENT_DISABLE                        _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_RETUNING_EVENT_ENABLE                 _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_INTERRUPT_SHIFT                  _MK_SHIFT_CONST(8)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_INTERRUPT_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_INTERRUPT_SHIFT)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_INTERRUPT_RANGE                  8:8
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_INTERRUPT_WOFFSET                        0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_INTERRUPT_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_INTERRUPT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_INTERRUPT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_INTERRUPT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_INTERRUPT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_INTERRUPT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_INTERRUPT_DISABLE                        _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_INTERRUPT_ENABLE                 _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_REMOVAL_SHIFT                    _MK_SHIFT_CONST(7)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_REMOVAL_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_REMOVAL_SHIFT)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_REMOVAL_RANGE                    7:7
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_REMOVAL_WOFFSET                  0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_REMOVAL_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_REMOVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_REMOVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_REMOVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_REMOVAL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_REMOVAL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_REMOVAL_DISABLE                  _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_REMOVAL_ENABLE                   _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_INSERTION_SHIFT                  _MK_SHIFT_CONST(6)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_INSERTION_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_INSERTION_SHIFT)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_INSERTION_RANGE                  6:6
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_INSERTION_WOFFSET                        0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_INSERTION_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_INSERTION_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_INSERTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_INSERTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_INSERTION_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_INSERTION_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_INSERTION_DISABLE                        _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_CARD_INSERTION_ENABLE                 _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_READ_READY_SHIFT                       _MK_SHIFT_CONST(5)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_READ_READY_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_READ_READY_SHIFT)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_READ_READY_RANGE                       5:5
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_READ_READY_WOFFSET                     0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_READ_READY_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_READ_READY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_READ_READY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_READ_READY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_READ_READY_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_READ_READY_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_READ_READY_DISABLE                     _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_READ_READY_ENABLE                      _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_WRITE_READY_SHIFT                      _MK_SHIFT_CONST(4)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_WRITE_READY_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_WRITE_READY_SHIFT)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_WRITE_READY_RANGE                      4:4
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_WRITE_READY_WOFFSET                    0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_WRITE_READY_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_WRITE_READY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_WRITE_READY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_WRITE_READY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_WRITE_READY_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_WRITE_READY_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_WRITE_READY_DISABLE                    _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_WRITE_READY_ENABLE                     _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DMA_INTERRUPT_SHIFT                   _MK_SHIFT_CONST(3)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DMA_INTERRUPT_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DMA_INTERRUPT_SHIFT)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DMA_INTERRUPT_RANGE                   3:3
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DMA_INTERRUPT_WOFFSET                 0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DMA_INTERRUPT_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DMA_INTERRUPT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DMA_INTERRUPT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DMA_INTERRUPT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DMA_INTERRUPT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DMA_INTERRUPT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DMA_INTERRUPT_DISABLE                 _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_DMA_INTERRUPT_ENABLE                  _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BLOCK_GAP_EVENT_SHIFT                 _MK_SHIFT_CONST(2)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BLOCK_GAP_EVENT_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BLOCK_GAP_EVENT_SHIFT)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BLOCK_GAP_EVENT_RANGE                 2:2
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BLOCK_GAP_EVENT_WOFFSET                       0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BLOCK_GAP_EVENT_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BLOCK_GAP_EVENT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BLOCK_GAP_EVENT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BLOCK_GAP_EVENT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BLOCK_GAP_EVENT_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BLOCK_GAP_EVENT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BLOCK_GAP_EVENT_DISABLE                       _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_BLOCK_GAP_EVENT_ENABLE                        _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TRANSFER_COMPLETE_SHIFT                       _MK_SHIFT_CONST(1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TRANSFER_COMPLETE_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TRANSFER_COMPLETE_SHIFT)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TRANSFER_COMPLETE_RANGE                       1:1
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TRANSFER_COMPLETE_WOFFSET                     0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TRANSFER_COMPLETE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TRANSFER_COMPLETE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TRANSFER_COMPLETE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TRANSFER_COMPLETE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TRANSFER_COMPLETE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TRANSFER_COMPLETE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TRANSFER_COMPLETE_DISABLE                     _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_TRANSFER_COMPLETE_ENABLE                      _MK_ENUM_CONST(1)

#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_COMPLETE_SHIFT                        _MK_SHIFT_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_COMPLETE_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_COMPLETE_SHIFT)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_COMPLETE_RANGE                        0:0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_COMPLETE_WOFFSET                      0x0
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_COMPLETE_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_COMPLETE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_COMPLETE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_COMPLETE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_COMPLETE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_COMPLETE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_COMPLETE_DISABLE                      _MK_ENUM_CONST(0)
#define SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_COMPLETE_ENABLE                       _MK_ENUM_CONST(1)


// Register SDMMCAB_AUTO_CMD12_ERR_STATUS_0
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0                 _MK_ADDR_CONST(0x3c)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_SECURE                  0x0
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_DUAL                    0x0
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_SCR                     0
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_WORD_COUNT                      0x1
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_RESET_MASK                      _MK_MASK_CONST(0xfdff00bf)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_READ_MASK                       _MK_MASK_CONST(0xfdff00bf)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_WRITE_MASK                      _MK_MASK_CONST(0xfdff0000)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_PRESET_VALUE_ENABLE_SHIFT                       _MK_SHIFT_CONST(31)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_PRESET_VALUE_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_AUTO_CMD12_ERR_STATUS_0_PRESET_VALUE_ENABLE_SHIFT)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_PRESET_VALUE_ENABLE_RANGE                       31:31
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_PRESET_VALUE_ENABLE_WOFFSET                     0x0
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_PRESET_VALUE_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_PRESET_VALUE_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_PRESET_VALUE_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_PRESET_VALUE_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_PRESET_VALUE_ENABLE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_PRESET_VALUE_ENABLE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_PRESET_VALUE_ENABLE_HW_SEL                      _MK_ENUM_CONST(0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_PRESET_VALUE_ENABLE_SW_SEL                      _MK_ENUM_CONST(1)

#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ASYNC_INTR_EN_SHIFT                     _MK_SHIFT_CONST(30)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ASYNC_INTR_EN_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ASYNC_INTR_EN_SHIFT)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ASYNC_INTR_EN_RANGE                     30:30
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ASYNC_INTR_EN_WOFFSET                   0x0
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ASYNC_INTR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ASYNC_INTR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ASYNC_INTR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ASYNC_INTR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ASYNC_INTR_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ASYNC_INTR_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ASYNC_INTR_EN_DISABLE                   _MK_ENUM_CONST(0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ASYNC_INTR_EN_ENABLE                    _MK_ENUM_CONST(1)

#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ADDRESSING_64BIT_EN_SHIFT                       _MK_SHIFT_CONST(29)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ADDRESSING_64BIT_EN_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ADDRESSING_64BIT_EN_SHIFT)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ADDRESSING_64BIT_EN_RANGE                       29:29
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ADDRESSING_64BIT_EN_WOFFSET                     0x0
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ADDRESSING_64BIT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ADDRESSING_64BIT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ADDRESSING_64BIT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ADDRESSING_64BIT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ADDRESSING_64BIT_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ADDRESSING_64BIT_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ADDRESSING_64BIT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ADDRESSING_64BIT_EN_ENABLE                      _MK_ENUM_CONST(1)

#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_HOST_VERSION_4_EN_SHIFT                 _MK_SHIFT_CONST(28)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_HOST_VERSION_4_EN_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_AUTO_CMD12_ERR_STATUS_0_HOST_VERSION_4_EN_SHIFT)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_HOST_VERSION_4_EN_RANGE                 28:28
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_HOST_VERSION_4_EN_WOFFSET                       0x0
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_HOST_VERSION_4_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_HOST_VERSION_4_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_HOST_VERSION_4_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_HOST_VERSION_4_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_HOST_VERSION_4_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_HOST_VERSION_4_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_HOST_VERSION_4_EN_DISABLE                       _MK_ENUM_CONST(0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_HOST_VERSION_4_EN_ENABLE                        _MK_ENUM_CONST(1)

#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_CMD23_EN_SHIFT                  _MK_SHIFT_CONST(27)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_CMD23_EN_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_AUTO_CMD12_ERR_STATUS_0_CMD23_EN_SHIFT)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_CMD23_EN_RANGE                  27:27
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_CMD23_EN_WOFFSET                        0x0
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_CMD23_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_CMD23_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_CMD23_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_CMD23_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_CMD23_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_CMD23_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_CMD23_EN_DISABLE                        _MK_ENUM_CONST(0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_CMD23_EN_ENABLE                 _MK_ENUM_CONST(1)

#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ADMA2_LEN_MODE_SHIFT                    _MK_SHIFT_CONST(26)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ADMA2_LEN_MODE_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ADMA2_LEN_MODE_SHIFT)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ADMA2_LEN_MODE_RANGE                    26:26
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ADMA2_LEN_MODE_WOFFSET                  0x0
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ADMA2_LEN_MODE_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ADMA2_LEN_MODE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ADMA2_LEN_MODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ADMA2_LEN_MODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ADMA2_LEN_MODE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ADMA2_LEN_MODE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ADMA2_LEN_MODE_LEN_16BIT                        _MK_ENUM_CONST(0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_ADMA2_LEN_MODE_LEN_26BIT                        _MK_ENUM_CONST(1)

#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS2_IF_EN_SHIFT                        _MK_SHIFT_CONST(24)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS2_IF_EN_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS2_IF_EN_SHIFT)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS2_IF_EN_RANGE                        24:24
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS2_IF_EN_WOFFSET                      0x0
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS2_IF_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS2_IF_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS2_IF_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS2_IF_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS2_IF_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS2_IF_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS2_IF_EN_DISABLE                      _MK_ENUM_CONST(0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS2_IF_EN_ENABLE                       _MK_ENUM_CONST(1)

#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_SAMPLING_CLK_SEL_SHIFT                  _MK_SHIFT_CONST(23)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_SAMPLING_CLK_SEL_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_AUTO_CMD12_ERR_STATUS_0_SAMPLING_CLK_SEL_SHIFT)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_SAMPLING_CLK_SEL_RANGE                  23:23
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_SAMPLING_CLK_SEL_WOFFSET                        0x0
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_SAMPLING_CLK_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_SAMPLING_CLK_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_SAMPLING_CLK_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_SAMPLING_CLK_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_SAMPLING_CLK_SEL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_SAMPLING_CLK_SEL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_SAMPLING_CLK_SEL_FIXED                  _MK_ENUM_CONST(0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_SAMPLING_CLK_SEL_TUNED                  _MK_ENUM_CONST(1)

#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_EXECUTE_TUNING_SHIFT                    _MK_SHIFT_CONST(22)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_EXECUTE_TUNING_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_AUTO_CMD12_ERR_STATUS_0_EXECUTE_TUNING_SHIFT)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_EXECUTE_TUNING_RANGE                    22:22
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_EXECUTE_TUNING_WOFFSET                  0x0
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_EXECUTE_TUNING_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_EXECUTE_TUNING_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_EXECUTE_TUNING_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_EXECUTE_TUNING_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_EXECUTE_TUNING_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_EXECUTE_TUNING_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_EXECUTE_TUNING_NOT_TUNED                        _MK_ENUM_CONST(0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_EXECUTE_TUNING_EXECUTE                  _MK_ENUM_CONST(1)

#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_DRIVE_STRENGTH_SEL_SHIFT                        _MK_SHIFT_CONST(20)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_DRIVE_STRENGTH_SEL_FIELD                        _MK_FIELD_CONST(0x3, SDMMCAB_AUTO_CMD12_ERR_STATUS_0_DRIVE_STRENGTH_SEL_SHIFT)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_DRIVE_STRENGTH_SEL_RANGE                        21:20
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_DRIVE_STRENGTH_SEL_WOFFSET                      0x0
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_DRIVE_STRENGTH_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_DRIVE_STRENGTH_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_DRIVE_STRENGTH_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_DRIVE_STRENGTH_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_DRIVE_STRENGTH_SEL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_DRIVE_STRENGTH_SEL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_DRIVE_STRENGTH_SEL_TYPE_B                       _MK_ENUM_CONST(0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_DRIVE_STRENGTH_SEL_TYPE_A                       _MK_ENUM_CONST(1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_DRIVE_STRENGTH_SEL_TYPE_C                       _MK_ENUM_CONST(2)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_DRIVE_STRENGTH_SEL_TYPE_D                       _MK_ENUM_CONST(3)

#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_VOLT_18_EN_SHIFT                        _MK_SHIFT_CONST(19)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_VOLT_18_EN_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_AUTO_CMD12_ERR_STATUS_0_VOLT_18_EN_SHIFT)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_VOLT_18_EN_RANGE                        19:19
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_VOLT_18_EN_WOFFSET                      0x0
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_VOLT_18_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_VOLT_18_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_VOLT_18_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_VOLT_18_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_VOLT_18_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_VOLT_18_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_VOLT_18_EN_V33                  _MK_ENUM_CONST(0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_VOLT_18_EN_V18                  _MK_ENUM_CONST(1)

#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS_MODE_SEL_SHIFT                      _MK_SHIFT_CONST(16)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS_MODE_SEL_FIELD                      _MK_FIELD_CONST(0x7, SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS_MODE_SEL_SHIFT)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS_MODE_SEL_RANGE                      18:16
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS_MODE_SEL_WOFFSET                    0x0
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS_MODE_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS_MODE_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS_MODE_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS_MODE_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS_MODE_SEL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS_MODE_SEL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS_MODE_SEL_SDR12                      _MK_ENUM_CONST(0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS_MODE_SEL_SDR25                      _MK_ENUM_CONST(1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS_MODE_SEL_SDR50                      _MK_ENUM_CONST(2)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS_MODE_SEL_SDR104                     _MK_ENUM_CONST(3)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS_MODE_SEL_DDR50                      _MK_ENUM_CONST(4)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS_MODE_SEL_HS400                      _MK_ENUM_CONST(5)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS_MODE_SEL_RSVD                       _MK_ENUM_CONST(6)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS_MODE_SEL_UHS2                       _MK_ENUM_CONST(7)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS_MODE_SEL__PROD_C_HS400                      _MK_ENUM_CONST(5)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS_MODE_SEL__PROD_C_HS200                      _MK_ENUM_CONST(3)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS_MODE_SEL__PROD_C_DDR52                      _MK_ENUM_CONST(4)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS_MODE_SEL__PROD_C_DDR50                      _MK_ENUM_CONST(4)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_UHS_MODE_SEL__PROD_C_SDR50                      _MK_ENUM_CONST(2)

#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_COMMAND_NOT_ISSUED_SHIFT                        _MK_SHIFT_CONST(7)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_COMMAND_NOT_ISSUED_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_AUTO_CMD12_ERR_STATUS_0_COMMAND_NOT_ISSUED_SHIFT)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_COMMAND_NOT_ISSUED_RANGE                        7:7
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_COMMAND_NOT_ISSUED_WOFFSET                      0x0
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_COMMAND_NOT_ISSUED_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_COMMAND_NOT_ISSUED_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_COMMAND_NOT_ISSUED_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_COMMAND_NOT_ISSUED_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_COMMAND_NOT_ISSUED_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_COMMAND_NOT_ISSUED_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_COMMAND_NOT_ISSUED_NO_ERR                       _MK_ENUM_CONST(0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_COMMAND_NOT_ISSUED_NOT_ISSUED                   _MK_ENUM_CONST(1)

#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_RESP_ERR_SHIFT                  _MK_SHIFT_CONST(5)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_RESP_ERR_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_AUTO_CMD12_ERR_STATUS_0_RESP_ERR_SHIFT)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_RESP_ERR_RANGE                  5:5
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_RESP_ERR_WOFFSET                        0x0
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_RESP_ERR_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_RESP_ERR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_RESP_ERR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_RESP_ERR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_RESP_ERR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_RESP_ERR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_RESP_ERR_NO_ERR                 _MK_ENUM_CONST(0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_RESP_ERR_ERR                    _MK_ENUM_CONST(1)

#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_INDEX_ERR_SHIFT                 _MK_SHIFT_CONST(4)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_INDEX_ERR_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_AUTO_CMD12_ERR_STATUS_0_INDEX_ERR_SHIFT)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_INDEX_ERR_RANGE                 4:4
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_INDEX_ERR_WOFFSET                       0x0
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_INDEX_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_INDEX_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_INDEX_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_INDEX_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_INDEX_ERR_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_INDEX_ERR_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_INDEX_ERR_NO_ERR                        _MK_ENUM_CONST(0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_INDEX_ERR_ERR                   _MK_ENUM_CONST(1)

#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_END_BIT_ERR_SHIFT                       _MK_SHIFT_CONST(3)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_END_BIT_ERR_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_AUTO_CMD12_ERR_STATUS_0_END_BIT_ERR_SHIFT)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_END_BIT_ERR_RANGE                       3:3
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_END_BIT_ERR_WOFFSET                     0x0
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_END_BIT_ERR_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_END_BIT_ERR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_END_BIT_ERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_END_BIT_ERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_END_BIT_ERR_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_END_BIT_ERR_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_END_BIT_ERR_NO_ERR                      _MK_ENUM_CONST(0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_END_BIT_ERR_END_BIT_ERR_GENERATED                       _MK_ENUM_CONST(1)

#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_CRC_ERR_SHIFT                   _MK_SHIFT_CONST(2)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_CRC_ERR_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_AUTO_CMD12_ERR_STATUS_0_CRC_ERR_SHIFT)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_CRC_ERR_RANGE                   2:2
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_CRC_ERR_WOFFSET                 0x0
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_CRC_ERR_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_CRC_ERR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_CRC_ERR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_CRC_ERR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_CRC_ERR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_CRC_ERR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_CRC_ERR_NO_ERR                  _MK_ENUM_CONST(0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_CRC_ERR_CRC_ERR_GENERATED                       _MK_ENUM_CONST(1)

#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_TIMEOUT_ERR_SHIFT                       _MK_SHIFT_CONST(1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_TIMEOUT_ERR_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_AUTO_CMD12_ERR_STATUS_0_TIMEOUT_ERR_SHIFT)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_TIMEOUT_ERR_RANGE                       1:1
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_TIMEOUT_ERR_WOFFSET                     0x0
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_TIMEOUT_ERR_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_TIMEOUT_ERR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_TIMEOUT_ERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_TIMEOUT_ERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_TIMEOUT_ERR_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_TIMEOUT_ERR_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_TIMEOUT_ERR_NO_ERR                      _MK_ENUM_CONST(0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_TIMEOUT_ERR_TIMEOUT                     _MK_ENUM_CONST(1)

#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_NOT_EXECUTED_SHIFT                      _MK_SHIFT_CONST(0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_NOT_EXECUTED_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_AUTO_CMD12_ERR_STATUS_0_NOT_EXECUTED_SHIFT)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_NOT_EXECUTED_RANGE                      0:0
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_NOT_EXECUTED_WOFFSET                    0x0
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_NOT_EXECUTED_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_NOT_EXECUTED_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_NOT_EXECUTED_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_NOT_EXECUTED_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_NOT_EXECUTED_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_NOT_EXECUTED_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_NOT_EXECUTED_EXECUTED                   _MK_ENUM_CONST(0)
#define SDMMCAB_AUTO_CMD12_ERR_STATUS_0_NOT_EXECUTED_NOT_EXECUTED                       _MK_ENUM_CONST(1)


// Register SDMMCAB_CAPABILITIES_0
#define SDMMCAB_CAPABILITIES_0                  _MK_ADDR_CONST(0x40)
#define SDMMCAB_CAPABILITIES_0_SECURE                   0x0
#define SDMMCAB_CAPABILITIES_0_DUAL                     0x0
#define SDMMCAB_CAPABILITIES_0_SCR                      0
#define SDMMCAB_CAPABILITIES_0_WORD_COUNT                       0x1
#define SDMMCAB_CAPABILITIES_0_RESET_VAL                        _MK_MASK_CONST(0x3f6cd080)
#define SDMMCAB_CAPABILITIES_0_RESET_MASK                       _MK_MASK_CONST(0xffefffbf)
#define SDMMCAB_CAPABILITIES_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_READ_MASK                        _MK_MASK_CONST(0xffefffbf)
#define SDMMCAB_CAPABILITIES_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_SLOT_TYPE_SHIFT                  _MK_SHIFT_CONST(30)
#define SDMMCAB_CAPABILITIES_0_SLOT_TYPE_FIELD                  _MK_FIELD_CONST(0x3, SDMMCAB_CAPABILITIES_0_SLOT_TYPE_SHIFT)
#define SDMMCAB_CAPABILITIES_0_SLOT_TYPE_RANGE                  31:30
#define SDMMCAB_CAPABILITIES_0_SLOT_TYPE_WOFFSET                        0x0
#define SDMMCAB_CAPABILITIES_0_SLOT_TYPE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_SLOT_TYPE_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define SDMMCAB_CAPABILITIES_0_SLOT_TYPE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_SLOT_TYPE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_SLOT_TYPE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_SLOT_TYPE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_SLOT_TYPE_REMOVABLE                      _MK_ENUM_CONST(0)
#define SDMMCAB_CAPABILITIES_0_SLOT_TYPE_EMBEDDED                       _MK_ENUM_CONST(1)
#define SDMMCAB_CAPABILITIES_0_SLOT_TYPE_SHARED                 _MK_ENUM_CONST(2)
#define SDMMCAB_CAPABILITIES_0_SLOT_TYPE_UHS2_MULTIPLE_EMBEDDED                 _MK_ENUM_CONST(3)

#define SDMMCAB_CAPABILITIES_0_ASYNC_INTR_SHIFT                 _MK_SHIFT_CONST(29)
#define SDMMCAB_CAPABILITIES_0_ASYNC_INTR_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_CAPABILITIES_0_ASYNC_INTR_SHIFT)
#define SDMMCAB_CAPABILITIES_0_ASYNC_INTR_RANGE                 29:29
#define SDMMCAB_CAPABILITIES_0_ASYNC_INTR_WOFFSET                       0x0
#define SDMMCAB_CAPABILITIES_0_ASYNC_INTR_DEFAULT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_ASYNC_INTR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_ASYNC_INTR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_ASYNC_INTR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_ASYNC_INTR_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_ASYNC_INTR_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_ASYNC_INTR_NOT_SUPPORTED                 _MK_ENUM_CONST(0)
#define SDMMCAB_CAPABILITIES_0_ASYNC_INTR_SUPPORTED                     _MK_ENUM_CONST(1)

#define SDMMCAB_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_SHIFT                   _MK_SHIFT_CONST(28)
#define SDMMCAB_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_SHIFT)
#define SDMMCAB_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_RANGE                   28:28
#define SDMMCAB_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_WOFFSET                 0x0
#define SDMMCAB_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_DEFAULT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_NOT_SUPPORTED                   _MK_ENUM_CONST(0)
#define SDMMCAB_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_SUPPORTED                       _MK_ENUM_CONST(1)

#define SDMMCAB_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_V4_SHIFT                        _MK_SHIFT_CONST(27)
#define SDMMCAB_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_V4_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_V4_SHIFT)
#define SDMMCAB_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_V4_RANGE                        27:27
#define SDMMCAB_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_V4_WOFFSET                      0x0
#define SDMMCAB_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_V4_DEFAULT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_V4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_V4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_V4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_V4_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_V4_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_V4_NOT_SUPPORTED                        _MK_ENUM_CONST(0)
#define SDMMCAB_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_V4_SUPPORTED                    _MK_ENUM_CONST(1)

#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_1_8_V_SHIFT                      _MK_SHIFT_CONST(26)
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_1_8_V_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_1_8_V_SHIFT)
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_1_8_V_RANGE                      26:26
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_1_8_V_WOFFSET                    0x0
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_1_8_V_DEFAULT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_1_8_V_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_1_8_V_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_1_8_V_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_1_8_V_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_1_8_V_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_1_8_V_NOT_SUPPORTED                      _MK_ENUM_CONST(0)
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_1_8_V_SUPPORTED                  _MK_ENUM_CONST(1)

#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_3_0_V_SHIFT                      _MK_SHIFT_CONST(25)
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_3_0_V_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_3_0_V_SHIFT)
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_3_0_V_RANGE                      25:25
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_3_0_V_WOFFSET                    0x0
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_3_0_V_DEFAULT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_3_0_V_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_3_0_V_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_3_0_V_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_3_0_V_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_3_0_V_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_3_0_V_NOT_SUPPORTED                      _MK_ENUM_CONST(0)
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_3_0_V_SUPPORTED                  _MK_ENUM_CONST(1)

#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_3_3_V_SHIFT                      _MK_SHIFT_CONST(24)
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_3_3_V_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_3_3_V_SHIFT)
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_3_3_V_RANGE                      24:24
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_3_3_V_WOFFSET                    0x0
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_3_3_V_DEFAULT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_3_3_V_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_3_3_V_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_3_3_V_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_3_3_V_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_3_3_V_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_3_3_V_NOT_SUPPORTED                      _MK_ENUM_CONST(0)
#define SDMMCAB_CAPABILITIES_0_VOLTAGE_SUPPORT_3_3_V_SUPPORTED                  _MK_ENUM_CONST(1)

#define SDMMCAB_CAPABILITIES_0_SUSPEND_RESUME_SUPPORT_SHIFT                     _MK_SHIFT_CONST(23)
#define SDMMCAB_CAPABILITIES_0_SUSPEND_RESUME_SUPPORT_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_CAPABILITIES_0_SUSPEND_RESUME_SUPPORT_SHIFT)
#define SDMMCAB_CAPABILITIES_0_SUSPEND_RESUME_SUPPORT_RANGE                     23:23
#define SDMMCAB_CAPABILITIES_0_SUSPEND_RESUME_SUPPORT_WOFFSET                   0x0
#define SDMMCAB_CAPABILITIES_0_SUSPEND_RESUME_SUPPORT_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_SUSPEND_RESUME_SUPPORT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_SUSPEND_RESUME_SUPPORT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_SUSPEND_RESUME_SUPPORT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_SUSPEND_RESUME_SUPPORT_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_SUSPEND_RESUME_SUPPORT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_SUSPEND_RESUME_SUPPORT_NOT_SUPPORTED                     _MK_ENUM_CONST(0)
#define SDMMCAB_CAPABILITIES_0_SUSPEND_RESUME_SUPPORT_SUPPORTED                 _MK_ENUM_CONST(1)

#define SDMMCAB_CAPABILITIES_0_DMA_SUPPORT_SHIFT                        _MK_SHIFT_CONST(22)
#define SDMMCAB_CAPABILITIES_0_DMA_SUPPORT_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_CAPABILITIES_0_DMA_SUPPORT_SHIFT)
#define SDMMCAB_CAPABILITIES_0_DMA_SUPPORT_RANGE                        22:22
#define SDMMCAB_CAPABILITIES_0_DMA_SUPPORT_WOFFSET                      0x0
#define SDMMCAB_CAPABILITIES_0_DMA_SUPPORT_DEFAULT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_DMA_SUPPORT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_DMA_SUPPORT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_DMA_SUPPORT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_DMA_SUPPORT_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_DMA_SUPPORT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_DMA_SUPPORT_NOT_SUPPORTED                        _MK_ENUM_CONST(0)
#define SDMMCAB_CAPABILITIES_0_DMA_SUPPORT_SUPPORTED                    _MK_ENUM_CONST(1)

#define SDMMCAB_CAPABILITIES_0_HIGH_SPEED_SUPPORT_SHIFT                 _MK_SHIFT_CONST(21)
#define SDMMCAB_CAPABILITIES_0_HIGH_SPEED_SUPPORT_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_CAPABILITIES_0_HIGH_SPEED_SUPPORT_SHIFT)
#define SDMMCAB_CAPABILITIES_0_HIGH_SPEED_SUPPORT_RANGE                 21:21
#define SDMMCAB_CAPABILITIES_0_HIGH_SPEED_SUPPORT_WOFFSET                       0x0
#define SDMMCAB_CAPABILITIES_0_HIGH_SPEED_SUPPORT_DEFAULT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_HIGH_SPEED_SUPPORT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_HIGH_SPEED_SUPPORT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_HIGH_SPEED_SUPPORT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_HIGH_SPEED_SUPPORT_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_HIGH_SPEED_SUPPORT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_HIGH_SPEED_SUPPORT_NOT_SUPPORTED                 _MK_ENUM_CONST(0)
#define SDMMCAB_CAPABILITIES_0_HIGH_SPEED_SUPPORT_SUPPORTED                     _MK_ENUM_CONST(1)

#define SDMMCAB_CAPABILITIES_0_ADMA2_SUPPORT_SHIFT                      _MK_SHIFT_CONST(19)
#define SDMMCAB_CAPABILITIES_0_ADMA2_SUPPORT_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_CAPABILITIES_0_ADMA2_SUPPORT_SHIFT)
#define SDMMCAB_CAPABILITIES_0_ADMA2_SUPPORT_RANGE                      19:19
#define SDMMCAB_CAPABILITIES_0_ADMA2_SUPPORT_WOFFSET                    0x0
#define SDMMCAB_CAPABILITIES_0_ADMA2_SUPPORT_DEFAULT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_ADMA2_SUPPORT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_ADMA2_SUPPORT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_ADMA2_SUPPORT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_ADMA2_SUPPORT_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_ADMA2_SUPPORT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_ADMA2_SUPPORT_NOT_SUPPORTED                      _MK_ENUM_CONST(0)
#define SDMMCAB_CAPABILITIES_0_ADMA2_SUPPORT_SUPPORTED                  _MK_ENUM_CONST(1)

#define SDMMCAB_CAPABILITIES_0_EXTENDED_MEDIA_BUS_SUPPORT_SHIFT                 _MK_SHIFT_CONST(18)
#define SDMMCAB_CAPABILITIES_0_EXTENDED_MEDIA_BUS_SUPPORT_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_CAPABILITIES_0_EXTENDED_MEDIA_BUS_SUPPORT_SHIFT)
#define SDMMCAB_CAPABILITIES_0_EXTENDED_MEDIA_BUS_SUPPORT_RANGE                 18:18
#define SDMMCAB_CAPABILITIES_0_EXTENDED_MEDIA_BUS_SUPPORT_WOFFSET                       0x0
#define SDMMCAB_CAPABILITIES_0_EXTENDED_MEDIA_BUS_SUPPORT_DEFAULT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_EXTENDED_MEDIA_BUS_SUPPORT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_EXTENDED_MEDIA_BUS_SUPPORT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_EXTENDED_MEDIA_BUS_SUPPORT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_EXTENDED_MEDIA_BUS_SUPPORT_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_EXTENDED_MEDIA_BUS_SUPPORT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_EXTENDED_MEDIA_BUS_SUPPORT_NOT_SUPPORTED                 _MK_ENUM_CONST(0)
#define SDMMCAB_CAPABILITIES_0_EXTENDED_MEDIA_BUS_SUPPORT_SUPPORTED                     _MK_ENUM_CONST(1)

#define SDMMCAB_CAPABILITIES_0_MAX_BLOCK_LENGTH_SHIFT                   _MK_SHIFT_CONST(16)
#define SDMMCAB_CAPABILITIES_0_MAX_BLOCK_LENGTH_FIELD                   _MK_FIELD_CONST(0x3, SDMMCAB_CAPABILITIES_0_MAX_BLOCK_LENGTH_SHIFT)
#define SDMMCAB_CAPABILITIES_0_MAX_BLOCK_LENGTH_RANGE                   17:16
#define SDMMCAB_CAPABILITIES_0_MAX_BLOCK_LENGTH_WOFFSET                 0x0
#define SDMMCAB_CAPABILITIES_0_MAX_BLOCK_LENGTH_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_MAX_BLOCK_LENGTH_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define SDMMCAB_CAPABILITIES_0_MAX_BLOCK_LENGTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_MAX_BLOCK_LENGTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_MAX_BLOCK_LENGTH_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_MAX_BLOCK_LENGTH_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_MAX_BLOCK_LENGTH_BYTE512                 _MK_ENUM_CONST(0)
#define SDMMCAB_CAPABILITIES_0_MAX_BLOCK_LENGTH_BYTE1024                        _MK_ENUM_CONST(1)
#define SDMMCAB_CAPABILITIES_0_MAX_BLOCK_LENGTH_BYTE2048                        _MK_ENUM_CONST(2)
#define SDMMCAB_CAPABILITIES_0_MAX_BLOCK_LENGTH_RESERVED                        _MK_ENUM_CONST(3)

#define SDMMCAB_CAPABILITIES_0_BASE_CLOCK_FREQUENCY_SHIFT                       _MK_SHIFT_CONST(8)
#define SDMMCAB_CAPABILITIES_0_BASE_CLOCK_FREQUENCY_FIELD                       _MK_FIELD_CONST(0xff, SDMMCAB_CAPABILITIES_0_BASE_CLOCK_FREQUENCY_SHIFT)
#define SDMMCAB_CAPABILITIES_0_BASE_CLOCK_FREQUENCY_RANGE                       15:8
#define SDMMCAB_CAPABILITIES_0_BASE_CLOCK_FREQUENCY_WOFFSET                     0x0
#define SDMMCAB_CAPABILITIES_0_BASE_CLOCK_FREQUENCY_DEFAULT                     _MK_MASK_CONST(0xd0)
#define SDMMCAB_CAPABILITIES_0_BASE_CLOCK_FREQUENCY_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define SDMMCAB_CAPABILITIES_0_BASE_CLOCK_FREQUENCY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_BASE_CLOCK_FREQUENCY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_BASE_CLOCK_FREQUENCY_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_BASE_CLOCK_FREQUENCY_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SDMMCAB_CAPABILITIES_0_TIMEOUT_CLOCK_UNIT_SHIFT                 _MK_SHIFT_CONST(7)
#define SDMMCAB_CAPABILITIES_0_TIMEOUT_CLOCK_UNIT_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_CAPABILITIES_0_TIMEOUT_CLOCK_UNIT_SHIFT)
#define SDMMCAB_CAPABILITIES_0_TIMEOUT_CLOCK_UNIT_RANGE                 7:7
#define SDMMCAB_CAPABILITIES_0_TIMEOUT_CLOCK_UNIT_WOFFSET                       0x0
#define SDMMCAB_CAPABILITIES_0_TIMEOUT_CLOCK_UNIT_DEFAULT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_TIMEOUT_CLOCK_UNIT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_TIMEOUT_CLOCK_UNIT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_TIMEOUT_CLOCK_UNIT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_TIMEOUT_CLOCK_UNIT_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_TIMEOUT_CLOCK_UNIT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_TIMEOUT_CLOCK_UNIT_KHZ                   _MK_ENUM_CONST(0)
#define SDMMCAB_CAPABILITIES_0_TIMEOUT_CLOCK_UNIT_MHZ                   _MK_ENUM_CONST(1)

#define SDMMCAB_CAPABILITIES_0_TIMEOUT_CLOCK_FREQUENCY_SHIFT                    _MK_SHIFT_CONST(0)
#define SDMMCAB_CAPABILITIES_0_TIMEOUT_CLOCK_FREQUENCY_FIELD                    _MK_FIELD_CONST(0x3f, SDMMCAB_CAPABILITIES_0_TIMEOUT_CLOCK_FREQUENCY_SHIFT)
#define SDMMCAB_CAPABILITIES_0_TIMEOUT_CLOCK_FREQUENCY_RANGE                    5:0
#define SDMMCAB_CAPABILITIES_0_TIMEOUT_CLOCK_FREQUENCY_WOFFSET                  0x0
#define SDMMCAB_CAPABILITIES_0_TIMEOUT_CLOCK_FREQUENCY_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_TIMEOUT_CLOCK_FREQUENCY_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
#define SDMMCAB_CAPABILITIES_0_TIMEOUT_CLOCK_FREQUENCY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_TIMEOUT_CLOCK_FREQUENCY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_TIMEOUT_CLOCK_FREQUENCY_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_0_TIMEOUT_CLOCK_FREQUENCY_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_0_TIMEOUT_CLOCK_FREQUENCY__PROD                    _MK_ENUM_CONST(12)


// Register SDMMCAB_CAPABILITIES_HIGHER_0
#define SDMMCAB_CAPABILITIES_HIGHER_0                   _MK_ADDR_CONST(0x44)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SECURE                    0x0
#define SDMMCAB_CAPABILITIES_HIGHER_0_DUAL                      0x0
#define SDMMCAB_CAPABILITIES_HIGHER_0_SCR                       0
#define SDMMCAB_CAPABILITIES_HIGHER_0_WORD_COUNT                        0x1
#define SDMMCAB_CAPABILITIES_HIGHER_0_RESET_VAL                         _MK_MASK_CONST(0x18002f73)
#define SDMMCAB_CAPABILITIES_HIGHER_0_RESET_MASK                        _MK_MASK_CONST(0x18ffef7f)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_READ_MASK                         _MK_MASK_CONST(0x18ffef7f)
#define SDMMCAB_CAPABILITIES_HIGHER_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_VDD2_1_8V_SUPPORT_SHIFT                   _MK_SHIFT_CONST(28)
#define SDMMCAB_CAPABILITIES_HIGHER_0_VDD2_1_8V_SUPPORT_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_CAPABILITIES_HIGHER_0_VDD2_1_8V_SUPPORT_SHIFT)
#define SDMMCAB_CAPABILITIES_HIGHER_0_VDD2_1_8V_SUPPORT_RANGE                   28:28
#define SDMMCAB_CAPABILITIES_HIGHER_0_VDD2_1_8V_SUPPORT_WOFFSET                 0x0
#define SDMMCAB_CAPABILITIES_HIGHER_0_VDD2_1_8V_SUPPORT_DEFAULT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_VDD2_1_8V_SUPPORT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_VDD2_1_8V_SUPPORT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_VDD2_1_8V_SUPPORT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_VDD2_1_8V_SUPPORT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_VDD2_1_8V_SUPPORT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_VDD2_1_8V_SUPPORT_NOT_SUPPORTED                   _MK_ENUM_CONST(0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_VDD2_1_8V_SUPPORT_SUPPORTED                       _MK_ENUM_CONST(1)

#define SDMMCAB_CAPABILITIES_HIGHER_0_ADMA3_SUPPORT_SHIFT                       _MK_SHIFT_CONST(27)
#define SDMMCAB_CAPABILITIES_HIGHER_0_ADMA3_SUPPORT_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_CAPABILITIES_HIGHER_0_ADMA3_SUPPORT_SHIFT)
#define SDMMCAB_CAPABILITIES_HIGHER_0_ADMA3_SUPPORT_RANGE                       27:27
#define SDMMCAB_CAPABILITIES_HIGHER_0_ADMA3_SUPPORT_WOFFSET                     0x0
#define SDMMCAB_CAPABILITIES_HIGHER_0_ADMA3_SUPPORT_DEFAULT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_ADMA3_SUPPORT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_ADMA3_SUPPORT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_ADMA3_SUPPORT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_ADMA3_SUPPORT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_ADMA3_SUPPORT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_ADMA3_SUPPORT_NOT_SUPPORTED                       _MK_ENUM_CONST(0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_ADMA3_SUPPORT_SUPPORTED                   _MK_ENUM_CONST(1)

#define SDMMCAB_CAPABILITIES_HIGHER_0_CLOCK_MULTIPLIER_SHIFT                    _MK_SHIFT_CONST(16)
#define SDMMCAB_CAPABILITIES_HIGHER_0_CLOCK_MULTIPLIER_FIELD                    _MK_FIELD_CONST(0xff, SDMMCAB_CAPABILITIES_HIGHER_0_CLOCK_MULTIPLIER_SHIFT)
#define SDMMCAB_CAPABILITIES_HIGHER_0_CLOCK_MULTIPLIER_RANGE                    23:16
#define SDMMCAB_CAPABILITIES_HIGHER_0_CLOCK_MULTIPLIER_WOFFSET                  0x0
#define SDMMCAB_CAPABILITIES_HIGHER_0_CLOCK_MULTIPLIER_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_CLOCK_MULTIPLIER_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SDMMCAB_CAPABILITIES_HIGHER_0_CLOCK_MULTIPLIER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_CLOCK_MULTIPLIER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_CLOCK_MULTIPLIER_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_CLOCK_MULTIPLIER_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SDMMCAB_CAPABILITIES_HIGHER_0_RETUNING_MODES_SHIFT                      _MK_SHIFT_CONST(14)
#define SDMMCAB_CAPABILITIES_HIGHER_0_RETUNING_MODES_FIELD                      _MK_FIELD_CONST(0x3, SDMMCAB_CAPABILITIES_HIGHER_0_RETUNING_MODES_SHIFT)
#define SDMMCAB_CAPABILITIES_HIGHER_0_RETUNING_MODES_RANGE                      15:14
#define SDMMCAB_CAPABILITIES_HIGHER_0_RETUNING_MODES_WOFFSET                    0x0
#define SDMMCAB_CAPABILITIES_HIGHER_0_RETUNING_MODES_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_RETUNING_MODES_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define SDMMCAB_CAPABILITIES_HIGHER_0_RETUNING_MODES_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_RETUNING_MODES_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_RETUNING_MODES_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_RETUNING_MODES_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_RETUNING_MODES_MODE1                      _MK_ENUM_CONST(0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_RETUNING_MODES_MODE2                      _MK_ENUM_CONST(1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_RETUNING_MODES_MODE3                      _MK_ENUM_CONST(2)
#define SDMMCAB_CAPABILITIES_HIGHER_0_RETUNING_MODES_MODE4                      _MK_ENUM_CONST(3)

#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR50_TUNING_SHIFT                        _MK_SHIFT_CONST(13)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR50_TUNING_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_CAPABILITIES_HIGHER_0_SDR50_TUNING_SHIFT)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR50_TUNING_RANGE                        13:13
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR50_TUNING_WOFFSET                      0x0
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR50_TUNING_DEFAULT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR50_TUNING_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR50_TUNING_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR50_TUNING_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR50_TUNING_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR50_TUNING_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR50_TUNING_NOT_REQUIRED                 _MK_ENUM_CONST(0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR50_TUNING_REQUIRED                     _MK_ENUM_CONST(1)

#define SDMMCAB_CAPABILITIES_HIGHER_0_RETUNING_TIMER_COUNT_SHIFT                        _MK_SHIFT_CONST(8)
#define SDMMCAB_CAPABILITIES_HIGHER_0_RETUNING_TIMER_COUNT_FIELD                        _MK_FIELD_CONST(0xf, SDMMCAB_CAPABILITIES_HIGHER_0_RETUNING_TIMER_COUNT_SHIFT)
#define SDMMCAB_CAPABILITIES_HIGHER_0_RETUNING_TIMER_COUNT_RANGE                        11:8
#define SDMMCAB_CAPABILITIES_HIGHER_0_RETUNING_TIMER_COUNT_WOFFSET                      0x0
#define SDMMCAB_CAPABILITIES_HIGHER_0_RETUNING_TIMER_COUNT_DEFAULT                      _MK_MASK_CONST(0xf)
#define SDMMCAB_CAPABILITIES_HIGHER_0_RETUNING_TIMER_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define SDMMCAB_CAPABILITIES_HIGHER_0_RETUNING_TIMER_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_RETUNING_TIMER_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_RETUNING_TIMER_COUNT_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_RETUNING_TIMER_COUNT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_D_DRIVER_SHIFT                       _MK_SHIFT_CONST(6)
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_D_DRIVER_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_D_DRIVER_SHIFT)
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_D_DRIVER_RANGE                       6:6
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_D_DRIVER_WOFFSET                     0x0
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_D_DRIVER_DEFAULT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_D_DRIVER_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_D_DRIVER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_D_DRIVER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_D_DRIVER_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_D_DRIVER_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_D_DRIVER_NOT_SUPPORTED                       _MK_ENUM_CONST(0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_D_DRIVER_SUPPORTED                   _MK_ENUM_CONST(1)

#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_C_DRIVER_SHIFT                       _MK_SHIFT_CONST(5)
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_C_DRIVER_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_C_DRIVER_SHIFT)
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_C_DRIVER_RANGE                       5:5
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_C_DRIVER_WOFFSET                     0x0
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_C_DRIVER_DEFAULT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_C_DRIVER_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_C_DRIVER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_C_DRIVER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_C_DRIVER_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_C_DRIVER_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_C_DRIVER_NOT_SUPPORTED                       _MK_ENUM_CONST(0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_C_DRIVER_SUPPORTED                   _MK_ENUM_CONST(1)

#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_A_DRIVER_SHIFT                       _MK_SHIFT_CONST(4)
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_A_DRIVER_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_A_DRIVER_SHIFT)
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_A_DRIVER_RANGE                       4:4
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_A_DRIVER_WOFFSET                     0x0
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_A_DRIVER_DEFAULT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_A_DRIVER_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_A_DRIVER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_A_DRIVER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_A_DRIVER_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_A_DRIVER_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_A_DRIVER_NOT_SUPPORTED                       _MK_ENUM_CONST(0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_TYPE_A_DRIVER_SUPPORTED                   _MK_ENUM_CONST(1)

#define SDMMCAB_CAPABILITIES_HIGHER_0_UHS2_SUPPORT_SHIFT                        _MK_SHIFT_CONST(3)
#define SDMMCAB_CAPABILITIES_HIGHER_0_UHS2_SUPPORT_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_CAPABILITIES_HIGHER_0_UHS2_SUPPORT_SHIFT)
#define SDMMCAB_CAPABILITIES_HIGHER_0_UHS2_SUPPORT_RANGE                        3:3
#define SDMMCAB_CAPABILITIES_HIGHER_0_UHS2_SUPPORT_WOFFSET                      0x0
#define SDMMCAB_CAPABILITIES_HIGHER_0_UHS2_SUPPORT_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_UHS2_SUPPORT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_UHS2_SUPPORT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_UHS2_SUPPORT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_UHS2_SUPPORT_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_UHS2_SUPPORT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_UHS2_SUPPORT_NOT_SUPPORTED                        _MK_ENUM_CONST(0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_UHS2_SUPPORT_SUPPORTED                    _MK_ENUM_CONST(1)

#define SDMMCAB_CAPABILITIES_HIGHER_0_DDR50_SHIFT                       _MK_SHIFT_CONST(2)
#define SDMMCAB_CAPABILITIES_HIGHER_0_DDR50_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_CAPABILITIES_HIGHER_0_DDR50_SHIFT)
#define SDMMCAB_CAPABILITIES_HIGHER_0_DDR50_RANGE                       2:2
#define SDMMCAB_CAPABILITIES_HIGHER_0_DDR50_WOFFSET                     0x0
#define SDMMCAB_CAPABILITIES_HIGHER_0_DDR50_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_DDR50_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_DDR50_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_DDR50_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_DDR50_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_DDR50_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_DDR50_NOT_SUPPORTED                       _MK_ENUM_CONST(0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_DDR50_SUPPORTED                   _MK_ENUM_CONST(1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_DDR50__PROD                       _MK_ENUM_CONST(1)

#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR104_SHIFT                      _MK_SHIFT_CONST(1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR104_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_CAPABILITIES_HIGHER_0_SDR104_SHIFT)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR104_RANGE                      1:1
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR104_WOFFSET                    0x0
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR104_DEFAULT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR104_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR104_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR104_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR104_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR104_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR104_NOT_SUPPORTED                      _MK_ENUM_CONST(0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR104_SUPPORTED                  _MK_ENUM_CONST(1)

#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR50_SHIFT                       _MK_SHIFT_CONST(0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR50_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_CAPABILITIES_HIGHER_0_SDR50_SHIFT)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR50_RANGE                       0:0
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR50_WOFFSET                     0x0
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR50_DEFAULT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR50_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR50_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR50_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR50_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR50_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR50_NOT_SUPPORTED                       _MK_ENUM_CONST(0)
#define SDMMCAB_CAPABILITIES_HIGHER_0_SDR50_SUPPORTED                   _MK_ENUM_CONST(1)


// Register SDMMCAB_MAXIMUM_CURRENT_0
#define SDMMCAB_MAXIMUM_CURRENT_0                       _MK_ADDR_CONST(0x48)
#define SDMMCAB_MAXIMUM_CURRENT_0_SECURE                        0x0
#define SDMMCAB_MAXIMUM_CURRENT_0_DUAL                  0x0
#define SDMMCAB_MAXIMUM_CURRENT_0_SCR                   0
#define SDMMCAB_MAXIMUM_CURRENT_0_WORD_COUNT                    0x1
#define SDMMCAB_MAXIMUM_CURRENT_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define SDMMCAB_MAXIMUM_CURRENT_0_RESET_MASK                    _MK_MASK_CONST(0xffffff)
#define SDMMCAB_MAXIMUM_CURRENT_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SDMMCAB_MAXIMUM_CURRENT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_MAXIMUM_CURRENT_0_READ_MASK                     _MK_MASK_CONST(0xffffff)
#define SDMMCAB_MAXIMUM_CURRENT_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_1_8V_SHIFT                        _MK_SHIFT_CONST(16)
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_1_8V_FIELD                        _MK_FIELD_CONST(0xff, SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_1_8V_SHIFT)
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_1_8V_RANGE                        23:16
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_1_8V_WOFFSET                      0x0
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_1_8V_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_1_8V_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_1_8V_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_1_8V_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_1_8V_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_1_8V_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_0V_SHIFT                        _MK_SHIFT_CONST(8)
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_0V_FIELD                        _MK_FIELD_CONST(0xff, SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_0V_SHIFT)
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_0V_RANGE                        15:8
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_0V_WOFFSET                      0x0
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_0V_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_0V_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_0V_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_0V_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_0V_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_0V_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_3V_SHIFT                        _MK_SHIFT_CONST(0)
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_3V_FIELD                        _MK_FIELD_CONST(0xff, SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_3V_SHIFT)
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_3V_RANGE                        7:0
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_3V_WOFFSET                      0x0
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_3V_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_3V_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_3V_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_3V_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_3V_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_3V_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register SDMMCAB_MAXIMUM_CURRENT_HI_0
#define SDMMCAB_MAXIMUM_CURRENT_HI_0                    _MK_ADDR_CONST(0x4c)
#define SDMMCAB_MAXIMUM_CURRENT_HI_0_SECURE                     0x0
#define SDMMCAB_MAXIMUM_CURRENT_HI_0_DUAL                       0x0
#define SDMMCAB_MAXIMUM_CURRENT_HI_0_SCR                        0
#define SDMMCAB_MAXIMUM_CURRENT_HI_0_WORD_COUNT                         0x1
#define SDMMCAB_MAXIMUM_CURRENT_HI_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SDMMCAB_MAXIMUM_CURRENT_HI_0_RESET_MASK                         _MK_MASK_CONST(0xff)
#define SDMMCAB_MAXIMUM_CURRENT_HI_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SDMMCAB_MAXIMUM_CURRENT_HI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_MAXIMUM_CURRENT_HI_0_READ_MASK                  _MK_MASK_CONST(0xff)
#define SDMMCAB_MAXIMUM_CURRENT_HI_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
#define SDMMCAB_MAXIMUM_CURRENT_HI_0_MAXIMUM_CURRENT_FOR_1_8V_VDD2_SHIFT                        _MK_SHIFT_CONST(0)
#define SDMMCAB_MAXIMUM_CURRENT_HI_0_MAXIMUM_CURRENT_FOR_1_8V_VDD2_FIELD                        _MK_FIELD_CONST(0xff, SDMMCAB_MAXIMUM_CURRENT_HI_0_MAXIMUM_CURRENT_FOR_1_8V_VDD2_SHIFT)
#define SDMMCAB_MAXIMUM_CURRENT_HI_0_MAXIMUM_CURRENT_FOR_1_8V_VDD2_RANGE                        7:0
#define SDMMCAB_MAXIMUM_CURRENT_HI_0_MAXIMUM_CURRENT_FOR_1_8V_VDD2_WOFFSET                      0x0
#define SDMMCAB_MAXIMUM_CURRENT_HI_0_MAXIMUM_CURRENT_FOR_1_8V_VDD2_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_MAXIMUM_CURRENT_HI_0_MAXIMUM_CURRENT_FOR_1_8V_VDD2_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SDMMCAB_MAXIMUM_CURRENT_HI_0_MAXIMUM_CURRENT_FOR_1_8V_VDD2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_MAXIMUM_CURRENT_HI_0_MAXIMUM_CURRENT_FOR_1_8V_VDD2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_MAXIMUM_CURRENT_HI_0_MAXIMUM_CURRENT_FOR_1_8V_VDD2_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_MAXIMUM_CURRENT_HI_0_MAXIMUM_CURRENT_FOR_1_8V_VDD2_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register SDMMCAB_FORCE_EVENT_0
#define SDMMCAB_FORCE_EVENT_0                   _MK_ADDR_CONST(0x50)
#define SDMMCAB_FORCE_EVENT_0_SECURE                    0x0
#define SDMMCAB_FORCE_EVENT_0_DUAL                      0x0
#define SDMMCAB_FORCE_EVENT_0_SCR                       0
#define SDMMCAB_FORCE_EVENT_0_WORD_COUNT                        0x1
#define SDMMCAB_FORCE_EVENT_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_RESET_MASK                        _MK_MASK_CONST(0xffff00bf)
#define SDMMCAB_FORCE_EVENT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_READ_MASK                         _MK_MASK_CONST(0xffff00bf)
#define SDMMCAB_FORCE_EVENT_0_WRITE_MASK                        _MK_MASK_CONST(0xffff00bf)
#define SDMMCAB_FORCE_EVENT_0_VENDOR_SPECIFIC_ERR_STATUS_SHIFT                  _MK_SHIFT_CONST(30)
#define SDMMCAB_FORCE_EVENT_0_VENDOR_SPECIFIC_ERR_STATUS_FIELD                  _MK_FIELD_CONST(0x3, SDMMCAB_FORCE_EVENT_0_VENDOR_SPECIFIC_ERR_STATUS_SHIFT)
#define SDMMCAB_FORCE_EVENT_0_VENDOR_SPECIFIC_ERR_STATUS_RANGE                  31:30
#define SDMMCAB_FORCE_EVENT_0_VENDOR_SPECIFIC_ERR_STATUS_WOFFSET                        0x0
#define SDMMCAB_FORCE_EVENT_0_VENDOR_SPECIFIC_ERR_STATUS_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_VENDOR_SPECIFIC_ERR_STATUS_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define SDMMCAB_FORCE_EVENT_0_VENDOR_SPECIFIC_ERR_STATUS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_VENDOR_SPECIFIC_ERR_STATUS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_VENDOR_SPECIFIC_ERR_STATUS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_VENDOR_SPECIFIC_ERR_STATUS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_VENDOR_SPECIFIC_ERR_STATUS_DISABLE                        _MK_ENUM_CONST(0)
#define SDMMCAB_FORCE_EVENT_0_VENDOR_SPECIFIC_ERR_STATUS_ENABLE                 _MK_ENUM_CONST(3)

#define SDMMCAB_FORCE_EVENT_0_SPI_ERR_SHIFT                     _MK_SHIFT_CONST(29)
#define SDMMCAB_FORCE_EVENT_0_SPI_ERR_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_FORCE_EVENT_0_SPI_ERR_SHIFT)
#define SDMMCAB_FORCE_EVENT_0_SPI_ERR_RANGE                     29:29
#define SDMMCAB_FORCE_EVENT_0_SPI_ERR_WOFFSET                   0x0
#define SDMMCAB_FORCE_EVENT_0_SPI_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_SPI_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_SPI_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_SPI_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_SPI_ERR_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_SPI_ERR_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_SPI_ERR_DISABLE                   _MK_ENUM_CONST(0)
#define SDMMCAB_FORCE_EVENT_0_SPI_ERR_ENABLE                    _MK_ENUM_CONST(1)

#define SDMMCAB_FORCE_EVENT_0_TARGET_RESP_ERROR_SHIFT                   _MK_SHIFT_CONST(28)
#define SDMMCAB_FORCE_EVENT_0_TARGET_RESP_ERROR_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_FORCE_EVENT_0_TARGET_RESP_ERROR_SHIFT)
#define SDMMCAB_FORCE_EVENT_0_TARGET_RESP_ERROR_RANGE                   28:28
#define SDMMCAB_FORCE_EVENT_0_TARGET_RESP_ERROR_WOFFSET                 0x0
#define SDMMCAB_FORCE_EVENT_0_TARGET_RESP_ERROR_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_TARGET_RESP_ERROR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_TARGET_RESP_ERROR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_TARGET_RESP_ERROR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_TARGET_RESP_ERROR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_TARGET_RESP_ERROR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_TARGET_RESP_ERROR_NO_ERROR                        _MK_ENUM_CONST(0)
#define SDMMCAB_FORCE_EVENT_0_TARGET_RESP_ERROR_ERROR                   _MK_ENUM_CONST(1)

#define SDMMCAB_FORCE_EVENT_0_RESP_ERROR_SHIFT                  _MK_SHIFT_CONST(27)
#define SDMMCAB_FORCE_EVENT_0_RESP_ERROR_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_FORCE_EVENT_0_RESP_ERROR_SHIFT)
#define SDMMCAB_FORCE_EVENT_0_RESP_ERROR_RANGE                  27:27
#define SDMMCAB_FORCE_EVENT_0_RESP_ERROR_WOFFSET                        0x0
#define SDMMCAB_FORCE_EVENT_0_RESP_ERROR_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_RESP_ERROR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_RESP_ERROR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_RESP_ERROR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_RESP_ERROR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_RESP_ERROR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_RESP_ERROR_NO_ERROR                       _MK_ENUM_CONST(0)
#define SDMMCAB_FORCE_EVENT_0_RESP_ERROR_ERROR                  _MK_ENUM_CONST(1)

#define SDMMCAB_FORCE_EVENT_0_TUNING_ERR_SHIFT                  _MK_SHIFT_CONST(26)
#define SDMMCAB_FORCE_EVENT_0_TUNING_ERR_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_FORCE_EVENT_0_TUNING_ERR_SHIFT)
#define SDMMCAB_FORCE_EVENT_0_TUNING_ERR_RANGE                  26:26
#define SDMMCAB_FORCE_EVENT_0_TUNING_ERR_WOFFSET                        0x0
#define SDMMCAB_FORCE_EVENT_0_TUNING_ERR_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_TUNING_ERR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_TUNING_ERR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_TUNING_ERR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_TUNING_ERR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_TUNING_ERR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_TUNING_ERR_DISABLE                        _MK_ENUM_CONST(0)
#define SDMMCAB_FORCE_EVENT_0_TUNING_ERR_ENABLE                 _MK_ENUM_CONST(1)

#define SDMMCAB_FORCE_EVENT_0_ADMA_ERR_SHIFT                    _MK_SHIFT_CONST(25)
#define SDMMCAB_FORCE_EVENT_0_ADMA_ERR_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_FORCE_EVENT_0_ADMA_ERR_SHIFT)
#define SDMMCAB_FORCE_EVENT_0_ADMA_ERR_RANGE                    25:25
#define SDMMCAB_FORCE_EVENT_0_ADMA_ERR_WOFFSET                  0x0
#define SDMMCAB_FORCE_EVENT_0_ADMA_ERR_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_ADMA_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_ADMA_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_ADMA_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_ADMA_ERR_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_ADMA_ERR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_ADMA_ERR_NO_INTERRUPT                     _MK_ENUM_CONST(0)
#define SDMMCAB_FORCE_EVENT_0_ADMA_ERR_INTERRUPT                        _MK_ENUM_CONST(1)

#define SDMMCAB_FORCE_EVENT_0_AUTOCMD12_ERR_SHIFT                       _MK_SHIFT_CONST(24)
#define SDMMCAB_FORCE_EVENT_0_AUTOCMD12_ERR_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_FORCE_EVENT_0_AUTOCMD12_ERR_SHIFT)
#define SDMMCAB_FORCE_EVENT_0_AUTOCMD12_ERR_RANGE                       24:24
#define SDMMCAB_FORCE_EVENT_0_AUTOCMD12_ERR_WOFFSET                     0x0
#define SDMMCAB_FORCE_EVENT_0_AUTOCMD12_ERR_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTOCMD12_ERR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_AUTOCMD12_ERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTOCMD12_ERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTOCMD12_ERR_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTOCMD12_ERR_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_AUTOCMD12_ERR_NO_INTERRUPT                        _MK_ENUM_CONST(0)
#define SDMMCAB_FORCE_EVENT_0_AUTOCMD12_ERR_INTERRUPT                   _MK_ENUM_CONST(1)

#define SDMMCAB_FORCE_EVENT_0_CURRENTLIMIT_ERR_SHIFT                    _MK_SHIFT_CONST(23)
#define SDMMCAB_FORCE_EVENT_0_CURRENTLIMIT_ERR_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_FORCE_EVENT_0_CURRENTLIMIT_ERR_SHIFT)
#define SDMMCAB_FORCE_EVENT_0_CURRENTLIMIT_ERR_RANGE                    23:23
#define SDMMCAB_FORCE_EVENT_0_CURRENTLIMIT_ERR_WOFFSET                  0x0
#define SDMMCAB_FORCE_EVENT_0_CURRENTLIMIT_ERR_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_CURRENTLIMIT_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_CURRENTLIMIT_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_CURRENTLIMIT_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_CURRENTLIMIT_ERR_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_CURRENTLIMIT_ERR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_CURRENTLIMIT_ERR_NO_INTERRUPT                     _MK_ENUM_CONST(0)
#define SDMMCAB_FORCE_EVENT_0_CURRENTLIMIT_ERR_INTERRUPT                        _MK_ENUM_CONST(1)

#define SDMMCAB_FORCE_EVENT_0_DATA_END_BIT_ERR_SHIFT                    _MK_SHIFT_CONST(22)
#define SDMMCAB_FORCE_EVENT_0_DATA_END_BIT_ERR_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_FORCE_EVENT_0_DATA_END_BIT_ERR_SHIFT)
#define SDMMCAB_FORCE_EVENT_0_DATA_END_BIT_ERR_RANGE                    22:22
#define SDMMCAB_FORCE_EVENT_0_DATA_END_BIT_ERR_WOFFSET                  0x0
#define SDMMCAB_FORCE_EVENT_0_DATA_END_BIT_ERR_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_DATA_END_BIT_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_DATA_END_BIT_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_DATA_END_BIT_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_DATA_END_BIT_ERR_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_DATA_END_BIT_ERR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_DATA_END_BIT_ERR_NO_INTERRUPT                     _MK_ENUM_CONST(0)
#define SDMMCAB_FORCE_EVENT_0_DATA_END_BIT_ERR_INTERRUPT                        _MK_ENUM_CONST(1)

#define SDMMCAB_FORCE_EVENT_0_DATACRC_ERR_SHIFT                 _MK_SHIFT_CONST(21)
#define SDMMCAB_FORCE_EVENT_0_DATACRC_ERR_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_FORCE_EVENT_0_DATACRC_ERR_SHIFT)
#define SDMMCAB_FORCE_EVENT_0_DATACRC_ERR_RANGE                 21:21
#define SDMMCAB_FORCE_EVENT_0_DATACRC_ERR_WOFFSET                       0x0
#define SDMMCAB_FORCE_EVENT_0_DATACRC_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_DATACRC_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_DATACRC_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_DATACRC_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_DATACRC_ERR_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_DATACRC_ERR_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_DATACRC_ERR_NO_INTERRUPT                  _MK_ENUM_CONST(0)
#define SDMMCAB_FORCE_EVENT_0_DATACRC_ERR_INTERRUPT                     _MK_ENUM_CONST(1)

#define SDMMCAB_FORCE_EVENT_0_DATATIMEOUT_ERR_SHIFT                     _MK_SHIFT_CONST(20)
#define SDMMCAB_FORCE_EVENT_0_DATATIMEOUT_ERR_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_FORCE_EVENT_0_DATATIMEOUT_ERR_SHIFT)
#define SDMMCAB_FORCE_EVENT_0_DATATIMEOUT_ERR_RANGE                     20:20
#define SDMMCAB_FORCE_EVENT_0_DATATIMEOUT_ERR_WOFFSET                   0x0
#define SDMMCAB_FORCE_EVENT_0_DATATIMEOUT_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_DATATIMEOUT_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_DATATIMEOUT_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_DATATIMEOUT_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_DATATIMEOUT_ERR_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_DATATIMEOUT_ERR_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_DATATIMEOUT_ERR_NO_INTERRUPT                      _MK_ENUM_CONST(0)
#define SDMMCAB_FORCE_EVENT_0_DATATIMEOUT_ERR_INTERRUPT                 _MK_ENUM_CONST(1)

#define SDMMCAB_FORCE_EVENT_0_COMMAND_INDEX_ERR_SHIFT                   _MK_SHIFT_CONST(19)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_INDEX_ERR_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_FORCE_EVENT_0_COMMAND_INDEX_ERR_SHIFT)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_INDEX_ERR_RANGE                   19:19
#define SDMMCAB_FORCE_EVENT_0_COMMAND_INDEX_ERR_WOFFSET                 0x0
#define SDMMCAB_FORCE_EVENT_0_COMMAND_INDEX_ERR_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_INDEX_ERR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_INDEX_ERR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_INDEX_ERR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_INDEX_ERR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_INDEX_ERR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_INDEX_ERR_NO_INTERRUPT                    _MK_ENUM_CONST(0)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_INDEX_ERR_INTERRUPT                       _MK_ENUM_CONST(1)

#define SDMMCAB_FORCE_EVENT_0_COMMAND_END_BIT_ERR_SHIFT                 _MK_SHIFT_CONST(18)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_END_BIT_ERR_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_FORCE_EVENT_0_COMMAND_END_BIT_ERR_SHIFT)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_END_BIT_ERR_RANGE                 18:18
#define SDMMCAB_FORCE_EVENT_0_COMMAND_END_BIT_ERR_WOFFSET                       0x0
#define SDMMCAB_FORCE_EVENT_0_COMMAND_END_BIT_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_END_BIT_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_END_BIT_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_END_BIT_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_END_BIT_ERR_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_END_BIT_ERR_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_END_BIT_ERR_NO_INTERRUPT                  _MK_ENUM_CONST(0)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_END_BIT_ERR_INTERRUPT                     _MK_ENUM_CONST(1)

#define SDMMCAB_FORCE_EVENT_0_COMMAND_CRC_ERR_SHIFT                     _MK_SHIFT_CONST(17)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_CRC_ERR_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_FORCE_EVENT_0_COMMAND_CRC_ERR_SHIFT)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_CRC_ERR_RANGE                     17:17
#define SDMMCAB_FORCE_EVENT_0_COMMAND_CRC_ERR_WOFFSET                   0x0
#define SDMMCAB_FORCE_EVENT_0_COMMAND_CRC_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_CRC_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_CRC_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_CRC_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_CRC_ERR_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_CRC_ERR_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_CRC_ERR_NO_INTERRUPT                      _MK_ENUM_CONST(0)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_CRC_ERR_INTERRUPT                 _MK_ENUM_CONST(1)

#define SDMMCAB_FORCE_EVENT_0_COMMAND_TIMEOUT_ERR_SHIFT                 _MK_SHIFT_CONST(16)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_TIMEOUT_ERR_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_FORCE_EVENT_0_COMMAND_TIMEOUT_ERR_SHIFT)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_TIMEOUT_ERR_RANGE                 16:16
#define SDMMCAB_FORCE_EVENT_0_COMMAND_TIMEOUT_ERR_WOFFSET                       0x0
#define SDMMCAB_FORCE_EVENT_0_COMMAND_TIMEOUT_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_TIMEOUT_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_TIMEOUT_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_TIMEOUT_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_TIMEOUT_ERR_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_TIMEOUT_ERR_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_TIMEOUT_ERR_NO_INTERRUPT                  _MK_ENUM_CONST(0)
#define SDMMCAB_FORCE_EVENT_0_COMMAND_TIMEOUT_ERR_INTERRUPT                     _MK_ENUM_CONST(1)

#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_NOT_ISSUED_SHIFT                       _MK_SHIFT_CONST(7)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_NOT_ISSUED_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_NOT_ISSUED_SHIFT)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_NOT_ISSUED_RANGE                       7:7
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_NOT_ISSUED_WOFFSET                     0x0
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_NOT_ISSUED_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_NOT_ISSUED_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_NOT_ISSUED_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_NOT_ISSUED_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_NOT_ISSUED_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_NOT_ISSUED_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_NOT_ISSUED_NO_INTERRUPT                        _MK_ENUM_CONST(0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_NOT_ISSUED_INTERRUPT                   _MK_ENUM_CONST(1)

#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_RESP_ERR_SHIFT                 _MK_SHIFT_CONST(5)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_RESP_ERR_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_RESP_ERR_SHIFT)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_RESP_ERR_RANGE                 5:5
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_RESP_ERR_WOFFSET                       0x0
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_RESP_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_RESP_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_RESP_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_RESP_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_RESP_ERR_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_RESP_ERR_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_RESP_ERR_NO_INTERRUPT                  _MK_ENUM_CONST(0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_RESP_ERR_INTERRUPT                     _MK_ENUM_CONST(1)

#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_INDEX_ERR_SHIFT                        _MK_SHIFT_CONST(4)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_INDEX_ERR_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_INDEX_ERR_SHIFT)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_INDEX_ERR_RANGE                        4:4
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_INDEX_ERR_WOFFSET                      0x0
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_INDEX_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_INDEX_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_INDEX_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_INDEX_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_INDEX_ERR_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_INDEX_ERR_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_INDEX_ERR_NO_INTERRUPT                 _MK_ENUM_CONST(0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_INDEX_ERR_INTERRUPT                    _MK_ENUM_CONST(1)

#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_END_BIT_ERR_SHIFT                      _MK_SHIFT_CONST(3)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_END_BIT_ERR_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_END_BIT_ERR_SHIFT)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_END_BIT_ERR_RANGE                      3:3
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_END_BIT_ERR_WOFFSET                    0x0
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_END_BIT_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_END_BIT_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_END_BIT_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_END_BIT_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_END_BIT_ERR_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_END_BIT_ERR_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_END_BIT_ERR_NO_INTERRUPT                       _MK_ENUM_CONST(0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_END_BIT_ERR_INTERRUPT                  _MK_ENUM_CONST(1)

#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_CRC_ERR_SHIFT                  _MK_SHIFT_CONST(2)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_CRC_ERR_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_CRC_ERR_SHIFT)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_CRC_ERR_RANGE                  2:2
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_CRC_ERR_WOFFSET                        0x0
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_CRC_ERR_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_CRC_ERR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_CRC_ERR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_CRC_ERR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_CRC_ERR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_CRC_ERR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_CRC_ERR_NO_INTERRUPT                   _MK_ENUM_CONST(0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_CRC_ERR_INTERRUPT                      _MK_ENUM_CONST(1)

#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_TIMEOUT_ERR_SHIFT                      _MK_SHIFT_CONST(1)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_TIMEOUT_ERR_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_TIMEOUT_ERR_SHIFT)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_TIMEOUT_ERR_RANGE                      1:1
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_TIMEOUT_ERR_WOFFSET                    0x0
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_TIMEOUT_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_TIMEOUT_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_TIMEOUT_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_TIMEOUT_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_TIMEOUT_ERR_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_TIMEOUT_ERR_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_TIMEOUT_ERR_NO_INTERRUPT                       _MK_ENUM_CONST(0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_TIMEOUT_ERR_INTERRUPT                  _MK_ENUM_CONST(1)

#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_NOT_EXECUTED_SHIFT                     _MK_SHIFT_CONST(0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_NOT_EXECUTED_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_NOT_EXECUTED_SHIFT)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_NOT_EXECUTED_RANGE                     0:0
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_NOT_EXECUTED_WOFFSET                   0x0
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_NOT_EXECUTED_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_NOT_EXECUTED_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_NOT_EXECUTED_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_NOT_EXECUTED_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_NOT_EXECUTED_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_NOT_EXECUTED_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_NOT_EXECUTED_NO_INTERRUPT                      _MK_ENUM_CONST(0)
#define SDMMCAB_FORCE_EVENT_0_AUTO_CMD12_NOT_EXECUTED_INTERRUPT                 _MK_ENUM_CONST(1)


// Register SDMMCAB_ADMA_ERR_STATUS_0
#define SDMMCAB_ADMA_ERR_STATUS_0                       _MK_ADDR_CONST(0x54)
#define SDMMCAB_ADMA_ERR_STATUS_0_SECURE                        0x0
#define SDMMCAB_ADMA_ERR_STATUS_0_DUAL                  0x0
#define SDMMCAB_ADMA_ERR_STATUS_0_SCR                   0
#define SDMMCAB_ADMA_ERR_STATUS_0_WORD_COUNT                    0x1
#define SDMMCAB_ADMA_ERR_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA_ERR_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x7)
#define SDMMCAB_ADMA_ERR_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA_ERR_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA_ERR_STATUS_0_READ_MASK                     _MK_MASK_CONST(0x7)
#define SDMMCAB_ADMA_ERR_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA_ERR_STATUS_0_ADMA_LENGTH_MISMATCH_ERR_SHIFT                        _MK_SHIFT_CONST(2)
#define SDMMCAB_ADMA_ERR_STATUS_0_ADMA_LENGTH_MISMATCH_ERR_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_ADMA_ERR_STATUS_0_ADMA_LENGTH_MISMATCH_ERR_SHIFT)
#define SDMMCAB_ADMA_ERR_STATUS_0_ADMA_LENGTH_MISMATCH_ERR_RANGE                        2:2
#define SDMMCAB_ADMA_ERR_STATUS_0_ADMA_LENGTH_MISMATCH_ERR_WOFFSET                      0x0
#define SDMMCAB_ADMA_ERR_STATUS_0_ADMA_LENGTH_MISMATCH_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA_ERR_STATUS_0_ADMA_LENGTH_MISMATCH_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_ADMA_ERR_STATUS_0_ADMA_LENGTH_MISMATCH_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA_ERR_STATUS_0_ADMA_LENGTH_MISMATCH_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA_ERR_STATUS_0_ADMA_LENGTH_MISMATCH_ERR_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA_ERR_STATUS_0_ADMA_LENGTH_MISMATCH_ERR_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_ADMA_ERR_STATUS_0_ADMA_LENGTH_MISMATCH_ERR_NO_ERR                       _MK_ENUM_CONST(0)
#define SDMMCAB_ADMA_ERR_STATUS_0_ADMA_LENGTH_MISMATCH_ERR_ERR                  _MK_ENUM_CONST(1)

#define SDMMCAB_ADMA_ERR_STATUS_0_ADMA_ERR_STATE_SHIFT                  _MK_SHIFT_CONST(0)
#define SDMMCAB_ADMA_ERR_STATUS_0_ADMA_ERR_STATE_FIELD                  _MK_FIELD_CONST(0x3, SDMMCAB_ADMA_ERR_STATUS_0_ADMA_ERR_STATE_SHIFT)
#define SDMMCAB_ADMA_ERR_STATUS_0_ADMA_ERR_STATE_RANGE                  1:0
#define SDMMCAB_ADMA_ERR_STATUS_0_ADMA_ERR_STATE_WOFFSET                        0x0
#define SDMMCAB_ADMA_ERR_STATUS_0_ADMA_ERR_STATE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA_ERR_STATUS_0_ADMA_ERR_STATE_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define SDMMCAB_ADMA_ERR_STATUS_0_ADMA_ERR_STATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA_ERR_STATUS_0_ADMA_ERR_STATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA_ERR_STATUS_0_ADMA_ERR_STATE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA_ERR_STATUS_0_ADMA_ERR_STATE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register SDMMCAB_ADMA_SYSTEM_ADDRESS_0
#define SDMMCAB_ADMA_SYSTEM_ADDRESS_0                   _MK_ADDR_CONST(0x58)
#define SDMMCAB_ADMA_SYSTEM_ADDRESS_0_SECURE                    0x0
#define SDMMCAB_ADMA_SYSTEM_ADDRESS_0_DUAL                      0x0
#define SDMMCAB_ADMA_SYSTEM_ADDRESS_0_SCR                       0
#define SDMMCAB_ADMA_SYSTEM_ADDRESS_0_WORD_COUNT                        0x1
#define SDMMCAB_ADMA_SYSTEM_ADDRESS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA_SYSTEM_ADDRESS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_ADMA_SYSTEM_ADDRESS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA_SYSTEM_ADDRESS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA_SYSTEM_ADDRESS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_ADMA_SYSTEM_ADDRESS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_ADMA_SYSTEM_ADDRESS_0_ADMA_SYSTEM_ADDRESS_SHIFT                 _MK_SHIFT_CONST(0)
#define SDMMCAB_ADMA_SYSTEM_ADDRESS_0_ADMA_SYSTEM_ADDRESS_FIELD                 _MK_FIELD_CONST(0xffffffff, SDMMCAB_ADMA_SYSTEM_ADDRESS_0_ADMA_SYSTEM_ADDRESS_SHIFT)
#define SDMMCAB_ADMA_SYSTEM_ADDRESS_0_ADMA_SYSTEM_ADDRESS_RANGE                 31:0
#define SDMMCAB_ADMA_SYSTEM_ADDRESS_0_ADMA_SYSTEM_ADDRESS_WOFFSET                       0x0
#define SDMMCAB_ADMA_SYSTEM_ADDRESS_0_ADMA_SYSTEM_ADDRESS_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA_SYSTEM_ADDRESS_0_ADMA_SYSTEM_ADDRESS_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_ADMA_SYSTEM_ADDRESS_0_ADMA_SYSTEM_ADDRESS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA_SYSTEM_ADDRESS_0_ADMA_SYSTEM_ADDRESS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA_SYSTEM_ADDRESS_0_ADMA_SYSTEM_ADDRESS_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA_SYSTEM_ADDRESS_0_ADMA_SYSTEM_ADDRESS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register SDMMCAB_UPPER_ADMA_SYSTEM_ADDRESS_0
#define SDMMCAB_UPPER_ADMA_SYSTEM_ADDRESS_0                     _MK_ADDR_CONST(0x5c)
#define SDMMCAB_UPPER_ADMA_SYSTEM_ADDRESS_0_SECURE                      0x0
#define SDMMCAB_UPPER_ADMA_SYSTEM_ADDRESS_0_DUAL                        0x0
#define SDMMCAB_UPPER_ADMA_SYSTEM_ADDRESS_0_SCR                         0
#define SDMMCAB_UPPER_ADMA_SYSTEM_ADDRESS_0_WORD_COUNT                  0x1
#define SDMMCAB_UPPER_ADMA_SYSTEM_ADDRESS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SDMMCAB_UPPER_ADMA_SYSTEM_ADDRESS_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_UPPER_ADMA_SYSTEM_ADDRESS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SDMMCAB_UPPER_ADMA_SYSTEM_ADDRESS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_UPPER_ADMA_SYSTEM_ADDRESS_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_UPPER_ADMA_SYSTEM_ADDRESS_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_UPPER_ADMA_SYSTEM_ADDRESS_0_UPPER_ADMA_SYSTEM_ADDRESS_SHIFT                     _MK_SHIFT_CONST(0)
#define SDMMCAB_UPPER_ADMA_SYSTEM_ADDRESS_0_UPPER_ADMA_SYSTEM_ADDRESS_FIELD                     _MK_FIELD_CONST(0xffffffff, SDMMCAB_UPPER_ADMA_SYSTEM_ADDRESS_0_UPPER_ADMA_SYSTEM_ADDRESS_SHIFT)
#define SDMMCAB_UPPER_ADMA_SYSTEM_ADDRESS_0_UPPER_ADMA_SYSTEM_ADDRESS_RANGE                     31:0
#define SDMMCAB_UPPER_ADMA_SYSTEM_ADDRESS_0_UPPER_ADMA_SYSTEM_ADDRESS_WOFFSET                   0x0
#define SDMMCAB_UPPER_ADMA_SYSTEM_ADDRESS_0_UPPER_ADMA_SYSTEM_ADDRESS_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_UPPER_ADMA_SYSTEM_ADDRESS_0_UPPER_ADMA_SYSTEM_ADDRESS_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_UPPER_ADMA_SYSTEM_ADDRESS_0_UPPER_ADMA_SYSTEM_ADDRESS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_UPPER_ADMA_SYSTEM_ADDRESS_0_UPPER_ADMA_SYSTEM_ADDRESS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_UPPER_ADMA_SYSTEM_ADDRESS_0_UPPER_ADMA_SYSTEM_ADDRESS_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_UPPER_ADMA_SYSTEM_ADDRESS_0_UPPER_ADMA_SYSTEM_ADDRESS_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register SDMMCAB_PRESET_DEFAULT_AND_INIT_0
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0                       _MK_ADDR_CONST(0x60)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_SECURE                        0x0
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_DUAL                  0x0
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_SCR                   0
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_WORD_COUNT                    0x1
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_RESET_VAL                     _MK_MASK_CONST(0x40000)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_RESET_MASK                    _MK_MASK_CONST(0xc7ffc7ff)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_READ_MASK                     _MK_MASK_CONST(0xc7ffc7ff)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_DRIVE_STRENGTH_VAL_HIGH_SHIFT                 _MK_SHIFT_CONST(30)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_DRIVE_STRENGTH_VAL_HIGH_FIELD                 _MK_FIELD_CONST(0x3, SDMMCAB_PRESET_DEFAULT_AND_INIT_0_DRIVE_STRENGTH_VAL_HIGH_SHIFT)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_DRIVE_STRENGTH_VAL_HIGH_RANGE                 31:30
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_DRIVE_STRENGTH_VAL_HIGH_WOFFSET                       0x0
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_DRIVE_STRENGTH_VAL_HIGH_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_DRIVE_STRENGTH_VAL_HIGH_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_DRIVE_STRENGTH_VAL_HIGH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_DRIVE_STRENGTH_VAL_HIGH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_DRIVE_STRENGTH_VAL_HIGH_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_DRIVE_STRENGTH_VAL_HIGH_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_CLK_GEN_VAL_HIGH_SHIFT                        _MK_SHIFT_CONST(26)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_CLK_GEN_VAL_HIGH_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_PRESET_DEFAULT_AND_INIT_0_CLK_GEN_VAL_HIGH_SHIFT)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_CLK_GEN_VAL_HIGH_RANGE                        26:26
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_CLK_GEN_VAL_HIGH_WOFFSET                      0x0
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_CLK_GEN_VAL_HIGH_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_CLK_GEN_VAL_HIGH_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_CLK_GEN_VAL_HIGH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_CLK_GEN_VAL_HIGH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_CLK_GEN_VAL_HIGH_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_CLK_GEN_VAL_HIGH_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_SDCLK_FREQ_VAL_HIGH_SHIFT                     _MK_SHIFT_CONST(16)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_SDCLK_FREQ_VAL_HIGH_FIELD                     _MK_FIELD_CONST(0x3ff, SDMMCAB_PRESET_DEFAULT_AND_INIT_0_SDCLK_FREQ_VAL_HIGH_SHIFT)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_SDCLK_FREQ_VAL_HIGH_RANGE                     25:16
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_SDCLK_FREQ_VAL_HIGH_WOFFSET                   0x0
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_SDCLK_FREQ_VAL_HIGH_DEFAULT                   _MK_MASK_CONST(0x4)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_SDCLK_FREQ_VAL_HIGH_DEFAULT_MASK                      _MK_MASK_CONST(0x3ff)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_SDCLK_FREQ_VAL_HIGH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_SDCLK_FREQ_VAL_HIGH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_SDCLK_FREQ_VAL_HIGH_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_SDCLK_FREQ_VAL_HIGH_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_DRIVE_STRENGTH_VAL_LOW_SHIFT                  _MK_SHIFT_CONST(14)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_DRIVE_STRENGTH_VAL_LOW_FIELD                  _MK_FIELD_CONST(0x3, SDMMCAB_PRESET_DEFAULT_AND_INIT_0_DRIVE_STRENGTH_VAL_LOW_SHIFT)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_DRIVE_STRENGTH_VAL_LOW_RANGE                  15:14
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_DRIVE_STRENGTH_VAL_LOW_WOFFSET                        0x0
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_DRIVE_STRENGTH_VAL_LOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_DRIVE_STRENGTH_VAL_LOW_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_DRIVE_STRENGTH_VAL_LOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_DRIVE_STRENGTH_VAL_LOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_DRIVE_STRENGTH_VAL_LOW_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_DRIVE_STRENGTH_VAL_LOW_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_CLK_GEN_VAL_LOW_SHIFT                 _MK_SHIFT_CONST(10)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_CLK_GEN_VAL_LOW_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_PRESET_DEFAULT_AND_INIT_0_CLK_GEN_VAL_LOW_SHIFT)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_CLK_GEN_VAL_LOW_RANGE                 10:10
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_CLK_GEN_VAL_LOW_WOFFSET                       0x0
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_CLK_GEN_VAL_LOW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_CLK_GEN_VAL_LOW_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_CLK_GEN_VAL_LOW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_CLK_GEN_VAL_LOW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_CLK_GEN_VAL_LOW_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_CLK_GEN_VAL_LOW_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_SDCLK_FREQ_VAL_LOW_SHIFT                      _MK_SHIFT_CONST(0)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_SDCLK_FREQ_VAL_LOW_FIELD                      _MK_FIELD_CONST(0x3ff, SDMMCAB_PRESET_DEFAULT_AND_INIT_0_SDCLK_FREQ_VAL_LOW_SHIFT)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_SDCLK_FREQ_VAL_LOW_RANGE                      9:0
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_SDCLK_FREQ_VAL_LOW_WOFFSET                    0x0
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_SDCLK_FREQ_VAL_LOW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_SDCLK_FREQ_VAL_LOW_DEFAULT_MASK                       _MK_MASK_CONST(0x3ff)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_SDCLK_FREQ_VAL_LOW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_SDCLK_FREQ_VAL_LOW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_SDCLK_FREQ_VAL_LOW_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DEFAULT_AND_INIT_0_SDCLK_FREQ_VAL_LOW_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register SDMMCAB_PRESET_SDR12_AND_HIGH_0
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0                 _MK_ADDR_CONST(0x64)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_SECURE                  0x0
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_DUAL                    0x0
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_SCR                     0
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_WORD_COUNT                      0x1
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_RESET_VAL                       _MK_MASK_CONST(0x40002)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_RESET_MASK                      _MK_MASK_CONST(0xc7ffc7ff)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_READ_MASK                       _MK_MASK_CONST(0xc7ffc7ff)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_DRIVE_STRENGTH_VAL_HIGH_SHIFT                   _MK_SHIFT_CONST(30)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_DRIVE_STRENGTH_VAL_HIGH_FIELD                   _MK_FIELD_CONST(0x3, SDMMCAB_PRESET_SDR12_AND_HIGH_0_DRIVE_STRENGTH_VAL_HIGH_SHIFT)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_DRIVE_STRENGTH_VAL_HIGH_RANGE                   31:30
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_DRIVE_STRENGTH_VAL_HIGH_WOFFSET                 0x0
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_DRIVE_STRENGTH_VAL_HIGH_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_DRIVE_STRENGTH_VAL_HIGH_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_DRIVE_STRENGTH_VAL_HIGH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_DRIVE_STRENGTH_VAL_HIGH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_DRIVE_STRENGTH_VAL_HIGH_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_DRIVE_STRENGTH_VAL_HIGH_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_CLK_GEN_VAL_HIGH_SHIFT                  _MK_SHIFT_CONST(26)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_CLK_GEN_VAL_HIGH_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_PRESET_SDR12_AND_HIGH_0_CLK_GEN_VAL_HIGH_SHIFT)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_CLK_GEN_VAL_HIGH_RANGE                  26:26
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_CLK_GEN_VAL_HIGH_WOFFSET                        0x0
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_CLK_GEN_VAL_HIGH_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_CLK_GEN_VAL_HIGH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_CLK_GEN_VAL_HIGH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_CLK_GEN_VAL_HIGH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_CLK_GEN_VAL_HIGH_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_CLK_GEN_VAL_HIGH_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_SDCLK_FREQ_VAL_HIGH_SHIFT                       _MK_SHIFT_CONST(16)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_SDCLK_FREQ_VAL_HIGH_FIELD                       _MK_FIELD_CONST(0x3ff, SDMMCAB_PRESET_SDR12_AND_HIGH_0_SDCLK_FREQ_VAL_HIGH_SHIFT)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_SDCLK_FREQ_VAL_HIGH_RANGE                       25:16
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_SDCLK_FREQ_VAL_HIGH_WOFFSET                     0x0
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_SDCLK_FREQ_VAL_HIGH_DEFAULT                     _MK_MASK_CONST(0x4)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_SDCLK_FREQ_VAL_HIGH_DEFAULT_MASK                        _MK_MASK_CONST(0x3ff)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_SDCLK_FREQ_VAL_HIGH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_SDCLK_FREQ_VAL_HIGH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_SDCLK_FREQ_VAL_HIGH_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_SDCLK_FREQ_VAL_HIGH_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_DRIVE_STRENGTH_VAL_LOW_SHIFT                    _MK_SHIFT_CONST(14)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_DRIVE_STRENGTH_VAL_LOW_FIELD                    _MK_FIELD_CONST(0x3, SDMMCAB_PRESET_SDR12_AND_HIGH_0_DRIVE_STRENGTH_VAL_LOW_SHIFT)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_DRIVE_STRENGTH_VAL_LOW_RANGE                    15:14
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_DRIVE_STRENGTH_VAL_LOW_WOFFSET                  0x0
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_DRIVE_STRENGTH_VAL_LOW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_DRIVE_STRENGTH_VAL_LOW_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_DRIVE_STRENGTH_VAL_LOW_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_DRIVE_STRENGTH_VAL_LOW_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_DRIVE_STRENGTH_VAL_LOW_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_DRIVE_STRENGTH_VAL_LOW_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_CLK_GEN_VAL_LOW_SHIFT                   _MK_SHIFT_CONST(10)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_CLK_GEN_VAL_LOW_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_PRESET_SDR12_AND_HIGH_0_CLK_GEN_VAL_LOW_SHIFT)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_CLK_GEN_VAL_LOW_RANGE                   10:10
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_CLK_GEN_VAL_LOW_WOFFSET                 0x0
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_CLK_GEN_VAL_LOW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_CLK_GEN_VAL_LOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_CLK_GEN_VAL_LOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_CLK_GEN_VAL_LOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_CLK_GEN_VAL_LOW_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_CLK_GEN_VAL_LOW_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_SDCLK_FREQ_VAL_LOW_SHIFT                        _MK_SHIFT_CONST(0)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_SDCLK_FREQ_VAL_LOW_FIELD                        _MK_FIELD_CONST(0x3ff, SDMMCAB_PRESET_SDR12_AND_HIGH_0_SDCLK_FREQ_VAL_LOW_SHIFT)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_SDCLK_FREQ_VAL_LOW_RANGE                        9:0
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_SDCLK_FREQ_VAL_LOW_WOFFSET                      0x0
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_SDCLK_FREQ_VAL_LOW_DEFAULT                      _MK_MASK_CONST(0x2)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_SDCLK_FREQ_VAL_LOW_DEFAULT_MASK                 _MK_MASK_CONST(0x3ff)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_SDCLK_FREQ_VAL_LOW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_SDCLK_FREQ_VAL_LOW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_SDCLK_FREQ_VAL_LOW_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR12_AND_HIGH_0_SDCLK_FREQ_VAL_LOW_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register SDMMCAB_PRESET_SDR50_AND_SDR25_0
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0                        _MK_ADDR_CONST(0x68)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_SECURE                         0x0
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_DUAL                   0x0
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_SCR                    0
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_WORD_COUNT                     0x1
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_RESET_VAL                      _MK_MASK_CONST(0x10002)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_RESET_MASK                     _MK_MASK_CONST(0xc7ffc7ff)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_READ_MASK                      _MK_MASK_CONST(0xc7ffc7ff)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_DRIVE_STRENGTH_VAL_HIGH_SHIFT                  _MK_SHIFT_CONST(30)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_DRIVE_STRENGTH_VAL_HIGH_FIELD                  _MK_FIELD_CONST(0x3, SDMMCAB_PRESET_SDR50_AND_SDR25_0_DRIVE_STRENGTH_VAL_HIGH_SHIFT)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_DRIVE_STRENGTH_VAL_HIGH_RANGE                  31:30
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_DRIVE_STRENGTH_VAL_HIGH_WOFFSET                        0x0
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_DRIVE_STRENGTH_VAL_HIGH_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_DRIVE_STRENGTH_VAL_HIGH_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_DRIVE_STRENGTH_VAL_HIGH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_DRIVE_STRENGTH_VAL_HIGH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_DRIVE_STRENGTH_VAL_HIGH_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_DRIVE_STRENGTH_VAL_HIGH_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_CLK_GEN_VAL_HIGH_SHIFT                 _MK_SHIFT_CONST(26)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_CLK_GEN_VAL_HIGH_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_PRESET_SDR50_AND_SDR25_0_CLK_GEN_VAL_HIGH_SHIFT)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_CLK_GEN_VAL_HIGH_RANGE                 26:26
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_CLK_GEN_VAL_HIGH_WOFFSET                       0x0
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_CLK_GEN_VAL_HIGH_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_CLK_GEN_VAL_HIGH_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_CLK_GEN_VAL_HIGH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_CLK_GEN_VAL_HIGH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_CLK_GEN_VAL_HIGH_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_CLK_GEN_VAL_HIGH_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_SDCLK_FREQ_VAL_HIGH_SHIFT                      _MK_SHIFT_CONST(16)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_SDCLK_FREQ_VAL_HIGH_FIELD                      _MK_FIELD_CONST(0x3ff, SDMMCAB_PRESET_SDR50_AND_SDR25_0_SDCLK_FREQ_VAL_HIGH_SHIFT)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_SDCLK_FREQ_VAL_HIGH_RANGE                      25:16
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_SDCLK_FREQ_VAL_HIGH_WOFFSET                    0x0
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_SDCLK_FREQ_VAL_HIGH_DEFAULT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_SDCLK_FREQ_VAL_HIGH_DEFAULT_MASK                       _MK_MASK_CONST(0x3ff)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_SDCLK_FREQ_VAL_HIGH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_SDCLK_FREQ_VAL_HIGH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_SDCLK_FREQ_VAL_HIGH_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_SDCLK_FREQ_VAL_HIGH_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_DRIVE_STRENGTH_VAL_LOW_SHIFT                   _MK_SHIFT_CONST(14)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_DRIVE_STRENGTH_VAL_LOW_FIELD                   _MK_FIELD_CONST(0x3, SDMMCAB_PRESET_SDR50_AND_SDR25_0_DRIVE_STRENGTH_VAL_LOW_SHIFT)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_DRIVE_STRENGTH_VAL_LOW_RANGE                   15:14
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_DRIVE_STRENGTH_VAL_LOW_WOFFSET                 0x0
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_DRIVE_STRENGTH_VAL_LOW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_DRIVE_STRENGTH_VAL_LOW_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_DRIVE_STRENGTH_VAL_LOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_DRIVE_STRENGTH_VAL_LOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_DRIVE_STRENGTH_VAL_LOW_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_DRIVE_STRENGTH_VAL_LOW_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_CLK_GEN_VAL_LOW_SHIFT                  _MK_SHIFT_CONST(10)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_CLK_GEN_VAL_LOW_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_PRESET_SDR50_AND_SDR25_0_CLK_GEN_VAL_LOW_SHIFT)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_CLK_GEN_VAL_LOW_RANGE                  10:10
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_CLK_GEN_VAL_LOW_WOFFSET                        0x0
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_CLK_GEN_VAL_LOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_CLK_GEN_VAL_LOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_CLK_GEN_VAL_LOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_CLK_GEN_VAL_LOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_CLK_GEN_VAL_LOW_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_CLK_GEN_VAL_LOW_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_SDCLK_FREQ_VAL_LOW_SHIFT                       _MK_SHIFT_CONST(0)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_SDCLK_FREQ_VAL_LOW_FIELD                       _MK_FIELD_CONST(0x3ff, SDMMCAB_PRESET_SDR50_AND_SDR25_0_SDCLK_FREQ_VAL_LOW_SHIFT)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_SDCLK_FREQ_VAL_LOW_RANGE                       9:0
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_SDCLK_FREQ_VAL_LOW_WOFFSET                     0x0
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_SDCLK_FREQ_VAL_LOW_DEFAULT                     _MK_MASK_CONST(0x2)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_SDCLK_FREQ_VAL_LOW_DEFAULT_MASK                        _MK_MASK_CONST(0x3ff)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_SDCLK_FREQ_VAL_LOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_SDCLK_FREQ_VAL_LOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_SDCLK_FREQ_VAL_LOW_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_SDR50_AND_SDR25_0_SDCLK_FREQ_VAL_LOW_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register SDMMCAB_PRESET_DDR50_AND_SDR104_0
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0                       _MK_ADDR_CONST(0x6c)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_SECURE                        0x0
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_DUAL                  0x0
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_SCR                   0
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_WORD_COUNT                    0x1
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_RESET_VAL                     _MK_MASK_CONST(0x20000)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_RESET_MASK                    _MK_MASK_CONST(0xc7ffc7ff)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_READ_MASK                     _MK_MASK_CONST(0xc7ffc7ff)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_DRIVE_STRENGTH_VAL_HIGH_SHIFT                 _MK_SHIFT_CONST(30)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_DRIVE_STRENGTH_VAL_HIGH_FIELD                 _MK_FIELD_CONST(0x3, SDMMCAB_PRESET_DDR50_AND_SDR104_0_DRIVE_STRENGTH_VAL_HIGH_SHIFT)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_DRIVE_STRENGTH_VAL_HIGH_RANGE                 31:30
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_DRIVE_STRENGTH_VAL_HIGH_WOFFSET                       0x0
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_DRIVE_STRENGTH_VAL_HIGH_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_DRIVE_STRENGTH_VAL_HIGH_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_DRIVE_STRENGTH_VAL_HIGH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_DRIVE_STRENGTH_VAL_HIGH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_DRIVE_STRENGTH_VAL_HIGH_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_DRIVE_STRENGTH_VAL_HIGH_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_CLK_GEN_VAL_HIGH_SHIFT                        _MK_SHIFT_CONST(26)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_CLK_GEN_VAL_HIGH_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_PRESET_DDR50_AND_SDR104_0_CLK_GEN_VAL_HIGH_SHIFT)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_CLK_GEN_VAL_HIGH_RANGE                        26:26
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_CLK_GEN_VAL_HIGH_WOFFSET                      0x0
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_CLK_GEN_VAL_HIGH_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_CLK_GEN_VAL_HIGH_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_CLK_GEN_VAL_HIGH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_CLK_GEN_VAL_HIGH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_CLK_GEN_VAL_HIGH_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_CLK_GEN_VAL_HIGH_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_SDCLK_FREQ_VAL_HIGH_SHIFT                     _MK_SHIFT_CONST(16)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_SDCLK_FREQ_VAL_HIGH_FIELD                     _MK_FIELD_CONST(0x3ff, SDMMCAB_PRESET_DDR50_AND_SDR104_0_SDCLK_FREQ_VAL_HIGH_SHIFT)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_SDCLK_FREQ_VAL_HIGH_RANGE                     25:16
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_SDCLK_FREQ_VAL_HIGH_WOFFSET                   0x0
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_SDCLK_FREQ_VAL_HIGH_DEFAULT                   _MK_MASK_CONST(0x2)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_SDCLK_FREQ_VAL_HIGH_DEFAULT_MASK                      _MK_MASK_CONST(0x3ff)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_SDCLK_FREQ_VAL_HIGH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_SDCLK_FREQ_VAL_HIGH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_SDCLK_FREQ_VAL_HIGH_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_SDCLK_FREQ_VAL_HIGH_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_DRIVE_STRENGTH_VAL_LOW_SHIFT                  _MK_SHIFT_CONST(14)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_DRIVE_STRENGTH_VAL_LOW_FIELD                  _MK_FIELD_CONST(0x3, SDMMCAB_PRESET_DDR50_AND_SDR104_0_DRIVE_STRENGTH_VAL_LOW_SHIFT)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_DRIVE_STRENGTH_VAL_LOW_RANGE                  15:14
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_DRIVE_STRENGTH_VAL_LOW_WOFFSET                        0x0
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_DRIVE_STRENGTH_VAL_LOW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_DRIVE_STRENGTH_VAL_LOW_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_DRIVE_STRENGTH_VAL_LOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_DRIVE_STRENGTH_VAL_LOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_DRIVE_STRENGTH_VAL_LOW_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_DRIVE_STRENGTH_VAL_LOW_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_CLK_GEN_VAL_LOW_SHIFT                 _MK_SHIFT_CONST(10)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_CLK_GEN_VAL_LOW_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_PRESET_DDR50_AND_SDR104_0_CLK_GEN_VAL_LOW_SHIFT)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_CLK_GEN_VAL_LOW_RANGE                 10:10
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_CLK_GEN_VAL_LOW_WOFFSET                       0x0
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_CLK_GEN_VAL_LOW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_CLK_GEN_VAL_LOW_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_CLK_GEN_VAL_LOW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_CLK_GEN_VAL_LOW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_CLK_GEN_VAL_LOW_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_CLK_GEN_VAL_LOW_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_SDCLK_FREQ_VAL_LOW_SHIFT                      _MK_SHIFT_CONST(0)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_SDCLK_FREQ_VAL_LOW_FIELD                      _MK_FIELD_CONST(0x3ff, SDMMCAB_PRESET_DDR50_AND_SDR104_0_SDCLK_FREQ_VAL_LOW_SHIFT)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_SDCLK_FREQ_VAL_LOW_RANGE                      9:0
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_SDCLK_FREQ_VAL_LOW_WOFFSET                    0x0
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_SDCLK_FREQ_VAL_LOW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_SDCLK_FREQ_VAL_LOW_DEFAULT_MASK                       _MK_MASK_CONST(0x3ff)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_SDCLK_FREQ_VAL_LOW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_SDCLK_FREQ_VAL_LOW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_SDCLK_FREQ_VAL_LOW_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_PRESET_DDR50_AND_SDR104_0_SDCLK_FREQ_VAL_LOW_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Reserved address 0x70

// Reserved address 0x74

// Register SDMMCAB_ADMA3_INT_DESC_LOWER_ADDRESS_0
#define SDMMCAB_ADMA3_INT_DESC_LOWER_ADDRESS_0                  _MK_ADDR_CONST(0x78)
#define SDMMCAB_ADMA3_INT_DESC_LOWER_ADDRESS_0_SECURE                   0x0
#define SDMMCAB_ADMA3_INT_DESC_LOWER_ADDRESS_0_DUAL                     0x0
#define SDMMCAB_ADMA3_INT_DESC_LOWER_ADDRESS_0_SCR                      0
#define SDMMCAB_ADMA3_INT_DESC_LOWER_ADDRESS_0_WORD_COUNT                       0x1
#define SDMMCAB_ADMA3_INT_DESC_LOWER_ADDRESS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA3_INT_DESC_LOWER_ADDRESS_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_ADMA3_INT_DESC_LOWER_ADDRESS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA3_INT_DESC_LOWER_ADDRESS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA3_INT_DESC_LOWER_ADDRESS_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_ADMA3_INT_DESC_LOWER_ADDRESS_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_ADMA3_INT_DESC_LOWER_ADDRESS_0_ADDRESS_31_0_SHIFT                       _MK_SHIFT_CONST(0)
#define SDMMCAB_ADMA3_INT_DESC_LOWER_ADDRESS_0_ADDRESS_31_0_FIELD                       _MK_FIELD_CONST(0xffffffff, SDMMCAB_ADMA3_INT_DESC_LOWER_ADDRESS_0_ADDRESS_31_0_SHIFT)
#define SDMMCAB_ADMA3_INT_DESC_LOWER_ADDRESS_0_ADDRESS_31_0_RANGE                       31:0
#define SDMMCAB_ADMA3_INT_DESC_LOWER_ADDRESS_0_ADDRESS_31_0_WOFFSET                     0x0
#define SDMMCAB_ADMA3_INT_DESC_LOWER_ADDRESS_0_ADDRESS_31_0_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA3_INT_DESC_LOWER_ADDRESS_0_ADDRESS_31_0_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_ADMA3_INT_DESC_LOWER_ADDRESS_0_ADDRESS_31_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA3_INT_DESC_LOWER_ADDRESS_0_ADDRESS_31_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA3_INT_DESC_LOWER_ADDRESS_0_ADDRESS_31_0_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA3_INT_DESC_LOWER_ADDRESS_0_ADDRESS_31_0_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register SDMMCAB_ADMA3_INT_DESC_UPPER_ADDRESS_0
#define SDMMCAB_ADMA3_INT_DESC_UPPER_ADDRESS_0                  _MK_ADDR_CONST(0x7c)
#define SDMMCAB_ADMA3_INT_DESC_UPPER_ADDRESS_0_SECURE                   0x0
#define SDMMCAB_ADMA3_INT_DESC_UPPER_ADDRESS_0_DUAL                     0x0
#define SDMMCAB_ADMA3_INT_DESC_UPPER_ADDRESS_0_SCR                      0
#define SDMMCAB_ADMA3_INT_DESC_UPPER_ADDRESS_0_WORD_COUNT                       0x1
#define SDMMCAB_ADMA3_INT_DESC_UPPER_ADDRESS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA3_INT_DESC_UPPER_ADDRESS_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_ADMA3_INT_DESC_UPPER_ADDRESS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA3_INT_DESC_UPPER_ADDRESS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA3_INT_DESC_UPPER_ADDRESS_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_ADMA3_INT_DESC_UPPER_ADDRESS_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_ADMA3_INT_DESC_UPPER_ADDRESS_0_ADDRESS_63_32_SHIFT                      _MK_SHIFT_CONST(0)
#define SDMMCAB_ADMA3_INT_DESC_UPPER_ADDRESS_0_ADDRESS_63_32_FIELD                      _MK_FIELD_CONST(0xffffffff, SDMMCAB_ADMA3_INT_DESC_UPPER_ADDRESS_0_ADDRESS_63_32_SHIFT)
#define SDMMCAB_ADMA3_INT_DESC_UPPER_ADDRESS_0_ADDRESS_63_32_RANGE                      31:0
#define SDMMCAB_ADMA3_INT_DESC_UPPER_ADDRESS_0_ADDRESS_63_32_WOFFSET                    0x0
#define SDMMCAB_ADMA3_INT_DESC_UPPER_ADDRESS_0_ADDRESS_63_32_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA3_INT_DESC_UPPER_ADDRESS_0_ADDRESS_63_32_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_ADMA3_INT_DESC_UPPER_ADDRESS_0_ADDRESS_63_32_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA3_INT_DESC_UPPER_ADDRESS_0_ADDRESS_63_32_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA3_INT_DESC_UPPER_ADDRESS_0_ADDRESS_63_32_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_ADMA3_INT_DESC_UPPER_ADDRESS_0_ADDRESS_63_32_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Reserved address 0x80

// Reserved address 0x84

// Reserved address 0x88

// Reserved address 0x8c

// Reserved address 0x90

// Reserved address 0x94

// Reserved address 0x98

// Reserved address 0x9c

// Reserved address 0xa0

// Reserved address 0xa4

// Reserved address 0xa8

// Reserved address 0xac

// Reserved address 0xb0

// Reserved address 0xb4

// Reserved address 0xb8

// Reserved address 0xbc

// Reserved address 0xc0

// Reserved address 0xc4

// Reserved address 0xc8

// Reserved address 0xcc

// Reserved address 0xd0

// Reserved address 0xd4

// Reserved address 0xd8

// Reserved address 0xdc

// Reserved address 0xe0

// Reserved address 0xe4

// Register SDMMCAB_VENDOR_REGS_PTR_0
#define SDMMCAB_VENDOR_REGS_PTR_0                       _MK_ADDR_CONST(0xe8)
#define SDMMCAB_VENDOR_REGS_PTR_0_SECURE                        0x0
#define SDMMCAB_VENDOR_REGS_PTR_0_DUAL                  0x0
#define SDMMCAB_VENDOR_REGS_PTR_0_SCR                   0
#define SDMMCAB_VENDOR_REGS_PTR_0_WORD_COUNT                    0x1
#define SDMMCAB_VENDOR_REGS_PTR_0_RESET_VAL                     _MK_MASK_CONST(0x100)
#define SDMMCAB_VENDOR_REGS_PTR_0_RESET_MASK                    _MK_MASK_CONST(0xfff)
#define SDMMCAB_VENDOR_REGS_PTR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_REGS_PTR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_REGS_PTR_0_READ_MASK                     _MK_MASK_CONST(0xfff)
#define SDMMCAB_VENDOR_REGS_PTR_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_REGS_PTR_0_VENDOR_PTR_SHIFT                      _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_REGS_PTR_0_VENDOR_PTR_FIELD                      _MK_FIELD_CONST(0xfff, SDMMCAB_VENDOR_REGS_PTR_0_VENDOR_PTR_SHIFT)
#define SDMMCAB_VENDOR_REGS_PTR_0_VENDOR_PTR_RANGE                      11:0
#define SDMMCAB_VENDOR_REGS_PTR_0_VENDOR_PTR_WOFFSET                    0x0
#define SDMMCAB_VENDOR_REGS_PTR_0_VENDOR_PTR_DEFAULT                    _MK_MASK_CONST(0x100)
#define SDMMCAB_VENDOR_REGS_PTR_0_VENDOR_PTR_DEFAULT_MASK                       _MK_MASK_CONST(0xfff)
#define SDMMCAB_VENDOR_REGS_PTR_0_VENDOR_PTR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_REGS_PTR_0_VENDOR_PTR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_REGS_PTR_0_VENDOR_PTR_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_REGS_PTR_0_VENDOR_PTR_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Reserved address 0xec

// Reserved address 0xf0

// Reserved address 0xf4

// Reserved address 0xf8

// Register SDMMCAB_SLOT_INTERRUPT_STATUS_0
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0                 _MK_ADDR_CONST(0xfc)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_SECURE                  0x0
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_DUAL                    0x0
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_SCR                     0
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_WORD_COUNT                      0x1
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_RESET_VAL                       _MK_MASK_CONST(0x5050000)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_RESET_MASK                      _MK_MASK_CONST(0xffff00ff)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_READ_MASK                       _MK_MASK_CONST(0xffff00ff)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_VENDOR_VERSION_NUMBER_SHIFT                     _MK_SHIFT_CONST(24)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_VENDOR_VERSION_NUMBER_FIELD                     _MK_FIELD_CONST(0xff, SDMMCAB_SLOT_INTERRUPT_STATUS_0_VENDOR_VERSION_NUMBER_SHIFT)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_VENDOR_VERSION_NUMBER_RANGE                     31:24
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_VENDOR_VERSION_NUMBER_WOFFSET                   0x0
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_VENDOR_VERSION_NUMBER_DEFAULT                   _MK_MASK_CONST(0x5)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_VENDOR_VERSION_NUMBER_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_VENDOR_VERSION_NUMBER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_VENDOR_VERSION_NUMBER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_VENDOR_VERSION_NUMBER_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_VENDOR_VERSION_NUMBER_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_SPECIFICATION_VERSION_NUMBER_SHIFT                      _MK_SHIFT_CONST(16)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_SPECIFICATION_VERSION_NUMBER_FIELD                      _MK_FIELD_CONST(0xff, SDMMCAB_SLOT_INTERRUPT_STATUS_0_SPECIFICATION_VERSION_NUMBER_SHIFT)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_SPECIFICATION_VERSION_NUMBER_RANGE                      23:16
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_SPECIFICATION_VERSION_NUMBER_WOFFSET                    0x0
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_SPECIFICATION_VERSION_NUMBER_DEFAULT                    _MK_MASK_CONST(0x5)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_SPECIFICATION_VERSION_NUMBER_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_SPECIFICATION_VERSION_NUMBER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_SPECIFICATION_VERSION_NUMBER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_SPECIFICATION_VERSION_NUMBER_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_SPECIFICATION_VERSION_NUMBER_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_INTERRUPT_SIGNAL_FOR_EACH_SLOT_SHIFT                    _MK_SHIFT_CONST(0)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_INTERRUPT_SIGNAL_FOR_EACH_SLOT_FIELD                    _MK_FIELD_CONST(0xff, SDMMCAB_SLOT_INTERRUPT_STATUS_0_INTERRUPT_SIGNAL_FOR_EACH_SLOT_SHIFT)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_INTERRUPT_SIGNAL_FOR_EACH_SLOT_RANGE                    7:0
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_INTERRUPT_SIGNAL_FOR_EACH_SLOT_WOFFSET                  0x0
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_INTERRUPT_SIGNAL_FOR_EACH_SLOT_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_INTERRUPT_SIGNAL_FOR_EACH_SLOT_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_INTERRUPT_SIGNAL_FOR_EACH_SLOT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_INTERRUPT_SIGNAL_FOR_EACH_SLOT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_INTERRUPT_SIGNAL_FOR_EACH_SLOT_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_SLOT_INTERRUPT_STATUS_0_INTERRUPT_SIGNAL_FOR_EACH_SLOT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register SDMMCAB_VENDOR_CLOCK_CNTRL_0
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0                    _MK_ADDR_CONST(0x100)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SECURE                     0x0
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_DUAL                       0x0
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SCR                        0
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_WORD_COUNT                         0x1
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_RESET_VAL                  _MK_MASK_CONST(0x804d06d)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_RESET_MASK                         _MK_MASK_CONST(0x3fffff7f)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_READ_MASK                  _MK_MASK_CONST(0x3fffff7f)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_WRITE_MASK                         _MK_MASK_CONST(0x3fffff7f)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDMMC_CLK_SHIFT                    _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDMMC_CLK_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDMMC_CLK_SHIFT)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDMMC_CLK_RANGE                    0:0
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDMMC_CLK_WOFFSET                  0x0
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDMMC_CLK_DEFAULT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDMMC_CLK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDMMC_CLK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDMMC_CLK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDMMC_CLK_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDMMC_CLK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDMMC_CLK_DISABLE                  _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDMMC_CLK_ENABLE                   _MK_ENUM_CONST(1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDMMC_CLK__PROD_C_PWRSAVE                  _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDMMC_CLK__PROD_C_NOPWRSAVE                        _MK_ENUM_CONST(1)

#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_INPUT_IO_CLK_SHIFT                 _MK_SHIFT_CONST(1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_INPUT_IO_CLK_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_CLOCK_CNTRL_0_INPUT_IO_CLK_SHIFT)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_INPUT_IO_CLK_RANGE                 1:1
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_INPUT_IO_CLK_WOFFSET                       0x0
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_INPUT_IO_CLK_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_INPUT_IO_CLK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_INPUT_IO_CLK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_INPUT_IO_CLK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_INPUT_IO_CLK_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_INPUT_IO_CLK_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_INPUT_IO_CLK_FEEDBACK                      _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_INPUT_IO_CLK_INTERNAL                      _MK_ENUM_CONST(1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_INPUT_IO_CLK__PROD                 _MK_ENUM_CONST(0)

#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SPI_MODE_CLKEN_OVERRIDE_SHIFT                      _MK_SHIFT_CONST(2)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SPI_MODE_CLKEN_OVERRIDE_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_CLOCK_CNTRL_0_SPI_MODE_CLKEN_OVERRIDE_SHIFT)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SPI_MODE_CLKEN_OVERRIDE_RANGE                      2:2
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SPI_MODE_CLKEN_OVERRIDE_WOFFSET                    0x0
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SPI_MODE_CLKEN_OVERRIDE_DEFAULT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SPI_MODE_CLKEN_OVERRIDE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SPI_MODE_CLKEN_OVERRIDE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SPI_MODE_CLKEN_OVERRIDE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SPI_MODE_CLKEN_OVERRIDE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SPI_MODE_CLKEN_OVERRIDE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SPI_MODE_CLKEN_OVERRIDE_NORMAL                     _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SPI_MODE_CLKEN_OVERRIDE_OVERRIDE                   _MK_ENUM_CONST(1)

#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_PADPIPE_CLKEN_OVERRIDE_SHIFT                       _MK_SHIFT_CONST(3)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_PADPIPE_CLKEN_OVERRIDE_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_CLOCK_CNTRL_0_PADPIPE_CLKEN_OVERRIDE_SHIFT)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_PADPIPE_CLKEN_OVERRIDE_RANGE                       3:3
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_PADPIPE_CLKEN_OVERRIDE_WOFFSET                     0x0
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_PADPIPE_CLKEN_OVERRIDE_DEFAULT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_PADPIPE_CLKEN_OVERRIDE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_PADPIPE_CLKEN_OVERRIDE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_PADPIPE_CLKEN_OVERRIDE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_PADPIPE_CLKEN_OVERRIDE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_PADPIPE_CLKEN_OVERRIDE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_PADPIPE_CLKEN_OVERRIDE_NORMAL                      _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_PADPIPE_CLKEN_OVERRIDE_OVERRIDE                    _MK_ENUM_CONST(1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_PADPIPE_CLKEN_OVERRIDE__PROD                       _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_PADPIPE_CLKEN_OVERRIDE__PROD_C_HS400                       _MK_ENUM_CONST(1)

#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_UHS2_CAPABILITY_OVERRIDE_SHIFT                     _MK_SHIFT_CONST(4)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_UHS2_CAPABILITY_OVERRIDE_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_CLOCK_CNTRL_0_UHS2_CAPABILITY_OVERRIDE_SHIFT)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_UHS2_CAPABILITY_OVERRIDE_RANGE                     4:4
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_UHS2_CAPABILITY_OVERRIDE_WOFFSET                   0x0
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_UHS2_CAPABILITY_OVERRIDE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_UHS2_CAPABILITY_OVERRIDE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_UHS2_CAPABILITY_OVERRIDE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_UHS2_CAPABILITY_OVERRIDE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_UHS2_CAPABILITY_OVERRIDE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_UHS2_CAPABILITY_OVERRIDE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_UHS2_CAPABILITY_OVERRIDE_NORMAL                    _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_UHS2_CAPABILITY_OVERRIDE_OVERRIDE                  _MK_ENUM_CONST(1)

#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDR50_TUNING_OVERRIDE_SHIFT                        _MK_SHIFT_CONST(5)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDR50_TUNING_OVERRIDE_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDR50_TUNING_OVERRIDE_SHIFT)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDR50_TUNING_OVERRIDE_RANGE                        5:5
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDR50_TUNING_OVERRIDE_WOFFSET                      0x0
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDR50_TUNING_OVERRIDE_DEFAULT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDR50_TUNING_OVERRIDE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDR50_TUNING_OVERRIDE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDR50_TUNING_OVERRIDE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDR50_TUNING_OVERRIDE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDR50_TUNING_OVERRIDE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDR50_TUNING_OVERRIDE_NORMAL                       _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDR50_TUNING_OVERRIDE_OVERRIDE                     _MK_ENUM_CONST(1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_SDR50_TUNING_OVERRIDE__PROD                        _MK_ENUM_CONST(1)

#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_LEGACY_CLKEN_OVERRIDE_SHIFT                        _MK_SHIFT_CONST(6)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_LEGACY_CLKEN_OVERRIDE_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_CLOCK_CNTRL_0_LEGACY_CLKEN_OVERRIDE_SHIFT)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_LEGACY_CLKEN_OVERRIDE_RANGE                        6:6
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_LEGACY_CLKEN_OVERRIDE_WOFFSET                      0x0
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_LEGACY_CLKEN_OVERRIDE_DEFAULT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_LEGACY_CLKEN_OVERRIDE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_LEGACY_CLKEN_OVERRIDE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_LEGACY_CLKEN_OVERRIDE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_LEGACY_CLKEN_OVERRIDE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_LEGACY_CLKEN_OVERRIDE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_LEGACY_CLKEN_OVERRIDE_NORMAL                       _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_LEGACY_CLKEN_OVERRIDE_OVERRIDE                     _MK_ENUM_CONST(1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_LEGACY_CLKEN_OVERRIDE__PROD                        _MK_ENUM_CONST(0)

#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_BASE_CLK_FREQ_SHIFT                        _MK_SHIFT_CONST(8)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_BASE_CLK_FREQ_FIELD                        _MK_FIELD_CONST(0xff, SDMMCAB_VENDOR_CLOCK_CNTRL_0_BASE_CLK_FREQ_SHIFT)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_BASE_CLK_FREQ_RANGE                        15:8
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_BASE_CLK_FREQ_WOFFSET                      0x0
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_BASE_CLK_FREQ_DEFAULT                      _MK_MASK_CONST(0xd0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_BASE_CLK_FREQ_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_BASE_CLK_FREQ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_BASE_CLK_FREQ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_BASE_CLK_FREQ_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_BASE_CLK_FREQ_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_TAP_VAL_SHIFT                      _MK_SHIFT_CONST(16)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_TAP_VAL_FIELD                      _MK_FIELD_CONST(0xff, SDMMCAB_VENDOR_CLOCK_CNTRL_0_TAP_VAL_SHIFT)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_TAP_VAL_RANGE                      23:16
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_TAP_VAL_WOFFSET                    0x0
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_TAP_VAL_DEFAULT                    _MK_MASK_CONST(0x4)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_TAP_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_TAP_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_TAP_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_TAP_VAL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_TAP_VAL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_TAP_VAL__PROD                      _MK_ENUM_CONST(8)

#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_TRIM_VAL_SHIFT                     _MK_SHIFT_CONST(24)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_TRIM_VAL_FIELD                     _MK_FIELD_CONST(0x1f, SDMMCAB_VENDOR_CLOCK_CNTRL_0_TRIM_VAL_SHIFT)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_TRIM_VAL_RANGE                     28:24
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_TRIM_VAL_WOFFSET                   0x0
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_TRIM_VAL_DEFAULT                   _MK_MASK_CONST(0x8)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_TRIM_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_TRIM_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_TRIM_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_TRIM_VAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_TRIM_VAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_TRIM_VAL__PROD                     _MK_ENUM_CONST(20)

#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_DIFF_CLK_SEL_SHIFT                 _MK_SHIFT_CONST(29)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_DIFF_CLK_SEL_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_CLOCK_CNTRL_0_DIFF_CLK_SEL_SHIFT)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_DIFF_CLK_SEL_RANGE                 29:29
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_DIFF_CLK_SEL_WOFFSET                       0x0
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_DIFF_CLK_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_DIFF_CLK_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_DIFF_CLK_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_DIFF_CLK_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_DIFF_CLK_SEL_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLOCK_CNTRL_0_DIFF_CLK_SEL_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register SDMMCAB_VENDOR_SYS_SW_CNTRL_0
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0                   _MK_ADDR_CONST(0x104)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SECURE                    0x0
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_DUAL                      0x0
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SCR                       0
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_WORD_COUNT                        0x1
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_RESET_VAL                         _MK_MASK_CONST(0x38600002)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_RESET_MASK                        _MK_MASK_CONST(0xffe07f7f)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_READ_MASK                         _MK_MASK_CONST(0xffe07f7f)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xffe07f7f)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SPI_MODE_SHIFT                    _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SPI_MODE_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SPI_MODE_SHIFT)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SPI_MODE_RANGE                    0:0
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SPI_MODE_WOFFSET                  0x0
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SPI_MODE_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SPI_MODE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SPI_MODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SPI_MODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SPI_MODE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SPI_MODE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SPI_MODE_DISABLE                  _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SPI_MODE_ENABLE                   _MK_ENUM_CONST(1)

#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_INT_MASK_WHILE_TUNING_SHIFT                       _MK_SHIFT_CONST(1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_INT_MASK_WHILE_TUNING_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_SYS_SW_CNTRL_0_INT_MASK_WHILE_TUNING_SHIFT)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_INT_MASK_WHILE_TUNING_RANGE                       1:1
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_INT_MASK_WHILE_TUNING_WOFFSET                     0x0
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_INT_MASK_WHILE_TUNING_DEFAULT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_INT_MASK_WHILE_TUNING_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_INT_MASK_WHILE_TUNING_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_INT_MASK_WHILE_TUNING_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_INT_MASK_WHILE_TUNING_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_INT_MASK_WHILE_TUNING_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_INT_MASK_WHILE_TUNING_DISABLE                     _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_INT_MASK_WHILE_TUNING_ENABLE                      _MK_ENUM_CONST(1)

#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_IO_TRIM_BYPASS_SHIFT                      _MK_SHIFT_CONST(2)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_IO_TRIM_BYPASS_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_SYS_SW_CNTRL_0_IO_TRIM_BYPASS_SHIFT)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_IO_TRIM_BYPASS_RANGE                      2:2
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_IO_TRIM_BYPASS_WOFFSET                    0x0
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_IO_TRIM_BYPASS_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_IO_TRIM_BYPASS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_IO_TRIM_BYPASS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_IO_TRIM_BYPASS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_IO_TRIM_BYPASS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_IO_TRIM_BYPASS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ASSERT_BUFF_RD_RDY_INT_SHIFT                      _MK_SHIFT_CONST(3)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ASSERT_BUFF_RD_RDY_INT_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ASSERT_BUFF_RD_RDY_INT_SHIFT)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ASSERT_BUFF_RD_RDY_INT_RANGE                      3:3
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ASSERT_BUFF_RD_RDY_INT_WOFFSET                    0x0
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ASSERT_BUFF_RD_RDY_INT_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ASSERT_BUFF_RD_RDY_INT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ASSERT_BUFF_RD_RDY_INT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ASSERT_BUFF_RD_RDY_INT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ASSERT_BUFF_RD_RDY_INT_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ASSERT_BUFF_RD_RDY_INT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ASSERT_BUFF_RD_RDY_INT_DISABLE                    _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ASSERT_BUFF_RD_RDY_INT_ENABLE                     _MK_ENUM_CONST(1)

#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_SYS_INT_ENABLE_SHIFT                       _MK_SHIFT_CONST(4)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_SYS_INT_ENABLE_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_SYS_INT_ENABLE_SHIFT)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_SYS_INT_ENABLE_RANGE                       4:4
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_SYS_INT_ENABLE_WOFFSET                     0x0
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_SYS_INT_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_SYS_INT_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_SYS_INT_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_SYS_INT_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_SYS_INT_ENABLE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_SYS_INT_ENABLE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_SYS_INT_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_SYS_INT_ENABLE_ENABLE                      _MK_ENUM_CONST(1)

#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_VOLT_SWITCH_INT_ENABLE_SHIFT                      _MK_SHIFT_CONST(5)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_VOLT_SWITCH_INT_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_SYS_SW_CNTRL_0_VOLT_SWITCH_INT_ENABLE_SHIFT)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_VOLT_SWITCH_INT_ENABLE_RANGE                      5:5
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_VOLT_SWITCH_INT_ENABLE_WOFFSET                    0x0
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_VOLT_SWITCH_INT_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_VOLT_SWITCH_INT_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_VOLT_SWITCH_INT_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_VOLT_SWITCH_INT_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_VOLT_SWITCH_INT_ENABLE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_VOLT_SWITCH_INT_ENABLE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_VOLT_SWITCH_INT_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_VOLT_SWITCH_INT_ENABLE_ENABLE                     _MK_ENUM_CONST(1)

#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SD_BUS_POWER_ON_OFF_INT_ENABLE_SHIFT                      _MK_SHIFT_CONST(6)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SD_BUS_POWER_ON_OFF_INT_ENABLE_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SD_BUS_POWER_ON_OFF_INT_ENABLE_SHIFT)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SD_BUS_POWER_ON_OFF_INT_ENABLE_RANGE                      6:6
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SD_BUS_POWER_ON_OFF_INT_ENABLE_WOFFSET                    0x0
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SD_BUS_POWER_ON_OFF_INT_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SD_BUS_POWER_ON_OFF_INT_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SD_BUS_POWER_ON_OFF_INT_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SD_BUS_POWER_ON_OFF_INT_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SD_BUS_POWER_ON_OFF_INT_ENABLE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SD_BUS_POWER_ON_OFF_INT_ENABLE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SD_BUS_POWER_ON_OFF_INT_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SD_BUS_POWER_ON_OFF_INT_ENABLE_ENABLE                     _MK_ENUM_CONST(1)

#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_ASYNC_FIFO_ADDNL_DELAY_SHIFT                       _MK_SHIFT_CONST(8)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_ASYNC_FIFO_ADDNL_DELAY_FIELD                       _MK_FIELD_CONST(0xf, SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_ASYNC_FIFO_ADDNL_DELAY_SHIFT)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_ASYNC_FIFO_ADDNL_DELAY_RANGE                       11:8
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_ASYNC_FIFO_ADDNL_DELAY_WOFFSET                     0x0
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_ASYNC_FIFO_ADDNL_DELAY_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_ASYNC_FIFO_ADDNL_DELAY_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_ASYNC_FIFO_ADDNL_DELAY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_ASYNC_FIFO_ADDNL_DELAY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_ASYNC_FIFO_ADDNL_DELAY_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_ASYNC_FIFO_ADDNL_DELAY_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_SYS_INT_STATUS_SHIFT                       _MK_SHIFT_CONST(12)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_SYS_INT_STATUS_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_SYS_INT_STATUS_SHIFT)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_SYS_INT_STATUS_RANGE                       12:12
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_SYS_INT_STATUS_WOFFSET                     0x0
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_SYS_INT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_SYS_INT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_SYS_INT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_SYS_INT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_SYS_INT_STATUS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_SYS_INT_STATUS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_SYS_INT_STATUS_NO_INT                      _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_TUNING_SYS_INT_STATUS_GEN_INT                     _MK_ENUM_CONST(1)

#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_VOLT_SWITCH_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(13)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_VOLT_SWITCH_INT_STATUS_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_SYS_SW_CNTRL_0_VOLT_SWITCH_INT_STATUS_SHIFT)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_VOLT_SWITCH_INT_STATUS_RANGE                      13:13
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_VOLT_SWITCH_INT_STATUS_WOFFSET                    0x0
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_VOLT_SWITCH_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_VOLT_SWITCH_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_VOLT_SWITCH_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_VOLT_SWITCH_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_VOLT_SWITCH_INT_STATUS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_VOLT_SWITCH_INT_STATUS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_VOLT_SWITCH_INT_STATUS_NO_INT                     _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_VOLT_SWITCH_INT_STATUS_GEN_INT                    _MK_ENUM_CONST(1)

#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SD_BUS_POWER_ON_OFF_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(14)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SD_BUS_POWER_ON_OFF_INT_STATUS_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SD_BUS_POWER_ON_OFF_INT_STATUS_SHIFT)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SD_BUS_POWER_ON_OFF_INT_STATUS_RANGE                      14:14
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SD_BUS_POWER_ON_OFF_INT_STATUS_WOFFSET                    0x0
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SD_BUS_POWER_ON_OFF_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SD_BUS_POWER_ON_OFF_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SD_BUS_POWER_ON_OFF_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SD_BUS_POWER_ON_OFF_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SD_BUS_POWER_ON_OFF_INT_STATUS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_SD_BUS_POWER_ON_OFF_INT_STATUS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_QUALIFY_WITH_RD_DATA_VLD_SHIFT                    _MK_SHIFT_CONST(21)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_QUALIFY_WITH_RD_DATA_VLD_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_SYS_SW_CNTRL_0_QUALIFY_WITH_RD_DATA_VLD_SHIFT)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_QUALIFY_WITH_RD_DATA_VLD_RANGE                    21:21
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_QUALIFY_WITH_RD_DATA_VLD_WOFFSET                  0x0
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_QUALIFY_WITH_RD_DATA_VLD_DEFAULT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_QUALIFY_WITH_RD_DATA_VLD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_QUALIFY_WITH_RD_DATA_VLD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_QUALIFY_WITH_RD_DATA_VLD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_QUALIFY_WITH_RD_DATA_VLD_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_QUALIFY_WITH_RD_DATA_VLD_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_EMMC_IOBRICK_CLK_DATA_SHIFT                       _MK_SHIFT_CONST(22)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_EMMC_IOBRICK_CLK_DATA_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_SYS_SW_CNTRL_0_EMMC_IOBRICK_CLK_DATA_SHIFT)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_EMMC_IOBRICK_CLK_DATA_RANGE                       22:22
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_EMMC_IOBRICK_CLK_DATA_WOFFSET                     0x0
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_EMMC_IOBRICK_CLK_DATA_DEFAULT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_EMMC_IOBRICK_CLK_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_EMMC_IOBRICK_CLK_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_EMMC_IOBRICK_CLK_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_EMMC_IOBRICK_CLK_DATA_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_EMMC_IOBRICK_CLK_DATA_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ALLOW_CARD_CLK_STALLS_IN_WR_SHIFT                 _MK_SHIFT_CONST(23)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ALLOW_CARD_CLK_STALLS_IN_WR_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ALLOW_CARD_CLK_STALLS_IN_WR_SHIFT)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ALLOW_CARD_CLK_STALLS_IN_WR_RANGE                 23:23
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ALLOW_CARD_CLK_STALLS_IN_WR_WOFFSET                       0x0
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ALLOW_CARD_CLK_STALLS_IN_WR_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ALLOW_CARD_CLK_STALLS_IN_WR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ALLOW_CARD_CLK_STALLS_IN_WR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ALLOW_CARD_CLK_STALLS_IN_WR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ALLOW_CARD_CLK_STALLS_IN_WR_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ALLOW_CARD_CLK_STALLS_IN_WR_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_DEVICE_BUSY_WAIT_CYCLES_SHIFT                     _MK_SHIFT_CONST(24)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_DEVICE_BUSY_WAIT_CYCLES_FIELD                     _MK_FIELD_CONST(0xf, SDMMCAB_VENDOR_SYS_SW_CNTRL_0_DEVICE_BUSY_WAIT_CYCLES_SHIFT)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_DEVICE_BUSY_WAIT_CYCLES_RANGE                     27:24
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_DEVICE_BUSY_WAIT_CYCLES_WOFFSET                   0x0
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_DEVICE_BUSY_WAIT_CYCLES_DEFAULT                   _MK_MASK_CONST(0x8)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_DEVICE_BUSY_WAIT_CYCLES_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_DEVICE_BUSY_WAIT_CYCLES_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_DEVICE_BUSY_WAIT_CYCLES_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_DEVICE_BUSY_WAIT_CYCLES_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_DEVICE_BUSY_WAIT_CYCLES_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_TMCLK_FOR_DATA_TIMEOUT_SHIFT                  _MK_SHIFT_CONST(28)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_TMCLK_FOR_DATA_TIMEOUT_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_TMCLK_FOR_DATA_TIMEOUT_SHIFT)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_TMCLK_FOR_DATA_TIMEOUT_RANGE                  28:28
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_TMCLK_FOR_DATA_TIMEOUT_WOFFSET                        0x0
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_TMCLK_FOR_DATA_TIMEOUT_DEFAULT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_TMCLK_FOR_DATA_TIMEOUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_TMCLK_FOR_DATA_TIMEOUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_TMCLK_FOR_DATA_TIMEOUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_TMCLK_FOR_DATA_TIMEOUT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_TMCLK_FOR_DATA_TIMEOUT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_NCRC_FOR_WR_CRC_STATUS_TIMEOUT_VAL_SHIFT                      _MK_SHIFT_CONST(29)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_NCRC_FOR_WR_CRC_STATUS_TIMEOUT_VAL_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_NCRC_FOR_WR_CRC_STATUS_TIMEOUT_VAL_SHIFT)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_NCRC_FOR_WR_CRC_STATUS_TIMEOUT_VAL_RANGE                      29:29
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_NCRC_FOR_WR_CRC_STATUS_TIMEOUT_VAL_WOFFSET                    0x0
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_NCRC_FOR_WR_CRC_STATUS_TIMEOUT_VAL_DEFAULT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_NCRC_FOR_WR_CRC_STATUS_TIMEOUT_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_NCRC_FOR_WR_CRC_STATUS_TIMEOUT_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_NCRC_FOR_WR_CRC_STATUS_TIMEOUT_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_NCRC_FOR_WR_CRC_STATUS_TIMEOUT_VAL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_NCRC_FOR_WR_CRC_STATUS_TIMEOUT_VAL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_TMCLK_FOR_WR_CRC_STATUS_TIMEOUT_SHIFT                 _MK_SHIFT_CONST(30)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_TMCLK_FOR_WR_CRC_STATUS_TIMEOUT_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_TMCLK_FOR_WR_CRC_STATUS_TIMEOUT_SHIFT)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_TMCLK_FOR_WR_CRC_STATUS_TIMEOUT_RANGE                 30:30
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_TMCLK_FOR_WR_CRC_STATUS_TIMEOUT_WOFFSET                       0x0
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_TMCLK_FOR_WR_CRC_STATUS_TIMEOUT_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_TMCLK_FOR_WR_CRC_STATUS_TIMEOUT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_TMCLK_FOR_WR_CRC_STATUS_TIMEOUT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_TMCLK_FOR_WR_CRC_STATUS_TIMEOUT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_TMCLK_FOR_WR_CRC_STATUS_TIMEOUT_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_USE_TMCLK_FOR_WR_CRC_STATUS_TIMEOUT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ENHANCED_STROBE_MODE_SHIFT                        _MK_SHIFT_CONST(31)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ENHANCED_STROBE_MODE_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ENHANCED_STROBE_MODE_SHIFT)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ENHANCED_STROBE_MODE_RANGE                        31:31
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ENHANCED_STROBE_MODE_WOFFSET                      0x0
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ENHANCED_STROBE_MODE_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ENHANCED_STROBE_MODE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ENHANCED_STROBE_MODE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ENHANCED_STROBE_MODE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ENHANCED_STROBE_MODE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ENHANCED_STROBE_MODE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_SYS_SW_CNTRL_0_ENHANCED_STROBE_MODE__PROD_C_ESM                  _MK_ENUM_CONST(1)


// Register SDMMCAB_VENDOR_ERR_INTR_STATUS_0
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0                        _MK_ADDR_CONST(0x108)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SECURE                         0x0
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_DUAL                   0x0
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SCR                    0
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_WORD_COUNT                     0x1
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0x3f1ff)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_READ_MASK                      _MK_MASK_CONST(0x7f1ff)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SDMMC_LEGACY_CTLR_IDLE_SHIFT                   _MK_SHIFT_CONST(18)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SDMMC_LEGACY_CTLR_IDLE_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SDMMC_LEGACY_CTLR_IDLE_SHIFT)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SDMMC_LEGACY_CTLR_IDLE_RANGE                   18:18
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SDMMC_LEGACY_CTLR_IDLE_WOFFSET                 0x0
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SDMMC_LEGACY_CTLR_IDLE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SDMMC_LEGACY_CTLR_IDLE_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SDMMC_LEGACY_CTLR_IDLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SDMMC_LEGACY_CTLR_IDLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SDMMC_LEGACY_CTLR_IDLE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SDMMC_LEGACY_CTLR_IDLE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_READ_DATA_TIMEOUT_SHIFT                        _MK_SHIFT_CONST(17)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_READ_DATA_TIMEOUT_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_ERR_INTR_STATUS_0_READ_DATA_TIMEOUT_SHIFT)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_READ_DATA_TIMEOUT_RANGE                        17:17
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_READ_DATA_TIMEOUT_WOFFSET                      0x0
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_READ_DATA_TIMEOUT_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_READ_DATA_TIMEOUT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_READ_DATA_TIMEOUT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_READ_DATA_TIMEOUT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_READ_DATA_TIMEOUT_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_READ_DATA_TIMEOUT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_WRITE_CRC_STATUS_TIMEOUT_SHIFT                 _MK_SHIFT_CONST(16)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_WRITE_CRC_STATUS_TIMEOUT_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_ERR_INTR_STATUS_0_WRITE_CRC_STATUS_TIMEOUT_SHIFT)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_WRITE_CRC_STATUS_TIMEOUT_RANGE                 16:16
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_WRITE_CRC_STATUS_TIMEOUT_WOFFSET                       0x0
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_WRITE_CRC_STATUS_TIMEOUT_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_WRITE_CRC_STATUS_TIMEOUT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_WRITE_CRC_STATUS_TIMEOUT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_WRITE_CRC_STATUS_TIMEOUT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_WRITE_CRC_STATUS_TIMEOUT_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_WRITE_CRC_STATUS_TIMEOUT_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_WRITE_BUSY_TIMEOUT_SHIFT                       _MK_SHIFT_CONST(15)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_WRITE_BUSY_TIMEOUT_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_ERR_INTR_STATUS_0_WRITE_BUSY_TIMEOUT_SHIFT)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_WRITE_BUSY_TIMEOUT_RANGE                       15:15
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_WRITE_BUSY_TIMEOUT_WOFFSET                     0x0
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_WRITE_BUSY_TIMEOUT_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_WRITE_BUSY_TIMEOUT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_WRITE_BUSY_TIMEOUT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_WRITE_BUSY_TIMEOUT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_WRITE_BUSY_TIMEOUT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_WRITE_BUSY_TIMEOUT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_RESP_BUSY_TIMEOUT_SHIFT                        _MK_SHIFT_CONST(14)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_RESP_BUSY_TIMEOUT_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_ERR_INTR_STATUS_0_RESP_BUSY_TIMEOUT_SHIFT)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_RESP_BUSY_TIMEOUT_RANGE                        14:14
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_RESP_BUSY_TIMEOUT_WOFFSET                      0x0
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_RESP_BUSY_TIMEOUT_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_RESP_BUSY_TIMEOUT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_RESP_BUSY_TIMEOUT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_RESP_BUSY_TIMEOUT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_RESP_BUSY_TIMEOUT_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_RESP_BUSY_TIMEOUT_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_WRITE_BUSY_TIMEOUT_SHIFT                   _MK_SHIFT_CONST(13)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_WRITE_BUSY_TIMEOUT_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_WRITE_BUSY_TIMEOUT_SHIFT)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_WRITE_BUSY_TIMEOUT_RANGE                   13:13
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_WRITE_BUSY_TIMEOUT_WOFFSET                 0x0
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_WRITE_BUSY_TIMEOUT_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_WRITE_BUSY_TIMEOUT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_WRITE_BUSY_TIMEOUT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_WRITE_BUSY_TIMEOUT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_WRITE_BUSY_TIMEOUT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_WRITE_BUSY_TIMEOUT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_RX_START_TOKEN_TIMEOUT_SHIFT                       _MK_SHIFT_CONST(12)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_RX_START_TOKEN_TIMEOUT_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_RX_START_TOKEN_TIMEOUT_SHIFT)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_RX_START_TOKEN_TIMEOUT_RANGE                       12:12
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_RX_START_TOKEN_TIMEOUT_WOFFSET                     0x0
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_RX_START_TOKEN_TIMEOUT_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_RX_START_TOKEN_TIMEOUT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_RX_START_TOKEN_TIMEOUT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_RX_START_TOKEN_TIMEOUT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_RX_START_TOKEN_TIMEOUT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_RX_START_TOKEN_TIMEOUT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_DAT_ERR_TOKEN_SHIFT                        _MK_SHIFT_CONST(5)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_DAT_ERR_TOKEN_FIELD                        _MK_FIELD_CONST(0xf, SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_DAT_ERR_TOKEN_SHIFT)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_DAT_ERR_TOKEN_RANGE                        8:5
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_DAT_ERR_TOKEN_WOFFSET                      0x0
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_DAT_ERR_TOKEN_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_DAT_ERR_TOKEN_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_DAT_ERR_TOKEN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_DAT_ERR_TOKEN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_DAT_ERR_TOKEN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_DAT_ERR_TOKEN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_DAT_RESPONSE_SHIFT                 _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_DAT_RESPONSE_FIELD                 _MK_FIELD_CONST(0x1f, SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_DAT_RESPONSE_SHIFT)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_DAT_RESPONSE_RANGE                 4:0
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_DAT_RESPONSE_WOFFSET                       0x0
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_DAT_RESPONSE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_DAT_RESPONSE_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_DAT_RESPONSE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_DAT_RESPONSE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_DAT_RESPONSE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_DAT_RESPONSE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_DAT_RESPONSE_DATA_ACCEPTED                 _MK_ENUM_CONST(5)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_DAT_RESPONSE_CRC_ERR                       _MK_ENUM_CONST(11)
#define SDMMCAB_VENDOR_ERR_INTR_STATUS_0_SPI_DAT_RESPONSE_WRITE_ERR                     _MK_ENUM_CONST(13)


// Register SDMMCAB_VENDOR_CAP_OVERRIDES_0
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0                  _MK_ADDR_CONST(0x10c)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_SECURE                   0x0
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_DUAL                     0x0
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_SCR                      0
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_WORD_COUNT                       0x1
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_RESET_VAL                        _MK_MASK_CONST(0x1107)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_RESET_MASK                       _MK_MASK_CONST(0x3f0f)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_READ_MASK                        _MK_MASK_CONST(0x3f0f)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_WRITE_MASK                       _MK_MASK_CONST(0x3f0f)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_DQS_TRIM_VAL_SHIFT                       _MK_SHIFT_CONST(8)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_DQS_TRIM_VAL_FIELD                       _MK_FIELD_CONST(0x3f, SDMMCAB_VENDOR_CAP_OVERRIDES_0_DQS_TRIM_VAL_SHIFT)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_DQS_TRIM_VAL_RANGE                       13:8
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_DQS_TRIM_VAL_WOFFSET                     0x0
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_DQS_TRIM_VAL_DEFAULT                     _MK_MASK_CONST(0x11)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_DQS_TRIM_VAL_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_DQS_TRIM_VAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_DQS_TRIM_VAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_DQS_TRIM_VAL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_DQS_TRIM_VAL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_DQS_TRIM_VAL__PROD_C_HS400                       _MK_ENUM_CONST(40)

#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_DRV_LPBK_CLK_ON_CMD_LINE_SHIFT                   _MK_SHIFT_CONST(3)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_DRV_LPBK_CLK_ON_CMD_LINE_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_CAP_OVERRIDES_0_DRV_LPBK_CLK_ON_CMD_LINE_SHIFT)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_DRV_LPBK_CLK_ON_CMD_LINE_RANGE                   3:3
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_DRV_LPBK_CLK_ON_CMD_LINE_WOFFSET                 0x0
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_DRV_LPBK_CLK_ON_CMD_LINE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_DRV_LPBK_CLK_ON_CMD_LINE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_DRV_LPBK_CLK_ON_CMD_LINE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_DRV_LPBK_CLK_ON_CMD_LINE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_DRV_LPBK_CLK_ON_CMD_LINE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_DRV_LPBK_CLK_ON_CMD_LINE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_3_3_V_SUPPORT_OVERRIDE_SHIFT                     _MK_SHIFT_CONST(2)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_3_3_V_SUPPORT_OVERRIDE_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_3_3_V_SUPPORT_OVERRIDE_SHIFT)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_3_3_V_SUPPORT_OVERRIDE_RANGE                     2:2
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_3_3_V_SUPPORT_OVERRIDE_WOFFSET                   0x0
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_3_3_V_SUPPORT_OVERRIDE_DEFAULT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_3_3_V_SUPPORT_OVERRIDE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_3_3_V_SUPPORT_OVERRIDE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_3_3_V_SUPPORT_OVERRIDE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_3_3_V_SUPPORT_OVERRIDE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_3_3_V_SUPPORT_OVERRIDE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_3_0_V_SUPPORT_OVERRIDE_SHIFT                     _MK_SHIFT_CONST(1)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_3_0_V_SUPPORT_OVERRIDE_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_3_0_V_SUPPORT_OVERRIDE_SHIFT)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_3_0_V_SUPPORT_OVERRIDE_RANGE                     1:1
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_3_0_V_SUPPORT_OVERRIDE_WOFFSET                   0x0
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_3_0_V_SUPPORT_OVERRIDE_DEFAULT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_3_0_V_SUPPORT_OVERRIDE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_3_0_V_SUPPORT_OVERRIDE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_3_0_V_SUPPORT_OVERRIDE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_3_0_V_SUPPORT_OVERRIDE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_3_0_V_SUPPORT_OVERRIDE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_1_8_V_SUPPORT_OVERRIDE_SHIFT                     _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_1_8_V_SUPPORT_OVERRIDE_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_1_8_V_SUPPORT_OVERRIDE_SHIFT)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_1_8_V_SUPPORT_OVERRIDE_RANGE                     0:0
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_1_8_V_SUPPORT_OVERRIDE_WOFFSET                   0x0
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_1_8_V_SUPPORT_OVERRIDE_DEFAULT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_1_8_V_SUPPORT_OVERRIDE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_1_8_V_SUPPORT_OVERRIDE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_1_8_V_SUPPORT_OVERRIDE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_1_8_V_SUPPORT_OVERRIDE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CAP_OVERRIDES_0_VOLTAGE_1_8_V_SUPPORT_OVERRIDE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register SDMMCAB_VENDOR_BOOT_CNTRL_0
#define SDMMCAB_VENDOR_BOOT_CNTRL_0                     _MK_ADDR_CONST(0x110)
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_SECURE                      0x0
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_DUAL                        0x0
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_SCR                         0
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_WORD_COUNT                  0x1
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_BOOT_ACK_SHIFT                      _MK_SHIFT_CONST(1)
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_BOOT_ACK_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_BOOT_CNTRL_0_BOOT_ACK_SHIFT)
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_BOOT_ACK_RANGE                      1:1
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_BOOT_ACK_WOFFSET                    0x0
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_BOOT_ACK_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_BOOT_ACK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_BOOT_ACK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_BOOT_ACK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_BOOT_ACK_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_BOOT_ACK_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_BOOT_ACK_DISABLE                    _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_BOOT_ACK_ENABLE                     _MK_ENUM_CONST(1)

#define SDMMCAB_VENDOR_BOOT_CNTRL_0_BOOT_SHIFT                  _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_BOOT_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_BOOT_CNTRL_0_BOOT_SHIFT)
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_BOOT_RANGE                  0:0
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_BOOT_WOFFSET                        0x0
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_BOOT_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_BOOT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_BOOT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_BOOT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_BOOT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_BOOT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_BOOT_DISABLE                        _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_BOOT_CNTRL_0_BOOT_ENABLE                 _MK_ENUM_CONST(1)


// Register SDMMCAB_VENDOR_BOOT_ACK_TIMEOUT_0
#define SDMMCAB_VENDOR_BOOT_ACK_TIMEOUT_0                       _MK_ADDR_CONST(0x114)
#define SDMMCAB_VENDOR_BOOT_ACK_TIMEOUT_0_SECURE                        0x0
#define SDMMCAB_VENDOR_BOOT_ACK_TIMEOUT_0_DUAL                  0x0
#define SDMMCAB_VENDOR_BOOT_ACK_TIMEOUT_0_SCR                   0
#define SDMMCAB_VENDOR_BOOT_ACK_TIMEOUT_0_WORD_COUNT                    0x1
#define SDMMCAB_VENDOR_BOOT_ACK_TIMEOUT_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_BOOT_ACK_TIMEOUT_0_RESET_MASK                    _MK_MASK_CONST(0xfffff)
#define SDMMCAB_VENDOR_BOOT_ACK_TIMEOUT_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_BOOT_ACK_TIMEOUT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_BOOT_ACK_TIMEOUT_0_READ_MASK                     _MK_MASK_CONST(0xfffff)
#define SDMMCAB_VENDOR_BOOT_ACK_TIMEOUT_0_WRITE_MASK                    _MK_MASK_CONST(0xfffff)
#define SDMMCAB_VENDOR_BOOT_ACK_TIMEOUT_0_VALUE_SHIFT                   _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_BOOT_ACK_TIMEOUT_0_VALUE_FIELD                   _MK_FIELD_CONST(0xfffff, SDMMCAB_VENDOR_BOOT_ACK_TIMEOUT_0_VALUE_SHIFT)
#define SDMMCAB_VENDOR_BOOT_ACK_TIMEOUT_0_VALUE_RANGE                   19:0
#define SDMMCAB_VENDOR_BOOT_ACK_TIMEOUT_0_VALUE_WOFFSET                 0x0
#define SDMMCAB_VENDOR_BOOT_ACK_TIMEOUT_0_VALUE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_BOOT_ACK_TIMEOUT_0_VALUE_DEFAULT_MASK                    _MK_MASK_CONST(0xfffff)
#define SDMMCAB_VENDOR_BOOT_ACK_TIMEOUT_0_VALUE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_BOOT_ACK_TIMEOUT_0_VALUE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_BOOT_ACK_TIMEOUT_0_VALUE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_BOOT_ACK_TIMEOUT_0_VALUE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register SDMMCAB_VENDOR_BOOT_DAT_TIMEOUT_0
#define SDMMCAB_VENDOR_BOOT_DAT_TIMEOUT_0                       _MK_ADDR_CONST(0x118)
#define SDMMCAB_VENDOR_BOOT_DAT_TIMEOUT_0_SECURE                        0x0
#define SDMMCAB_VENDOR_BOOT_DAT_TIMEOUT_0_DUAL                  0x0
#define SDMMCAB_VENDOR_BOOT_DAT_TIMEOUT_0_SCR                   0
#define SDMMCAB_VENDOR_BOOT_DAT_TIMEOUT_0_WORD_COUNT                    0x1
#define SDMMCAB_VENDOR_BOOT_DAT_TIMEOUT_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_BOOT_DAT_TIMEOUT_0_RESET_MASK                    _MK_MASK_CONST(0x1ffffff)
#define SDMMCAB_VENDOR_BOOT_DAT_TIMEOUT_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_BOOT_DAT_TIMEOUT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_BOOT_DAT_TIMEOUT_0_READ_MASK                     _MK_MASK_CONST(0x1ffffff)
#define SDMMCAB_VENDOR_BOOT_DAT_TIMEOUT_0_WRITE_MASK                    _MK_MASK_CONST(0x1ffffff)
#define SDMMCAB_VENDOR_BOOT_DAT_TIMEOUT_0_VALUE_SHIFT                   _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_BOOT_DAT_TIMEOUT_0_VALUE_FIELD                   _MK_FIELD_CONST(0x1ffffff, SDMMCAB_VENDOR_BOOT_DAT_TIMEOUT_0_VALUE_SHIFT)
#define SDMMCAB_VENDOR_BOOT_DAT_TIMEOUT_0_VALUE_RANGE                   24:0
#define SDMMCAB_VENDOR_BOOT_DAT_TIMEOUT_0_VALUE_WOFFSET                 0x0
#define SDMMCAB_VENDOR_BOOT_DAT_TIMEOUT_0_VALUE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_BOOT_DAT_TIMEOUT_0_VALUE_DEFAULT_MASK                    _MK_MASK_CONST(0x1ffffff)
#define SDMMCAB_VENDOR_BOOT_DAT_TIMEOUT_0_VALUE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_BOOT_DAT_TIMEOUT_0_VALUE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_BOOT_DAT_TIMEOUT_0_VALUE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_BOOT_DAT_TIMEOUT_0_VALUE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register SDMMCAB_VENDOR_DEBOUNCE_COUNT_0
#define SDMMCAB_VENDOR_DEBOUNCE_COUNT_0                 _MK_ADDR_CONST(0x11c)
#define SDMMCAB_VENDOR_DEBOUNCE_COUNT_0_SECURE                  0x0
#define SDMMCAB_VENDOR_DEBOUNCE_COUNT_0_DUAL                    0x0
#define SDMMCAB_VENDOR_DEBOUNCE_COUNT_0_SCR                     0
#define SDMMCAB_VENDOR_DEBOUNCE_COUNT_0_WORD_COUNT                      0x1
#define SDMMCAB_VENDOR_DEBOUNCE_COUNT_0_RESET_VAL                       _MK_MASK_CONST(0xc80)
#define SDMMCAB_VENDOR_DEBOUNCE_COUNT_0_RESET_MASK                      _MK_MASK_CONST(0xffffff)
#define SDMMCAB_VENDOR_DEBOUNCE_COUNT_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DEBOUNCE_COUNT_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DEBOUNCE_COUNT_0_READ_MASK                       _MK_MASK_CONST(0xffffff)
#define SDMMCAB_VENDOR_DEBOUNCE_COUNT_0_WRITE_MASK                      _MK_MASK_CONST(0xffffff)
#define SDMMCAB_VENDOR_DEBOUNCE_COUNT_0_VALUE_SHIFT                     _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_DEBOUNCE_COUNT_0_VALUE_FIELD                     _MK_FIELD_CONST(0xffffff, SDMMCAB_VENDOR_DEBOUNCE_COUNT_0_VALUE_SHIFT)
#define SDMMCAB_VENDOR_DEBOUNCE_COUNT_0_VALUE_RANGE                     23:0
#define SDMMCAB_VENDOR_DEBOUNCE_COUNT_0_VALUE_WOFFSET                   0x0
#define SDMMCAB_VENDOR_DEBOUNCE_COUNT_0_VALUE_DEFAULT                   _MK_MASK_CONST(0xc80)
#define SDMMCAB_VENDOR_DEBOUNCE_COUNT_0_VALUE_DEFAULT_MASK                      _MK_MASK_CONST(0xffffff)
#define SDMMCAB_VENDOR_DEBOUNCE_COUNT_0_VALUE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DEBOUNCE_COUNT_0_VALUE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DEBOUNCE_COUNT_0_VALUE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DEBOUNCE_COUNT_0_VALUE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register SDMMCAB_VENDOR_MISC_CNTRL_0
#define SDMMCAB_VENDOR_MISC_CNTRL_0                     _MK_ADDR_CONST(0x120)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_SECURE                      0x0
#define SDMMCAB_VENDOR_MISC_CNTRL_0_DUAL                        0x0
#define SDMMCAB_VENDOR_MISC_CNTRL_0_SCR                         0
#define SDMMCAB_VENDOR_MISC_CNTRL_0_WORD_COUNT                  0x1
#define SDMMCAB_VENDOR_MISC_CNTRL_0_RESET_VAL                   _MK_MASK_CONST(0xffff0098)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_ERASE_TIMEOUT_LIMIT_SHIFT                   _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_ERASE_TIMEOUT_LIMIT_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_MISC_CNTRL_0_ERASE_TIMEOUT_LIMIT_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_ERASE_TIMEOUT_LIMIT_RANGE                   0:0
#define SDMMCAB_VENDOR_MISC_CNTRL_0_ERASE_TIMEOUT_LIMIT_WOFFSET                 0x0
#define SDMMCAB_VENDOR_MISC_CNTRL_0_ERASE_TIMEOUT_LIMIT_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_ERASE_TIMEOUT_LIMIT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_ERASE_TIMEOUT_LIMIT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_ERASE_TIMEOUT_LIMIT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_ERASE_TIMEOUT_LIMIT_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_ERASE_TIMEOUT_LIMIT_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_ERASE_TIMEOUT_LIMIT_FINITE                  _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_ERASE_TIMEOUT_LIMIT_INFINITE                        _MK_ENUM_CONST(1)

#define SDMMCAB_VENDOR_MISC_CNTRL_0_SDMMC_SPARE0_SHIFT                  _MK_SHIFT_CONST(1)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_SDMMC_SPARE0_FIELD                  _MK_FIELD_CONST(0x7fff, SDMMCAB_VENDOR_MISC_CNTRL_0_SDMMC_SPARE0_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_SDMMC_SPARE0_RANGE                  15:1
#define SDMMCAB_VENDOR_MISC_CNTRL_0_SDMMC_SPARE0_WOFFSET                        0x0
#define SDMMCAB_VENDOR_MISC_CNTRL_0_SDMMC_SPARE0_DEFAULT                        _MK_MASK_CONST(0x4c)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_SDMMC_SPARE0_DEFAULT_MASK                   _MK_MASK_CONST(0x7fff)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_SDMMC_SPARE0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_SDMMC_SPARE0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_SDMMC_SPARE0_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_SDMMC_SPARE0_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_SDMMC_SPARE0__PROD                  _MK_ENUM_CONST(332)

#define SDMMCAB_VENDOR_MISC_CNTRL_0_SDMMC_SPARE1_SHIFT                  _MK_SHIFT_CONST(16)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_SDMMC_SPARE1_FIELD                  _MK_FIELD_CONST(0xffff, SDMMCAB_VENDOR_MISC_CNTRL_0_SDMMC_SPARE1_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_SDMMC_SPARE1_RANGE                  31:16
#define SDMMCAB_VENDOR_MISC_CNTRL_0_SDMMC_SPARE1_WOFFSET                        0x0
#define SDMMCAB_VENDOR_MISC_CNTRL_0_SDMMC_SPARE1_DEFAULT                        _MK_MASK_CONST(0xffff)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_SDMMC_SPARE1_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_SDMMC_SPARE1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_SDMMC_SPARE1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_SDMMC_SPARE1_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL_0_SDMMC_SPARE1_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register SDMMCAB_VENDOR_MISC_CNTRL1_0
#define SDMMCAB_VENDOR_MISC_CNTRL1_0                    _MK_ADDR_CONST(0x124)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_SECURE                     0x0
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_DUAL                       0x0
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_SCR                        0
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_WORD_COUNT                         0x1
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_RESET_MASK                         _MK_MASK_CONST(0xffffff)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_READ_MASK                  _MK_MASK_CONST(0xffffff)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_WRITE_MASK                         _MK_MASK_CONST(0xffffff)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_3_3V_SHIFT                    _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_3_3V_FIELD                    _MK_FIELD_CONST(0xff, SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_3_3V_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_3_3V_RANGE                    7:0
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_3_3V_WOFFSET                  0x0
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_3_3V_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_3_3V_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_3_3V_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_3_3V_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_3_3V_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_3_3V_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_3_0V_SHIFT                    _MK_SHIFT_CONST(8)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_3_0V_FIELD                    _MK_FIELD_CONST(0xff, SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_3_0V_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_3_0V_RANGE                    15:8
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_3_0V_WOFFSET                  0x0
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_3_0V_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_3_0V_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_3_0V_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_3_0V_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_3_0V_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_3_0V_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_1_8V_SHIFT                    _MK_SHIFT_CONST(16)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_1_8V_FIELD                    _MK_FIELD_CONST(0xff, SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_1_8V_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_1_8V_RANGE                    23:16
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_1_8V_WOFFSET                  0x0
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_1_8V_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_1_8V_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_1_8V_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_1_8V_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_1_8V_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL1_0_OVERRIDE_FOR_1_8V_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register SDMMCAB_VENDOR_MISC_CNTRL2_0
#define SDMMCAB_VENDOR_MISC_CNTRL2_0                    _MK_ADDR_CONST(0x128)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SECURE                     0x0
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DUAL                       0x0
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SCR                        0
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_WORD_COUNT                         0x1
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_RESET_VAL                  _MK_MASK_CONST(0x63e00000)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_RESET_MASK                         _MK_MASK_CONST(0xffefffff)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_READ_MASK                  _MK_MASK_CONST(0xffefffff)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_WRITE_MASK                         _MK_MASK_CONST(0xffefffff)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_VGPIO_MODE_EN_SHIFT                        _MK_SHIFT_CONST(31)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_VGPIO_MODE_EN_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_MISC_CNTRL2_0_VGPIO_MODE_EN_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_VGPIO_MODE_EN_RANGE                        31:31
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_VGPIO_MODE_EN_WOFFSET                      0x0
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_VGPIO_MODE_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_VGPIO_MODE_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_VGPIO_MODE_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_VGPIO_MODE_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_VGPIO_MODE_EN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_VGPIO_MODE_EN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SDMMC_CLK_OVR_ON_SHIFT                     _MK_SHIFT_CONST(30)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SDMMC_CLK_OVR_ON_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_MISC_CNTRL2_0_SDMMC_CLK_OVR_ON_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SDMMC_CLK_OVR_ON_RANGE                     30:30
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SDMMC_CLK_OVR_ON_WOFFSET                   0x0
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SDMMC_CLK_OVR_ON_DEFAULT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SDMMC_CLK_OVR_ON_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SDMMC_CLK_OVR_ON_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SDMMC_CLK_OVR_ON_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SDMMC_CLK_OVR_ON_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SDMMC_CLK_OVR_ON_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SDMMC_CLK_OVR_ON__PROD                     _MK_ENUM_CONST(0)

#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SD_CARD_DETECT_STATUS_N_SHIFT                      _MK_SHIFT_CONST(29)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SD_CARD_DETECT_STATUS_N_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_MISC_CNTRL2_0_SD_CARD_DETECT_STATUS_N_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SD_CARD_DETECT_STATUS_N_RANGE                      29:29
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SD_CARD_DETECT_STATUS_N_WOFFSET                    0x0
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SD_CARD_DETECT_STATUS_N_DEFAULT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SD_CARD_DETECT_STATUS_N_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SD_CARD_DETECT_STATUS_N_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SD_CARD_DETECT_STATUS_N_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SD_CARD_DETECT_STATUS_N_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SD_CARD_DETECT_STATUS_N_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SD_CARD_WP_STATUS_SHIFT                    _MK_SHIFT_CONST(28)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SD_CARD_WP_STATUS_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_MISC_CNTRL2_0_SD_CARD_WP_STATUS_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SD_CARD_WP_STATUS_RANGE                    28:28
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SD_CARD_WP_STATUS_WOFFSET                  0x0
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SD_CARD_WP_STATUS_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SD_CARD_WP_STATUS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SD_CARD_WP_STATUS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SD_CARD_WP_STATUS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SD_CARD_WP_STATUS_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_SD_CARD_WP_STATUS_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CMD_TFIFO_HOT_RESET_SHIFT                  _MK_SHIFT_CONST(27)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CMD_TFIFO_HOT_RESET_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_MISC_CNTRL2_0_CMD_TFIFO_HOT_RESET_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CMD_TFIFO_HOT_RESET_RANGE                  27:27
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CMD_TFIFO_HOT_RESET_WOFFSET                        0x0
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CMD_TFIFO_HOT_RESET_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CMD_TFIFO_HOT_RESET_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CMD_TFIFO_HOT_RESET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CMD_TFIFO_HOT_RESET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CMD_TFIFO_HOT_RESET_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CMD_TFIFO_HOT_RESET_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DAT_TFIFO_HOT_RESET_SHIFT                  _MK_SHIFT_CONST(26)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DAT_TFIFO_HOT_RESET_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_MISC_CNTRL2_0_DAT_TFIFO_HOT_RESET_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DAT_TFIFO_HOT_RESET_RANGE                  26:26
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DAT_TFIFO_HOT_RESET_WOFFSET                        0x0
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DAT_TFIFO_HOT_RESET_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DAT_TFIFO_HOT_RESET_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DAT_TFIFO_HOT_RESET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DAT_TFIFO_HOT_RESET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DAT_TFIFO_HOT_RESET_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DAT_TFIFO_HOT_RESET_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA3_CLKEN_OVERRIDE_SHIFT                 _MK_SHIFT_CONST(25)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA3_CLKEN_OVERRIDE_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA3_CLKEN_OVERRIDE_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA3_CLKEN_OVERRIDE_RANGE                 25:25
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA3_CLKEN_OVERRIDE_WOFFSET                       0x0
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA3_CLKEN_OVERRIDE_DEFAULT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA3_CLKEN_OVERRIDE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA3_CLKEN_OVERRIDE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA3_CLKEN_OVERRIDE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA3_CLKEN_OVERRIDE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA3_CLKEN_OVERRIDE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA3_CLKEN_OVERRIDE_NORMAL                        _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA3_CLKEN_OVERRIDE_OVERRIDE                      _MK_ENUM_CONST(1)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA3_CLKEN_OVERRIDE__PROD                 _MK_ENUM_CONST(0)

#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CQE_CLKEN_OVERRIDE_SHIFT                   _MK_SHIFT_CONST(24)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CQE_CLKEN_OVERRIDE_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_MISC_CNTRL2_0_CQE_CLKEN_OVERRIDE_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CQE_CLKEN_OVERRIDE_RANGE                   24:24
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CQE_CLKEN_OVERRIDE_WOFFSET                 0x0
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CQE_CLKEN_OVERRIDE_DEFAULT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CQE_CLKEN_OVERRIDE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CQE_CLKEN_OVERRIDE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CQE_CLKEN_OVERRIDE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CQE_CLKEN_OVERRIDE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CQE_CLKEN_OVERRIDE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CQE_CLKEN_OVERRIDE_NORMAL                  _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CQE_CLKEN_OVERRIDE_OVERRIDE                        _MK_ENUM_CONST(1)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CQE_CLKEN_OVERRIDE__PROD                   _MK_ENUM_CONST(0)

#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CQE_DESC_PREFETCH_EN_SHIFT                 _MK_SHIFT_CONST(23)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CQE_DESC_PREFETCH_EN_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_MISC_CNTRL2_0_CQE_DESC_PREFETCH_EN_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CQE_DESC_PREFETCH_EN_RANGE                 23:23
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CQE_DESC_PREFETCH_EN_WOFFSET                       0x0
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CQE_DESC_PREFETCH_EN_DEFAULT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CQE_DESC_PREFETCH_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CQE_DESC_PREFETCH_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CQE_DESC_PREFETCH_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CQE_DESC_PREFETCH_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_CQE_DESC_PREFETCH_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA3_DESC_PREFETCH_EN_SHIFT                       _MK_SHIFT_CONST(22)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA3_DESC_PREFETCH_EN_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA3_DESC_PREFETCH_EN_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA3_DESC_PREFETCH_EN_RANGE                       22:22
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA3_DESC_PREFETCH_EN_WOFFSET                     0x0
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA3_DESC_PREFETCH_EN_DEFAULT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA3_DESC_PREFETCH_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA3_DESC_PREFETCH_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA3_DESC_PREFETCH_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA3_DESC_PREFETCH_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA3_DESC_PREFETCH_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA2_DESC_PREFETCH_EN_SHIFT                       _MK_SHIFT_CONST(21)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA2_DESC_PREFETCH_EN_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA2_DESC_PREFETCH_EN_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA2_DESC_PREFETCH_EN_RANGE                       21:21
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA2_DESC_PREFETCH_EN_WOFFSET                     0x0
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA2_DESC_PREFETCH_EN_DEFAULT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA2_DESC_PREFETCH_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA2_DESC_PREFETCH_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA2_DESC_PREFETCH_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA2_DESC_PREFETCH_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADMA2_DESC_PREFETCH_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DATA_TIMEOUT_VAL_MULTIPLIER_SHIFT                  _MK_SHIFT_CONST(16)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DATA_TIMEOUT_VAL_MULTIPLIER_FIELD                  _MK_FIELD_CONST(0xf, SDMMCAB_VENDOR_MISC_CNTRL2_0_DATA_TIMEOUT_VAL_MULTIPLIER_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DATA_TIMEOUT_VAL_MULTIPLIER_RANGE                  19:16
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DATA_TIMEOUT_VAL_MULTIPLIER_WOFFSET                        0x0
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DATA_TIMEOUT_VAL_MULTIPLIER_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DATA_TIMEOUT_VAL_MULTIPLIER_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DATA_TIMEOUT_VAL_MULTIPLIER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DATA_TIMEOUT_VAL_MULTIPLIER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DATA_TIMEOUT_VAL_MULTIPLIER_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DATA_TIMEOUT_VAL_MULTIPLIER_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DAT_TUNING_ASYNC_FIFO_ADDNL_DELAY_SHIFT                    _MK_SHIFT_CONST(12)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DAT_TUNING_ASYNC_FIFO_ADDNL_DELAY_FIELD                    _MK_FIELD_CONST(0xf, SDMMCAB_VENDOR_MISC_CNTRL2_0_DAT_TUNING_ASYNC_FIFO_ADDNL_DELAY_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DAT_TUNING_ASYNC_FIFO_ADDNL_DELAY_RANGE                    15:12
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DAT_TUNING_ASYNC_FIFO_ADDNL_DELAY_WOFFSET                  0x0
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DAT_TUNING_ASYNC_FIFO_ADDNL_DELAY_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DAT_TUNING_ASYNC_FIFO_ADDNL_DELAY_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DAT_TUNING_ASYNC_FIFO_ADDNL_DELAY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DAT_TUNING_ASYNC_FIFO_ADDNL_DELAY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DAT_TUNING_ASYNC_FIFO_ADDNL_DELAY_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_DAT_TUNING_ASYNC_FIFO_ADDNL_DELAY_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADDITIONAL_NCR_CYCLES_SHIFT                        _MK_SHIFT_CONST(8)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADDITIONAL_NCR_CYCLES_FIELD                        _MK_FIELD_CONST(0xf, SDMMCAB_VENDOR_MISC_CNTRL2_0_ADDITIONAL_NCR_CYCLES_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADDITIONAL_NCR_CYCLES_RANGE                        11:8
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADDITIONAL_NCR_CYCLES_WOFFSET                      0x0
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADDITIONAL_NCR_CYCLES_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADDITIONAL_NCR_CYCLES_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADDITIONAL_NCR_CYCLES_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADDITIONAL_NCR_CYCLES_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADDITIONAL_NCR_CYCLES_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_ADDITIONAL_NCR_CYCLES_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_MISC_CNTRL2_0_OVERRIDE_FOR_1_8V_VDD2_SHIFT                       _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_OVERRIDE_FOR_1_8V_VDD2_FIELD                       _MK_FIELD_CONST(0xff, SDMMCAB_VENDOR_MISC_CNTRL2_0_OVERRIDE_FOR_1_8V_VDD2_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_OVERRIDE_FOR_1_8V_VDD2_RANGE                       7:0
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_OVERRIDE_FOR_1_8V_VDD2_WOFFSET                     0x0
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_OVERRIDE_FOR_1_8V_VDD2_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_OVERRIDE_FOR_1_8V_VDD2_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_OVERRIDE_FOR_1_8V_VDD2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_OVERRIDE_FOR_1_8V_VDD2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_OVERRIDE_FOR_1_8V_VDD2_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL2_0_OVERRIDE_FOR_1_8V_VDD2_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Reserved address 0x12c

// Reserved address 0x130

// Reserved address 0x134

// Reserved address 0x138

// Reserved address 0x13c

// Reserved address 0x140

// Reserved address 0x144

// Reserved address 0x148

// Reserved address 0x14c

// Reserved address 0x150

// Reserved address 0x154

// Reserved address 0x158

// Reserved address 0x15c

// Reserved address 0x160

// Reserved address 0x164

// Reserved address 0x168

// Reserved address 0x16c

// Reserved address 0x170

// Reserved address 0x174

// Reserved address 0x178

// Reserved address 0x17c

// Reserved address 0x180

// Reserved address 0x184

// Reserved address 0x188

// Reserved address 0x18c

// Reserved address 0x190

// Reserved address 0x194

// Reserved address 0x198

// Reserved address 0x19c

// Reserved address 0x1a0

// Reserved address 0x1a4

// Reserved address 0x1a8

// Register SDMMCAB_VENDOR_IO_TRIM_CNTRL_0
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0                  _MK_ADDR_CONST(0x1ac)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SECURE                   0x0
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_DUAL                     0x0
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SCR                      0
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_WORD_COUNT                       0x1
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_RESET_VAL                        _MK_MASK_CONST(0x15)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_RESET_MASK                       _MK_MASK_CONST(0xf00000ff)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_READ_MASK                        _MK_MASK_CONST(0xf00000ff)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_WRITE_MASK                       _MK_MASK_CONST(0xf00000ff)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_PAD_RFU_IN_SHIFT                    _MK_SHIFT_CONST(28)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_PAD_RFU_IN_FIELD                    _MK_FIELD_CONST(0xf, SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_PAD_RFU_IN_SHIFT)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_PAD_RFU_IN_RANGE                    31:28
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_PAD_RFU_IN_WOFFSET                  0x0
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_PAD_RFU_IN_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_PAD_RFU_IN_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_PAD_RFU_IN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_PAD_RFU_IN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_PAD_RFU_IN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_PAD_RFU_IN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_SEL_ATEST_SHIFT                     _MK_SHIFT_CONST(6)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_SEL_ATEST_FIELD                     _MK_FIELD_CONST(0x3, SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_SEL_ATEST_SHIFT)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_SEL_ATEST_RANGE                     7:6
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_SEL_ATEST_WOFFSET                   0x0
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_SEL_ATEST_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_SEL_ATEST_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_SEL_ATEST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_SEL_ATEST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_SEL_ATEST_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_SEL_ATEST_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_PWRSAVE_SHIFT                       _MK_SHIFT_CONST(5)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_PWRSAVE_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_PWRSAVE_SHIFT)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_PWRSAVE_RANGE                       5:5
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_PWRSAVE_WOFFSET                     0x0
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_PWRSAVE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_PWRSAVE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_PWRSAVE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_PWRSAVE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_PWRSAVE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_PWRSAVE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_PWRSAVE_INIT_ENUM                   ENABLE
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_PWRSAVE_ENABLE                      _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_TRIM_PWRSAVE_DISABLE                     _MK_ENUM_CONST(1)

#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREF_LEVEL_SHIFT                     _MK_SHIFT_CONST(3)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREF_LEVEL_FIELD                     _MK_FIELD_CONST(0x3, SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREF_LEVEL_SHIFT)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREF_LEVEL_RANGE                     4:3
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREF_LEVEL_WOFFSET                   0x0
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREF_LEVEL_DEFAULT                   _MK_MASK_CONST(0x2)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREF_LEVEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREF_LEVEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREF_LEVEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREF_LEVEL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREF_LEVEL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREF_LEVEL_INIT_ENUM                 VREF_825_MV
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREF_LEVEL_VREF_775_MV                       _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREF_LEVEL_VREF_800_MV                       _MK_ENUM_CONST(1)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREF_LEVEL_VREF_825_MV                       _MK_ENUM_CONST(2)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREF_LEVEL_VREF_850_MV                       _MK_ENUM_CONST(3)

#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREG_SHIFT                   _MK_SHIFT_CONST(2)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREG_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREG_SHIFT)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREG_RANGE                   2:2
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREG_WOFFSET                 0x0
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREG_DEFAULT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREG_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREG_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREG_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREG__PROD_C_NOPWRSAVE                       _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREG__PROD_C_PWRSAVE                 _MK_ENUM_CONST(1)

#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREF_SHIFT                   _MK_SHIFT_CONST(1)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREF_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREF_SHIFT)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREF_RANGE                   1:1
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREF_WOFFSET                 0x0
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREF_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREF_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_SEL_VREF_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_PD_BGREG_SHIFT                   _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_PD_BGREG_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_PD_BGREG_SHIFT)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_PD_BGREG_RANGE                   0:0
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_PD_BGREG_WOFFSET                 0x0
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_PD_BGREG_DEFAULT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_PD_BGREG_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_PD_BGREG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_PD_BGREG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_PD_BGREG_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_IO_TRIM_CNTRL_0_PD_BGREG_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register SDMMCAB_VENDOR_DLLCAL_CFG_0
#define SDMMCAB_VENDOR_DLLCAL_CFG_0                     _MK_ADDR_CONST(0x1b0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_SECURE                      0x0
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_DUAL                        0x0
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_SCR                         0
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_WORD_COUNT                  0x1
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_RESET_VAL                   _MK_MASK_CONST(0x16083504)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_RESET_MASK                  _MK_MASK_CONST(0xbfffffff)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_READ_MASK                   _MK_MASK_CONST(0xbfffffff)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_WRITE_MASK                  _MK_MASK_CONST(0xbfffffff)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_CALIBRATE_SHIFT                     _MK_SHIFT_CONST(31)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_CALIBRATE_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_DLLCAL_CFG_0_CALIBRATE_SHIFT)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_CALIBRATE_RANGE                     31:31
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_CALIBRATE_WOFFSET                   0x0
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_CALIBRATE_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_CALIBRATE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_CALIBRATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_CALIBRATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_CALIBRATE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_CALIBRATE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_DLLCAL_CFG_0_END_COUNT_SHIFT                     _MK_SHIFT_CONST(25)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_END_COUNT_FIELD                     _MK_FIELD_CONST(0x1f, SDMMCAB_VENDOR_DLLCAL_CFG_0_END_COUNT_SHIFT)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_END_COUNT_RANGE                     29:25
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_END_COUNT_WOFFSET                   0x0
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_END_COUNT_DEFAULT                   _MK_MASK_CONST(0xb)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_END_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_END_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_END_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_END_COUNT_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_END_COUNT_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_DLLCAL_CFG_0_USE_STATIC_CYCLES_SHIFT                     _MK_SHIFT_CONST(24)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_USE_STATIC_CYCLES_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_DLLCAL_CFG_0_USE_STATIC_CYCLES_SHIFT)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_USE_STATIC_CYCLES_RANGE                     24:24
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_USE_STATIC_CYCLES_WOFFSET                   0x0
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_USE_STATIC_CYCLES_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_USE_STATIC_CYCLES_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_USE_STATIC_CYCLES_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_USE_STATIC_CYCLES_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_USE_STATIC_CYCLES_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_USE_STATIC_CYCLES_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_DLLCAL_CFG_0_IGNORE_START_TRIM_SHIFT                     _MK_SHIFT_CONST(23)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_IGNORE_START_TRIM_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_DLLCAL_CFG_0_IGNORE_START_TRIM_SHIFT)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_IGNORE_START_TRIM_RANGE                     23:23
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_IGNORE_START_TRIM_WOFFSET                   0x0
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_IGNORE_START_TRIM_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_IGNORE_START_TRIM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_IGNORE_START_TRIM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_IGNORE_START_TRIM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_IGNORE_START_TRIM_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_IGNORE_START_TRIM_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_DLLCAL_CFG_0_START_TRIM_SHIFT                    _MK_SHIFT_CONST(16)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_START_TRIM_FIELD                    _MK_FIELD_CONST(0x7f, SDMMCAB_VENDOR_DLLCAL_CFG_0_START_TRIM_SHIFT)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_START_TRIM_RANGE                    22:16
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_START_TRIM_WOFFSET                  0x0
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_START_TRIM_DEFAULT                  _MK_MASK_CONST(0x8)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_START_TRIM_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_START_TRIM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_START_TRIM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_START_TRIM_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_START_TRIM_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_DLLCAL_CFG_0_FILTER_BITS_SHIFT                   _MK_SHIFT_CONST(12)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_FILTER_BITS_FIELD                   _MK_FIELD_CONST(0xf, SDMMCAB_VENDOR_DLLCAL_CFG_0_FILTER_BITS_SHIFT)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_FILTER_BITS_RANGE                   15:12
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_FILTER_BITS_WOFFSET                 0x0
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_FILTER_BITS_DEFAULT                 _MK_MASK_CONST(0x3)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_FILTER_BITS_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_FILTER_BITS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_FILTER_BITS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_FILTER_BITS_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_FILTER_BITS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_DLLCAL_CFG_0_SAMPLE_COUNT_SHIFT                  _MK_SHIFT_CONST(8)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_SAMPLE_COUNT_FIELD                  _MK_FIELD_CONST(0xf, SDMMCAB_VENDOR_DLLCAL_CFG_0_SAMPLE_COUNT_SHIFT)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_SAMPLE_COUNT_RANGE                  11:8
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_SAMPLE_COUNT_WOFFSET                        0x0
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_SAMPLE_COUNT_DEFAULT                        _MK_MASK_CONST(0x5)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_SAMPLE_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_SAMPLE_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_SAMPLE_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_SAMPLE_COUNT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_SAMPLE_COUNT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_DLLCAL_CFG_0_SAMPLE_DELAY_SHIFT                  _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_SAMPLE_DELAY_FIELD                  _MK_FIELD_CONST(0xff, SDMMCAB_VENDOR_DLLCAL_CFG_0_SAMPLE_DELAY_SHIFT)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_SAMPLE_DELAY_RANGE                  7:0
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_SAMPLE_DELAY_WOFFSET                        0x0
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_SAMPLE_DELAY_DEFAULT                        _MK_MASK_CONST(0x4)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_SAMPLE_DELAY_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_SAMPLE_DELAY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_SAMPLE_DELAY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_SAMPLE_DELAY_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_0_SAMPLE_DELAY_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register SDMMCAB_VENDOR_DLL_CTRL0_0
#define SDMMCAB_VENDOR_DLL_CTRL0_0                      _MK_ADDR_CONST(0x1b4)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_SECURE                       0x0
#define SDMMCAB_VENDOR_DLL_CTRL0_0_DUAL                         0x0
#define SDMMCAB_VENDOR_DLL_CTRL0_0_SCR                  0
#define SDMMCAB_VENDOR_DLL_CTRL0_0_WORD_COUNT                   0x1
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RESET_VAL                    _MK_MASK_CONST(0x60000000)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_MST_DLL_CLK_EN_OVERRIDE_SHIFT                        _MK_SHIFT_CONST(31)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_MST_DLL_CLK_EN_OVERRIDE_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_DLL_CTRL0_0_MST_DLL_CLK_EN_OVERRIDE_SHIFT)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_MST_DLL_CLK_EN_OVERRIDE_RANGE                        31:31
#define SDMMCAB_VENDOR_DLL_CTRL0_0_MST_DLL_CLK_EN_OVERRIDE_WOFFSET                      0x0
#define SDMMCAB_VENDOR_DLL_CTRL0_0_MST_DLL_CLK_EN_OVERRIDE_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_MST_DLL_CLK_EN_OVERRIDE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_MST_DLL_CLK_EN_OVERRIDE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_MST_DLL_CLK_EN_OVERRIDE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_MST_DLL_CLK_EN_OVERRIDE_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_MST_DLL_CLK_EN_OVERRIDE_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_MST_DLL_CLK_EN_OVERRIDE_NORMAL                       _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_MST_DLL_CLK_EN_OVERRIDE_OVERRIDE                     _MK_ENUM_CONST(1)

#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_SLV_DLL_PWRSAVE_SHIFT                     _MK_SHIFT_CONST(30)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_SLV_DLL_PWRSAVE_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_DLL_CTRL0_0_TX_SLV_DLL_PWRSAVE_SHIFT)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_SLV_DLL_PWRSAVE_RANGE                     30:30
#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_SLV_DLL_PWRSAVE_WOFFSET                   0x0
#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_SLV_DLL_PWRSAVE_DEFAULT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_SLV_DLL_PWRSAVE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_SLV_DLL_PWRSAVE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_SLV_DLL_PWRSAVE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_SLV_DLL_PWRSAVE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_SLV_DLL_PWRSAVE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_SLV_DLL_PWRSAVE_SHIFT                     _MK_SHIFT_CONST(29)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_SLV_DLL_PWRSAVE_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_DLL_CTRL0_0_RX_SLV_DLL_PWRSAVE_SHIFT)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_SLV_DLL_PWRSAVE_RANGE                     29:29
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_SLV_DLL_PWRSAVE_WOFFSET                   0x0
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_SLV_DLL_PWRSAVE_DEFAULT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_SLV_DLL_PWRSAVE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_SLV_DLL_PWRSAVE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_SLV_DLL_PWRSAVE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_SLV_DLL_PWRSAVE_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_SLV_DLL_PWRSAVE_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_SLV_DLL_DLY_CODE_SHIFT                    _MK_SHIFT_CONST(22)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_SLV_DLL_DLY_CODE_FIELD                    _MK_FIELD_CONST(0x7f, SDMMCAB_VENDOR_DLL_CTRL0_0_TX_SLV_DLL_DLY_CODE_SHIFT)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_SLV_DLL_DLY_CODE_RANGE                    28:22
#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_SLV_DLL_DLY_CODE_WOFFSET                  0x0
#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_SLV_DLL_DLY_CODE_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_SLV_DLL_DLY_CODE_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_SLV_DLL_DLY_CODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_SLV_DLL_DLY_CODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_SLV_DLL_DLY_CODE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_SLV_DLL_DLY_CODE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_SLV_DLL_DLY_CODE_SHIFT                    _MK_SHIFT_CONST(15)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_SLV_DLL_DLY_CODE_FIELD                    _MK_FIELD_CONST(0x7f, SDMMCAB_VENDOR_DLL_CTRL0_0_RX_SLV_DLL_DLY_CODE_SHIFT)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_SLV_DLL_DLY_CODE_RANGE                    21:15
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_SLV_DLL_DLY_CODE_WOFFSET                  0x0
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_SLV_DLL_DLY_CODE_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_SLV_DLL_DLY_CODE_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_SLV_DLL_DLY_CODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_SLV_DLL_DLY_CODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_SLV_DLL_DLY_CODE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_SLV_DLL_DLY_CODE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_DLL_CTRL0_0_DLLCAL_BYPASS_SHIFT                  _MK_SHIFT_CONST(14)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_DLLCAL_BYPASS_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_DLL_CTRL0_0_DLLCAL_BYPASS_SHIFT)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_DLLCAL_BYPASS_RANGE                  14:14
#define SDMMCAB_VENDOR_DLL_CTRL0_0_DLLCAL_BYPASS_WOFFSET                        0x0
#define SDMMCAB_VENDOR_DLL_CTRL0_0_DLLCAL_BYPASS_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_DLLCAL_BYPASS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_DLLCAL_BYPASS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_DLLCAL_BYPASS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_DLLCAL_BYPASS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_DLLCAL_BYPASS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_DLLCAL_BYPASS_INIT_ENUM                      DISABLED
#define SDMMCAB_VENDOR_DLL_CTRL0_0_DLLCAL_BYPASS_DISABLED                       _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_DLLCAL_BYPASS_ENABLED                        _MK_ENUM_CONST(1)

#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_DLY_CODE_OFFSET_SHIFT                     _MK_SHIFT_CONST(7)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_DLY_CODE_OFFSET_FIELD                     _MK_FIELD_CONST(0x7f, SDMMCAB_VENDOR_DLL_CTRL0_0_TX_DLY_CODE_OFFSET_SHIFT)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_DLY_CODE_OFFSET_RANGE                     13:7
#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_DLY_CODE_OFFSET_WOFFSET                   0x0
#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_DLY_CODE_OFFSET_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_DLY_CODE_OFFSET_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_DLY_CODE_OFFSET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_DLY_CODE_OFFSET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_DLY_CODE_OFFSET_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_TX_DLY_CODE_OFFSET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_DLY_CODE_OFFSET_SHIFT                     _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_DLY_CODE_OFFSET_FIELD                     _MK_FIELD_CONST(0x7f, SDMMCAB_VENDOR_DLL_CTRL0_0_RX_DLY_CODE_OFFSET_SHIFT)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_DLY_CODE_OFFSET_RANGE                     6:0
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_DLY_CODE_OFFSET_WOFFSET                   0x0
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_DLY_CODE_OFFSET_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_DLY_CODE_OFFSET_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_DLY_CODE_OFFSET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_DLY_CODE_OFFSET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_DLY_CODE_OFFSET_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL0_0_RX_DLY_CODE_OFFSET_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register SDMMCAB_VENDOR_DLL_CTRL1_0
#define SDMMCAB_VENDOR_DLL_CTRL1_0                      _MK_ADDR_CONST(0x1b8)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_SECURE                       0x0
#define SDMMCAB_VENDOR_DLL_CTRL1_0_DUAL                         0x0
#define SDMMCAB_VENDOR_DLL_CTRL1_0_SCR                  0
#define SDMMCAB_VENDOR_DLL_CTRL1_0_WORD_COUNT                   0x1
#define SDMMCAB_VENDOR_DLL_CTRL1_0_RESET_VAL                    _MK_MASK_CONST(0x20208780)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_RESET_MASK                   _MK_MASK_CONST(0x7f7fffff)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_READ_MASK                    _MK_MASK_CONST(0x7f7fffff)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_WRITE_MASK                   _MK_MASK_CONST(0x7f7fffff)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_REQD_DELAY_STEPS_TX_SHIFT                    _MK_SHIFT_CONST(24)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_REQD_DELAY_STEPS_TX_FIELD                    _MK_FIELD_CONST(0x7f, SDMMCAB_VENDOR_DLL_CTRL1_0_REQD_DELAY_STEPS_TX_SHIFT)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_REQD_DELAY_STEPS_TX_RANGE                    30:24
#define SDMMCAB_VENDOR_DLL_CTRL1_0_REQD_DELAY_STEPS_TX_WOFFSET                  0x0
#define SDMMCAB_VENDOR_DLL_CTRL1_0_REQD_DELAY_STEPS_TX_DEFAULT                  _MK_MASK_CONST(0x20)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_REQD_DELAY_STEPS_TX_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_REQD_DELAY_STEPS_TX_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_REQD_DELAY_STEPS_TX_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_REQD_DELAY_STEPS_TX_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_REQD_DELAY_STEPS_TX_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_DLL_CTRL1_0_REQD_DELAY_STEPS_RX_SHIFT                    _MK_SHIFT_CONST(16)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_REQD_DELAY_STEPS_RX_FIELD                    _MK_FIELD_CONST(0x7f, SDMMCAB_VENDOR_DLL_CTRL1_0_REQD_DELAY_STEPS_RX_SHIFT)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_REQD_DELAY_STEPS_RX_RANGE                    22:16
#define SDMMCAB_VENDOR_DLL_CTRL1_0_REQD_DELAY_STEPS_RX_WOFFSET                  0x0
#define SDMMCAB_VENDOR_DLL_CTRL1_0_REQD_DELAY_STEPS_RX_DEFAULT                  _MK_MASK_CONST(0x20)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_REQD_DELAY_STEPS_RX_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_REQD_DELAY_STEPS_RX_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_REQD_DELAY_STEPS_RX_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_REQD_DELAY_STEPS_RX_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_REQD_DELAY_STEPS_RX_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_DLL_CTRL1_0_MST_DLL_RESET_TIME_SHIFT                     _MK_SHIFT_CONST(11)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_MST_DLL_RESET_TIME_FIELD                     _MK_FIELD_CONST(0x1f, SDMMCAB_VENDOR_DLL_CTRL1_0_MST_DLL_RESET_TIME_SHIFT)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_MST_DLL_RESET_TIME_RANGE                     15:11
#define SDMMCAB_VENDOR_DLL_CTRL1_0_MST_DLL_RESET_TIME_WOFFSET                   0x0
#define SDMMCAB_VENDOR_DLL_CTRL1_0_MST_DLL_RESET_TIME_DEFAULT                   _MK_MASK_CONST(0x10)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_MST_DLL_RESET_TIME_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_MST_DLL_RESET_TIME_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_MST_DLL_RESET_TIME_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_MST_DLL_RESET_TIME_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_MST_DLL_RESET_TIME_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_DLL_CTRL1_0_SLV_DLL_SETTLE_TIME_SHIFT                    _MK_SHIFT_CONST(7)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_SLV_DLL_SETTLE_TIME_FIELD                    _MK_FIELD_CONST(0xf, SDMMCAB_VENDOR_DLL_CTRL1_0_SLV_DLL_SETTLE_TIME_SHIFT)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_SLV_DLL_SETTLE_TIME_RANGE                    10:7
#define SDMMCAB_VENDOR_DLL_CTRL1_0_SLV_DLL_SETTLE_TIME_WOFFSET                  0x0
#define SDMMCAB_VENDOR_DLL_CTRL1_0_SLV_DLL_SETTLE_TIME_DEFAULT                  _MK_MASK_CONST(0xf)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_SLV_DLL_SETTLE_TIME_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_SLV_DLL_SETTLE_TIME_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_SLV_DLL_SETTLE_TIME_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_SLV_DLL_SETTLE_TIME_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_SLV_DLL_SETTLE_TIME_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_DLL_CTRL1_0_MST_DLL_DLY_CODE_SHIFT                       _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_MST_DLL_DLY_CODE_FIELD                       _MK_FIELD_CONST(0x7f, SDMMCAB_VENDOR_DLL_CTRL1_0_MST_DLL_DLY_CODE_SHIFT)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_MST_DLL_DLY_CODE_RANGE                       6:0
#define SDMMCAB_VENDOR_DLL_CTRL1_0_MST_DLL_DLY_CODE_WOFFSET                     0x0
#define SDMMCAB_VENDOR_DLL_CTRL1_0_MST_DLL_DLY_CODE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_MST_DLL_DLY_CODE_DEFAULT_MASK                        _MK_MASK_CONST(0x7f)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_MST_DLL_DLY_CODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_MST_DLL_DLY_CODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_MST_DLL_DLY_CODE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLL_CTRL1_0_MST_DLL_DLY_CODE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register SDMMCAB_VENDOR_DLLCAL_CFG_STA_0
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0                 _MK_ADDR_CONST(0x1bc)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_SECURE                  0x0
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DUAL                    0x0
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_SCR                     0
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_WORD_COUNT                      0x1
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_RESET_VAL                       _MK_MASK_CONST(0x10000000)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_RESET_MASK                      _MK_MASK_CONST(0xff7f7f7f)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_READ_MASK                       _MK_MASK_CONST(0xff7f7f7f)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_WRITE_MASK                      _MK_MASK_CONST(0x3f000000)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLL_CAL_ACTIVE_SHIFT                    _MK_SHIFT_CONST(31)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLL_CAL_ACTIVE_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLL_CAL_ACTIVE_SHIFT)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLL_CAL_ACTIVE_RANGE                    31:31
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLL_CAL_ACTIVE_WOFFSET                  0x0
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLL_CAL_ACTIVE_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLL_CAL_ACTIVE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLL_CAL_ACTIVE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLL_CAL_ACTIVE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLL_CAL_ACTIVE_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLL_CAL_ACTIVE_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLL_CAL_ACTIVE_INIT_ENUM                        DONE
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLL_CAL_ACTIVE_DONE                     _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLL_CAL_ACTIVE_RUNNING                  _MK_ENUM_CONST(1)

#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLL_PD_SHIFT                    _MK_SHIFT_CONST(30)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLL_PD_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLL_PD_SHIFT)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLL_PD_RANGE                    30:30
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLL_PD_WOFFSET                  0x0
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLL_PD_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLL_PD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLL_PD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLL_PD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLL_PD_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLL_PD_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_RST_OVERRIDE_EN_SHIFT                   _MK_SHIFT_CONST(29)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_RST_OVERRIDE_EN_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_RST_OVERRIDE_EN_SHIFT)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_RST_OVERRIDE_EN_RANGE                   29:29
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_RST_OVERRIDE_EN_WOFFSET                 0x0
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_RST_OVERRIDE_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_RST_OVERRIDE_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_RST_OVERRIDE_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_RST_OVERRIDE_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_RST_OVERRIDE_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_RST_OVERRIDE_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_RST__SHIFT                      _MK_SHIFT_CONST(28)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_RST__FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_RST__SHIFT)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_RST__RANGE                      28:28
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_RST__WOFFSET                    0x0
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_RST__DEFAULT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_RST__DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_RST__SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_RST__SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_RST__PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_RST__PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_SLV_DLL_CLK_OUT_DIS_OVERRIDE_EN_SHIFT                   _MK_SHIFT_CONST(27)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_SLV_DLL_CLK_OUT_DIS_OVERRIDE_EN_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_SLV_DLL_CLK_OUT_DIS_OVERRIDE_EN_SHIFT)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_SLV_DLL_CLK_OUT_DIS_OVERRIDE_EN_RANGE                   27:27
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_SLV_DLL_CLK_OUT_DIS_OVERRIDE_EN_WOFFSET                 0x0
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_SLV_DLL_CLK_OUT_DIS_OVERRIDE_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_SLV_DLL_CLK_OUT_DIS_OVERRIDE_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_SLV_DLL_CLK_OUT_DIS_OVERRIDE_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_SLV_DLL_CLK_OUT_DIS_OVERRIDE_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_SLV_DLL_CLK_OUT_DIS_OVERRIDE_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_SLV_DLL_CLK_OUT_DIS_OVERRIDE_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_SLV_DLL_CLK_OUT_DIS_SHIFT                       _MK_SHIFT_CONST(26)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_SLV_DLL_CLK_OUT_DIS_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_SLV_DLL_CLK_OUT_DIS_SHIFT)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_SLV_DLL_CLK_OUT_DIS_RANGE                       26:26
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_SLV_DLL_CLK_OUT_DIS_WOFFSET                     0x0
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_SLV_DLL_CLK_OUT_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_SLV_DLL_CLK_OUT_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_SLV_DLL_CLK_OUT_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_SLV_DLL_CLK_OUT_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_SLV_DLL_CLK_OUT_DIS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_SLV_DLL_CLK_OUT_DIS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_PWRDN_OVERRIDE_EN_SHIFT                 _MK_SHIFT_CONST(25)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_PWRDN_OVERRIDE_EN_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_PWRDN_OVERRIDE_EN_SHIFT)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_PWRDN_OVERRIDE_EN_RANGE                 25:25
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_PWRDN_OVERRIDE_EN_WOFFSET                       0x0
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_PWRDN_OVERRIDE_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_PWRDN_OVERRIDE_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_PWRDN_OVERRIDE_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_PWRDN_OVERRIDE_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_PWRDN_OVERRIDE_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_PWRDN_OVERRIDE_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_PWRDN_SHIFT                     _MK_SHIFT_CONST(24)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_PWRDN_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_PWRDN_SHIFT)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_PWRDN_RANGE                     24:24
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_PWRDN_WOFFSET                   0x0
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_PWRDN_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_PWRDN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_PWRDN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_PWRDN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_PWRDN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_MST_DLL_PWRDN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_TX_DLY_CODE_ADJ_SHIFT                   _MK_SHIFT_CONST(16)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_TX_DLY_CODE_ADJ_FIELD                   _MK_FIELD_CONST(0x7f, SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_TX_DLY_CODE_ADJ_SHIFT)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_TX_DLY_CODE_ADJ_RANGE                   22:16
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_TX_DLY_CODE_ADJ_WOFFSET                 0x0
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_TX_DLY_CODE_ADJ_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_TX_DLY_CODE_ADJ_DEFAULT_MASK                    _MK_MASK_CONST(0x7f)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_TX_DLY_CODE_ADJ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_TX_DLY_CODE_ADJ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_TX_DLY_CODE_ADJ_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_TX_DLY_CODE_ADJ_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_RX_DLY_CODE_ADJ_SHIFT                   _MK_SHIFT_CONST(8)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_RX_DLY_CODE_ADJ_FIELD                   _MK_FIELD_CONST(0x7f, SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_RX_DLY_CODE_ADJ_SHIFT)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_RX_DLY_CODE_ADJ_RANGE                   14:8
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_RX_DLY_CODE_ADJ_WOFFSET                 0x0
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_RX_DLY_CODE_ADJ_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_RX_DLY_CODE_ADJ_DEFAULT_MASK                    _MK_MASK_CONST(0x7f)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_RX_DLY_CODE_ADJ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_RX_DLY_CODE_ADJ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_RX_DLY_CODE_ADJ_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_RX_DLY_CODE_ADJ_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLY_CODE_SHIFT                  _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLY_CODE_FIELD                  _MK_FIELD_CONST(0x7f, SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLY_CODE_SHIFT)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLY_CODE_RANGE                  6:0
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLY_CODE_WOFFSET                        0x0
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLY_CODE_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLY_CODE_DEFAULT_MASK                   _MK_MASK_CONST(0x7f)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLY_CODE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLY_CODE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLY_CODE_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_DLLCAL_CFG_STA_0_DLY_CODE_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register SDMMCAB_VENDOR_TUNING_CNTRL0_0
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0                  _MK_ADDR_CONST(0x1c0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_SECURE                   0x0
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_DUAL                     0x0
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_SCR                      0
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_WORD_COUNT                       0x1
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_RESET_VAL                        _MK_MASK_CONST(0x74020090)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_RESET_MASK                       _MK_MASK_CONST(0x7ffeffff)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_READ_MASK                        _MK_MASK_CONST(0x7ffeffff)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_WRITE_MASK                       _MK_MASK_CONST(0x7ffeffff)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_RD_DATA_CRC_ERR_EN_SHIFT                 _MK_SHIFT_CONST(30)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_RD_DATA_CRC_ERR_EN_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_TUNING_CNTRL0_0_RD_DATA_CRC_ERR_EN_SHIFT)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_RD_DATA_CRC_ERR_EN_RANGE                 30:30
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_RD_DATA_CRC_ERR_EN_WOFFSET                       0x0
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_RD_DATA_CRC_ERR_EN_DEFAULT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_RD_DATA_CRC_ERR_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_RD_DATA_CRC_ERR_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_RD_DATA_CRC_ERR_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_RD_DATA_CRC_ERR_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_RD_DATA_CRC_ERR_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_WR_DATA_CRC_ERR_EN_SHIFT                 _MK_SHIFT_CONST(29)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_WR_DATA_CRC_ERR_EN_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_TUNING_CNTRL0_0_WR_DATA_CRC_ERR_EN_SHIFT)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_WR_DATA_CRC_ERR_EN_RANGE                 29:29
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_WR_DATA_CRC_ERR_EN_WOFFSET                       0x0
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_WR_DATA_CRC_ERR_EN_DEFAULT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_WR_DATA_CRC_ERR_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_WR_DATA_CRC_ERR_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_WR_DATA_CRC_ERR_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_WR_DATA_CRC_ERR_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_WR_DATA_CRC_ERR_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_CMD_CRC_ERR_EN_SHIFT                     _MK_SHIFT_CONST(28)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_CMD_CRC_ERR_EN_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_TUNING_CNTRL0_0_CMD_CRC_ERR_EN_SHIFT)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_CMD_CRC_ERR_EN_RANGE                     28:28
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_CMD_CRC_ERR_EN_WOFFSET                   0x0
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_CMD_CRC_ERR_EN_DEFAULT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_CMD_CRC_ERR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_CMD_CRC_ERR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_CMD_CRC_ERR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_CMD_CRC_ERR_EN_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_CMD_CRC_ERR_EN_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_RETUNING_REQ_EN_ON_CRC_ERR_DETECTION_SHIFT                       _MK_SHIFT_CONST(27)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_RETUNING_REQ_EN_ON_CRC_ERR_DETECTION_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_TUNING_CNTRL0_0_RETUNING_REQ_EN_ON_CRC_ERR_DETECTION_SHIFT)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_RETUNING_REQ_EN_ON_CRC_ERR_DETECTION_RANGE                       27:27
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_RETUNING_REQ_EN_ON_CRC_ERR_DETECTION_WOFFSET                     0x0
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_RETUNING_REQ_EN_ON_CRC_ERR_DETECTION_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_RETUNING_REQ_EN_ON_CRC_ERR_DETECTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_RETUNING_REQ_EN_ON_CRC_ERR_DETECTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_RETUNING_REQ_EN_ON_CRC_ERR_DETECTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_RETUNING_REQ_EN_ON_CRC_ERR_DETECTION_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_RETUNING_REQ_EN_ON_CRC_ERR_DETECTION_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TUNING_ERR_EN_ON_CRC_ERR_DETECTION_SHIFT                 _MK_SHIFT_CONST(26)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TUNING_ERR_EN_ON_CRC_ERR_DETECTION_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_TUNING_CNTRL0_0_TUNING_ERR_EN_ON_CRC_ERR_DETECTION_SHIFT)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TUNING_ERR_EN_ON_CRC_ERR_DETECTION_RANGE                 26:26
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TUNING_ERR_EN_ON_CRC_ERR_DETECTION_WOFFSET                       0x0
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TUNING_ERR_EN_ON_CRC_ERR_DETECTION_DEFAULT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TUNING_ERR_EN_ON_CRC_ERR_DETECTION_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TUNING_ERR_EN_ON_CRC_ERR_DETECTION_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TUNING_ERR_EN_ON_CRC_ERR_DETECTION_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TUNING_ERR_EN_ON_CRC_ERR_DETECTION_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TUNING_ERR_EN_ON_CRC_ERR_DETECTION_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_START_TAP_VAL_SHIFT                      _MK_SHIFT_CONST(18)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_START_TAP_VAL_FIELD                      _MK_FIELD_CONST(0xff, SDMMCAB_VENDOR_TUNING_CNTRL0_0_START_TAP_VAL_SHIFT)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_START_TAP_VAL_RANGE                      25:18
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_START_TAP_VAL_WOFFSET                    0x0
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_START_TAP_VAL_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_START_TAP_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_START_TAP_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_START_TAP_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_START_TAP_VAL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_START_TAP_VAL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TAP_VAL_UPDATED_BY_HW_SHIFT                      _MK_SHIFT_CONST(17)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TAP_VAL_UPDATED_BY_HW_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_TUNING_CNTRL0_0_TAP_VAL_UPDATED_BY_HW_SHIFT)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TAP_VAL_UPDATED_BY_HW_RANGE                      17:17
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TAP_VAL_UPDATED_BY_HW_WOFFSET                    0x0
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TAP_VAL_UPDATED_BY_HW_DEFAULT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TAP_VAL_UPDATED_BY_HW_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TAP_VAL_UPDATED_BY_HW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TAP_VAL_UPDATED_BY_HW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TAP_VAL_UPDATED_BY_HW_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TAP_VAL_UPDATED_BY_HW_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_NUM_TUNING_ITERATIONS_SHIFT                      _MK_SHIFT_CONST(13)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_NUM_TUNING_ITERATIONS_FIELD                      _MK_FIELD_CONST(0x7, SDMMCAB_VENDOR_TUNING_CNTRL0_0_NUM_TUNING_ITERATIONS_SHIFT)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_NUM_TUNING_ITERATIONS_RANGE                      15:13
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_NUM_TUNING_ITERATIONS_WOFFSET                    0x0
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_NUM_TUNING_ITERATIONS_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_NUM_TUNING_ITERATIONS_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_NUM_TUNING_ITERATIONS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_NUM_TUNING_ITERATIONS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_NUM_TUNING_ITERATIONS_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_NUM_TUNING_ITERATIONS_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_NUM_TUNING_ITERATIONS_INIT_ENUM                  TRIES_40
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_NUM_TUNING_ITERATIONS_TRIES_40                   _MK_ENUM_CONST(0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_NUM_TUNING_ITERATIONS_TRIES_64                   _MK_ENUM_CONST(1)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_NUM_TUNING_ITERATIONS_TRIES_128                  _MK_ENUM_CONST(2)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_NUM_TUNING_ITERATIONS_TRIES_192                  _MK_ENUM_CONST(3)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_NUM_TUNING_ITERATIONS_TRIES_256                  _MK_ENUM_CONST(4)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_NUM_TUNING_ITERATIONS__PROD_C_HS200                      _MK_ENUM_CONST(2)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_NUM_TUNING_ITERATIONS__PROD_C_HS400                      _MK_ENUM_CONST(2)

#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_MUL_M_SHIFT                      _MK_SHIFT_CONST(6)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_MUL_M_FIELD                      _MK_FIELD_CONST(0x7f, SDMMCAB_VENDOR_TUNING_CNTRL0_0_MUL_M_SHIFT)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_MUL_M_RANGE                      12:6
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_MUL_M_WOFFSET                    0x0
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_MUL_M_DEFAULT                    _MK_MASK_CONST(0x2)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_MUL_M_DEFAULT_MASK                       _MK_MASK_CONST(0x7f)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_MUL_M_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_MUL_M_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_MUL_M_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_MUL_M_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_MUL_M__PROD                      _MK_ENUM_CONST(1)

#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_DIV_N_SHIFT                      _MK_SHIFT_CONST(3)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_DIV_N_FIELD                      _MK_FIELD_CONST(0x7, SDMMCAB_VENDOR_TUNING_CNTRL0_0_DIV_N_SHIFT)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_DIV_N_RANGE                      5:3
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_DIV_N_WOFFSET                    0x0
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_DIV_N_DEFAULT                    _MK_MASK_CONST(0x2)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_DIV_N_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_DIV_N_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_DIV_N_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_DIV_N_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_DIV_N_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TUNING_WORD_SEL_SHIFT                    _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TUNING_WORD_SEL_FIELD                    _MK_FIELD_CONST(0x7, SDMMCAB_VENDOR_TUNING_CNTRL0_0_TUNING_WORD_SEL_SHIFT)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TUNING_WORD_SEL_RANGE                    2:0
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TUNING_WORD_SEL_WOFFSET                  0x0
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TUNING_WORD_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TUNING_WORD_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TUNING_WORD_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TUNING_WORD_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TUNING_WORD_SEL_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL0_0_TUNING_WORD_SEL_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register SDMMCAB_VENDOR_TUNING_CNTRL1_0
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0                  _MK_ADDR_CONST(0x1c4)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_SECURE                   0x0
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_DUAL                     0x0
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_SCR                      0
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_WORD_COUNT                       0x1
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_RESET_VAL                        _MK_MASK_CONST(0x400)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_RESET_MASK                       _MK_MASK_CONST(0x3ff77)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_READ_MASK                        _MK_MASK_CONST(0x3ff77)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_WRITE_MASK                       _MK_MASK_CONST(0x3ff77)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_FIRST_PASS_WINDOW_SEL_SHIFT                      _MK_SHIFT_CONST(17)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_FIRST_PASS_WINDOW_SEL_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_TUNING_CNTRL1_0_FIRST_PASS_WINDOW_SEL_SHIFT)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_FIRST_PASS_WINDOW_SEL_RANGE                      17:17
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_FIRST_PASS_WINDOW_SEL_WOFFSET                    0x0
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_FIRST_PASS_WINDOW_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_FIRST_PASS_WINDOW_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_FIRST_PASS_WINDOW_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_FIRST_PASS_WINDOW_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_FIRST_PASS_WINDOW_SEL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_FIRST_PASS_WINDOW_SEL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_FALSE_PASS_MASK_SHIFT                    _MK_SHIFT_CONST(16)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_FALSE_PASS_MASK_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_TUNING_CNTRL1_0_FALSE_PASS_MASK_SHIFT)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_FALSE_PASS_MASK_RANGE                    16:16
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_FALSE_PASS_MASK_WOFFSET                  0x0
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_FALSE_PASS_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_FALSE_PASS_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_FALSE_PASS_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_FALSE_PASS_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_FALSE_PASS_MASK_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_FALSE_PASS_MASK_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_MIN_PASS_WINDOW_WIDTH_SHIFT                      _MK_SHIFT_CONST(8)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_MIN_PASS_WINDOW_WIDTH_FIELD                      _MK_FIELD_CONST(0xff, SDMMCAB_VENDOR_TUNING_CNTRL1_0_MIN_PASS_WINDOW_WIDTH_SHIFT)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_MIN_PASS_WINDOW_WIDTH_RANGE                      15:8
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_MIN_PASS_WINDOW_WIDTH_WOFFSET                    0x0
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_MIN_PASS_WINDOW_WIDTH_DEFAULT                    _MK_MASK_CONST(0x4)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_MIN_PASS_WINDOW_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_MIN_PASS_WINDOW_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_MIN_PASS_WINDOW_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_MIN_PASS_WINDOW_WIDTH_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_MIN_PASS_WINDOW_WIDTH_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_STEP_SIZE_SDR104_HS200_SHIFT                     _MK_SHIFT_CONST(4)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_STEP_SIZE_SDR104_HS200_FIELD                     _MK_FIELD_CONST(0x7, SDMMCAB_VENDOR_TUNING_CNTRL1_0_STEP_SIZE_SDR104_HS200_SHIFT)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_STEP_SIZE_SDR104_HS200_RANGE                     6:4
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_STEP_SIZE_SDR104_HS200_WOFFSET                   0x0
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_STEP_SIZE_SDR104_HS200_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_STEP_SIZE_SDR104_HS200_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_STEP_SIZE_SDR104_HS200_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_STEP_SIZE_SDR104_HS200_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_STEP_SIZE_SDR104_HS200_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_STEP_SIZE_SDR104_HS200_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_STEP_SIZE_SDR50_SHIFT                    _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_STEP_SIZE_SDR50_FIELD                    _MK_FIELD_CONST(0x7, SDMMCAB_VENDOR_TUNING_CNTRL1_0_STEP_SIZE_SDR50_SHIFT)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_STEP_SIZE_SDR50_RANGE                    2:0
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_STEP_SIZE_SDR50_WOFFSET                  0x0
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_STEP_SIZE_SDR50_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_STEP_SIZE_SDR50_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_STEP_SIZE_SDR50_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_STEP_SIZE_SDR50_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_STEP_SIZE_SDR50_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_CNTRL1_0_STEP_SIZE_SDR50_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register SDMMCAB_VENDOR_TUNING_STATUS0_0
#define SDMMCAB_VENDOR_TUNING_STATUS0_0                 _MK_ADDR_CONST(0x1c8)
#define SDMMCAB_VENDOR_TUNING_STATUS0_0_SECURE                  0x0
#define SDMMCAB_VENDOR_TUNING_STATUS0_0_DUAL                    0x0
#define SDMMCAB_VENDOR_TUNING_STATUS0_0_SCR                     0
#define SDMMCAB_VENDOR_TUNING_STATUS0_0_WORD_COUNT                      0x1
#define SDMMCAB_VENDOR_TUNING_STATUS0_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_VENDOR_TUNING_STATUS0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_VENDOR_TUNING_STATUS0_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS0_0_STATUS_WORD_SHIFT                       _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_TUNING_STATUS0_0_STATUS_WORD_FIELD                       _MK_FIELD_CONST(0xffffffff, SDMMCAB_VENDOR_TUNING_STATUS0_0_STATUS_WORD_SHIFT)
#define SDMMCAB_VENDOR_TUNING_STATUS0_0_STATUS_WORD_RANGE                       31:0
#define SDMMCAB_VENDOR_TUNING_STATUS0_0_STATUS_WORD_WOFFSET                     0x0
#define SDMMCAB_VENDOR_TUNING_STATUS0_0_STATUS_WORD_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS0_0_STATUS_WORD_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_VENDOR_TUNING_STATUS0_0_STATUS_WORD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS0_0_STATUS_WORD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS0_0_STATUS_WORD_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS0_0_STATUS_WORD_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register SDMMCAB_VENDOR_TUNING_STATUS1_0
#define SDMMCAB_VENDOR_TUNING_STATUS1_0                 _MK_ADDR_CONST(0x1cc)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_SECURE                  0x0
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_DUAL                    0x0
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_SCR                     0
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_WORD_COUNT                      0x1
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_END_BEFORE_FINE_TUNING_SHIFT                        _MK_SHIFT_CONST(24)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_END_BEFORE_FINE_TUNING_FIELD                        _MK_FIELD_CONST(0xff, SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_END_BEFORE_FINE_TUNING_SHIFT)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_END_BEFORE_FINE_TUNING_RANGE                        31:24
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_END_BEFORE_FINE_TUNING_WOFFSET                      0x0
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_END_BEFORE_FINE_TUNING_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_END_BEFORE_FINE_TUNING_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_END_BEFORE_FINE_TUNING_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_END_BEFORE_FINE_TUNING_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_END_BEFORE_FINE_TUNING_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_END_BEFORE_FINE_TUNING_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_START_BEFORE_FINE_TUNING_SHIFT                      _MK_SHIFT_CONST(16)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_START_BEFORE_FINE_TUNING_FIELD                      _MK_FIELD_CONST(0xff, SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_START_BEFORE_FINE_TUNING_SHIFT)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_START_BEFORE_FINE_TUNING_RANGE                      23:16
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_START_BEFORE_FINE_TUNING_WOFFSET                    0x0
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_START_BEFORE_FINE_TUNING_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_START_BEFORE_FINE_TUNING_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_START_BEFORE_FINE_TUNING_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_START_BEFORE_FINE_TUNING_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_START_BEFORE_FINE_TUNING_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_START_BEFORE_FINE_TUNING_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_END_AFTER_FINE_TUNING_SHIFT                 _MK_SHIFT_CONST(8)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_END_AFTER_FINE_TUNING_FIELD                 _MK_FIELD_CONST(0xff, SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_END_AFTER_FINE_TUNING_SHIFT)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_END_AFTER_FINE_TUNING_RANGE                 15:8
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_END_AFTER_FINE_TUNING_WOFFSET                       0x0
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_END_AFTER_FINE_TUNING_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_END_AFTER_FINE_TUNING_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_END_AFTER_FINE_TUNING_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_END_AFTER_FINE_TUNING_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_END_AFTER_FINE_TUNING_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_END_AFTER_FINE_TUNING_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_START_AFTER_FINE_TUNING_SHIFT                       _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_START_AFTER_FINE_TUNING_FIELD                       _MK_FIELD_CONST(0xff, SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_START_AFTER_FINE_TUNING_SHIFT)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_START_AFTER_FINE_TUNING_RANGE                       7:0
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_START_AFTER_FINE_TUNING_WOFFSET                     0x0
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_START_AFTER_FINE_TUNING_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_START_AFTER_FINE_TUNING_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_START_AFTER_FINE_TUNING_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_START_AFTER_FINE_TUNING_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_START_AFTER_FINE_TUNING_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_TUNING_STATUS1_0_PASS_WINDOW_START_AFTER_FINE_TUNING_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register SDMMCAB_VENDOR_CLK_GATE_HYSTERESIS_COUNT_0
#define SDMMCAB_VENDOR_CLK_GATE_HYSTERESIS_COUNT_0                      _MK_ADDR_CONST(0x1d0)
#define SDMMCAB_VENDOR_CLK_GATE_HYSTERESIS_COUNT_0_SECURE                       0x0
#define SDMMCAB_VENDOR_CLK_GATE_HYSTERESIS_COUNT_0_DUAL                         0x0
#define SDMMCAB_VENDOR_CLK_GATE_HYSTERESIS_COUNT_0_SCR                  0
#define SDMMCAB_VENDOR_CLK_GATE_HYSTERESIS_COUNT_0_WORD_COUNT                   0x1
#define SDMMCAB_VENDOR_CLK_GATE_HYSTERESIS_COUNT_0_RESET_VAL                    _MK_MASK_CONST(0xf)
#define SDMMCAB_VENDOR_CLK_GATE_HYSTERESIS_COUNT_0_RESET_MASK                   _MK_MASK_CONST(0x3f)
#define SDMMCAB_VENDOR_CLK_GATE_HYSTERESIS_COUNT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLK_GATE_HYSTERESIS_COUNT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLK_GATE_HYSTERESIS_COUNT_0_READ_MASK                    _MK_MASK_CONST(0x3f)
#define SDMMCAB_VENDOR_CLK_GATE_HYSTERESIS_COUNT_0_WRITE_MASK                   _MK_MASK_CONST(0x3f)
#define SDMMCAB_VENDOR_CLK_GATE_HYSTERESIS_COUNT_0_CLK_COUNT_SHIFT                      _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_CLK_GATE_HYSTERESIS_COUNT_0_CLK_COUNT_FIELD                      _MK_FIELD_CONST(0x3f, SDMMCAB_VENDOR_CLK_GATE_HYSTERESIS_COUNT_0_CLK_COUNT_SHIFT)
#define SDMMCAB_VENDOR_CLK_GATE_HYSTERESIS_COUNT_0_CLK_COUNT_RANGE                      5:0
#define SDMMCAB_VENDOR_CLK_GATE_HYSTERESIS_COUNT_0_CLK_COUNT_WOFFSET                    0x0
#define SDMMCAB_VENDOR_CLK_GATE_HYSTERESIS_COUNT_0_CLK_COUNT_DEFAULT                    _MK_MASK_CONST(0xf)
#define SDMMCAB_VENDOR_CLK_GATE_HYSTERESIS_COUNT_0_CLK_COUNT_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
#define SDMMCAB_VENDOR_CLK_GATE_HYSTERESIS_COUNT_0_CLK_COUNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLK_GATE_HYSTERESIS_COUNT_0_CLK_COUNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLK_GATE_HYSTERESIS_COUNT_0_CLK_COUNT_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CLK_GATE_HYSTERESIS_COUNT_0_CLK_COUNT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register SDMMCAB_VENDOR_PRESET_VAL0_0
#define SDMMCAB_VENDOR_PRESET_VAL0_0                    _MK_ADDR_CONST(0x1d4)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SECURE                     0x0
#define SDMMCAB_VENDOR_PRESET_VAL0_0_DUAL                       0x0
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SCR                        0
#define SDMMCAB_VENDOR_PRESET_VAL0_0_WORD_COUNT                         0x1
#define SDMMCAB_VENDOR_PRESET_VAL0_0_RESET_VAL                  _MK_MASK_CONST(0x201000)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_RESET_MASK                         _MK_MASK_CONST(0x3fffffff)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_READ_MASK                  _MK_MASK_CONST(0x3fffffff)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_WRITE_MASK                         _MK_MASK_CONST(0x3fffffff)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_HIGH_SPEED_SHIFT                    _MK_SHIFT_CONST(20)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_HIGH_SPEED_FIELD                    _MK_FIELD_CONST(0x3ff, SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_HIGH_SPEED_SHIFT)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_HIGH_SPEED_RANGE                    29:20
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_HIGH_SPEED_WOFFSET                  0x0
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_HIGH_SPEED_DEFAULT                  _MK_MASK_CONST(0x2)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_HIGH_SPEED_DEFAULT_MASK                     _MK_MASK_CONST(0x3ff)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_HIGH_SPEED_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_HIGH_SPEED_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_HIGH_SPEED_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_HIGH_SPEED_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_DEFAULT_SHIFT                       _MK_SHIFT_CONST(10)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_DEFAULT_FIELD                       _MK_FIELD_CONST(0x3ff, SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_DEFAULT_SHIFT)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_DEFAULT_RANGE                       19:10
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_DEFAULT_WOFFSET                     0x0
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_DEFAULT_DEFAULT                     _MK_MASK_CONST(0x4)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_DEFAULT_DEFAULT_MASK                        _MK_MASK_CONST(0x3ff)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_DEFAULT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_DEFAULT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_DEFAULT_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_DEFAULT_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_INIT_SHIFT                  _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_INIT_FIELD                  _MK_FIELD_CONST(0x3ff, SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_INIT_SHIFT)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_INIT_RANGE                  9:0
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_INIT_WOFFSET                        0x0
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_INIT_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_INIT_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_INIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_INIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_INIT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL0_0_SDCLK_FREQ_SEL_INIT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register SDMMCAB_VENDOR_PRESET_VAL1_0
#define SDMMCAB_VENDOR_PRESET_VAL1_0                    _MK_ADDR_CONST(0x1d8)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SECURE                     0x0
#define SDMMCAB_VENDOR_PRESET_VAL1_0_DUAL                       0x0
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SCR                        0
#define SDMMCAB_VENDOR_PRESET_VAL1_0_WORD_COUNT                         0x1
#define SDMMCAB_VENDOR_PRESET_VAL1_0_RESET_VAL                  _MK_MASK_CONST(0x100804)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_RESET_MASK                         _MK_MASK_CONST(0x3fffffff)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_READ_MASK                  _MK_MASK_CONST(0x3fffffff)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_WRITE_MASK                         _MK_MASK_CONST(0x3fffffff)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR50_SHIFT                 _MK_SHIFT_CONST(20)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR50_FIELD                 _MK_FIELD_CONST(0x3ff, SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR50_SHIFT)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR50_RANGE                 29:20
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR50_WOFFSET                       0x0
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR50_DEFAULT                       _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR50_DEFAULT_MASK                  _MK_MASK_CONST(0x3ff)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR50_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR50_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR50_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR50_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR25_SHIFT                 _MK_SHIFT_CONST(10)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR25_FIELD                 _MK_FIELD_CONST(0x3ff, SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR25_SHIFT)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR25_RANGE                 19:10
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR25_WOFFSET                       0x0
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR25_DEFAULT                       _MK_MASK_CONST(0x2)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR25_DEFAULT_MASK                  _MK_MASK_CONST(0x3ff)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR25_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR25_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR25_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR25_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR12_SHIFT                 _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR12_FIELD                 _MK_FIELD_CONST(0x3ff, SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR12_SHIFT)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR12_RANGE                 9:0
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR12_WOFFSET                       0x0
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR12_DEFAULT                       _MK_MASK_CONST(0x4)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR12_DEFAULT_MASK                  _MK_MASK_CONST(0x3ff)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR12_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR12_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR12_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL1_0_SDCLK_FREQ_SEL_SDR12_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register SDMMCAB_VENDOR_PRESET_VAL2_0
#define SDMMCAB_VENDOR_PRESET_VAL2_0                    _MK_ADDR_CONST(0x1dc)
#define SDMMCAB_VENDOR_PRESET_VAL2_0_SECURE                     0x0
#define SDMMCAB_VENDOR_PRESET_VAL2_0_DUAL                       0x0
#define SDMMCAB_VENDOR_PRESET_VAL2_0_SCR                        0
#define SDMMCAB_VENDOR_PRESET_VAL2_0_WORD_COUNT                         0x1
#define SDMMCAB_VENDOR_PRESET_VAL2_0_RESET_VAL                  _MK_MASK_CONST(0x800)
#define SDMMCAB_VENDOR_PRESET_VAL2_0_RESET_MASK                         _MK_MASK_CONST(0xfffff)
#define SDMMCAB_VENDOR_PRESET_VAL2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL2_0_READ_MASK                  _MK_MASK_CONST(0xfffff)
#define SDMMCAB_VENDOR_PRESET_VAL2_0_WRITE_MASK                         _MK_MASK_CONST(0xfffff)
#define SDMMCAB_VENDOR_PRESET_VAL2_0_SDCLK_FREQ_SEL_DDR50_SHIFT                 _MK_SHIFT_CONST(10)
#define SDMMCAB_VENDOR_PRESET_VAL2_0_SDCLK_FREQ_SEL_DDR50_FIELD                 _MK_FIELD_CONST(0x3ff, SDMMCAB_VENDOR_PRESET_VAL2_0_SDCLK_FREQ_SEL_DDR50_SHIFT)
#define SDMMCAB_VENDOR_PRESET_VAL2_0_SDCLK_FREQ_SEL_DDR50_RANGE                 19:10
#define SDMMCAB_VENDOR_PRESET_VAL2_0_SDCLK_FREQ_SEL_DDR50_WOFFSET                       0x0
#define SDMMCAB_VENDOR_PRESET_VAL2_0_SDCLK_FREQ_SEL_DDR50_DEFAULT                       _MK_MASK_CONST(0x2)
#define SDMMCAB_VENDOR_PRESET_VAL2_0_SDCLK_FREQ_SEL_DDR50_DEFAULT_MASK                  _MK_MASK_CONST(0x3ff)
#define SDMMCAB_VENDOR_PRESET_VAL2_0_SDCLK_FREQ_SEL_DDR50_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL2_0_SDCLK_FREQ_SEL_DDR50_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL2_0_SDCLK_FREQ_SEL_DDR50_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL2_0_SDCLK_FREQ_SEL_DDR50_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_PRESET_VAL2_0_SDCLK_FREQ_SEL_SDR104_SHIFT                        _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_PRESET_VAL2_0_SDCLK_FREQ_SEL_SDR104_FIELD                        _MK_FIELD_CONST(0x3ff, SDMMCAB_VENDOR_PRESET_VAL2_0_SDCLK_FREQ_SEL_SDR104_SHIFT)
#define SDMMCAB_VENDOR_PRESET_VAL2_0_SDCLK_FREQ_SEL_SDR104_RANGE                        9:0
#define SDMMCAB_VENDOR_PRESET_VAL2_0_SDCLK_FREQ_SEL_SDR104_WOFFSET                      0x0
#define SDMMCAB_VENDOR_PRESET_VAL2_0_SDCLK_FREQ_SEL_SDR104_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL2_0_SDCLK_FREQ_SEL_SDR104_DEFAULT_MASK                 _MK_MASK_CONST(0x3ff)
#define SDMMCAB_VENDOR_PRESET_VAL2_0_SDCLK_FREQ_SEL_SDR104_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL2_0_SDCLK_FREQ_SEL_SDR104_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL2_0_SDCLK_FREQ_SEL_SDR104_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_PRESET_VAL2_0_SDCLK_FREQ_SEL_SDR104_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register SDMMCAB_SDMEMCOMPPADCTRL_0
#define SDMMCAB_SDMEMCOMPPADCTRL_0                      _MK_ADDR_CONST(0x1e0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_SECURE                       0x0
#define SDMMCAB_SDMEMCOMPPADCTRL_0_DUAL                         0x0
#define SDMMCAB_SDMEMCOMPPADCTRL_0_SCR                  0
#define SDMMCAB_SDMEMCOMPPADCTRL_0_WORD_COUNT                   0x1
#define SDMMCAB_SDMEMCOMPPADCTRL_0_RESET_VAL                    _MK_MASK_CONST(0x8000000)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_RESET_MASK                   _MK_MASK_CONST(0xdff7ffff)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_READ_MASK                    _MK_MASK_CONST(0xdff7ffff)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_WRITE_MASK                   _MK_MASK_CONST(0xdff7ffff)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL_SHIFT                       _MK_SHIFT_CONST(0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL_FIELD                       _MK_FIELD_CONST(0xf, SDMMCAB_SDMEMCOMPPADCTRL_0_SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL_SHIFT)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL_RANGE                       3:0
#define SDMMCAB_SDMEMCOMPPADCTRL_0_SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL_WOFFSET                     0x0
#define SDMMCAB_SDMEMCOMPPADCTRL_0_SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_TEST_SEL_SHIFT                      _MK_SHIFT_CONST(4)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_TEST_SEL_FIELD                      _MK_FIELD_CONST(0x7, SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_TEST_SEL_SHIFT)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_TEST_SEL_RANGE                      6:4
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_TEST_SEL_WOFFSET                    0x0
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_TEST_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_TEST_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_TEST_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_TEST_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_TEST_SEL_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_TEST_SEL_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_RFU_IN_SHIFT                        _MK_SHIFT_CONST(7)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_RFU_IN_FIELD                        _MK_FIELD_CONST(0xf, SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_RFU_IN_SHIFT)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_RFU_IN_RANGE                        10:7
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_RFU_IN_WOFFSET                      0x0
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_RFU_IN_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_RFU_IN_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_RFU_IN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_RFU_IN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_RFU_IN_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_RFU_IN_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_E_TEST_OUT_SHIFT                    _MK_SHIFT_CONST(11)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_E_TEST_OUT_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_E_TEST_OUT_SHIFT)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_E_TEST_OUT_RANGE                    11:11
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_E_TEST_OUT_WOFFSET                  0x0
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_E_TEST_OUT_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_E_TEST_OUT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_E_TEST_OUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_E_TEST_OUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_E_TEST_OUT_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_E_TEST_OUT_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRVDN_OVR_SHIFT                     _MK_SHIFT_CONST(12)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRVDN_OVR_FIELD                     _MK_FIELD_CONST(0x7f, SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRVDN_OVR_SHIFT)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRVDN_OVR_RANGE                     18:12
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRVDN_OVR_WOFFSET                   0x0
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRVDN_OVR_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRVDN_OVR_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRVDN_OVR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRVDN_OVR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRVDN_OVR_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRVDN_OVR_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRVDN_OVR__PROD                     _MK_ENUM_CONST(10)

#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRVUP_OVR_SHIFT                     _MK_SHIFT_CONST(20)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRVUP_OVR_FIELD                     _MK_FIELD_CONST(0x7f, SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRVUP_OVR_SHIFT)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRVUP_OVR_RANGE                     26:20
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRVUP_OVR_WOFFSET                   0x0
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRVUP_OVR_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRVUP_OVR_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRVUP_OVR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRVUP_OVR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRVUP_OVR_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRVUP_OVR_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRVUP_OVR__PROD                     _MK_ENUM_CONST(10)

#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRV_TYPE_SHIFT                      _MK_SHIFT_CONST(27)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRV_TYPE_FIELD                      _MK_FIELD_CONST(0x3, SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRV_TYPE_SHIFT)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRV_TYPE_RANGE                      28:27
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRV_TYPE_WOFFSET                    0x0
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRV_TYPE_DEFAULT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRV_TYPE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRV_TYPE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRV_TYPE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRV_TYPE_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_DRV_TYPE_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_E_PBIAS_BUF_SHIFT                   _MK_SHIFT_CONST(30)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_E_PBIAS_BUF_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_E_PBIAS_BUF_SHIFT)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_E_PBIAS_BUF_RANGE                   30:30
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_E_PBIAS_BUF_WOFFSET                 0x0
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_E_PBIAS_BUF_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_E_PBIAS_BUF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_E_PBIAS_BUF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_E_PBIAS_BUF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_E_PBIAS_BUF_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_COMP_PAD_E_PBIAS_BUF_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SDMMCAB_SDMEMCOMPPADCTRL_0_PAD_E_INPUT_OR_E_PWRD_SHIFT                  _MK_SHIFT_CONST(31)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_PAD_E_INPUT_OR_E_PWRD_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_SDMEMCOMPPADCTRL_0_PAD_E_INPUT_OR_E_PWRD_SHIFT)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_PAD_E_INPUT_OR_E_PWRD_RANGE                  31:31
#define SDMMCAB_SDMEMCOMPPADCTRL_0_PAD_E_INPUT_OR_E_PWRD_WOFFSET                        0x0
#define SDMMCAB_SDMEMCOMPPADCTRL_0_PAD_E_INPUT_OR_E_PWRD_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_PAD_E_INPUT_OR_E_PWRD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_PAD_E_INPUT_OR_E_PWRD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_PAD_E_INPUT_OR_E_PWRD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_PAD_E_INPUT_OR_E_PWRD_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_0_PAD_E_INPUT_OR_E_PWRD_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register SDMMCAB_AUTO_CAL_CONFIG_0
#define SDMMCAB_AUTO_CAL_CONFIG_0                       _MK_ADDR_CONST(0x1e4)
#define SDMMCAB_AUTO_CAL_CONFIG_0_SECURE                        0x0
#define SDMMCAB_AUTO_CAL_CONFIG_0_DUAL                  0x0
#define SDMMCAB_AUTO_CAL_CONFIG_0_SCR                   0
#define SDMMCAB_AUTO_CAL_CONFIG_0_WORD_COUNT                    0x1
#define SDMMCAB_AUTO_CAL_CONFIG_0_RESET_VAL                     _MK_MASK_CONST(0x10000)
#define SDMMCAB_AUTO_CAL_CONFIG_0_RESET_MASK                    _MK_MASK_CONST(0xf0077f7f)
#define SDMMCAB_AUTO_CAL_CONFIG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_READ_MASK                     _MK_MASK_CONST(0xf0077f7f)
#define SDMMCAB_AUTO_CAL_CONFIG_0_WRITE_MASK                    _MK_MASK_CONST(0xf0077f7f)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_SHIFT                      _MK_SHIFT_CONST(0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_FIELD                      _MK_FIELD_CONST(0x7f, SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_SHIFT)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_RANGE                      6:0
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_WOFFSET                    0x0
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_DEFAULT_MASK                       _MK_MASK_CONST(0x7f)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_SHIFT                      _MK_SHIFT_CONST(8)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_FIELD                      _MK_FIELD_CONST(0x7f, SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_SHIFT)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_RANGE                      14:8
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_WOFFSET                    0x0
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_DEFAULT_MASK                       _MK_MASK_CONST(0x7f)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_SHIFT                   _MK_SHIFT_CONST(16)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_FIELD                   _MK_FIELD_CONST(0x7, SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_SHIFT)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_RANGE                   18:16
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_WOFFSET                 0x0
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_DEFAULT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_SLW_OVERRIDE_SHIFT                   _MK_SHIFT_CONST(28)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_SLW_OVERRIDE_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_SLW_OVERRIDE_SHIFT)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_SLW_OVERRIDE_RANGE                   28:28
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_SLW_OVERRIDE_WOFFSET                 0x0
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_SLW_OVERRIDE_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_SLW_OVERRIDE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_SLW_OVERRIDE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_SLW_OVERRIDE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_SLW_OVERRIDE_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_SLW_OVERRIDE_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_SLW_OVERRIDE_NORMAL                  _MK_ENUM_CONST(0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_SLW_OVERRIDE_OVERRIDE                        _MK_ENUM_CONST(1)

#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_SHIFT                 _MK_SHIFT_CONST(29)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_SHIFT)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_RANGE                 29:29
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_WOFFSET                       0x0
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_INIT_ENUM                     DISABLED
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE__PROD                 _MK_ENUM_CONST(1)

#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_SHIFT                       _MK_SHIFT_CONST(30)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_SHIFT)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_RANGE                       30:30
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_WOFFSET                     0x0
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_NORMAL                      _MK_ENUM_CONST(0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_OVERRIDE                    _MK_ENUM_CONST(1)

#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_START_SHIFT                  _MK_SHIFT_CONST(31)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_START_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_START_SHIFT)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_START_RANGE                  31:31
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_START_WOFFSET                        0x0
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_START_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_START_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_START_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_START_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_START_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_CONFIG_0_AUTO_CAL_START_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register SDMMCAB_AUTO_CAL_INTERVAL_0
#define SDMMCAB_AUTO_CAL_INTERVAL_0                     _MK_ADDR_CONST(0x1e8)
#define SDMMCAB_AUTO_CAL_INTERVAL_0_SECURE                      0x0
#define SDMMCAB_AUTO_CAL_INTERVAL_0_DUAL                        0x0
#define SDMMCAB_AUTO_CAL_INTERVAL_0_SCR                         0
#define SDMMCAB_AUTO_CAL_INTERVAL_0_WORD_COUNT                  0x1
#define SDMMCAB_AUTO_CAL_INTERVAL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_INTERVAL_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_AUTO_CAL_INTERVAL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_INTERVAL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_INTERVAL_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_AUTO_CAL_INTERVAL_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_SHIFT                     _MK_SHIFT_CONST(0)
#define SDMMCAB_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_FIELD                     _MK_FIELD_CONST(0xffffffff, SDMMCAB_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_SHIFT)
#define SDMMCAB_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_RANGE                     31:0
#define SDMMCAB_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_WOFFSET                   0x0
#define SDMMCAB_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register SDMMCAB_AUTO_CAL_STATUS_0
#define SDMMCAB_AUTO_CAL_STATUS_0                       _MK_ADDR_CONST(0x1ec)
#define SDMMCAB_AUTO_CAL_STATUS_0_SECURE                        0x0
#define SDMMCAB_AUTO_CAL_STATUS_0_DUAL                  0x0
#define SDMMCAB_AUTO_CAL_STATUS_0_SCR                   0
#define SDMMCAB_AUTO_CAL_STATUS_0_WORD_COUNT                    0x1
#define SDMMCAB_AUTO_CAL_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0xff7f7f7f)
#define SDMMCAB_AUTO_CAL_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_STATUS_0_READ_MASK                     _MK_MASK_CONST(0xff7f7f7f)
#define SDMMCAB_AUTO_CAL_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_SHIFT                 _MK_SHIFT_CONST(0)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_FIELD                 _MK_FIELD_CONST(0x7f, SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_SHIFT)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_RANGE                 6:0
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_WOFFSET                       0x0
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_DEFAULT_MASK                  _MK_MASK_CONST(0x7f)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_SHIFT                       _MK_SHIFT_CONST(8)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_FIELD                       _MK_FIELD_CONST(0x7f, SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_SHIFT)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_RANGE                       14:8
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_WOFFSET                     0x0
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_DEFAULT_MASK                        _MK_MASK_CONST(0x7f)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_SHIFT                     _MK_SHIFT_CONST(16)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_FIELD                     _MK_FIELD_CONST(0x7f, SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_SHIFT)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_RANGE                     22:16
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_WOFFSET                   0x0
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_SHIFT                   _MK_SHIFT_CONST(24)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_FIELD                   _MK_FIELD_CONST(0x7f, SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_SHIFT)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_RANGE                   30:24
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_WOFFSET                 0x0
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_DEFAULT_MASK                    _MK_MASK_CONST(0x7f)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_SHIFT                 _MK_SHIFT_CONST(31)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_SHIFT)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_RANGE                 31:31
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_WOFFSET                       0x0
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register SDMMCAB_IO_SPARE_0
#define SDMMCAB_IO_SPARE_0                      _MK_ADDR_CONST(0x1f0)
#define SDMMCAB_IO_SPARE_0_SECURE                       0x0
#define SDMMCAB_IO_SPARE_0_DUAL                         0x0
#define SDMMCAB_IO_SPARE_0_SCR                  0
#define SDMMCAB_IO_SPARE_0_WORD_COUNT                   0x1
#define SDMMCAB_IO_SPARE_0_RESET_VAL                    _MK_MASK_CONST(0x80000)
#define SDMMCAB_IO_SPARE_0_RESET_MASK                   _MK_MASK_CONST(0xffff0000)
#define SDMMCAB_IO_SPARE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SDMMCAB_IO_SPARE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_IO_SPARE_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_IO_SPARE_0_WRITE_MASK                   _MK_MASK_CONST(0xffff0000)
#define SDMMCAB_IO_SPARE_0_SPARE_IN_SHIFT                       _MK_SHIFT_CONST(0)
#define SDMMCAB_IO_SPARE_0_SPARE_IN_FIELD                       _MK_FIELD_CONST(0xffff, SDMMCAB_IO_SPARE_0_SPARE_IN_SHIFT)
#define SDMMCAB_IO_SPARE_0_SPARE_IN_RANGE                       15:0
#define SDMMCAB_IO_SPARE_0_SPARE_IN_WOFFSET                     0x0
#define SDMMCAB_IO_SPARE_0_SPARE_IN_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_IO_SPARE_0_SPARE_IN_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_IO_SPARE_0_SPARE_IN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_IO_SPARE_0_SPARE_IN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_IO_SPARE_0_SPARE_IN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_IO_SPARE_0_SPARE_IN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SDMMCAB_IO_SPARE_0_SPARE_OUT_SHIFT                      _MK_SHIFT_CONST(16)
#define SDMMCAB_IO_SPARE_0_SPARE_OUT_FIELD                      _MK_FIELD_CONST(0xffff, SDMMCAB_IO_SPARE_0_SPARE_OUT_SHIFT)
#define SDMMCAB_IO_SPARE_0_SPARE_OUT_RANGE                      31:16
#define SDMMCAB_IO_SPARE_0_SPARE_OUT_WOFFSET                    0x0
#define SDMMCAB_IO_SPARE_0_SPARE_OUT_DEFAULT                    _MK_MASK_CONST(0x8)
#define SDMMCAB_IO_SPARE_0_SPARE_OUT_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
#define SDMMCAB_IO_SPARE_0_SPARE_OUT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_IO_SPARE_0_SPARE_OUT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_IO_SPARE_0_SPARE_OUT_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_IO_SPARE_0_SPARE_OUT_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Reserved address 0x1f4

// Reserved address 0x1f8

// Register SDMMCAB_CIF2AXI_CTRL_0
#define SDMMCAB_CIF2AXI_CTRL_0                  _MK_ADDR_CONST(0x1fc)
#define SDMMCAB_CIF2AXI_CTRL_0_SECURE                   0x0
#define SDMMCAB_CIF2AXI_CTRL_0_DUAL                     0x0
#define SDMMCAB_CIF2AXI_CTRL_0_SCR                      0
#define SDMMCAB_CIF2AXI_CTRL_0_WORD_COUNT                       0x1
#define SDMMCAB_CIF2AXI_CTRL_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CIF2AXI_CTRL_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
#define SDMMCAB_CIF2AXI_CTRL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CIF2AXI_CTRL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CIF2AXI_CTRL_0_READ_MASK                        _MK_MASK_CONST(0xffff)
#define SDMMCAB_CIF2AXI_CTRL_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
#define SDMMCAB_CIF2AXI_CTRL_0_MC_WRITE_REQ_STREAM_ID_SHIFT                     _MK_SHIFT_CONST(8)
#define SDMMCAB_CIF2AXI_CTRL_0_MC_WRITE_REQ_STREAM_ID_FIELD                     _MK_FIELD_CONST(0xff, SDMMCAB_CIF2AXI_CTRL_0_MC_WRITE_REQ_STREAM_ID_SHIFT)
#define SDMMCAB_CIF2AXI_CTRL_0_MC_WRITE_REQ_STREAM_ID_RANGE                     15:8
#define SDMMCAB_CIF2AXI_CTRL_0_MC_WRITE_REQ_STREAM_ID_WOFFSET                   0x0
#define SDMMCAB_CIF2AXI_CTRL_0_MC_WRITE_REQ_STREAM_ID_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CIF2AXI_CTRL_0_MC_WRITE_REQ_STREAM_ID_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
#define SDMMCAB_CIF2AXI_CTRL_0_MC_WRITE_REQ_STREAM_ID_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CIF2AXI_CTRL_0_MC_WRITE_REQ_STREAM_ID_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CIF2AXI_CTRL_0_MC_WRITE_REQ_STREAM_ID_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CIF2AXI_CTRL_0_MC_WRITE_REQ_STREAM_ID_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SDMMCAB_CIF2AXI_CTRL_0_MC_READ_REQ_STREAM_ID_SHIFT                      _MK_SHIFT_CONST(0)
#define SDMMCAB_CIF2AXI_CTRL_0_MC_READ_REQ_STREAM_ID_FIELD                      _MK_FIELD_CONST(0xff, SDMMCAB_CIF2AXI_CTRL_0_MC_READ_REQ_STREAM_ID_SHIFT)
#define SDMMCAB_CIF2AXI_CTRL_0_MC_READ_REQ_STREAM_ID_RANGE                      7:0
#define SDMMCAB_CIF2AXI_CTRL_0_MC_READ_REQ_STREAM_ID_WOFFSET                    0x0
#define SDMMCAB_CIF2AXI_CTRL_0_MC_READ_REQ_STREAM_ID_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CIF2AXI_CTRL_0_MC_READ_REQ_STREAM_ID_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
#define SDMMCAB_CIF2AXI_CTRL_0_MC_READ_REQ_STREAM_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CIF2AXI_CTRL_0_MC_READ_REQ_STREAM_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CIF2AXI_CTRL_0_MC_READ_REQ_STREAM_ID_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CIF2AXI_CTRL_0_MC_READ_REQ_STREAM_ID_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register SDMMCAB_TZ_DMA_CTRL_0
#define SDMMCAB_TZ_DMA_CTRL_0                   _MK_ADDR_CONST(0x200)
#define SDMMCAB_TZ_DMA_CTRL_0_SECURE                    0x1
#define SDMMCAB_TZ_DMA_CTRL_0_DUAL                      0x0
#define SDMMCAB_TZ_DMA_CTRL_0_SCR                       0
#define SDMMCAB_TZ_DMA_CTRL_0_WORD_COUNT                        0x1
#define SDMMCAB_TZ_DMA_CTRL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SDMMCAB_TZ_DMA_CTRL_0_RESET_MASK                        _MK_MASK_CONST(0x3)
#define SDMMCAB_TZ_DMA_CTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SDMMCAB_TZ_DMA_CTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_TZ_DMA_CTRL_0_READ_MASK                         _MK_MASK_CONST(0x3)
#define SDMMCAB_TZ_DMA_CTRL_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
#define SDMMCAB_TZ_DMA_CTRL_0_MC_WRITE_REQ_TZ_ACCESS_EN_SHIFT                   _MK_SHIFT_CONST(1)
#define SDMMCAB_TZ_DMA_CTRL_0_MC_WRITE_REQ_TZ_ACCESS_EN_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_TZ_DMA_CTRL_0_MC_WRITE_REQ_TZ_ACCESS_EN_SHIFT)
#define SDMMCAB_TZ_DMA_CTRL_0_MC_WRITE_REQ_TZ_ACCESS_EN_RANGE                   1:1
#define SDMMCAB_TZ_DMA_CTRL_0_MC_WRITE_REQ_TZ_ACCESS_EN_WOFFSET                 0x0
#define SDMMCAB_TZ_DMA_CTRL_0_MC_WRITE_REQ_TZ_ACCESS_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_TZ_DMA_CTRL_0_MC_WRITE_REQ_TZ_ACCESS_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_TZ_DMA_CTRL_0_MC_WRITE_REQ_TZ_ACCESS_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_TZ_DMA_CTRL_0_MC_WRITE_REQ_TZ_ACCESS_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_TZ_DMA_CTRL_0_MC_WRITE_REQ_TZ_ACCESS_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_TZ_DMA_CTRL_0_MC_WRITE_REQ_TZ_ACCESS_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SDMMCAB_TZ_DMA_CTRL_0_MC_READ_REQ_TZ_ACCESS_EN_SHIFT                    _MK_SHIFT_CONST(0)
#define SDMMCAB_TZ_DMA_CTRL_0_MC_READ_REQ_TZ_ACCESS_EN_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_TZ_DMA_CTRL_0_MC_READ_REQ_TZ_ACCESS_EN_SHIFT)
#define SDMMCAB_TZ_DMA_CTRL_0_MC_READ_REQ_TZ_ACCESS_EN_RANGE                    0:0
#define SDMMCAB_TZ_DMA_CTRL_0_MC_READ_REQ_TZ_ACCESS_EN_WOFFSET                  0x0
#define SDMMCAB_TZ_DMA_CTRL_0_MC_READ_REQ_TZ_ACCESS_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_TZ_DMA_CTRL_0_MC_READ_REQ_TZ_ACCESS_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_TZ_DMA_CTRL_0_MC_READ_REQ_TZ_ACCESS_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_TZ_DMA_CTRL_0_MC_READ_REQ_TZ_ACCESS_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_TZ_DMA_CTRL_0_MC_READ_REQ_TZ_ACCESS_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_TZ_DMA_CTRL_0_MC_READ_REQ_TZ_ACCESS_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register SDMMCAB_VENDOR_MISC_CNTRL3_0
#define SDMMCAB_VENDOR_MISC_CNTRL3_0                    _MK_ADDR_CONST(0x204)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_SECURE                     0x0
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_DUAL                       0x0
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_SCR                        0
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_WORD_COUNT                         0x1
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_RESET_VAL                  _MK_MASK_CONST(0x4f01000f)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_RESET_MASK                         _MK_MASK_CONST(0xff01ff1f)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_READ_MASK                  _MK_MASK_CONST(0xff01ff1f)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_WRITE_MASK                         _MK_MASK_CONST(0xff01ff1f)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_ALLOW_INTRABLOCK_CLK_STALLING_IN_SDR50_SHIFT                       _MK_SHIFT_CONST(31)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_ALLOW_INTRABLOCK_CLK_STALLING_IN_SDR50_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_MISC_CNTRL3_0_ALLOW_INTRABLOCK_CLK_STALLING_IN_SDR50_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_ALLOW_INTRABLOCK_CLK_STALLING_IN_SDR50_RANGE                       31:31
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_ALLOW_INTRABLOCK_CLK_STALLING_IN_SDR50_WOFFSET                     0x0
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_ALLOW_INTRABLOCK_CLK_STALLING_IN_SDR50_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_ALLOW_INTRABLOCK_CLK_STALLING_IN_SDR50_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_ALLOW_INTRABLOCK_CLK_STALLING_IN_SDR50_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_ALLOW_INTRABLOCK_CLK_STALLING_IN_SDR50_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_ALLOW_INTRABLOCK_CLK_STALLING_IN_SDR50_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_ALLOW_INTRABLOCK_CLK_STALLING_IN_SDR50_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_MISC_CNTRL3_0_STOP_TRIM_IN_CLK_DURING_TUNING_SHIFT                       _MK_SHIFT_CONST(30)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_STOP_TRIM_IN_CLK_DURING_TUNING_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_MISC_CNTRL3_0_STOP_TRIM_IN_CLK_DURING_TUNING_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_STOP_TRIM_IN_CLK_DURING_TUNING_RANGE                       30:30
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_STOP_TRIM_IN_CLK_DURING_TUNING_WOFFSET                     0x0
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_STOP_TRIM_IN_CLK_DURING_TUNING_DEFAULT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_STOP_TRIM_IN_CLK_DURING_TUNING_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_STOP_TRIM_IN_CLK_DURING_TUNING_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_STOP_TRIM_IN_CLK_DURING_TUNING_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_STOP_TRIM_IN_CLK_DURING_TUNING_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_STOP_TRIM_IN_CLK_DURING_TUNING_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_MISC_CNTRL3_0_TUNING_TRIMMER_RECOVERY_TIME_SHIFT                 _MK_SHIFT_CONST(24)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_TUNING_TRIMMER_RECOVERY_TIME_FIELD                 _MK_FIELD_CONST(0x3f, SDMMCAB_VENDOR_MISC_CNTRL3_0_TUNING_TRIMMER_RECOVERY_TIME_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_TUNING_TRIMMER_RECOVERY_TIME_RANGE                 29:24
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_TUNING_TRIMMER_RECOVERY_TIME_WOFFSET                       0x0
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_TUNING_TRIMMER_RECOVERY_TIME_DEFAULT                       _MK_MASK_CONST(0xf)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_TUNING_TRIMMER_RECOVERY_TIME_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_TUNING_TRIMMER_RECOVERY_TIME_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_TUNING_TRIMMER_RECOVERY_TIME_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_TUNING_TRIMMER_RECOVERY_TIME_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_TUNING_TRIMMER_RECOVERY_TIME_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_MISC_CNTRL3_0_EXTEND_SYNC_INTR_MASK_DURING_ABORT_OR_STOP_CMD_SHIFT                       _MK_SHIFT_CONST(16)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_EXTEND_SYNC_INTR_MASK_DURING_ABORT_OR_STOP_CMD_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_MISC_CNTRL3_0_EXTEND_SYNC_INTR_MASK_DURING_ABORT_OR_STOP_CMD_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_EXTEND_SYNC_INTR_MASK_DURING_ABORT_OR_STOP_CMD_RANGE                       16:16
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_EXTEND_SYNC_INTR_MASK_DURING_ABORT_OR_STOP_CMD_WOFFSET                     0x0
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_EXTEND_SYNC_INTR_MASK_DURING_ABORT_OR_STOP_CMD_DEFAULT                     _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_EXTEND_SYNC_INTR_MASK_DURING_ABORT_OR_STOP_CMD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_EXTEND_SYNC_INTR_MASK_DURING_ABORT_OR_STOP_CMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_EXTEND_SYNC_INTR_MASK_DURING_ABORT_OR_STOP_CMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_EXTEND_SYNC_INTR_MASK_DURING_ABORT_OR_STOP_CMD_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_EXTEND_SYNC_INTR_MASK_DURING_ABORT_OR_STOP_CMD_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_MISC_CNTRL3_0_E_DIFF_DQ_SHIFT                    _MK_SHIFT_CONST(8)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_E_DIFF_DQ_FIELD                    _MK_FIELD_CONST(0xff, SDMMCAB_VENDOR_MISC_CNTRL3_0_E_DIFF_DQ_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_E_DIFF_DQ_RANGE                    15:8
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_E_DIFF_DQ_WOFFSET                  0x0
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_E_DIFF_DQ_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_E_DIFF_DQ_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_E_DIFF_DQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_E_DIFF_DQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_E_DIFF_DQ_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_E_DIFF_DQ_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_MISC_CNTRL3_0_E_DIFF_CMD_SHIFT                   _MK_SHIFT_CONST(4)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_E_DIFF_CMD_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_MISC_CNTRL3_0_E_DIFF_CMD_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_E_DIFF_CMD_RANGE                   4:4
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_E_DIFF_CMD_WOFFSET                 0x0
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_E_DIFF_CMD_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_E_DIFF_CMD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_E_DIFF_CMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_E_DIFF_CMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_E_DIFF_CMD_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_E_DIFF_CMD_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_MISC_CNTRL3_0_DAT_OE_POSTAMBLE_EN_SHIFT                  _MK_SHIFT_CONST(3)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_DAT_OE_POSTAMBLE_EN_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_MISC_CNTRL3_0_DAT_OE_POSTAMBLE_EN_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_DAT_OE_POSTAMBLE_EN_RANGE                  3:3
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_DAT_OE_POSTAMBLE_EN_WOFFSET                        0x0
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_DAT_OE_POSTAMBLE_EN_DEFAULT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_DAT_OE_POSTAMBLE_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_DAT_OE_POSTAMBLE_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_DAT_OE_POSTAMBLE_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_DAT_OE_POSTAMBLE_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_DAT_OE_POSTAMBLE_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_MISC_CNTRL3_0_DAT_OE_PREAMBLE_EN_SHIFT                   _MK_SHIFT_CONST(2)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_DAT_OE_PREAMBLE_EN_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_MISC_CNTRL3_0_DAT_OE_PREAMBLE_EN_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_DAT_OE_PREAMBLE_EN_RANGE                   2:2
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_DAT_OE_PREAMBLE_EN_WOFFSET                 0x0
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_DAT_OE_PREAMBLE_EN_DEFAULT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_DAT_OE_PREAMBLE_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_DAT_OE_PREAMBLE_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_DAT_OE_PREAMBLE_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_DAT_OE_PREAMBLE_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_DAT_OE_PREAMBLE_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_MISC_CNTRL3_0_CMD_OE_POSTAMBLE_EN_SHIFT                  _MK_SHIFT_CONST(1)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_CMD_OE_POSTAMBLE_EN_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_MISC_CNTRL3_0_CMD_OE_POSTAMBLE_EN_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_CMD_OE_POSTAMBLE_EN_RANGE                  1:1
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_CMD_OE_POSTAMBLE_EN_WOFFSET                        0x0
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_CMD_OE_POSTAMBLE_EN_DEFAULT                        _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_CMD_OE_POSTAMBLE_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_CMD_OE_POSTAMBLE_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_CMD_OE_POSTAMBLE_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_CMD_OE_POSTAMBLE_EN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_CMD_OE_POSTAMBLE_EN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_MISC_CNTRL3_0_CMD_OE_PREAMBLE_EN_SHIFT                   _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_CMD_OE_PREAMBLE_EN_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_MISC_CNTRL3_0_CMD_OE_PREAMBLE_EN_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_CMD_OE_PREAMBLE_EN_RANGE                   0:0
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_CMD_OE_PREAMBLE_EN_WOFFSET                 0x0
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_CMD_OE_PREAMBLE_EN_DEFAULT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_CMD_OE_PREAMBLE_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_CMD_OE_PREAMBLE_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_CMD_OE_PREAMBLE_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_CMD_OE_PREAMBLE_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL3_0_CMD_OE_PREAMBLE_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register SDMMCAB_VENDOR_CQE_CNTRL0_0
#define SDMMCAB_VENDOR_CQE_CNTRL0_0                     _MK_ADDR_CONST(0x208)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_SECURE                      0x0
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_DUAL                        0x0
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_SCR                         0
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_WORD_COUNT                  0x1
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_RESET_VAL                   _MK_MASK_CONST(0xe0000c82)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_RESET_MASK                  _MK_MASK_CONST(0xf0003fff)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_READ_MASK                   _MK_MASK_CONST(0xf0003fff)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_WRITE_MASK                  _MK_MASK_CONST(0xf0003fff)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_TASK_SELECTION_PRIORITY_EN_SHIFT                    _MK_SHIFT_CONST(31)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_TASK_SELECTION_PRIORITY_EN_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_CQE_CNTRL0_0_TASK_SELECTION_PRIORITY_EN_SHIFT)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_TASK_SELECTION_PRIORITY_EN_RANGE                    31:31
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_TASK_SELECTION_PRIORITY_EN_WOFFSET                  0x0
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_TASK_SELECTION_PRIORITY_EN_DEFAULT                  _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_TASK_SELECTION_PRIORITY_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_TASK_SELECTION_PRIORITY_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_TASK_SELECTION_PRIORITY_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_TASK_SELECTION_PRIORITY_EN_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_TASK_SELECTION_PRIORITY_EN_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_CQE_CNTRL0_0_MASK_CMD_COMPLETE_INTR_SHIFT                        _MK_SHIFT_CONST(30)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_MASK_CMD_COMPLETE_INTR_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_CQE_CNTRL0_0_MASK_CMD_COMPLETE_INTR_SHIFT)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_MASK_CMD_COMPLETE_INTR_RANGE                        30:30
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_MASK_CMD_COMPLETE_INTR_WOFFSET                      0x0
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_MASK_CMD_COMPLETE_INTR_DEFAULT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_MASK_CMD_COMPLETE_INTR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_MASK_CMD_COMPLETE_INTR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_MASK_CMD_COMPLETE_INTR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_MASK_CMD_COMPLETE_INTR_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_MASK_CMD_COMPLETE_INTR_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_CQE_CNTRL0_0_MASK_DAT_XFER_COMPLETE_INTR_SHIFT                   _MK_SHIFT_CONST(29)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_MASK_DAT_XFER_COMPLETE_INTR_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_CQE_CNTRL0_0_MASK_DAT_XFER_COMPLETE_INTR_SHIFT)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_MASK_DAT_XFER_COMPLETE_INTR_RANGE                   29:29
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_MASK_DAT_XFER_COMPLETE_INTR_WOFFSET                 0x0
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_MASK_DAT_XFER_COMPLETE_INTR_DEFAULT                 _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_MASK_DAT_XFER_COMPLETE_INTR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_MASK_DAT_XFER_COMPLETE_INTR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_MASK_DAT_XFER_COMPLETE_INTR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_MASK_DAT_XFER_COMPLETE_INTR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_MASK_DAT_XFER_COMPLETE_INTR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_CQE_CNTRL0_0_CQE_SW_CLR_ALL_SHIFT                        _MK_SHIFT_CONST(28)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_CQE_SW_CLR_ALL_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_CQE_CNTRL0_0_CQE_SW_CLR_ALL_SHIFT)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_CQE_SW_CLR_ALL_RANGE                        28:28
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_CQE_SW_CLR_ALL_WOFFSET                      0x0
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_CQE_SW_CLR_ALL_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_CQE_SW_CLR_ALL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_CQE_SW_CLR_ALL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_CQE_SW_CLR_ALL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_CQE_SW_CLR_ALL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_CQE_SW_CLR_ALL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_CQE_CNTRL0_0_ITC_FREQ_VAL_OVR_SHIFT                      _MK_SHIFT_CONST(4)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_ITC_FREQ_VAL_OVR_FIELD                      _MK_FIELD_CONST(0x3ff, SDMMCAB_VENDOR_CQE_CNTRL0_0_ITC_FREQ_VAL_OVR_SHIFT)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_ITC_FREQ_VAL_OVR_RANGE                      13:4
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_ITC_FREQ_VAL_OVR_WOFFSET                    0x0
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_ITC_FREQ_VAL_OVR_DEFAULT                    _MK_MASK_CONST(0xc8)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_ITC_FREQ_VAL_OVR_DEFAULT_MASK                       _MK_MASK_CONST(0x3ff)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_ITC_FREQ_VAL_OVR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_ITC_FREQ_VAL_OVR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_ITC_FREQ_VAL_OVR_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_ITC_FREQ_VAL_OVR_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_CQE_CNTRL0_0_ITC_FREQ_MUL_OVR_SHIFT                      _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_ITC_FREQ_MUL_OVR_FIELD                      _MK_FIELD_CONST(0xf, SDMMCAB_VENDOR_CQE_CNTRL0_0_ITC_FREQ_MUL_OVR_SHIFT)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_ITC_FREQ_MUL_OVR_RANGE                      3:0
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_ITC_FREQ_MUL_OVR_WOFFSET                    0x0
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_ITC_FREQ_MUL_OVR_DEFAULT                    _MK_MASK_CONST(0x2)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_ITC_FREQ_MUL_OVR_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_ITC_FREQ_MUL_OVR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_ITC_FREQ_MUL_OVR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_ITC_FREQ_MUL_OVR_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL0_0_ITC_FREQ_MUL_OVR_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register SDMMCAB_VENDOR_MISC_CNTRL4_0
#define SDMMCAB_VENDOR_MISC_CNTRL4_0                    _MK_ADDR_CONST(0x20c)
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_SECURE                     0x0
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_DUAL                       0x0
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_SCR                        0
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_WORD_COUNT                         0x1
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_RESET_VAL                  _MK_MASK_CONST(0xffff0000)
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_SDMMC_SPARE2_SHIFT                 _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_SDMMC_SPARE2_FIELD                 _MK_FIELD_CONST(0xffff, SDMMCAB_VENDOR_MISC_CNTRL4_0_SDMMC_SPARE2_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_SDMMC_SPARE2_RANGE                 15:0
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_SDMMC_SPARE2_WOFFSET                       0x0
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_SDMMC_SPARE2_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_SDMMC_SPARE2_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_SDMMC_SPARE2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_SDMMC_SPARE2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_SDMMC_SPARE2_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_SDMMC_SPARE2_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_MISC_CNTRL4_0_SDMMC_SPARE3_SHIFT                 _MK_SHIFT_CONST(16)
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_SDMMC_SPARE3_FIELD                 _MK_FIELD_CONST(0xffff, SDMMCAB_VENDOR_MISC_CNTRL4_0_SDMMC_SPARE3_SHIFT)
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_SDMMC_SPARE3_RANGE                 31:16
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_SDMMC_SPARE3_WOFFSET                       0x0
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_SDMMC_SPARE3_DEFAULT                       _MK_MASK_CONST(0xffff)
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_SDMMC_SPARE3_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_SDMMC_SPARE3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_SDMMC_SPARE3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_SDMMC_SPARE3_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_MISC_CNTRL4_0_SDMMC_SPARE3_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register SDMMCAB_IST_AXI_P2P_CNTRL_0
#define SDMMCAB_IST_AXI_P2P_CNTRL_0                     _MK_ADDR_CONST(0x210)
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_SECURE                      0x0
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_DUAL                        0x0
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_SCR                         0
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_WORD_COUNT                  0x1
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_RESET_MASK                  _MK_MASK_CONST(0x3)
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_READ_MASK                   _MK_MASK_CONST(0x3)
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_AXI_P2P_FIFO_HOT_RESET_SHIFT                        _MK_SHIFT_CONST(1)
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_AXI_P2P_FIFO_HOT_RESET_FIELD                        _MK_FIELD_CONST(0x1, SDMMCAB_IST_AXI_P2P_CNTRL_0_AXI_P2P_FIFO_HOT_RESET_SHIFT)
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_AXI_P2P_FIFO_HOT_RESET_RANGE                        1:1
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_AXI_P2P_FIFO_HOT_RESET_WOFFSET                      0x0
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_AXI_P2P_FIFO_HOT_RESET_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_AXI_P2P_FIFO_HOT_RESET_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_AXI_P2P_FIFO_HOT_RESET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_AXI_P2P_FIFO_HOT_RESET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_AXI_P2P_FIFO_HOT_RESET_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_AXI_P2P_FIFO_HOT_RESET_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SDMMCAB_IST_AXI_P2P_CNTRL_0_IST_AXI_P2P_FIFO_HOT_RESET_SHIFT                    _MK_SHIFT_CONST(0)
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_IST_AXI_P2P_FIFO_HOT_RESET_FIELD                    _MK_FIELD_CONST(0x1, SDMMCAB_IST_AXI_P2P_CNTRL_0_IST_AXI_P2P_FIFO_HOT_RESET_SHIFT)
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_IST_AXI_P2P_FIFO_HOT_RESET_RANGE                    0:0
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_IST_AXI_P2P_FIFO_HOT_RESET_WOFFSET                  0x0
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_IST_AXI_P2P_FIFO_HOT_RESET_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_IST_AXI_P2P_FIFO_HOT_RESET_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_IST_AXI_P2P_FIFO_HOT_RESET_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_IST_AXI_P2P_FIFO_HOT_RESET_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_IST_AXI_P2P_FIFO_HOT_RESET_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_IST_AXI_P2P_CNTRL_0_IST_AXI_P2P_FIFO_HOT_RESET_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0                     _MK_ADDR_CONST(0x214)
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_SECURE                      0x0
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_DUAL                        0x0
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_SCR                         0
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_WORD_COUNT                  0x1
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_RESET_MASK                  _MK_MASK_CONST(0xff)
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_READ_MASK                   _MK_MASK_CONST(0xff)
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_COMP_PAD_SPARE_VAUXC_SHIFT                  _MK_SHIFT_CONST(0)
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_COMP_PAD_SPARE_VAUXC_FIELD                  _MK_FIELD_CONST(0xf, SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_COMP_PAD_SPARE_VAUXC_SHIFT)
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_COMP_PAD_SPARE_VAUXC_RANGE                  3:0
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_COMP_PAD_SPARE_VAUXC_WOFFSET                        0x0
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_COMP_PAD_SPARE_VAUXC_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_COMP_PAD_SPARE_VAUXC_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_COMP_PAD_SPARE_VAUXC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_COMP_PAD_SPARE_VAUXC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_COMP_PAD_SPARE_VAUXC_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_COMP_PAD_SPARE_VAUXC_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_COMP_PAD_SPARE_VDD_SHIFT                    _MK_SHIFT_CONST(4)
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_COMP_PAD_SPARE_VDD_FIELD                    _MK_FIELD_CONST(0xf, SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_COMP_PAD_SPARE_VDD_SHIFT)
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_COMP_PAD_SPARE_VDD_RANGE                    7:4
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_COMP_PAD_SPARE_VDD_WOFFSET                  0x0
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_COMP_PAD_SPARE_VDD_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_COMP_PAD_SPARE_VDD_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_COMP_PAD_SPARE_VDD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_COMP_PAD_SPARE_VDD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_COMP_PAD_SPARE_VDD_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0_COMP_PAD_SPARE_VDD_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register SDMMCAB_VENDOR_CQE_CNTRL1_0
#define SDMMCAB_VENDOR_CQE_CNTRL1_0                     _MK_ADDR_CONST(0x218)
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_SECURE                      0x0
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_DUAL                        0x0
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_SCR                         0
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_WORD_COUNT                  0x1
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_RESET_VAL                   _MK_MASK_CONST(0x7fffffff)
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_VENDOR_INTR_COAL_TIMEOUT_EN_SHIFT                   _MK_SHIFT_CONST(31)
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_VENDOR_INTR_COAL_TIMEOUT_EN_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_VENDOR_CQE_CNTRL1_0_VENDOR_INTR_COAL_TIMEOUT_EN_SHIFT)
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_VENDOR_INTR_COAL_TIMEOUT_EN_RANGE                   31:31
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_VENDOR_INTR_COAL_TIMEOUT_EN_WOFFSET                 0x0
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_VENDOR_INTR_COAL_TIMEOUT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_VENDOR_INTR_COAL_TIMEOUT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_VENDOR_INTR_COAL_TIMEOUT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_VENDOR_INTR_COAL_TIMEOUT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_VENDOR_INTR_COAL_TIMEOUT_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_VENDOR_INTR_COAL_TIMEOUT_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SDMMCAB_VENDOR_CQE_CNTRL1_0_VENDOR_INTR_COAL_TIMEOUT_VAL_SHIFT                  _MK_SHIFT_CONST(0)
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_VENDOR_INTR_COAL_TIMEOUT_VAL_FIELD                  _MK_FIELD_CONST(0x7fffffff, SDMMCAB_VENDOR_CQE_CNTRL1_0_VENDOR_INTR_COAL_TIMEOUT_VAL_SHIFT)
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_VENDOR_INTR_COAL_TIMEOUT_VAL_RANGE                  30:0
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_VENDOR_INTR_COAL_TIMEOUT_VAL_WOFFSET                        0x0
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_VENDOR_INTR_COAL_TIMEOUT_VAL_DEFAULT                        _MK_MASK_CONST(0x7fffffff)
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_VENDOR_INTR_COAL_TIMEOUT_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x7fffffff)
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_VENDOR_INTR_COAL_TIMEOUT_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_VENDOR_INTR_COAL_TIMEOUT_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_VENDOR_INTR_COAL_TIMEOUT_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_VENDOR_CQE_CNTRL1_0_VENDOR_INTR_COAL_TIMEOUT_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register SDMMCAB_CQE_CQVER_0
#define SDMMCAB_CQE_CQVER_0                     _MK_ADDR_CONST(0xf000)
#define SDMMCAB_CQE_CQVER_0_SECURE                      0x0
#define SDMMCAB_CQE_CQVER_0_DUAL                        0x0
#define SDMMCAB_CQE_CQVER_0_SCR                         0
#define SDMMCAB_CQE_CQVER_0_WORD_COUNT                  0x1
#define SDMMCAB_CQE_CQVER_0_RESET_VAL                   _MK_MASK_CONST(0x510)
#define SDMMCAB_CQE_CQVER_0_RESET_MASK                  _MK_MASK_CONST(0xfff)
#define SDMMCAB_CQE_CQVER_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQVER_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQVER_0_READ_MASK                   _MK_MASK_CONST(0xfff)
#define SDMMCAB_CQE_CQVER_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQVER_0_EMMC_MAJOR_VER_SHIFT                        _MK_SHIFT_CONST(8)
#define SDMMCAB_CQE_CQVER_0_EMMC_MAJOR_VER_FIELD                        _MK_FIELD_CONST(0xf, SDMMCAB_CQE_CQVER_0_EMMC_MAJOR_VER_SHIFT)
#define SDMMCAB_CQE_CQVER_0_EMMC_MAJOR_VER_RANGE                        11:8
#define SDMMCAB_CQE_CQVER_0_EMMC_MAJOR_VER_WOFFSET                      0x0
#define SDMMCAB_CQE_CQVER_0_EMMC_MAJOR_VER_DEFAULT                      _MK_MASK_CONST(0x5)
#define SDMMCAB_CQE_CQVER_0_EMMC_MAJOR_VER_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define SDMMCAB_CQE_CQVER_0_EMMC_MAJOR_VER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQVER_0_EMMC_MAJOR_VER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQVER_0_EMMC_MAJOR_VER_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQVER_0_EMMC_MAJOR_VER_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SDMMCAB_CQE_CQVER_0_EMMC_MINOR_VER_SHIFT                        _MK_SHIFT_CONST(4)
#define SDMMCAB_CQE_CQVER_0_EMMC_MINOR_VER_FIELD                        _MK_FIELD_CONST(0xf, SDMMCAB_CQE_CQVER_0_EMMC_MINOR_VER_SHIFT)
#define SDMMCAB_CQE_CQVER_0_EMMC_MINOR_VER_RANGE                        7:4
#define SDMMCAB_CQE_CQVER_0_EMMC_MINOR_VER_WOFFSET                      0x0
#define SDMMCAB_CQE_CQVER_0_EMMC_MINOR_VER_DEFAULT                      _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQVER_0_EMMC_MINOR_VER_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define SDMMCAB_CQE_CQVER_0_EMMC_MINOR_VER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQVER_0_EMMC_MINOR_VER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQVER_0_EMMC_MINOR_VER_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQVER_0_EMMC_MINOR_VER_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SDMMCAB_CQE_CQVER_0_EMMC_VER_SUFFIX_SHIFT                       _MK_SHIFT_CONST(0)
#define SDMMCAB_CQE_CQVER_0_EMMC_VER_SUFFIX_FIELD                       _MK_FIELD_CONST(0xf, SDMMCAB_CQE_CQVER_0_EMMC_VER_SUFFIX_SHIFT)
#define SDMMCAB_CQE_CQVER_0_EMMC_VER_SUFFIX_RANGE                       3:0
#define SDMMCAB_CQE_CQVER_0_EMMC_VER_SUFFIX_WOFFSET                     0x0
#define SDMMCAB_CQE_CQVER_0_EMMC_VER_SUFFIX_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQVER_0_EMMC_VER_SUFFIX_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define SDMMCAB_CQE_CQVER_0_EMMC_VER_SUFFIX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQVER_0_EMMC_VER_SUFFIX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQVER_0_EMMC_VER_SUFFIX_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQVER_0_EMMC_VER_SUFFIX_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)


// Register SDMMCAB_CQE_CQCAP_0
#define SDMMCAB_CQE_CQCAP_0                     _MK_ADDR_CONST(0xf004)
#define SDMMCAB_CQE_CQCAP_0_SECURE                      0x0
#define SDMMCAB_CQE_CQCAP_0_DUAL                        0x0
#define SDMMCAB_CQE_CQCAP_0_SCR                         0
#define SDMMCAB_CQE_CQCAP_0_WORD_COUNT                  0x1
#define SDMMCAB_CQE_CQCAP_0_RESET_VAL                   _MK_MASK_CONST(0x20c8)
#define SDMMCAB_CQE_CQCAP_0_RESET_MASK                  _MK_MASK_CONST(0xf3ff)
#define SDMMCAB_CQE_CQCAP_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCAP_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCAP_0_READ_MASK                   _MK_MASK_CONST(0xf3ff)
#define SDMMCAB_CQE_CQCAP_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCAP_0_ITC_FREQ_MUL_SHIFT                  _MK_SHIFT_CONST(12)
#define SDMMCAB_CQE_CQCAP_0_ITC_FREQ_MUL_FIELD                  _MK_FIELD_CONST(0xf, SDMMCAB_CQE_CQCAP_0_ITC_FREQ_MUL_SHIFT)
#define SDMMCAB_CQE_CQCAP_0_ITC_FREQ_MUL_RANGE                  15:12
#define SDMMCAB_CQE_CQCAP_0_ITC_FREQ_MUL_WOFFSET                        0x0
#define SDMMCAB_CQE_CQCAP_0_ITC_FREQ_MUL_DEFAULT                        _MK_MASK_CONST(0x2)
#define SDMMCAB_CQE_CQCAP_0_ITC_FREQ_MUL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define SDMMCAB_CQE_CQCAP_0_ITC_FREQ_MUL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCAP_0_ITC_FREQ_MUL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCAP_0_ITC_FREQ_MUL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCAP_0_ITC_FREQ_MUL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SDMMCAB_CQE_CQCAP_0_ITC_FREQ_VAL_SHIFT                  _MK_SHIFT_CONST(0)
#define SDMMCAB_CQE_CQCAP_0_ITC_FREQ_VAL_FIELD                  _MK_FIELD_CONST(0x3ff, SDMMCAB_CQE_CQCAP_0_ITC_FREQ_VAL_SHIFT)
#define SDMMCAB_CQE_CQCAP_0_ITC_FREQ_VAL_RANGE                  9:0
#define SDMMCAB_CQE_CQCAP_0_ITC_FREQ_VAL_WOFFSET                        0x0
#define SDMMCAB_CQE_CQCAP_0_ITC_FREQ_VAL_DEFAULT                        _MK_MASK_CONST(0xc8)
#define SDMMCAB_CQE_CQCAP_0_ITC_FREQ_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
#define SDMMCAB_CQE_CQCAP_0_ITC_FREQ_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCAP_0_ITC_FREQ_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCAP_0_ITC_FREQ_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCAP_0_ITC_FREQ_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register SDMMCAB_CQE_CQCFG_0
#define SDMMCAB_CQE_CQCFG_0                     _MK_ADDR_CONST(0xf008)
#define SDMMCAB_CQE_CQCFG_0_SECURE                      0x0
#define SDMMCAB_CQE_CQCFG_0_DUAL                        0x0
#define SDMMCAB_CQE_CQCFG_0_SCR                         0
#define SDMMCAB_CQE_CQCFG_0_WORD_COUNT                  0x1
#define SDMMCAB_CQE_CQCFG_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCFG_0_RESET_MASK                  _MK_MASK_CONST(0x1101)
#define SDMMCAB_CQE_CQCFG_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCFG_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCFG_0_READ_MASK                   _MK_MASK_CONST(0x1101)
#define SDMMCAB_CQE_CQCFG_0_WRITE_MASK                  _MK_MASK_CONST(0x1101)
#define SDMMCAB_CQE_CQCFG_0_DCMD_EN_SHIFT                       _MK_SHIFT_CONST(12)
#define SDMMCAB_CQE_CQCFG_0_DCMD_EN_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_CQE_CQCFG_0_DCMD_EN_SHIFT)
#define SDMMCAB_CQE_CQCFG_0_DCMD_EN_RANGE                       12:12
#define SDMMCAB_CQE_CQCFG_0_DCMD_EN_WOFFSET                     0x0
#define SDMMCAB_CQE_CQCFG_0_DCMD_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCFG_0_DCMD_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQCFG_0_DCMD_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCFG_0_DCMD_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCFG_0_DCMD_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCFG_0_DCMD_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SDMMCAB_CQE_CQCFG_0_TASK_DESCR_SIZE_SHIFT                       _MK_SHIFT_CONST(8)
#define SDMMCAB_CQE_CQCFG_0_TASK_DESCR_SIZE_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_CQE_CQCFG_0_TASK_DESCR_SIZE_SHIFT)
#define SDMMCAB_CQE_CQCFG_0_TASK_DESCR_SIZE_RANGE                       8:8
#define SDMMCAB_CQE_CQCFG_0_TASK_DESCR_SIZE_WOFFSET                     0x0
#define SDMMCAB_CQE_CQCFG_0_TASK_DESCR_SIZE_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCFG_0_TASK_DESCR_SIZE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQCFG_0_TASK_DESCR_SIZE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCFG_0_TASK_DESCR_SIZE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCFG_0_TASK_DESCR_SIZE_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCFG_0_TASK_DESCR_SIZE_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SDMMCAB_CQE_CQCFG_0_CQ_EN_SHIFT                 _MK_SHIFT_CONST(0)
#define SDMMCAB_CQE_CQCFG_0_CQ_EN_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_CQE_CQCFG_0_CQ_EN_SHIFT)
#define SDMMCAB_CQE_CQCFG_0_CQ_EN_RANGE                 0:0
#define SDMMCAB_CQE_CQCFG_0_CQ_EN_WOFFSET                       0x0
#define SDMMCAB_CQE_CQCFG_0_CQ_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCFG_0_CQ_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQCFG_0_CQ_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCFG_0_CQ_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCFG_0_CQ_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCFG_0_CQ_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQCFG_0_CQ_EN__PROD_C_CQE_ENABLED                   _MK_ENUM_CONST(1)
#define SDMMCAB_CQE_CQCFG_0_CQ_EN__PROD_C_CQE_DISABLED                  _MK_ENUM_CONST(0)


// Register SDMMCAB_CQE_CQCTL_0
#define SDMMCAB_CQE_CQCTL_0                     _MK_ADDR_CONST(0xf00c)
#define SDMMCAB_CQE_CQCTL_0_SECURE                      0x0
#define SDMMCAB_CQE_CQCTL_0_DUAL                        0x0
#define SDMMCAB_CQE_CQCTL_0_SCR                         0
#define SDMMCAB_CQE_CQCTL_0_WORD_COUNT                  0x1
#define SDMMCAB_CQE_CQCTL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCTL_0_RESET_MASK                  _MK_MASK_CONST(0x101)
#define SDMMCAB_CQE_CQCTL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCTL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCTL_0_READ_MASK                   _MK_MASK_CONST(0x101)
#define SDMMCAB_CQE_CQCTL_0_WRITE_MASK                  _MK_MASK_CONST(0x101)
#define SDMMCAB_CQE_CQCTL_0_CLR_ALL_TASKS_SHIFT                 _MK_SHIFT_CONST(8)
#define SDMMCAB_CQE_CQCTL_0_CLR_ALL_TASKS_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_CQE_CQCTL_0_CLR_ALL_TASKS_SHIFT)
#define SDMMCAB_CQE_CQCTL_0_CLR_ALL_TASKS_RANGE                 8:8
#define SDMMCAB_CQE_CQCTL_0_CLR_ALL_TASKS_WOFFSET                       0x0
#define SDMMCAB_CQE_CQCTL_0_CLR_ALL_TASKS_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCTL_0_CLR_ALL_TASKS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQCTL_0_CLR_ALL_TASKS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCTL_0_CLR_ALL_TASKS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCTL_0_CLR_ALL_TASKS_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCTL_0_CLR_ALL_TASKS_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SDMMCAB_CQE_CQCTL_0_HALT_SHIFT                  _MK_SHIFT_CONST(0)
#define SDMMCAB_CQE_CQCTL_0_HALT_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_CQE_CQCTL_0_HALT_SHIFT)
#define SDMMCAB_CQE_CQCTL_0_HALT_RANGE                  0:0
#define SDMMCAB_CQE_CQCTL_0_HALT_WOFFSET                        0x0
#define SDMMCAB_CQE_CQCTL_0_HALT_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCTL_0_HALT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQCTL_0_HALT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCTL_0_HALT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCTL_0_HALT_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCTL_0_HALT_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register SDMMCAB_CQE_CQIS_0
#define SDMMCAB_CQE_CQIS_0                      _MK_ADDR_CONST(0xf010)
#define SDMMCAB_CQE_CQIS_0_SECURE                       0x0
#define SDMMCAB_CQE_CQIS_0_DUAL                         0x0
#define SDMMCAB_CQE_CQIS_0_SCR                  0
#define SDMMCAB_CQE_CQIS_0_WORD_COUNT                   0x1
#define SDMMCAB_CQE_CQIS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIS_0_RESET_MASK                   _MK_MASK_CONST(0xf)
#define SDMMCAB_CQE_CQIS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIS_0_READ_MASK                    _MK_MASK_CONST(0xf)
#define SDMMCAB_CQE_CQIS_0_WRITE_MASK                   _MK_MASK_CONST(0xf)
#define SDMMCAB_CQE_CQIS_0_TASK_CLR_INTR_SHIFT                  _MK_SHIFT_CONST(3)
#define SDMMCAB_CQE_CQIS_0_TASK_CLR_INTR_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_CQE_CQIS_0_TASK_CLR_INTR_SHIFT)
#define SDMMCAB_CQE_CQIS_0_TASK_CLR_INTR_RANGE                  3:3
#define SDMMCAB_CQE_CQIS_0_TASK_CLR_INTR_WOFFSET                        0x0
#define SDMMCAB_CQE_CQIS_0_TASK_CLR_INTR_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIS_0_TASK_CLR_INTR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQIS_0_TASK_CLR_INTR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIS_0_TASK_CLR_INTR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIS_0_TASK_CLR_INTR_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIS_0_TASK_CLR_INTR_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SDMMCAB_CQE_CQIS_0_RESP_ERR_DETECT_INTR_SHIFT                   _MK_SHIFT_CONST(2)
#define SDMMCAB_CQE_CQIS_0_RESP_ERR_DETECT_INTR_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_CQE_CQIS_0_RESP_ERR_DETECT_INTR_SHIFT)
#define SDMMCAB_CQE_CQIS_0_RESP_ERR_DETECT_INTR_RANGE                   2:2
#define SDMMCAB_CQE_CQIS_0_RESP_ERR_DETECT_INTR_WOFFSET                 0x0
#define SDMMCAB_CQE_CQIS_0_RESP_ERR_DETECT_INTR_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIS_0_RESP_ERR_DETECT_INTR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQIS_0_RESP_ERR_DETECT_INTR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIS_0_RESP_ERR_DETECT_INTR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIS_0_RESP_ERR_DETECT_INTR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIS_0_RESP_ERR_DETECT_INTR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SDMMCAB_CQE_CQIS_0_TASK_COMPLETE_INTR_SHIFT                     _MK_SHIFT_CONST(1)
#define SDMMCAB_CQE_CQIS_0_TASK_COMPLETE_INTR_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_CQE_CQIS_0_TASK_COMPLETE_INTR_SHIFT)
#define SDMMCAB_CQE_CQIS_0_TASK_COMPLETE_INTR_RANGE                     1:1
#define SDMMCAB_CQE_CQIS_0_TASK_COMPLETE_INTR_WOFFSET                   0x0
#define SDMMCAB_CQE_CQIS_0_TASK_COMPLETE_INTR_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIS_0_TASK_COMPLETE_INTR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQIS_0_TASK_COMPLETE_INTR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIS_0_TASK_COMPLETE_INTR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIS_0_TASK_COMPLETE_INTR_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIS_0_TASK_COMPLETE_INTR_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SDMMCAB_CQE_CQIS_0_HALT_COMPLETE_INTR_SHIFT                     _MK_SHIFT_CONST(0)
#define SDMMCAB_CQE_CQIS_0_HALT_COMPLETE_INTR_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_CQE_CQIS_0_HALT_COMPLETE_INTR_SHIFT)
#define SDMMCAB_CQE_CQIS_0_HALT_COMPLETE_INTR_RANGE                     0:0
#define SDMMCAB_CQE_CQIS_0_HALT_COMPLETE_INTR_WOFFSET                   0x0
#define SDMMCAB_CQE_CQIS_0_HALT_COMPLETE_INTR_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIS_0_HALT_COMPLETE_INTR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQIS_0_HALT_COMPLETE_INTR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIS_0_HALT_COMPLETE_INTR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIS_0_HALT_COMPLETE_INTR_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIS_0_HALT_COMPLETE_INTR_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register SDMMCAB_CQE_CQISTE_0
#define SDMMCAB_CQE_CQISTE_0                    _MK_ADDR_CONST(0xf014)
#define SDMMCAB_CQE_CQISTE_0_SECURE                     0x0
#define SDMMCAB_CQE_CQISTE_0_DUAL                       0x0
#define SDMMCAB_CQE_CQISTE_0_SCR                        0
#define SDMMCAB_CQE_CQISTE_0_WORD_COUNT                         0x1
#define SDMMCAB_CQE_CQISTE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISTE_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define SDMMCAB_CQE_CQISTE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISTE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISTE_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define SDMMCAB_CQE_CQISTE_0_WRITE_MASK                         _MK_MASK_CONST(0xf)
#define SDMMCAB_CQE_CQISTE_0_TASK_CLR_INTR_STATUS_EN_SHIFT                      _MK_SHIFT_CONST(3)
#define SDMMCAB_CQE_CQISTE_0_TASK_CLR_INTR_STATUS_EN_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_CQE_CQISTE_0_TASK_CLR_INTR_STATUS_EN_SHIFT)
#define SDMMCAB_CQE_CQISTE_0_TASK_CLR_INTR_STATUS_EN_RANGE                      3:3
#define SDMMCAB_CQE_CQISTE_0_TASK_CLR_INTR_STATUS_EN_WOFFSET                    0x0
#define SDMMCAB_CQE_CQISTE_0_TASK_CLR_INTR_STATUS_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISTE_0_TASK_CLR_INTR_STATUS_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQISTE_0_TASK_CLR_INTR_STATUS_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISTE_0_TASK_CLR_INTR_STATUS_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISTE_0_TASK_CLR_INTR_STATUS_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISTE_0_TASK_CLR_INTR_STATUS_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SDMMCAB_CQE_CQISTE_0_RESP_ERR_DETECT_INTR_STATUS_EN_SHIFT                       _MK_SHIFT_CONST(2)
#define SDMMCAB_CQE_CQISTE_0_RESP_ERR_DETECT_INTR_STATUS_EN_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_CQE_CQISTE_0_RESP_ERR_DETECT_INTR_STATUS_EN_SHIFT)
#define SDMMCAB_CQE_CQISTE_0_RESP_ERR_DETECT_INTR_STATUS_EN_RANGE                       2:2
#define SDMMCAB_CQE_CQISTE_0_RESP_ERR_DETECT_INTR_STATUS_EN_WOFFSET                     0x0
#define SDMMCAB_CQE_CQISTE_0_RESP_ERR_DETECT_INTR_STATUS_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISTE_0_RESP_ERR_DETECT_INTR_STATUS_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQISTE_0_RESP_ERR_DETECT_INTR_STATUS_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISTE_0_RESP_ERR_DETECT_INTR_STATUS_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISTE_0_RESP_ERR_DETECT_INTR_STATUS_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISTE_0_RESP_ERR_DETECT_INTR_STATUS_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SDMMCAB_CQE_CQISTE_0_TASK_COMPLETE_INTR_STATUS_EN_SHIFT                 _MK_SHIFT_CONST(1)
#define SDMMCAB_CQE_CQISTE_0_TASK_COMPLETE_INTR_STATUS_EN_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_CQE_CQISTE_0_TASK_COMPLETE_INTR_STATUS_EN_SHIFT)
#define SDMMCAB_CQE_CQISTE_0_TASK_COMPLETE_INTR_STATUS_EN_RANGE                 1:1
#define SDMMCAB_CQE_CQISTE_0_TASK_COMPLETE_INTR_STATUS_EN_WOFFSET                       0x0
#define SDMMCAB_CQE_CQISTE_0_TASK_COMPLETE_INTR_STATUS_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISTE_0_TASK_COMPLETE_INTR_STATUS_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQISTE_0_TASK_COMPLETE_INTR_STATUS_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISTE_0_TASK_COMPLETE_INTR_STATUS_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISTE_0_TASK_COMPLETE_INTR_STATUS_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISTE_0_TASK_COMPLETE_INTR_STATUS_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SDMMCAB_CQE_CQISTE_0_HALT_COMPLETE_INTR_STATUS_EN_SHIFT                 _MK_SHIFT_CONST(0)
#define SDMMCAB_CQE_CQISTE_0_HALT_COMPLETE_INTR_STATUS_EN_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_CQE_CQISTE_0_HALT_COMPLETE_INTR_STATUS_EN_SHIFT)
#define SDMMCAB_CQE_CQISTE_0_HALT_COMPLETE_INTR_STATUS_EN_RANGE                 0:0
#define SDMMCAB_CQE_CQISTE_0_HALT_COMPLETE_INTR_STATUS_EN_WOFFSET                       0x0
#define SDMMCAB_CQE_CQISTE_0_HALT_COMPLETE_INTR_STATUS_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISTE_0_HALT_COMPLETE_INTR_STATUS_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQISTE_0_HALT_COMPLETE_INTR_STATUS_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISTE_0_HALT_COMPLETE_INTR_STATUS_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISTE_0_HALT_COMPLETE_INTR_STATUS_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISTE_0_HALT_COMPLETE_INTR_STATUS_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register SDMMCAB_CQE_CQISGE_0
#define SDMMCAB_CQE_CQISGE_0                    _MK_ADDR_CONST(0xf018)
#define SDMMCAB_CQE_CQISGE_0_SECURE                     0x0
#define SDMMCAB_CQE_CQISGE_0_DUAL                       0x0
#define SDMMCAB_CQE_CQISGE_0_SCR                        0
#define SDMMCAB_CQE_CQISGE_0_WORD_COUNT                         0x1
#define SDMMCAB_CQE_CQISGE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISGE_0_RESET_MASK                         _MK_MASK_CONST(0xf)
#define SDMMCAB_CQE_CQISGE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISGE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISGE_0_READ_MASK                  _MK_MASK_CONST(0xf)
#define SDMMCAB_CQE_CQISGE_0_WRITE_MASK                         _MK_MASK_CONST(0xf)
#define SDMMCAB_CQE_CQISGE_0_TASK_CLR_INTR_SIGNAL_EN_SHIFT                      _MK_SHIFT_CONST(3)
#define SDMMCAB_CQE_CQISGE_0_TASK_CLR_INTR_SIGNAL_EN_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_CQE_CQISGE_0_TASK_CLR_INTR_SIGNAL_EN_SHIFT)
#define SDMMCAB_CQE_CQISGE_0_TASK_CLR_INTR_SIGNAL_EN_RANGE                      3:3
#define SDMMCAB_CQE_CQISGE_0_TASK_CLR_INTR_SIGNAL_EN_WOFFSET                    0x0
#define SDMMCAB_CQE_CQISGE_0_TASK_CLR_INTR_SIGNAL_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISGE_0_TASK_CLR_INTR_SIGNAL_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQISGE_0_TASK_CLR_INTR_SIGNAL_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISGE_0_TASK_CLR_INTR_SIGNAL_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISGE_0_TASK_CLR_INTR_SIGNAL_EN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISGE_0_TASK_CLR_INTR_SIGNAL_EN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SDMMCAB_CQE_CQISGE_0_RESP_ERR_DETECT_INTR_SIGNAL_EN_SHIFT                       _MK_SHIFT_CONST(2)
#define SDMMCAB_CQE_CQISGE_0_RESP_ERR_DETECT_INTR_SIGNAL_EN_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_CQE_CQISGE_0_RESP_ERR_DETECT_INTR_SIGNAL_EN_SHIFT)
#define SDMMCAB_CQE_CQISGE_0_RESP_ERR_DETECT_INTR_SIGNAL_EN_RANGE                       2:2
#define SDMMCAB_CQE_CQISGE_0_RESP_ERR_DETECT_INTR_SIGNAL_EN_WOFFSET                     0x0
#define SDMMCAB_CQE_CQISGE_0_RESP_ERR_DETECT_INTR_SIGNAL_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISGE_0_RESP_ERR_DETECT_INTR_SIGNAL_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQISGE_0_RESP_ERR_DETECT_INTR_SIGNAL_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISGE_0_RESP_ERR_DETECT_INTR_SIGNAL_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISGE_0_RESP_ERR_DETECT_INTR_SIGNAL_EN_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISGE_0_RESP_ERR_DETECT_INTR_SIGNAL_EN_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SDMMCAB_CQE_CQISGE_0_TASK_COMPLETE_INTR_SIGNAL_EN_SHIFT                 _MK_SHIFT_CONST(1)
#define SDMMCAB_CQE_CQISGE_0_TASK_COMPLETE_INTR_SIGNAL_EN_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_CQE_CQISGE_0_TASK_COMPLETE_INTR_SIGNAL_EN_SHIFT)
#define SDMMCAB_CQE_CQISGE_0_TASK_COMPLETE_INTR_SIGNAL_EN_RANGE                 1:1
#define SDMMCAB_CQE_CQISGE_0_TASK_COMPLETE_INTR_SIGNAL_EN_WOFFSET                       0x0
#define SDMMCAB_CQE_CQISGE_0_TASK_COMPLETE_INTR_SIGNAL_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISGE_0_TASK_COMPLETE_INTR_SIGNAL_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQISGE_0_TASK_COMPLETE_INTR_SIGNAL_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISGE_0_TASK_COMPLETE_INTR_SIGNAL_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISGE_0_TASK_COMPLETE_INTR_SIGNAL_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISGE_0_TASK_COMPLETE_INTR_SIGNAL_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SDMMCAB_CQE_CQISGE_0_HALT_COMPLETE_INTR_SIGNAL_EN_SHIFT                 _MK_SHIFT_CONST(0)
#define SDMMCAB_CQE_CQISGE_0_HALT_COMPLETE_INTR_SIGNAL_EN_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_CQE_CQISGE_0_HALT_COMPLETE_INTR_SIGNAL_EN_SHIFT)
#define SDMMCAB_CQE_CQISGE_0_HALT_COMPLETE_INTR_SIGNAL_EN_RANGE                 0:0
#define SDMMCAB_CQE_CQISGE_0_HALT_COMPLETE_INTR_SIGNAL_EN_WOFFSET                       0x0
#define SDMMCAB_CQE_CQISGE_0_HALT_COMPLETE_INTR_SIGNAL_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISGE_0_HALT_COMPLETE_INTR_SIGNAL_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQISGE_0_HALT_COMPLETE_INTR_SIGNAL_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISGE_0_HALT_COMPLETE_INTR_SIGNAL_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISGE_0_HALT_COMPLETE_INTR_SIGNAL_EN_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQISGE_0_HALT_COMPLETE_INTR_SIGNAL_EN_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)


// Register SDMMCAB_CQE_CQIC_0
#define SDMMCAB_CQE_CQIC_0                      _MK_ADDR_CONST(0xf01c)
#define SDMMCAB_CQE_CQIC_0_SECURE                       0x0
#define SDMMCAB_CQE_CQIC_0_DUAL                         0x0
#define SDMMCAB_CQE_CQIC_0_SCR                  0
#define SDMMCAB_CQE_CQIC_0_WORD_COUNT                   0x1
#define SDMMCAB_CQE_CQIC_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_RESET_MASK                   _MK_MASK_CONST(0x80119fff)
#define SDMMCAB_CQE_CQIC_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_READ_MASK                    _MK_MASK_CONST(0x80119fff)
#define SDMMCAB_CQE_CQIC_0_WRITE_MASK                   _MK_MASK_CONST(0x80019fff)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_EN_SHIFT                   _MK_SHIFT_CONST(31)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_EN_FIELD                   _MK_FIELD_CONST(0x1, SDMMCAB_CQE_CQIC_0_INTR_COAL_EN_SHIFT)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_EN_RANGE                   31:31
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_EN_WOFFSET                 0x0
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_EN_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_EN_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)

#define SDMMCAB_CQE_CQIC_0_INTR_COAL_STATUS_SHIFT                       _MK_SHIFT_CONST(20)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_STATUS_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_CQE_CQIC_0_INTR_COAL_STATUS_SHIFT)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_STATUS_RANGE                       20:20
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_STATUS_WOFFSET                     0x0
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_STATUS_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_STATUS_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_TIMER_RST_SHIFT                       _MK_SHIFT_CONST(16)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_TIMER_RST_FIELD                       _MK_FIELD_CONST(0x1, SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_TIMER_RST_SHIFT)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_TIMER_RST_RANGE                       16:16
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_TIMER_RST_WOFFSET                     0x0
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_TIMER_RST_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_TIMER_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_TIMER_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_TIMER_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_TIMER_RST_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_TIMER_RST_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_TH_WEN_SHIFT                  _MK_SHIFT_CONST(15)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_TH_WEN_FIELD                  _MK_FIELD_CONST(0x1, SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_TH_WEN_SHIFT)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_TH_WEN_RANGE                  15:15
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_TH_WEN_WOFFSET                        0x0
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_TH_WEN_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_TH_WEN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_TH_WEN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_TH_WEN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_TH_WEN_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_TH_WEN_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)

#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_THRESHOLD_SHIFT                       _MK_SHIFT_CONST(8)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_THRESHOLD_FIELD                       _MK_FIELD_CONST(0x1f, SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_THRESHOLD_SHIFT)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_THRESHOLD_RANGE                       12:8
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_THRESHOLD_WOFFSET                     0x0
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_THRESHOLD_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_THRESHOLD_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_THRESHOLD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_THRESHOLD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_THRESHOLD_PARITY_PROTECTION                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_CNTR_THRESHOLD_PLATFORM_DEPENDENT                  _MK_MASK_CONST(0x1)

#define SDMMCAB_CQE_CQIC_0_INTR_COAL_TIMEOUT_VAL_WEN_SHIFT                      _MK_SHIFT_CONST(7)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_TIMEOUT_VAL_WEN_FIELD                      _MK_FIELD_CONST(0x1, SDMMCAB_CQE_CQIC_0_INTR_COAL_TIMEOUT_VAL_WEN_SHIFT)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_TIMEOUT_VAL_WEN_RANGE                      7:7
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_TIMEOUT_VAL_WEN_WOFFSET                    0x0
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_TIMEOUT_VAL_WEN_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_TIMEOUT_VAL_WEN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_TIMEOUT_VAL_WEN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_TIMEOUT_VAL_WEN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_TIMEOUT_VAL_WEN_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_TIMEOUT_VAL_WEN_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)

#define SDMMCAB_CQE_CQIC_0_INTR_COAL_TIMEOUT_VAL_SHIFT                  _MK_SHIFT_CONST(0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_TIMEOUT_VAL_FIELD                  _MK_FIELD_CONST(0x7f, SDMMCAB_CQE_CQIC_0_INTR_COAL_TIMEOUT_VAL_SHIFT)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_TIMEOUT_VAL_RANGE                  6:0
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_TIMEOUT_VAL_WOFFSET                        0x0
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_TIMEOUT_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_TIMEOUT_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x7f)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_TIMEOUT_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_TIMEOUT_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_TIMEOUT_VAL_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQIC_0_INTR_COAL_TIMEOUT_VAL_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register SDMMCAB_CQE_CQTDLBA_0
#define SDMMCAB_CQE_CQTDLBA_0                   _MK_ADDR_CONST(0xf020)
#define SDMMCAB_CQE_CQTDLBA_0_SECURE                    0x0
#define SDMMCAB_CQE_CQTDLBA_0_DUAL                      0x0
#define SDMMCAB_CQE_CQTDLBA_0_SCR                       0
#define SDMMCAB_CQE_CQTDLBA_0_WORD_COUNT                        0x1
#define SDMMCAB_CQE_CQTDLBA_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTDLBA_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQTDLBA_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTDLBA_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTDLBA_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQTDLBA_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQTDLBA_0_TASK_DESCR_LIST_BASE_ADDR_SHIFT                   _MK_SHIFT_CONST(0)
#define SDMMCAB_CQE_CQTDLBA_0_TASK_DESCR_LIST_BASE_ADDR_FIELD                   _MK_FIELD_CONST(0xffffffff, SDMMCAB_CQE_CQTDLBA_0_TASK_DESCR_LIST_BASE_ADDR_SHIFT)
#define SDMMCAB_CQE_CQTDLBA_0_TASK_DESCR_LIST_BASE_ADDR_RANGE                   31:0
#define SDMMCAB_CQE_CQTDLBA_0_TASK_DESCR_LIST_BASE_ADDR_WOFFSET                 0x0
#define SDMMCAB_CQE_CQTDLBA_0_TASK_DESCR_LIST_BASE_ADDR_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTDLBA_0_TASK_DESCR_LIST_BASE_ADDR_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQTDLBA_0_TASK_DESCR_LIST_BASE_ADDR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTDLBA_0_TASK_DESCR_LIST_BASE_ADDR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTDLBA_0_TASK_DESCR_LIST_BASE_ADDR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTDLBA_0_TASK_DESCR_LIST_BASE_ADDR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register SDMMCAB_CQE_CQTDLBAU_0
#define SDMMCAB_CQE_CQTDLBAU_0                  _MK_ADDR_CONST(0xf024)
#define SDMMCAB_CQE_CQTDLBAU_0_SECURE                   0x0
#define SDMMCAB_CQE_CQTDLBAU_0_DUAL                     0x0
#define SDMMCAB_CQE_CQTDLBAU_0_SCR                      0
#define SDMMCAB_CQE_CQTDLBAU_0_WORD_COUNT                       0x1
#define SDMMCAB_CQE_CQTDLBAU_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTDLBAU_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQTDLBAU_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTDLBAU_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTDLBAU_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQTDLBAU_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQTDLBAU_0_TASK_DESCR_LIST_BASE_UPPER_ADDR_SHIFT                    _MK_SHIFT_CONST(0)
#define SDMMCAB_CQE_CQTDLBAU_0_TASK_DESCR_LIST_BASE_UPPER_ADDR_FIELD                    _MK_FIELD_CONST(0xffffffff, SDMMCAB_CQE_CQTDLBAU_0_TASK_DESCR_LIST_BASE_UPPER_ADDR_SHIFT)
#define SDMMCAB_CQE_CQTDLBAU_0_TASK_DESCR_LIST_BASE_UPPER_ADDR_RANGE                    31:0
#define SDMMCAB_CQE_CQTDLBAU_0_TASK_DESCR_LIST_BASE_UPPER_ADDR_WOFFSET                  0x0
#define SDMMCAB_CQE_CQTDLBAU_0_TASK_DESCR_LIST_BASE_UPPER_ADDR_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTDLBAU_0_TASK_DESCR_LIST_BASE_UPPER_ADDR_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQTDLBAU_0_TASK_DESCR_LIST_BASE_UPPER_ADDR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTDLBAU_0_TASK_DESCR_LIST_BASE_UPPER_ADDR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTDLBAU_0_TASK_DESCR_LIST_BASE_UPPER_ADDR_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTDLBAU_0_TASK_DESCR_LIST_BASE_UPPER_ADDR_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register SDMMCAB_CQE_CQTDBR_0
#define SDMMCAB_CQE_CQTDBR_0                    _MK_ADDR_CONST(0xf028)
#define SDMMCAB_CQE_CQTDBR_0_SECURE                     0x0
#define SDMMCAB_CQE_CQTDBR_0_DUAL                       0x0
#define SDMMCAB_CQE_CQTDBR_0_SCR                        0
#define SDMMCAB_CQE_CQTDBR_0_WORD_COUNT                         0x1
#define SDMMCAB_CQE_CQTDBR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTDBR_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQTDBR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTDBR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTDBR_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQTDBR_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQTDBR_0_TASK_DOORBELL_SHIFT                        _MK_SHIFT_CONST(0)
#define SDMMCAB_CQE_CQTDBR_0_TASK_DOORBELL_FIELD                        _MK_FIELD_CONST(0xffffffff, SDMMCAB_CQE_CQTDBR_0_TASK_DOORBELL_SHIFT)
#define SDMMCAB_CQE_CQTDBR_0_TASK_DOORBELL_RANGE                        31:0
#define SDMMCAB_CQE_CQTDBR_0_TASK_DOORBELL_WOFFSET                      0x0
#define SDMMCAB_CQE_CQTDBR_0_TASK_DOORBELL_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTDBR_0_TASK_DOORBELL_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQTDBR_0_TASK_DOORBELL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTDBR_0_TASK_DOORBELL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTDBR_0_TASK_DOORBELL_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTDBR_0_TASK_DOORBELL_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)


// Register SDMMCAB_CQE_CQTCN_0
#define SDMMCAB_CQE_CQTCN_0                     _MK_ADDR_CONST(0xf02c)
#define SDMMCAB_CQE_CQTCN_0_SECURE                      0x0
#define SDMMCAB_CQE_CQTCN_0_DUAL                        0x0
#define SDMMCAB_CQE_CQTCN_0_SCR                         0
#define SDMMCAB_CQE_CQTCN_0_WORD_COUNT                  0x1
#define SDMMCAB_CQE_CQTCN_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTCN_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQTCN_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTCN_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTCN_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQTCN_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQTCN_0_TASK_COMPLETE_NOTIFICATION_SHIFT                    _MK_SHIFT_CONST(0)
#define SDMMCAB_CQE_CQTCN_0_TASK_COMPLETE_NOTIFICATION_FIELD                    _MK_FIELD_CONST(0xffffffff, SDMMCAB_CQE_CQTCN_0_TASK_COMPLETE_NOTIFICATION_SHIFT)
#define SDMMCAB_CQE_CQTCN_0_TASK_COMPLETE_NOTIFICATION_RANGE                    31:0
#define SDMMCAB_CQE_CQTCN_0_TASK_COMPLETE_NOTIFICATION_WOFFSET                  0x0
#define SDMMCAB_CQE_CQTCN_0_TASK_COMPLETE_NOTIFICATION_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTCN_0_TASK_COMPLETE_NOTIFICATION_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQTCN_0_TASK_COMPLETE_NOTIFICATION_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTCN_0_TASK_COMPLETE_NOTIFICATION_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTCN_0_TASK_COMPLETE_NOTIFICATION_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTCN_0_TASK_COMPLETE_NOTIFICATION_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register SDMMCAB_CQE_CQDQS_0
#define SDMMCAB_CQE_CQDQS_0                     _MK_ADDR_CONST(0xf030)
#define SDMMCAB_CQE_CQDQS_0_SECURE                      0x0
#define SDMMCAB_CQE_CQDQS_0_DUAL                        0x0
#define SDMMCAB_CQE_CQDQS_0_SCR                         0
#define SDMMCAB_CQE_CQDQS_0_WORD_COUNT                  0x1
#define SDMMCAB_CQE_CQDQS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQDQS_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQDQS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQDQS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQDQS_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQDQS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQDQS_0_DEVICE_QUEUE_STATUS_SHIFT                   _MK_SHIFT_CONST(0)
#define SDMMCAB_CQE_CQDQS_0_DEVICE_QUEUE_STATUS_FIELD                   _MK_FIELD_CONST(0xffffffff, SDMMCAB_CQE_CQDQS_0_DEVICE_QUEUE_STATUS_SHIFT)
#define SDMMCAB_CQE_CQDQS_0_DEVICE_QUEUE_STATUS_RANGE                   31:0
#define SDMMCAB_CQE_CQDQS_0_DEVICE_QUEUE_STATUS_WOFFSET                 0x0
#define SDMMCAB_CQE_CQDQS_0_DEVICE_QUEUE_STATUS_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQDQS_0_DEVICE_QUEUE_STATUS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQDQS_0_DEVICE_QUEUE_STATUS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQDQS_0_DEVICE_QUEUE_STATUS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQDQS_0_DEVICE_QUEUE_STATUS_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQDQS_0_DEVICE_QUEUE_STATUS_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register SDMMCAB_CQE_CQDPT_0
#define SDMMCAB_CQE_CQDPT_0                     _MK_ADDR_CONST(0xf034)
#define SDMMCAB_CQE_CQDPT_0_SECURE                      0x0
#define SDMMCAB_CQE_CQDPT_0_DUAL                        0x0
#define SDMMCAB_CQE_CQDPT_0_SCR                         0
#define SDMMCAB_CQE_CQDPT_0_WORD_COUNT                  0x1
#define SDMMCAB_CQE_CQDPT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQDPT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQDPT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQDPT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQDPT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQDPT_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQDPT_0_DEVICE_PENDING_TASKS_SHIFT                  _MK_SHIFT_CONST(0)
#define SDMMCAB_CQE_CQDPT_0_DEVICE_PENDING_TASKS_FIELD                  _MK_FIELD_CONST(0xffffffff, SDMMCAB_CQE_CQDPT_0_DEVICE_PENDING_TASKS_SHIFT)
#define SDMMCAB_CQE_CQDPT_0_DEVICE_PENDING_TASKS_RANGE                  31:0
#define SDMMCAB_CQE_CQDPT_0_DEVICE_PENDING_TASKS_WOFFSET                        0x0
#define SDMMCAB_CQE_CQDPT_0_DEVICE_PENDING_TASKS_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQDPT_0_DEVICE_PENDING_TASKS_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQDPT_0_DEVICE_PENDING_TASKS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQDPT_0_DEVICE_PENDING_TASKS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQDPT_0_DEVICE_PENDING_TASKS_PARITY_PROTECTION                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQDPT_0_DEVICE_PENDING_TASKS_PLATFORM_DEPENDENT                     _MK_MASK_CONST(0x1)


// Register SDMMCAB_CQE_CQTCLR_0
#define SDMMCAB_CQE_CQTCLR_0                    _MK_ADDR_CONST(0xf038)
#define SDMMCAB_CQE_CQTCLR_0_SECURE                     0x0
#define SDMMCAB_CQE_CQTCLR_0_DUAL                       0x0
#define SDMMCAB_CQE_CQTCLR_0_SCR                        0
#define SDMMCAB_CQE_CQTCLR_0_WORD_COUNT                         0x1
#define SDMMCAB_CQE_CQTCLR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTCLR_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQTCLR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTCLR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTCLR_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQTCLR_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQTCLR_0_TASK_CLEAR_SHIFT                   _MK_SHIFT_CONST(0)
#define SDMMCAB_CQE_CQTCLR_0_TASK_CLEAR_FIELD                   _MK_FIELD_CONST(0xffffffff, SDMMCAB_CQE_CQTCLR_0_TASK_CLEAR_SHIFT)
#define SDMMCAB_CQE_CQTCLR_0_TASK_CLEAR_RANGE                   31:0
#define SDMMCAB_CQE_CQTCLR_0_TASK_CLEAR_WOFFSET                 0x0
#define SDMMCAB_CQE_CQTCLR_0_TASK_CLEAR_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTCLR_0_TASK_CLEAR_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQTCLR_0_TASK_CLEAR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTCLR_0_TASK_CLEAR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTCLR_0_TASK_CLEAR_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTCLR_0_TASK_CLEAR_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Reserved address 0xf03c

// Register SDMMCAB_CQE_CQSSC1_0
#define SDMMCAB_CQE_CQSSC1_0                    _MK_ADDR_CONST(0xf040)
#define SDMMCAB_CQE_CQSSC1_0_SECURE                     0x0
#define SDMMCAB_CQE_CQSSC1_0_DUAL                       0x0
#define SDMMCAB_CQE_CQSSC1_0_SCR                        0
#define SDMMCAB_CQE_CQSSC1_0_WORD_COUNT                         0x1
#define SDMMCAB_CQE_CQSSC1_0_RESET_VAL                  _MK_MASK_CONST(0x11000)
#define SDMMCAB_CQE_CQSSC1_0_RESET_MASK                         _MK_MASK_CONST(0xfffff)
#define SDMMCAB_CQE_CQSSC1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQSSC1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQSSC1_0_READ_MASK                  _MK_MASK_CONST(0xfffff)
#define SDMMCAB_CQE_CQSSC1_0_WRITE_MASK                         _MK_MASK_CONST(0xfffff)
#define SDMMCAB_CQE_CQSSC1_0_SQS_CMD_BLK_CNTR_SHIFT                     _MK_SHIFT_CONST(16)
#define SDMMCAB_CQE_CQSSC1_0_SQS_CMD_BLK_CNTR_FIELD                     _MK_FIELD_CONST(0xf, SDMMCAB_CQE_CQSSC1_0_SQS_CMD_BLK_CNTR_SHIFT)
#define SDMMCAB_CQE_CQSSC1_0_SQS_CMD_BLK_CNTR_RANGE                     19:16
#define SDMMCAB_CQE_CQSSC1_0_SQS_CMD_BLK_CNTR_WOFFSET                   0x0
#define SDMMCAB_CQE_CQSSC1_0_SQS_CMD_BLK_CNTR_DEFAULT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQSSC1_0_SQS_CMD_BLK_CNTR_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define SDMMCAB_CQE_CQSSC1_0_SQS_CMD_BLK_CNTR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQSSC1_0_SQS_CMD_BLK_CNTR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQSSC1_0_SQS_CMD_BLK_CNTR_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQSSC1_0_SQS_CMD_BLK_CNTR_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SDMMCAB_CQE_CQSSC1_0_SQS_CMD_IDLE_TIMER_SHIFT                   _MK_SHIFT_CONST(0)
#define SDMMCAB_CQE_CQSSC1_0_SQS_CMD_IDLE_TIMER_FIELD                   _MK_FIELD_CONST(0xffff, SDMMCAB_CQE_CQSSC1_0_SQS_CMD_IDLE_TIMER_SHIFT)
#define SDMMCAB_CQE_CQSSC1_0_SQS_CMD_IDLE_TIMER_RANGE                   15:0
#define SDMMCAB_CQE_CQSSC1_0_SQS_CMD_IDLE_TIMER_WOFFSET                 0x0
#define SDMMCAB_CQE_CQSSC1_0_SQS_CMD_IDLE_TIMER_DEFAULT                 _MK_MASK_CONST(0x1000)
#define SDMMCAB_CQE_CQSSC1_0_SQS_CMD_IDLE_TIMER_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define SDMMCAB_CQE_CQSSC1_0_SQS_CMD_IDLE_TIMER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQSSC1_0_SQS_CMD_IDLE_TIMER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQSSC1_0_SQS_CMD_IDLE_TIMER_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQSSC1_0_SQS_CMD_IDLE_TIMER_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Register SDMMCAB_CQE_CQSSC2_0
#define SDMMCAB_CQE_CQSSC2_0                    _MK_ADDR_CONST(0xf044)
#define SDMMCAB_CQE_CQSSC2_0_SECURE                     0x0
#define SDMMCAB_CQE_CQSSC2_0_DUAL                       0x0
#define SDMMCAB_CQE_CQSSC2_0_SCR                        0
#define SDMMCAB_CQE_CQSSC2_0_WORD_COUNT                         0x1
#define SDMMCAB_CQE_CQSSC2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQSSC2_0_RESET_MASK                         _MK_MASK_CONST(0xffff)
#define SDMMCAB_CQE_CQSSC2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQSSC2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQSSC2_0_READ_MASK                  _MK_MASK_CONST(0xffff)
#define SDMMCAB_CQE_CQSSC2_0_WRITE_MASK                         _MK_MASK_CONST(0xffff)
#define SDMMCAB_CQE_CQSSC2_0_SQS_RCA_SHIFT                      _MK_SHIFT_CONST(0)
#define SDMMCAB_CQE_CQSSC2_0_SQS_RCA_FIELD                      _MK_FIELD_CONST(0xffff, SDMMCAB_CQE_CQSSC2_0_SQS_RCA_SHIFT)
#define SDMMCAB_CQE_CQSSC2_0_SQS_RCA_RANGE                      15:0
#define SDMMCAB_CQE_CQSSC2_0_SQS_RCA_WOFFSET                    0x0
#define SDMMCAB_CQE_CQSSC2_0_SQS_RCA_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQSSC2_0_SQS_RCA_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
#define SDMMCAB_CQE_CQSSC2_0_SQS_RCA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQSSC2_0_SQS_RCA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQSSC2_0_SQS_RCA_PARITY_PROTECTION                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQSSC2_0_SQS_RCA_PLATFORM_DEPENDENT                 _MK_MASK_CONST(0x1)


// Register SDMMCAB_CQE_CQCRDCT_0
#define SDMMCAB_CQE_CQCRDCT_0                   _MK_ADDR_CONST(0xf048)
#define SDMMCAB_CQE_CQCRDCT_0_SECURE                    0x0
#define SDMMCAB_CQE_CQCRDCT_0_DUAL                      0x0
#define SDMMCAB_CQE_CQCRDCT_0_SCR                       0
#define SDMMCAB_CQE_CQCRDCT_0_WORD_COUNT                        0x1
#define SDMMCAB_CQE_CQCRDCT_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCRDCT_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQCRDCT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCRDCT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCRDCT_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQCRDCT_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCRDCT_0_DCMD_RESP_SHIFT                   _MK_SHIFT_CONST(0)
#define SDMMCAB_CQE_CQCRDCT_0_DCMD_RESP_FIELD                   _MK_FIELD_CONST(0xffffffff, SDMMCAB_CQE_CQCRDCT_0_DCMD_RESP_SHIFT)
#define SDMMCAB_CQE_CQCRDCT_0_DCMD_RESP_RANGE                   31:0
#define SDMMCAB_CQE_CQCRDCT_0_DCMD_RESP_WOFFSET                 0x0
#define SDMMCAB_CQE_CQCRDCT_0_DCMD_RESP_DEFAULT                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCRDCT_0_DCMD_RESP_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQCRDCT_0_DCMD_RESP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCRDCT_0_DCMD_RESP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCRDCT_0_DCMD_RESP_PARITY_PROTECTION                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCRDCT_0_DCMD_RESP_PLATFORM_DEPENDENT                      _MK_MASK_CONST(0x1)


// Reserved address 0xf04c

// Register SDMMCAB_CQE_CQRMEM_0
#define SDMMCAB_CQE_CQRMEM_0                    _MK_ADDR_CONST(0xf050)
#define SDMMCAB_CQE_CQRMEM_0_SECURE                     0x0
#define SDMMCAB_CQE_CQRMEM_0_DUAL                       0x0
#define SDMMCAB_CQE_CQRMEM_0_SCR                        0
#define SDMMCAB_CQE_CQRMEM_0_WORD_COUNT                         0x1
#define SDMMCAB_CQE_CQRMEM_0_RESET_VAL                  _MK_MASK_CONST(0xfdf9a080)
#define SDMMCAB_CQE_CQRMEM_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQRMEM_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQRMEM_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQRMEM_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQRMEM_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQRMEM_0_RESP_ERR_MASK_SHIFT                        _MK_SHIFT_CONST(0)
#define SDMMCAB_CQE_CQRMEM_0_RESP_ERR_MASK_FIELD                        _MK_FIELD_CONST(0xffffffff, SDMMCAB_CQE_CQRMEM_0_RESP_ERR_MASK_SHIFT)
#define SDMMCAB_CQE_CQRMEM_0_RESP_ERR_MASK_RANGE                        31:0
#define SDMMCAB_CQE_CQRMEM_0_RESP_ERR_MASK_WOFFSET                      0x0
#define SDMMCAB_CQE_CQRMEM_0_RESP_ERR_MASK_DEFAULT                      _MK_MASK_CONST(0xfdf9a080)
#define SDMMCAB_CQE_CQRMEM_0_RESP_ERR_MASK_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQRMEM_0_RESP_ERR_MASK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQRMEM_0_RESP_ERR_MASK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQRMEM_0_RESP_ERR_MASK_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQRMEM_0_RESP_ERR_MASK_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQRMEM_0_RESP_ERR_MASK_INIT_ENUM                    -33972096


// Register SDMMCAB_CQE_CQTERRI_0
#define SDMMCAB_CQE_CQTERRI_0                   _MK_ADDR_CONST(0xf054)
#define SDMMCAB_CQE_CQTERRI_0_SECURE                    0x0
#define SDMMCAB_CQE_CQTERRI_0_DUAL                      0x0
#define SDMMCAB_CQE_CQTERRI_0_SCR                       0
#define SDMMCAB_CQE_CQTERRI_0_WORD_COUNT                        0x1
#define SDMMCAB_CQE_CQTERRI_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_RESET_MASK                        _MK_MASK_CONST(0x9f3f9f3f)
#define SDMMCAB_CQE_CQTERRI_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_READ_MASK                         _MK_MASK_CONST(0x9f3f9f3f)
#define SDMMCAB_CQE_CQTERRI_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_FIELDS_VLD_SHIFT                     _MK_SHIFT_CONST(31)
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_FIELDS_VLD_FIELD                     _MK_FIELD_CONST(0x1, SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_FIELDS_VLD_SHIFT)
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_FIELDS_VLD_RANGE                     31:31
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_FIELDS_VLD_WOFFSET                   0x0
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_FIELDS_VLD_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_FIELDS_VLD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_FIELDS_VLD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_FIELDS_VLD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_FIELDS_VLD_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_FIELDS_VLD_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)

#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_TASK_ID_SHIFT                        _MK_SHIFT_CONST(24)
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_TASK_ID_FIELD                        _MK_FIELD_CONST(0x1f, SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_TASK_ID_SHIFT)
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_TASK_ID_RANGE                        28:24
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_TASK_ID_WOFFSET                      0x0
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_TASK_ID_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_TASK_ID_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_TASK_ID_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_TASK_ID_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_TASK_ID_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_TASK_ID_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_CMD_IDX_SHIFT                        _MK_SHIFT_CONST(16)
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_CMD_IDX_FIELD                        _MK_FIELD_CONST(0x3f, SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_CMD_IDX_SHIFT)
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_CMD_IDX_RANGE                        21:16
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_CMD_IDX_WOFFSET                      0x0
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_CMD_IDX_DEFAULT                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_CMD_IDX_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_CMD_IDX_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_CMD_IDX_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_CMD_IDX_PARITY_PROTECTION                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_DAT_XFER_ERR_CMD_IDX_PLATFORM_DEPENDENT                   _MK_MASK_CONST(0x1)

#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_FIELDS_VLD_SHIFT                 _MK_SHIFT_CONST(15)
#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_FIELDS_VLD_FIELD                 _MK_FIELD_CONST(0x1, SDMMCAB_CQE_CQTERRI_0_RESP_ERR_FIELDS_VLD_SHIFT)
#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_FIELDS_VLD_RANGE                 15:15
#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_FIELDS_VLD_WOFFSET                       0x0
#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_FIELDS_VLD_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_FIELDS_VLD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_FIELDS_VLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_FIELDS_VLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_FIELDS_VLD_PARITY_PROTECTION                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_FIELDS_VLD_PLATFORM_DEPENDENT                    _MK_MASK_CONST(0x1)

#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_TASK_ID_SHIFT                    _MK_SHIFT_CONST(8)
#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_TASK_ID_FIELD                    _MK_FIELD_CONST(0x1f, SDMMCAB_CQE_CQTERRI_0_RESP_ERR_TASK_ID_SHIFT)
#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_TASK_ID_RANGE                    12:8
#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_TASK_ID_WOFFSET                  0x0
#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_TASK_ID_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_TASK_ID_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_TASK_ID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_TASK_ID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_TASK_ID_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_TASK_ID_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)

#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_CMD_IDX_SHIFT                    _MK_SHIFT_CONST(0)
#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_CMD_IDX_FIELD                    _MK_FIELD_CONST(0x3f, SDMMCAB_CQE_CQTERRI_0_RESP_ERR_CMD_IDX_SHIFT)
#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_CMD_IDX_RANGE                    5:0
#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_CMD_IDX_WOFFSET                  0x0
#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_CMD_IDX_DEFAULT                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_CMD_IDX_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_CMD_IDX_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_CMD_IDX_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_CMD_IDX_PARITY_PROTECTION                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQTERRI_0_RESP_ERR_CMD_IDX_PLATFORM_DEPENDENT                       _MK_MASK_CONST(0x1)


// Register SDMMCAB_CQE_CQCRI_0
#define SDMMCAB_CQE_CQCRI_0                     _MK_ADDR_CONST(0xf058)
#define SDMMCAB_CQE_CQCRI_0_SECURE                      0x0
#define SDMMCAB_CQE_CQCRI_0_DUAL                        0x0
#define SDMMCAB_CQE_CQCRI_0_SCR                         0
#define SDMMCAB_CQE_CQCRI_0_WORD_COUNT                  0x1
#define SDMMCAB_CQE_CQCRI_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCRI_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
#define SDMMCAB_CQE_CQCRI_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCRI_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCRI_0_READ_MASK                   _MK_MASK_CONST(0x3f)
#define SDMMCAB_CQE_CQCRI_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCRI_0_LAST_CMD_RESP_IDX_SHIFT                     _MK_SHIFT_CONST(0)
#define SDMMCAB_CQE_CQCRI_0_LAST_CMD_RESP_IDX_FIELD                     _MK_FIELD_CONST(0x3f, SDMMCAB_CQE_CQCRI_0_LAST_CMD_RESP_IDX_SHIFT)
#define SDMMCAB_CQE_CQCRI_0_LAST_CMD_RESP_IDX_RANGE                     5:0
#define SDMMCAB_CQE_CQCRI_0_LAST_CMD_RESP_IDX_WOFFSET                   0x0
#define SDMMCAB_CQE_CQCRI_0_LAST_CMD_RESP_IDX_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCRI_0_LAST_CMD_RESP_IDX_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
#define SDMMCAB_CQE_CQCRI_0_LAST_CMD_RESP_IDX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCRI_0_LAST_CMD_RESP_IDX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCRI_0_LAST_CMD_RESP_IDX_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCRI_0_LAST_CMD_RESP_IDX_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


// Register SDMMCAB_CQE_CQCRA_0
#define SDMMCAB_CQE_CQCRA_0                     _MK_ADDR_CONST(0xf05c)
#define SDMMCAB_CQE_CQCRA_0_SECURE                      0x0
#define SDMMCAB_CQE_CQCRA_0_DUAL                        0x0
#define SDMMCAB_CQE_CQCRA_0_SCR                         0
#define SDMMCAB_CQE_CQCRA_0_WORD_COUNT                  0x1
#define SDMMCAB_CQE_CQCRA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCRA_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQCRA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCRA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCRA_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQCRA_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCRA_0_LAST_CMD_RESP_ARG_SHIFT                     _MK_SHIFT_CONST(0)
#define SDMMCAB_CQE_CQCRA_0_LAST_CMD_RESP_ARG_FIELD                     _MK_FIELD_CONST(0xffffffff, SDMMCAB_CQE_CQCRA_0_LAST_CMD_RESP_ARG_SHIFT)
#define SDMMCAB_CQE_CQCRA_0_LAST_CMD_RESP_ARG_RANGE                     31:0
#define SDMMCAB_CQE_CQCRA_0_LAST_CMD_RESP_ARG_WOFFSET                   0x0
#define SDMMCAB_CQE_CQCRA_0_LAST_CMD_RESP_ARG_DEFAULT                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCRA_0_LAST_CMD_RESP_ARG_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define SDMMCAB_CQE_CQCRA_0_LAST_CMD_RESP_ARG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCRA_0_LAST_CMD_RESP_ARG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCRA_0_LAST_CMD_RESP_ARG_PARITY_PROTECTION                 _MK_MASK_CONST(0x0)
#define SDMMCAB_CQE_CQCRA_0_LAST_CMD_RESP_ARG_PLATFORM_DEPENDENT                        _MK_MASK_CONST(0x1)


//
// REGISTER LIST
//
#define LIST_ARSDMMCAB_REGS(_op_) \
_op_(SDMMCAB_SYSTEM_ADDRESS_0) \
_op_(SDMMCAB_BLOCK_SIZE_BLOCK_COUNT_0) \
_op_(SDMMCAB_ARGUMENT_0) \
_op_(SDMMCAB_CMD_XFER_MODE_0) \
_op_(SDMMCAB_RESPONSE_R0_R1_0) \
_op_(SDMMCAB_RESPONSE_R2_R3_0) \
_op_(SDMMCAB_RESPONSE_R4_R5_0) \
_op_(SDMMCAB_RESPONSE_R6_R7_0) \
_op_(SDMMCAB_BUFFER_DATA_PORT_0) \
_op_(SDMMCAB_PRESENT_STATE_0) \
_op_(SDMMCAB_POWER_CONTROL_HOST_0) \
_op_(SDMMCAB_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0) \
_op_(SDMMCAB_INTERRUPT_STATUS_0) \
_op_(SDMMCAB_INTERRUPT_STATUS_ENABLE_0) \
_op_(SDMMCAB_INTERRUPT_SIGNAL_ENABLE_0) \
_op_(SDMMCAB_AUTO_CMD12_ERR_STATUS_0) \
_op_(SDMMCAB_CAPABILITIES_0) \
_op_(SDMMCAB_CAPABILITIES_HIGHER_0) \
_op_(SDMMCAB_MAXIMUM_CURRENT_0) \
_op_(SDMMCAB_MAXIMUM_CURRENT_HI_0) \
_op_(SDMMCAB_FORCE_EVENT_0) \
_op_(SDMMCAB_ADMA_ERR_STATUS_0) \
_op_(SDMMCAB_ADMA_SYSTEM_ADDRESS_0) \
_op_(SDMMCAB_UPPER_ADMA_SYSTEM_ADDRESS_0) \
_op_(SDMMCAB_PRESET_DEFAULT_AND_INIT_0) \
_op_(SDMMCAB_PRESET_SDR12_AND_HIGH_0) \
_op_(SDMMCAB_PRESET_SDR50_AND_SDR25_0) \
_op_(SDMMCAB_PRESET_DDR50_AND_SDR104_0) \
_op_(SDMMCAB_ADMA3_INT_DESC_LOWER_ADDRESS_0) \
_op_(SDMMCAB_ADMA3_INT_DESC_UPPER_ADDRESS_0) \
_op_(SDMMCAB_VENDOR_REGS_PTR_0) \
_op_(SDMMCAB_SLOT_INTERRUPT_STATUS_0) \
_op_(SDMMCAB_VENDOR_CLOCK_CNTRL_0) \
_op_(SDMMCAB_VENDOR_SYS_SW_CNTRL_0) \
_op_(SDMMCAB_VENDOR_ERR_INTR_STATUS_0) \
_op_(SDMMCAB_VENDOR_CAP_OVERRIDES_0) \
_op_(SDMMCAB_VENDOR_BOOT_CNTRL_0) \
_op_(SDMMCAB_VENDOR_BOOT_ACK_TIMEOUT_0) \
_op_(SDMMCAB_VENDOR_BOOT_DAT_TIMEOUT_0) \
_op_(SDMMCAB_VENDOR_DEBOUNCE_COUNT_0) \
_op_(SDMMCAB_VENDOR_MISC_CNTRL_0) \
_op_(SDMMCAB_VENDOR_MISC_CNTRL1_0) \
_op_(SDMMCAB_VENDOR_MISC_CNTRL2_0) \
_op_(SDMMCAB_VENDOR_IO_TRIM_CNTRL_0) \
_op_(SDMMCAB_VENDOR_DLLCAL_CFG_0) \
_op_(SDMMCAB_VENDOR_DLL_CTRL0_0) \
_op_(SDMMCAB_VENDOR_DLL_CTRL1_0) \
_op_(SDMMCAB_VENDOR_DLLCAL_CFG_STA_0) \
_op_(SDMMCAB_VENDOR_TUNING_CNTRL0_0) \
_op_(SDMMCAB_VENDOR_TUNING_CNTRL1_0) \
_op_(SDMMCAB_VENDOR_TUNING_STATUS0_0) \
_op_(SDMMCAB_VENDOR_TUNING_STATUS1_0) \
_op_(SDMMCAB_VENDOR_CLK_GATE_HYSTERESIS_COUNT_0) \
_op_(SDMMCAB_VENDOR_PRESET_VAL0_0) \
_op_(SDMMCAB_VENDOR_PRESET_VAL1_0) \
_op_(SDMMCAB_VENDOR_PRESET_VAL2_0) \
_op_(SDMMCAB_SDMEMCOMPPADCTRL_0) \
_op_(SDMMCAB_AUTO_CAL_CONFIG_0) \
_op_(SDMMCAB_AUTO_CAL_INTERVAL_0) \
_op_(SDMMCAB_AUTO_CAL_STATUS_0) \
_op_(SDMMCAB_IO_SPARE_0) \
_op_(SDMMCAB_CIF2AXI_CTRL_0) \
_op_(SDMMCAB_TZ_DMA_CTRL_0) \
_op_(SDMMCAB_VENDOR_MISC_CNTRL3_0) \
_op_(SDMMCAB_VENDOR_CQE_CNTRL0_0) \
_op_(SDMMCAB_VENDOR_MISC_CNTRL4_0) \
_op_(SDMMCAB_IST_AXI_P2P_CNTRL_0) \
_op_(SDMMCAB_SDMEMCOMPPADCTRL_MISC_CTL_0) \
_op_(SDMMCAB_VENDOR_CQE_CNTRL1_0) \
_op_(SDMMCAB_CQE_CQVER_0) \
_op_(SDMMCAB_CQE_CQCAP_0) \
_op_(SDMMCAB_CQE_CQCFG_0) \
_op_(SDMMCAB_CQE_CQCTL_0) \
_op_(SDMMCAB_CQE_CQIS_0) \
_op_(SDMMCAB_CQE_CQISTE_0) \
_op_(SDMMCAB_CQE_CQISGE_0) \
_op_(SDMMCAB_CQE_CQIC_0) \
_op_(SDMMCAB_CQE_CQTDLBA_0) \
_op_(SDMMCAB_CQE_CQTDLBAU_0) \
_op_(SDMMCAB_CQE_CQTDBR_0) \
_op_(SDMMCAB_CQE_CQTCN_0) \
_op_(SDMMCAB_CQE_CQDQS_0) \
_op_(SDMMCAB_CQE_CQDPT_0) \
_op_(SDMMCAB_CQE_CQTCLR_0) \
_op_(SDMMCAB_CQE_CQSSC1_0) \
_op_(SDMMCAB_CQE_CQSSC2_0) \
_op_(SDMMCAB_CQE_CQCRDCT_0) \
_op_(SDMMCAB_CQE_CQRMEM_0) \
_op_(SDMMCAB_CQE_CQTERRI_0) \
_op_(SDMMCAB_CQE_CQCRI_0) \
_op_(SDMMCAB_CQE_CQCRA_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_SDMMCAB    0x00000000
#define BASE_ADDRESS_SDMMCAB_CQE        0x0000f000

//
// ARSDMMCAB REGISTER BANKS
//

#define SDMMCAB0_FIRST_REG 0x0000 // SDMMCAB_SYSTEM_ADDRESS_0
#define SDMMCAB0_LAST_REG 0x006c // SDMMCAB_PRESET_DDR50_AND_SDR104_0
#define SDMMCAB1_FIRST_REG 0x0078 // SDMMCAB_ADMA3_INT_DESC_LOWER_ADDRESS_0
#define SDMMCAB1_LAST_REG 0x007c // SDMMCAB_ADMA3_INT_DESC_UPPER_ADDRESS_0
#define SDMMCAB2_FIRST_REG 0x00e8 // SDMMCAB_VENDOR_REGS_PTR_0
#define SDMMCAB2_LAST_REG 0x00e8 // SDMMCAB_VENDOR_REGS_PTR_0
#define SDMMCAB3_FIRST_REG 0x00fc // SDMMCAB_SLOT_INTERRUPT_STATUS_0
#define SDMMCAB3_LAST_REG 0x0128 // SDMMCAB_VENDOR_MISC_CNTRL2_0
#define SDMMCAB4_FIRST_REG 0x01ac // SDMMCAB_VENDOR_IO_TRIM_CNTRL_0
#define SDMMCAB4_LAST_REG 0x01f0 // SDMMCAB_IO_SPARE_0
#define SDMMCAB5_FIRST_REG 0x01fc // SDMMCAB_CIF2AXI_CTRL_0
#define SDMMCAB5_LAST_REG 0x0218 // SDMMCAB_VENDOR_CQE_CNTRL1_0
#define SDMMCAB_CQE0_FIRST_REG 0xf000 // SDMMCAB_CQE_CQVER_0
#define SDMMCAB_CQE0_LAST_REG 0xf038 // SDMMCAB_CQE_CQTCLR_0
#define SDMMCAB_CQE1_FIRST_REG 0xf040 // SDMMCAB_CQE_CQSSC1_0
#define SDMMCAB_CQE1_LAST_REG 0xf048 // SDMMCAB_CQE_CQCRDCT_0
#define SDMMCAB_CQE2_FIRST_REG 0xf050 // SDMMCAB_CQE_CQRMEM_0
#define SDMMCAB_CQE2_LAST_REG 0xf05c // SDMMCAB_CQE_CQCRA_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif
#ifndef _MK_FIELD_CONST
  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
#endif

#endif // ifndef ___ARSDMMCAB_H_INC_
